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- From 181467f0be9b3a1daf61a5d3aff458063cacadca Mon Sep 17 00:00:00 2001
- From: Frank Chang <frank.chang@sifive.com>
- Date: Mon, 13 Sep 2021 20:35:05 +0800
- Subject: [PATCH 105/107] target/riscv: Backup/restore mstatus.SD bit when
- virtual register swapped
- When virtual registers are swapped, mstatus.SD bit should also be
- backed up/restored. Otherwise, mstatus.SD bit will be incorrectly kept
- across the world switches.
- Signed-off-by: Frank Chang <frank.chang@sifive.com>
- Reviewed-by: Vincent Chen <vincent.chen@sifive.com>
- ---
- target/riscv/cpu_helper.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
- diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
- index 8605e23a7b..64ad003299 100644
- --- a/target/riscv/cpu_helper.c
- +++ b/target/riscv/cpu_helper.c
- @@ -126,7 +126,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
- {
- uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
- MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
- - MSTATUS64_UXL | MSTATUS_VS;
- + MSTATUS64_UXL | MSTATUS_VS | MSTATUS_SD;
- bool current_virt = riscv_cpu_virt_enabled(env);
-
- g_assert(riscv_has_ext(env, RVH));
- --
- 2.33.1
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