0105-target-riscv-Backup-restore-mstatus.SD-bit-when-virt.patch 1.2 KB

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  1. From 181467f0be9b3a1daf61a5d3aff458063cacadca Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Mon, 13 Sep 2021 20:35:05 +0800
  4. Subject: [PATCH 105/107] target/riscv: Backup/restore mstatus.SD bit when
  5. virtual register swapped
  6. When virtual registers are swapped, mstatus.SD bit should also be
  7. backed up/restored. Otherwise, mstatus.SD bit will be incorrectly kept
  8. across the world switches.
  9. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  10. Reviewed-by: Vincent Chen <vincent.chen@sifive.com>
  11. ---
  12. target/riscv/cpu_helper.c | 2 +-
  13. 1 file changed, 1 insertion(+), 1 deletion(-)
  14. diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
  15. index 8605e23a7b..64ad003299 100644
  16. --- a/target/riscv/cpu_helper.c
  17. +++ b/target/riscv/cpu_helper.c
  18. @@ -126,7 +126,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
  19. {
  20. uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
  21. MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
  22. - MSTATUS64_UXL | MSTATUS_VS;
  23. + MSTATUS64_UXL | MSTATUS_VS | MSTATUS_SD;
  24. bool current_virt = riscv_cpu_virt_enabled(env);
  25. g_assert(riscv_has_ext(env, RVH));
  26. --
  27. 2.33.1