0104-target-riscv-Pass-the-same-value-to-oprsz-and-maxsz.patch 21 KB

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  1. From bac53f716dea5638ec75e65fbbd2ab3de5be130b Mon Sep 17 00:00:00 2001
  2. From: LIU Zhiwei <zhiwei_liu@c-sky.com>
  3. Date: Tue, 24 Aug 2021 21:54:52 +0800
  4. Subject: [PATCH 104/107] target/riscv: Pass the same value to oprsz and maxsz.
  5. Since commit e2e7168, if oprsz
  6. is still zero(as we don't use this field), simd_desc will trigger an
  7. assert.
  8. Besides, tcg_gen_gvec_*_ptr calls simd_desc in it's implementation.
  9. Here we pass the value to maxsz and oprsz to bypass the assert.
  10. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
  11. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  12. Message-id: 20210521054816.1784297-1-zhiwei_liu@c-sky.com
  13. Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
  14. ---
  15. target/riscv/insn_trans/trans_rvv.c.inc | 109 +++++++++++++-----------
  16. 1 file changed, 61 insertions(+), 48 deletions(-)
  17. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  18. index 84e81ffa4d..3084d3cd7c 100644
  19. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  20. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  21. @@ -649,7 +649,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
  22. * The first part is vlen in bytes, encoded in maxsz of simd_desc.
  23. * The second part is lmul, encoded in data of simd_desc.
  24. */
  25. - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
  26. + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
  27. gen_get_gpr(base, rs1);
  28. tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
  29. @@ -808,7 +808,7 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
  30. mask = tcg_temp_new_ptr();
  31. base = tcg_temp_new();
  32. stride = tcg_temp_new();
  33. - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
  34. + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
  35. gen_get_gpr(base, rs1);
  36. gen_get_gpr(stride, rs2);
  37. @@ -917,7 +917,7 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
  38. mask = tcg_temp_new_ptr();
  39. index = tcg_temp_new_ptr();
  40. base = tcg_temp_new();
  41. - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
  42. + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
  43. gen_get_gpr(base, rs1);
  44. tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
  45. @@ -1058,7 +1058,7 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
  46. dest = tcg_temp_new_ptr();
  47. mask = tcg_temp_new_ptr();
  48. base = tcg_temp_new();
  49. - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
  50. + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
  51. gen_get_gpr(base, rs1);
  52. tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
  53. @@ -1117,7 +1117,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
  54. uint32_t data = FIELD_DP32(0, VDATA, NF, nf);
  55. dest = tcg_temp_new_ptr();
  56. base = tcg_temp_new();
  57. - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
  58. + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
  59. gen_get_gpr(base, rs1);
  60. tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
  61. @@ -1190,7 +1190,7 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
  62. mask = tcg_temp_new_ptr();
  63. index = tcg_temp_new_ptr();
  64. base = tcg_temp_new();
  65. - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
  66. + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
  67. gen_get_gpr(base, rs1);
  68. tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
  69. @@ -1381,7 +1381,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
  70. data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
  71. tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
  72. vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
  73. - cpu_env, 0, s->vlen / 8, data, fn);
  74. + cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
  75. }
  76. mark_vs_dirty(s);
  77. gen_set_label(over);
  78. @@ -1424,7 +1424,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
  79. data = FIELD_DP32(data, VDATA, VM, vm);
  80. data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
  81. - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
  82. + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
  83. tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
  84. tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
  85. @@ -1592,7 +1592,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
  86. data = FIELD_DP32(data, VDATA, VM, vm);
  87. data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
  88. - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
  89. + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
  90. tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
  91. tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
  92. @@ -1678,7 +1678,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
  93. tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
  94. vreg_ofs(s, a->rs1),
  95. vreg_ofs(s, a->rs2),
  96. - cpu_env, 0, s->vlen / 8,
  97. + cpu_env, s->vlen / 8, s->vlen / 8,
  98. data, fn);
  99. mark_vs_dirty(s);
  100. gen_set_label(over);
  101. @@ -1757,7 +1757,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
  102. tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
  103. vreg_ofs(s, a->rs1),
  104. vreg_ofs(s, a->rs2),
  105. - cpu_env, 0, s->vlen / 8, data, fn);
  106. + cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
  107. mark_vs_dirty(s);
  108. gen_set_label(over);
  109. return true;
  110. @@ -1832,8 +1832,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  111. data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
  112. tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
  113. vreg_ofs(s, a->rs1), \
  114. - vreg_ofs(s, a->rs2), cpu_env, 0, \
  115. - s->vlen / 8, data, fns[s->sew]); \
  116. + vreg_ofs(s, a->rs2), cpu_env, \
  117. + s->vlen / 8, s->vlen / 8, data, \
  118. + fns[s->sew]); \
  119. mark_vs_dirty(s); \
  120. gen_set_label(over); \
  121. return true; \
  122. @@ -2014,8 +2015,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  123. data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
  124. tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
  125. vreg_ofs(s, a->rs1), \
  126. - vreg_ofs(s, a->rs2), cpu_env, 0, \
  127. - s->vlen / 8, data, fns[s->sew]); \
  128. + vreg_ofs(s, a->rs2), cpu_env, \
  129. + s->vlen / 8, s->vlen / 8, data, \
  130. + fns[s->sew]); \
  131. mark_vs_dirty(s); \
  132. gen_set_label(over); \
  133. return true; \
  134. @@ -2190,7 +2192,8 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
  135. tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
  136. tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
  137. - cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
  138. + cpu_env, s->vlen / 8, s->vlen / 8, data,
  139. + fns[s->sew]);
  140. gen_set_label(over);
  141. }
  142. mark_vs_dirty(s);
  143. @@ -2227,7 +2230,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
  144. };
  145. tcg_gen_ext_tl_i64(s1_i64, s1);
  146. - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
  147. + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
  148. tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
  149. fns[s->sew](dest, s1_i64, cpu_env, desc);
  150. @@ -2269,7 +2272,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
  151. s1 = tcg_const_i64(simm);
  152. dest = tcg_temp_new_ptr();
  153. - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
  154. + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
  155. tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
  156. fns[s->sew](dest, s1, cpu_env, desc);
  157. @@ -2397,8 +2400,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  158. data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
  159. tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
  160. vreg_ofs(s, a->rs1), \
  161. - vreg_ofs(s, a->rs2), cpu_env, 0, \
  162. - s->vlen / 8, data, fns[s->sew - 1]); \
  163. + vreg_ofs(s, a->rs2), cpu_env, \
  164. + s->vlen / 8, s->vlen / 8, data, \
  165. + fns[s->sew - 1]); \
  166. mark_vs_dirty(s); \
  167. gen_set_label(over); \
  168. return true; \
  169. @@ -2424,7 +2428,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
  170. dest = tcg_temp_new_ptr();
  171. mask = tcg_temp_new_ptr();
  172. src2 = tcg_temp_new_ptr();
  173. - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
  174. + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
  175. tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
  176. tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
  177. @@ -2508,8 +2512,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  178. data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
  179. tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
  180. vreg_ofs(s, a->rs1), \
  181. - vreg_ofs(s, a->rs2), cpu_env, 0, \
  182. - s->vlen / 8, data, fns[s->sew - 1]); \
  183. + vreg_ofs(s, a->rs2), cpu_env, \
  184. + s->vlen / 8, s->vlen / 8, data, \
  185. + fns[s->sew - 1]); \
  186. mark_vs_dirty(s); \
  187. gen_set_label(over); \
  188. return true; \
  189. @@ -2574,8 +2579,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  190. data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
  191. tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
  192. vreg_ofs(s, a->rs1), \
  193. - vreg_ofs(s, a->rs2), cpu_env, 0, \
  194. - s->vlen / 8, data, fns[s->sew - 1]); \
  195. + vreg_ofs(s, a->rs2), cpu_env, \
  196. + s->vlen / 8, s->vlen / 8, data, \
  197. + fns[s->sew - 1]); \
  198. mark_vs_dirty(s); \
  199. gen_set_label(over); \
  200. return true; \
  201. @@ -2687,8 +2693,8 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
  202. data = FIELD_DP32(data, VDATA, VM, a->vm);
  203. data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
  204. tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
  205. - vreg_ofs(s, a->rs2), cpu_env, 0,
  206. - s->vlen / 8, data, fn);
  207. + vreg_ofs(s, a->rs2), cpu_env,
  208. + s->vlen / 8, s->vlen / 8, data, fn);
  209. mark_vs_dirty(s);
  210. gen_set_label(over);
  211. return true;
  212. @@ -2795,7 +2801,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
  213. do_nanbox(s, t1, cpu_fpr[a->rs1]);
  214. dest = tcg_temp_new_ptr();
  215. - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
  216. + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
  217. tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
  218. fns[s->sew - 1](dest, t1, cpu_env, desc);
  219. @@ -2866,8 +2872,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  220. data = FIELD_DP32(data, VDATA, VM, a->vm); \
  221. data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
  222. tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
  223. - vreg_ofs(s, a->rs2), cpu_env, 0, \
  224. - s->vlen / 8, data, fns[s->sew - 1]); \
  225. + vreg_ofs(s, a->rs2), cpu_env, \
  226. + s->vlen / 8, s->vlen / 8, data, \
  227. + fns[s->sew - 1]); \
  228. mark_vs_dirty(s); \
  229. gen_set_label(over); \
  230. return true; \
  231. @@ -2907,8 +2914,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  232. \
  233. data = FIELD_DP32(data, VDATA, VM, a->vm); \
  234. tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
  235. - vreg_ofs(s, a->rs2), cpu_env, 0, \
  236. - s->vlen / 8, data, fns[s->sew]); \
  237. + vreg_ofs(s, a->rs2), cpu_env, \
  238. + s->vlen / 8, s->vlen / 8, data, \
  239. + fns[s->sew]); \
  240. mark_vs_dirty(s); \
  241. gen_set_label(over); \
  242. return true; \
  243. @@ -2955,8 +2963,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  244. data = FIELD_DP32(data, VDATA, VM, a->vm); \
  245. data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
  246. tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
  247. - vreg_ofs(s, a->rs2), cpu_env, 0, \
  248. - s->vlen / 8, data, fns[s->sew - 1]); \
  249. + vreg_ofs(s, a->rs2), cpu_env, \
  250. + s->vlen / 8, s->vlen / 8, data, \
  251. + fns[s->sew - 1]); \
  252. mark_vs_dirty(s); \
  253. gen_set_label(over); \
  254. return true; \
  255. @@ -2999,8 +3008,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  256. \
  257. data = FIELD_DP32(data, VDATA, VM, a->vm); \
  258. tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
  259. - vreg_ofs(s, a->rs2), cpu_env, 0, \
  260. - s->vlen / 8, data, fns[s->sew]); \
  261. + vreg_ofs(s, a->rs2), cpu_env, \
  262. + s->vlen / 8, s->vlen / 8, data, \
  263. + fns[s->sew]); \
  264. mark_vs_dirty(s); \
  265. gen_set_label(over); \
  266. return true; \
  267. @@ -3084,8 +3094,8 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
  268. data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
  269. tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
  270. vreg_ofs(s, a->rs1), \
  271. - vreg_ofs(s, a->rs2), cpu_env, 0, \
  272. - s->vlen / 8, data, fn); \
  273. + vreg_ofs(s, a->rs2), cpu_env, \
  274. + s->vlen / 8, s->vlen / 8, data, fn); \
  275. mark_vs_dirty(s); \
  276. gen_set_label(over); \
  277. return true; \
  278. @@ -3118,7 +3128,7 @@ static bool trans_vpopc_m(DisasContext *s, arg_rmr *a)
  279. mask = tcg_temp_new_ptr();
  280. src2 = tcg_temp_new_ptr();
  281. dst = tcg_temp_new();
  282. - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
  283. + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
  284. tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
  285. tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
  286. @@ -3152,7 +3162,7 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
  287. mask = tcg_temp_new_ptr();
  288. src2 = tcg_temp_new_ptr();
  289. dst = tcg_temp_new();
  290. - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
  291. + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
  292. tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
  293. tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
  294. @@ -3189,7 +3199,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  295. data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
  296. tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
  297. vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
  298. - cpu_env, 0, s->vlen / 8, data, fn); \
  299. + cpu_env, s->vlen / 8, s->vlen / 8, \
  300. + data, fn); \
  301. mark_vs_dirty(s); \
  302. gen_set_label(over); \
  303. return true; \
  304. @@ -3227,8 +3238,8 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
  305. gen_helper_viota_m_w, gen_helper_viota_m_d,
  306. };
  307. tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
  308. - vreg_ofs(s, a->rs2), cpu_env, 0,
  309. - s->vlen / 8, data, fns[s->sew]);
  310. + vreg_ofs(s, a->rs2), cpu_env,
  311. + s->vlen / 8, s->vlen / 8, data, fns[s->sew]);
  312. mark_vs_dirty(s);
  313. gen_set_label(over);
  314. return true;
  315. @@ -3254,7 +3265,8 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
  316. gen_helper_vid_v_w, gen_helper_vid_v_d,
  317. };
  318. tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
  319. - cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
  320. + cpu_env, s->vlen / 8, s->vlen / 8, data,
  321. + fns[s->sew]);
  322. mark_vs_dirty(s);
  323. gen_set_label(over);
  324. return true;
  325. @@ -3688,7 +3700,8 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
  326. data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
  327. tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
  328. vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
  329. - cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
  330. + cpu_env, s->vlen / 8, s->vlen / 8, data,
  331. + fns[s->sew]);
  332. mark_vs_dirty(s);
  333. gen_set_label(over);
  334. return true;
  335. @@ -3721,7 +3734,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
  336. gen_helper_vmv4r_v, gen_helper_vmv8r_v, \
  337. }; \
  338. tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
  339. - cpu_env, 0, maxsz, 0, fns[SEQ]); \
  340. + cpu_env, maxsz, maxsz, 0, fns[SEQ]); \
  341. mark_vs_dirty(s); \
  342. gen_set_label(over); \
  343. } \
  344. @@ -3790,8 +3803,8 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
  345. data = FIELD_DP32(data, VDATA, VM, a->vm);
  346. tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
  347. - vreg_ofs(s, a->rs2), cpu_env, 0,
  348. - s->vlen / 8, data, fn);
  349. + vreg_ofs(s, a->rs2), cpu_env,
  350. + s->vlen / 8, s->vlen / 8, data, fn);
  351. mark_vs_dirty(s);
  352. gen_set_label(over);
  353. --
  354. 2.33.1