123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381 |
- From bac53f716dea5638ec75e65fbbd2ab3de5be130b Mon Sep 17 00:00:00 2001
- From: LIU Zhiwei <zhiwei_liu@c-sky.com>
- Date: Tue, 24 Aug 2021 21:54:52 +0800
- Subject: [PATCH 104/107] target/riscv: Pass the same value to oprsz and maxsz.
- Since commit e2e7168, if oprsz
- is still zero(as we don't use this field), simd_desc will trigger an
- assert.
- Besides, tcg_gen_gvec_*_ptr calls simd_desc in it's implementation.
- Here we pass the value to maxsz and oprsz to bypass the assert.
- Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
- Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
- Message-id: 20210521054816.1784297-1-zhiwei_liu@c-sky.com
- Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
- ---
- target/riscv/insn_trans/trans_rvv.c.inc | 109 +++++++++++++-----------
- 1 file changed, 61 insertions(+), 48 deletions(-)
- diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
- index 84e81ffa4d..3084d3cd7c 100644
- --- a/target/riscv/insn_trans/trans_rvv.c.inc
- +++ b/target/riscv/insn_trans/trans_rvv.c.inc
- @@ -649,7 +649,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
- * The first part is vlen in bytes, encoded in maxsz of simd_desc.
- * The second part is lmul, encoded in data of simd_desc.
- */
- - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-
- gen_get_gpr(base, rs1);
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- @@ -808,7 +808,7 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
- mask = tcg_temp_new_ptr();
- base = tcg_temp_new();
- stride = tcg_temp_new();
- - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-
- gen_get_gpr(base, rs1);
- gen_get_gpr(stride, rs2);
- @@ -917,7 +917,7 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
- mask = tcg_temp_new_ptr();
- index = tcg_temp_new_ptr();
- base = tcg_temp_new();
- - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-
- gen_get_gpr(base, rs1);
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- @@ -1058,7 +1058,7 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
- dest = tcg_temp_new_ptr();
- mask = tcg_temp_new_ptr();
- base = tcg_temp_new();
- - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-
- gen_get_gpr(base, rs1);
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- @@ -1117,7 +1117,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
- uint32_t data = FIELD_DP32(0, VDATA, NF, nf);
- dest = tcg_temp_new_ptr();
- base = tcg_temp_new();
- - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-
- gen_get_gpr(base, rs1);
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- @@ -1190,7 +1190,7 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
- mask = tcg_temp_new_ptr();
- index = tcg_temp_new_ptr();
- base = tcg_temp_new();
- - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-
- gen_get_gpr(base, rs1);
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- @@ -1381,7 +1381,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
- - cpu_env, 0, s->vlen / 8, data, fn);
- + cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
- }
- mark_vs_dirty(s);
- gen_set_label(over);
- @@ -1424,7 +1424,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
-
- data = FIELD_DP32(data, VDATA, VM, vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
- @@ -1592,7 +1592,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
-
- data = FIELD_DP32(data, VDATA, VM, vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
- @@ -1678,7 +1678,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- vreg_ofs(s, a->rs1),
- vreg_ofs(s, a->rs2),
- - cpu_env, 0, s->vlen / 8,
- + cpu_env, s->vlen / 8, s->vlen / 8,
- data, fn);
- mark_vs_dirty(s);
- gen_set_label(over);
- @@ -1757,7 +1757,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- vreg_ofs(s, a->rs1),
- vreg_ofs(s, a->rs2),
- - cpu_env, 0, s->vlen / 8, data, fn);
- + cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
- mark_vs_dirty(s);
- gen_set_label(over);
- return true;
- @@ -1832,8 +1832,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs1), \
- - vreg_ofs(s, a->rs2), cpu_env, 0, \
- - s->vlen / 8, data, fns[s->sew]); \
- + vreg_ofs(s, a->rs2), cpu_env, \
- + s->vlen / 8, s->vlen / 8, data, \
- + fns[s->sew]); \
- mark_vs_dirty(s); \
- gen_set_label(over); \
- return true; \
- @@ -2014,8 +2015,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs1), \
- - vreg_ofs(s, a->rs2), cpu_env, 0, \
- - s->vlen / 8, data, fns[s->sew]); \
- + vreg_ofs(s, a->rs2), cpu_env, \
- + s->vlen / 8, s->vlen / 8, data, \
- + fns[s->sew]); \
- mark_vs_dirty(s); \
- gen_set_label(over); \
- return true; \
- @@ -2190,7 +2192,8 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-
- tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
- - cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
- + cpu_env, s->vlen / 8, s->vlen / 8, data,
- + fns[s->sew]);
- gen_set_label(over);
- }
- mark_vs_dirty(s);
- @@ -2227,7 +2230,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
- };
-
- tcg_gen_ext_tl_i64(s1_i64, s1);
- - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew](dest, s1_i64, cpu_env, desc);
-
- @@ -2269,7 +2272,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
-
- s1 = tcg_const_i64(simm);
- dest = tcg_temp_new_ptr();
- - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew](dest, s1, cpu_env, desc);
-
- @@ -2397,8 +2400,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs1), \
- - vreg_ofs(s, a->rs2), cpu_env, 0, \
- - s->vlen / 8, data, fns[s->sew - 1]); \
- + vreg_ofs(s, a->rs2), cpu_env, \
- + s->vlen / 8, s->vlen / 8, data, \
- + fns[s->sew - 1]); \
- mark_vs_dirty(s); \
- gen_set_label(over); \
- return true; \
- @@ -2424,7 +2428,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
- dest = tcg_temp_new_ptr();
- mask = tcg_temp_new_ptr();
- src2 = tcg_temp_new_ptr();
- - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
- @@ -2508,8 +2512,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs1), \
- - vreg_ofs(s, a->rs2), cpu_env, 0, \
- - s->vlen / 8, data, fns[s->sew - 1]); \
- + vreg_ofs(s, a->rs2), cpu_env, \
- + s->vlen / 8, s->vlen / 8, data, \
- + fns[s->sew - 1]); \
- mark_vs_dirty(s); \
- gen_set_label(over); \
- return true; \
- @@ -2574,8 +2579,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs1), \
- - vreg_ofs(s, a->rs2), cpu_env, 0, \
- - s->vlen / 8, data, fns[s->sew - 1]); \
- + vreg_ofs(s, a->rs2), cpu_env, \
- + s->vlen / 8, s->vlen / 8, data, \
- + fns[s->sew - 1]); \
- mark_vs_dirty(s); \
- gen_set_label(over); \
- return true; \
- @@ -2687,8 +2693,8 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
- data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- - vreg_ofs(s, a->rs2), cpu_env, 0,
- - s->vlen / 8, data, fn);
- + vreg_ofs(s, a->rs2), cpu_env,
- + s->vlen / 8, s->vlen / 8, data, fn);
- mark_vs_dirty(s);
- gen_set_label(over);
- return true;
- @@ -2795,7 +2801,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
- do_nanbox(s, t1, cpu_fpr[a->rs1]);
-
- dest = tcg_temp_new_ptr();
- - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
-
- fns[s->sew - 1](dest, t1, cpu_env, desc);
- @@ -2866,8 +2872,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- - vreg_ofs(s, a->rs2), cpu_env, 0, \
- - s->vlen / 8, data, fns[s->sew - 1]); \
- + vreg_ofs(s, a->rs2), cpu_env, \
- + s->vlen / 8, s->vlen / 8, data, \
- + fns[s->sew - 1]); \
- mark_vs_dirty(s); \
- gen_set_label(over); \
- return true; \
- @@ -2907,8 +2914,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
- \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- - vreg_ofs(s, a->rs2), cpu_env, 0, \
- - s->vlen / 8, data, fns[s->sew]); \
- + vreg_ofs(s, a->rs2), cpu_env, \
- + s->vlen / 8, s->vlen / 8, data, \
- + fns[s->sew]); \
- mark_vs_dirty(s); \
- gen_set_label(over); \
- return true; \
- @@ -2955,8 +2963,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- - vreg_ofs(s, a->rs2), cpu_env, 0, \
- - s->vlen / 8, data, fns[s->sew - 1]); \
- + vreg_ofs(s, a->rs2), cpu_env, \
- + s->vlen / 8, s->vlen / 8, data, \
- + fns[s->sew - 1]); \
- mark_vs_dirty(s); \
- gen_set_label(over); \
- return true; \
- @@ -2999,8 +3008,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
- \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- - vreg_ofs(s, a->rs2), cpu_env, 0, \
- - s->vlen / 8, data, fns[s->sew]); \
- + vreg_ofs(s, a->rs2), cpu_env, \
- + s->vlen / 8, s->vlen / 8, data, \
- + fns[s->sew]); \
- mark_vs_dirty(s); \
- gen_set_label(over); \
- return true; \
- @@ -3084,8 +3094,8 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs1), \
- - vreg_ofs(s, a->rs2), cpu_env, 0, \
- - s->vlen / 8, data, fn); \
- + vreg_ofs(s, a->rs2), cpu_env, \
- + s->vlen / 8, s->vlen / 8, data, fn); \
- mark_vs_dirty(s); \
- gen_set_label(over); \
- return true; \
- @@ -3118,7 +3128,7 @@ static bool trans_vpopc_m(DisasContext *s, arg_rmr *a)
- mask = tcg_temp_new_ptr();
- src2 = tcg_temp_new_ptr();
- dst = tcg_temp_new();
- - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
- @@ -3152,7 +3162,7 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
- mask = tcg_temp_new_ptr();
- src2 = tcg_temp_new_ptr();
- dst = tcg_temp_new();
- - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
- + desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
- @@ -3189,7 +3199,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
- vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
- - cpu_env, 0, s->vlen / 8, data, fn); \
- + cpu_env, s->vlen / 8, s->vlen / 8, \
- + data, fn); \
- mark_vs_dirty(s); \
- gen_set_label(over); \
- return true; \
- @@ -3227,8 +3238,8 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
- gen_helper_viota_m_w, gen_helper_viota_m_d,
- };
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- - vreg_ofs(s, a->rs2), cpu_env, 0,
- - s->vlen / 8, data, fns[s->sew]);
- + vreg_ofs(s, a->rs2), cpu_env,
- + s->vlen / 8, s->vlen / 8, data, fns[s->sew]);
- mark_vs_dirty(s);
- gen_set_label(over);
- return true;
- @@ -3254,7 +3265,8 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
- gen_helper_vid_v_w, gen_helper_vid_v_d,
- };
- tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- - cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
- + cpu_env, s->vlen / 8, s->vlen / 8, data,
- + fns[s->sew]);
- mark_vs_dirty(s);
- gen_set_label(over);
- return true;
- @@ -3688,7 +3700,8 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
- - cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
- + cpu_env, s->vlen / 8, s->vlen / 8, data,
- + fns[s->sew]);
- mark_vs_dirty(s);
- gen_set_label(over);
- return true;
- @@ -3721,7 +3734,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
- gen_helper_vmv4r_v, gen_helper_vmv8r_v, \
- }; \
- tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
- - cpu_env, 0, maxsz, 0, fns[SEQ]); \
- + cpu_env, maxsz, maxsz, 0, fns[SEQ]); \
- mark_vs_dirty(s); \
- gen_set_label(over); \
- } \
- @@ -3790,8 +3803,8 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
- data = FIELD_DP32(data, VDATA, VM, a->vm);
-
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- - vreg_ofs(s, a->rs2), cpu_env, 0,
- - s->vlen / 8, data, fn);
- + vreg_ofs(s, a->rs2), cpu_env,
- + s->vlen / 8, s->vlen / 8, data, fn);
-
- mark_vs_dirty(s);
- gen_set_label(over);
- --
- 2.33.1
|