0100-target-riscv-rvb-support-and-turn-on-B-extension-fro.patch 2.1 KB

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  1. From 5828dd1148c3e2d69c11861288834a17cec378f9 Mon Sep 17 00:00:00 2001
  2. From: Kito Cheng <kito.cheng@sifive.com>
  3. Date: Tue, 20 Oct 2020 23:23:26 +0800
  4. Subject: [PATCH 100/107] target/riscv: rvb: support and turn on B-extension
  5. from command line
  6. B-extension is default off, use cpu rv32 or rv64 with x-b=true to
  7. enable B-extension.
  8. Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
  9. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  10. Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
  11. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  12. ---
  13. target/riscv/cpu.c | 4 ++++
  14. target/riscv/cpu.h | 2 ++
  15. 2 files changed, 6 insertions(+)
  16. diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
  17. index f6d79c5aa9..b0519793ed 100644
  18. --- a/target/riscv/cpu.c
  19. +++ b/target/riscv/cpu.c
  20. @@ -473,6 +473,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
  21. if (cpu->cfg.ext_h) {
  22. target_misa |= RVH;
  23. }
  24. + if (cpu->cfg.ext_b) {
  25. + target_misa |= RVB;
  26. + }
  27. if (cpu->cfg.ext_v) {
  28. target_misa |= RVV;
  29. if (!is_power_of_2(cpu->cfg.vlen)) {
  30. @@ -543,6 +546,7 @@ static Property riscv_cpu_properties[] = {
  31. DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
  32. DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
  33. /* This is experimental so mark with 'x-' */
  34. + DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
  35. DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
  36. DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
  37. DEFINE_PROP_BOOL("x-Zfh", RISCVCPU, cfg.ext_zfh, false),
  38. diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
  39. index e223ab550b..457d95eff1 100644
  40. --- a/target/riscv/cpu.h
  41. +++ b/target/riscv/cpu.h
  42. @@ -72,6 +72,7 @@
  43. #define RVS RV('S')
  44. #define RVU RV('U')
  45. #define RVH RV('H')
  46. +#define RVB RV('B')
  47. /* S extension denotes that Supervisor mode exists, however it is possible
  48. to have a core that support S mode but does not have an MMU and there
  49. @@ -291,6 +292,7 @@ struct RISCVCPU {
  50. bool ext_f;
  51. bool ext_d;
  52. bool ext_c;
  53. + bool ext_b;
  54. bool ext_s;
  55. bool ext_u;
  56. bool ext_h;
  57. --
  58. 2.33.1