0098-target-riscv-rvb-address-calculation.patch 5.3 KB

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  1. From b16cbd463bf78d9642f48a44b6b24d3e4f7748d1 Mon Sep 17 00:00:00 2001
  2. From: Kito Cheng <kito.cheng@sifive.com>
  3. Date: Tue, 20 Oct 2020 18:26:58 +0800
  4. Subject: [PATCH 098/107] target/riscv: rvb: address calculation
  5. Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. ---
  9. target/riscv/insn32-64.decode | 3 +++
  10. target/riscv/insn32.decode | 3 +++
  11. target/riscv/insn_trans/trans_rvb.c.inc | 23 ++++++++++++++++++
  12. target/riscv/translate.c | 32 +++++++++++++++++++++++++
  13. 4 files changed, 61 insertions(+)
  14. diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
  15. index d95c845e95..d4fa4498be 100644
  16. --- a/target/riscv/insn32-64.decode
  17. +++ b/target/riscv/insn32-64.decode
  18. @@ -110,6 +110,9 @@ rorw 0110000 .......... 101 ..... 0111011 @r
  19. rolw 0110000 .......... 001 ..... 0111011 @r
  20. grevw 0110100 .......... 101 ..... 0111011 @r
  21. gorcw 0010100 .......... 101 ..... 0111011 @r
  22. +sh1add_uw 0010000 .......... 010 ..... 0111011 @r
  23. +sh2add_uw 0010000 .......... 100 ..... 0111011 @r
  24. +sh3add_uw 0010000 .......... 110 ..... 0111011 @r
  25. bsetiw 0010100 .......... 001 ..... 0011011 @sh5
  26. bclriw 0100100 .......... 001 ..... 0011011 @sh5
  27. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  28. index c519d5f8d0..9a45f2265b 100644
  29. --- a/target/riscv/insn32.decode
  30. +++ b/target/riscv/insn32.decode
  31. @@ -717,6 +717,9 @@ ror 0110000 .......... 101 ..... 0110011 @r
  32. rol 0110000 .......... 001 ..... 0110011 @r
  33. grev 0110100 .......... 101 ..... 0110011 @r
  34. gorc 0010100 .......... 101 ..... 0110011 @r
  35. +sh1add 0010000 .......... 010 ..... 0110011 @r
  36. +sh2add 0010000 .......... 100 ..... 0110011 @r
  37. +sh3add 0010000 .......... 110 ..... 0110011 @r
  38. bseti 00101. ........... 001 ..... 0010011 @sh
  39. bclri 01001. ........... 001 ..... 0010011 @sh
  40. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  41. index a4181dbf0d..ca987f2705 100644
  42. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  43. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  44. @@ -226,6 +226,17 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
  45. return gen_shifti(ctx, a, gen_helper_gorc);
  46. }
  47. +#define GEN_TRANS_SHADD(SHAMT) \
  48. +static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
  49. +{ \
  50. + REQUIRE_EXT(ctx, RVB); \
  51. + return gen_arith(ctx, a, gen_sh##SHAMT##add); \
  52. +}
  53. +
  54. +GEN_TRANS_SHADD(1)
  55. +GEN_TRANS_SHADD(2)
  56. +GEN_TRANS_SHADD(3)
  57. +
  58. /* RV64-only instructions */
  59. #ifdef TARGET_RISCV64
  60. @@ -367,4 +378,16 @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
  61. return gen_shiftiw(ctx, a, gen_gorcw);
  62. }
  63. +#define GEN_TRANS_SHADD_UW(SHAMT) \
  64. +static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
  65. + arg_sh##SHAMT##add_uw *a) \
  66. +{ \
  67. + REQUIRE_EXT(ctx, RVB); \
  68. + return gen_arith(ctx, a, gen_sh##SHAMT##add_uw); \
  69. +}
  70. +
  71. +GEN_TRANS_SHADD_UW(1)
  72. +GEN_TRANS_SHADD_UW(2)
  73. +GEN_TRANS_SHADD_UW(3)
  74. +
  75. #endif
  76. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  77. index e1ed27b76f..f02ab479aa 100644
  78. --- a/target/riscv/translate.c
  79. +++ b/target/riscv/translate.c
  80. @@ -702,6 +702,21 @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
  81. return true;
  82. }
  83. +#define GEN_SHADD(SHAMT) \
  84. +static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
  85. +{ \
  86. + TCGv t = tcg_temp_new(); \
  87. + \
  88. + tcg_gen_shli_tl(t, arg1, SHAMT); \
  89. + tcg_gen_add_tl(ret, t, arg2); \
  90. + \
  91. + tcg_temp_free(t); \
  92. +}
  93. +
  94. +GEN_SHADD(1)
  95. +GEN_SHADD(2)
  96. +GEN_SHADD(3)
  97. +
  98. #ifdef TARGET_RISCV64
  99. static void gen_ctzw(TCGv ret, TCGv arg1)
  100. @@ -788,6 +803,23 @@ static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
  101. gen_helper_gorcw(ret, arg1, arg2);
  102. }
  103. +#define GEN_SHADD_UW(SHAMT) \
  104. +static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
  105. +{ \
  106. + TCGv t = tcg_temp_new(); \
  107. + \
  108. + tcg_gen_ext32u_tl(t, arg1); \
  109. + \
  110. + tcg_gen_shli_tl(t, t, SHAMT); \
  111. + tcg_gen_add_tl(ret, t, arg2); \
  112. + \
  113. + tcg_temp_free(t); \
  114. +}
  115. +
  116. +GEN_SHADD_UW(1)
  117. +GEN_SHADD_UW(2)
  118. +GEN_SHADD_UW(3)
  119. +
  120. #endif
  121. static bool gen_arith(DisasContext *ctx, arg_r *a,
  122. --
  123. 2.33.1