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- From b16cbd463bf78d9642f48a44b6b24d3e4f7748d1 Mon Sep 17 00:00:00 2001
- From: Kito Cheng <kito.cheng@sifive.com>
- Date: Tue, 20 Oct 2020 18:26:58 +0800
- Subject: [PATCH 098/107] target/riscv: rvb: address calculation
- Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
- Signed-off-by: Frank Chang <frank.chang@sifive.com>
- Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
- ---
- target/riscv/insn32-64.decode | 3 +++
- target/riscv/insn32.decode | 3 +++
- target/riscv/insn_trans/trans_rvb.c.inc | 23 ++++++++++++++++++
- target/riscv/translate.c | 32 +++++++++++++++++++++++++
- 4 files changed, 61 insertions(+)
- diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
- index d95c845e95..d4fa4498be 100644
- --- a/target/riscv/insn32-64.decode
- +++ b/target/riscv/insn32-64.decode
- @@ -110,6 +110,9 @@ rorw 0110000 .......... 101 ..... 0111011 @r
- rolw 0110000 .......... 001 ..... 0111011 @r
- grevw 0110100 .......... 101 ..... 0111011 @r
- gorcw 0010100 .......... 101 ..... 0111011 @r
- +sh1add_uw 0010000 .......... 010 ..... 0111011 @r
- +sh2add_uw 0010000 .......... 100 ..... 0111011 @r
- +sh3add_uw 0010000 .......... 110 ..... 0111011 @r
-
- bsetiw 0010100 .......... 001 ..... 0011011 @sh5
- bclriw 0100100 .......... 001 ..... 0011011 @sh5
- diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
- index c519d5f8d0..9a45f2265b 100644
- --- a/target/riscv/insn32.decode
- +++ b/target/riscv/insn32.decode
- @@ -717,6 +717,9 @@ ror 0110000 .......... 101 ..... 0110011 @r
- rol 0110000 .......... 001 ..... 0110011 @r
- grev 0110100 .......... 101 ..... 0110011 @r
- gorc 0010100 .......... 101 ..... 0110011 @r
- +sh1add 0010000 .......... 010 ..... 0110011 @r
- +sh2add 0010000 .......... 100 ..... 0110011 @r
- +sh3add 0010000 .......... 110 ..... 0110011 @r
-
- bseti 00101. ........... 001 ..... 0010011 @sh
- bclri 01001. ........... 001 ..... 0010011 @sh
- diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
- index a4181dbf0d..ca987f2705 100644
- --- a/target/riscv/insn_trans/trans_rvb.c.inc
- +++ b/target/riscv/insn_trans/trans_rvb.c.inc
- @@ -226,6 +226,17 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
- return gen_shifti(ctx, a, gen_helper_gorc);
- }
-
- +#define GEN_TRANS_SHADD(SHAMT) \
- +static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
- +{ \
- + REQUIRE_EXT(ctx, RVB); \
- + return gen_arith(ctx, a, gen_sh##SHAMT##add); \
- +}
- +
- +GEN_TRANS_SHADD(1)
- +GEN_TRANS_SHADD(2)
- +GEN_TRANS_SHADD(3)
- +
- /* RV64-only instructions */
- #ifdef TARGET_RISCV64
-
- @@ -367,4 +378,16 @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
- return gen_shiftiw(ctx, a, gen_gorcw);
- }
-
- +#define GEN_TRANS_SHADD_UW(SHAMT) \
- +static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
- + arg_sh##SHAMT##add_uw *a) \
- +{ \
- + REQUIRE_EXT(ctx, RVB); \
- + return gen_arith(ctx, a, gen_sh##SHAMT##add_uw); \
- +}
- +
- +GEN_TRANS_SHADD_UW(1)
- +GEN_TRANS_SHADD_UW(2)
- +GEN_TRANS_SHADD_UW(3)
- +
- #endif
- diff --git a/target/riscv/translate.c b/target/riscv/translate.c
- index e1ed27b76f..f02ab479aa 100644
- --- a/target/riscv/translate.c
- +++ b/target/riscv/translate.c
- @@ -702,6 +702,21 @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
- return true;
- }
-
- +#define GEN_SHADD(SHAMT) \
- +static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
- +{ \
- + TCGv t = tcg_temp_new(); \
- + \
- + tcg_gen_shli_tl(t, arg1, SHAMT); \
- + tcg_gen_add_tl(ret, t, arg2); \
- + \
- + tcg_temp_free(t); \
- +}
- +
- +GEN_SHADD(1)
- +GEN_SHADD(2)
- +GEN_SHADD(3)
- +
- #ifdef TARGET_RISCV64
-
- static void gen_ctzw(TCGv ret, TCGv arg1)
- @@ -788,6 +803,23 @@ static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
- gen_helper_gorcw(ret, arg1, arg2);
- }
-
- +#define GEN_SHADD_UW(SHAMT) \
- +static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
- +{ \
- + TCGv t = tcg_temp_new(); \
- + \
- + tcg_gen_ext32u_tl(t, arg1); \
- + \
- + tcg_gen_shli_tl(t, t, SHAMT); \
- + tcg_gen_add_tl(ret, t, arg2); \
- + \
- + tcg_temp_free(t); \
- +}
- +
- +GEN_SHADD_UW(1)
- +GEN_SHADD_UW(2)
- +GEN_SHADD_UW(3)
- +
- #endif
-
- static bool gen_arith(DisasContext *ctx, arg_r *a,
- --
- 2.33.1
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