0097-target-riscv-rvb-generalized-or-combine.patch 5.4 KB

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  1. From 28d63f93946ba320169224c86a14b19f75febc6e Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Tue, 20 Oct 2020 18:22:42 +0800
  4. Subject: [PATCH 097/107] target/riscv: rvb: generalized or-combine
  5. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  6. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  7. ---
  8. target/riscv/bitmanip_helper.c | 31 +++++++++++++++++++++++++
  9. target/riscv/helper.h | 2 ++
  10. target/riscv/insn32-64.decode | 2 ++
  11. target/riscv/insn32.decode | 2 ++
  12. target/riscv/insn_trans/trans_rvb.c.inc | 24 +++++++++++++++++++
  13. target/riscv/translate.c | 6 +++++
  14. 6 files changed, 67 insertions(+)
  15. diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
  16. index 1d3235bc0d..389b52eccd 100644
  17. --- a/target/riscv/bitmanip_helper.c
  18. +++ b/target/riscv/bitmanip_helper.c
  19. @@ -69,3 +69,34 @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
  20. }
  21. #endif
  22. +
  23. +static target_ulong do_gorc(target_ulong rs1,
  24. + target_ulong rs2,
  25. + int bits)
  26. +{
  27. + target_ulong x = rs1;
  28. + int i, shift;
  29. +
  30. + for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
  31. + if (rs2 & shift) {
  32. + x |= do_swap(x, adjacent_masks[i], shift);
  33. + }
  34. + }
  35. +
  36. + return x;
  37. +}
  38. +
  39. +target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
  40. +{
  41. + return do_gorc(rs1, rs2, TARGET_LONG_BITS);
  42. +}
  43. +
  44. +/* RV64-only instruction */
  45. +#ifdef TARGET_RISCV64
  46. +
  47. +target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
  48. +{
  49. + return do_gorc(rs1, rs2, 32);
  50. +}
  51. +
  52. +#endif
  53. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  54. index e810303aff..9bbf93d47e 100644
  55. --- a/target/riscv/helper.h
  56. +++ b/target/riscv/helper.h
  57. @@ -94,9 +94,11 @@ DEF_HELPER_FLAGS_1(fclass_h, TCG_CALL_NO_RWG_SE, tl, i64)
  58. /* Bitmanip */
  59. DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  60. +DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  61. #if defined(TARGET_RISCV64)
  62. DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  63. +DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  64. #endif
  65. /* Special functions */
  66. diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
  67. index 18460e023d..d95c845e95 100644
  68. --- a/target/riscv/insn32-64.decode
  69. +++ b/target/riscv/insn32-64.decode
  70. @@ -109,6 +109,7 @@ srow 0010000 .......... 101 ..... 0111011 @r
  71. rorw 0110000 .......... 101 ..... 0111011 @r
  72. rolw 0110000 .......... 001 ..... 0111011 @r
  73. grevw 0110100 .......... 101 ..... 0111011 @r
  74. +gorcw 0010100 .......... 101 ..... 0111011 @r
  75. bsetiw 0010100 .......... 001 ..... 0011011 @sh5
  76. bclriw 0100100 .......... 001 ..... 0011011 @sh5
  77. @@ -117,3 +118,4 @@ sloiw 0010000 .......... 001 ..... 0011011 @sh5
  78. sroiw 0010000 .......... 101 ..... 0011011 @sh5
  79. roriw 0110000 .......... 101 ..... 0011011 @sh5
  80. greviw 0110100 .......... 101 ..... 0011011 @sh5
  81. +gorciw 0010100 .......... 101 ..... 0011011 @sh5
  82. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  83. index 95c31a362a..c519d5f8d0 100644
  84. --- a/target/riscv/insn32.decode
  85. +++ b/target/riscv/insn32.decode
  86. @@ -716,6 +716,7 @@ sro 0010000 .......... 101 ..... 0110011 @r
  87. ror 0110000 .......... 101 ..... 0110011 @r
  88. rol 0110000 .......... 001 ..... 0110011 @r
  89. grev 0110100 .......... 101 ..... 0110011 @r
  90. +gorc 0010100 .......... 101 ..... 0110011 @r
  91. bseti 00101. ........... 001 ..... 0010011 @sh
  92. bclri 01001. ........... 001 ..... 0010011 @sh
  93. @@ -725,3 +726,4 @@ sloi 00100. ........... 001 ..... 0010011 @sh
  94. sroi 00100. ........... 101 ..... 0010011 @sh
  95. rori 01100. ........... 101 ..... 0010011 @sh
  96. grevi 01101. ........... 101 ..... 0010011 @sh
  97. +gorci 00101. ........... 101 ..... 0010011 @sh
  98. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  99. index 286643cd18..a4181dbf0d 100644
  100. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  101. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  102. @@ -214,6 +214,18 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
  103. return gen_grevi(ctx, a);
  104. }
  105. +static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
  106. +{
  107. + REQUIRE_EXT(ctx, RVB);
  108. + return gen_shift(ctx, a, gen_helper_gorc);
  109. +}
  110. +
  111. +static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
  112. +{
  113. + REQUIRE_EXT(ctx, RVB);
  114. + return gen_shifti(ctx, a, gen_helper_gorc);
  115. +}
  116. +
  117. /* RV64-only instructions */
  118. #ifdef TARGET_RISCV64
  119. @@ -343,4 +355,16 @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
  120. return gen_shiftiw(ctx, a, gen_grevw);
  121. }
  122. +static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
  123. +{
  124. + REQUIRE_EXT(ctx, RVB);
  125. + return gen_shiftw(ctx, a, gen_gorcw);
  126. +}
  127. +
  128. +static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
  129. +{
  130. + REQUIRE_EXT(ctx, RVB);
  131. + return gen_shiftiw(ctx, a, gen_gorcw);
  132. +}
  133. +
  134. #endif
  135. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  136. index b349bf76d9..e1ed27b76f 100644
  137. --- a/target/riscv/translate.c
  138. +++ b/target/riscv/translate.c
  139. @@ -782,6 +782,12 @@ static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
  140. gen_helper_grev(ret, arg1, arg2);
  141. }
  142. +static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
  143. +{
  144. + tcg_gen_ext32u_tl(arg1, arg1);
  145. + gen_helper_gorcw(ret, arg1, arg2);
  146. +}
  147. +
  148. #endif
  149. static bool gen_arith(DisasContext *ctx, arg_r *a,
  150. --
  151. 2.33.1