0094-target-riscv-rvb-shift-ones.patch 4.4 KB

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  1. From daa9e0672a0a27cd3540fa66dd11a5b7030a8c1b Mon Sep 17 00:00:00 2001
  2. From: Kito Cheng <kito.cheng@sifive.com>
  3. Date: Tue, 20 Oct 2020 18:11:28 +0800
  4. Subject: [PATCH 094/107] target/riscv: rvb: shift ones
  5. Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. ---
  9. target/riscv/insn32-64.decode | 4 +++
  10. target/riscv/insn32.decode | 4 +++
  11. target/riscv/insn_trans/trans_rvb.c.inc | 48 +++++++++++++++++++++++++
  12. target/riscv/translate.c | 14 ++++++++
  13. 4 files changed, 70 insertions(+)
  14. diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
  15. index 3543342fca..d2daee4a05 100644
  16. --- a/target/riscv/insn32-64.decode
  17. +++ b/target/riscv/insn32-64.decode
  18. @@ -104,7 +104,11 @@ bsetw 0010100 .......... 001 ..... 0111011 @r
  19. bclrw 0100100 .......... 001 ..... 0111011 @r
  20. binvw 0110100 .......... 001 ..... 0111011 @r
  21. bextw 0100100 .......... 101 ..... 0111011 @r
  22. +slow 0010000 .......... 001 ..... 0111011 @r
  23. +srow 0010000 .......... 101 ..... 0111011 @r
  24. bsetiw 0010100 .......... 001 ..... 0011011 @sh5
  25. bclriw 0100100 .......... 001 ..... 0011011 @sh5
  26. binviw 0110100 .......... 001 ..... 0011011 @sh5
  27. +sloiw 0010000 .......... 001 ..... 0011011 @sh5
  28. +sroiw 0010000 .......... 101 ..... 0011011 @sh5
  29. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  30. index 14ffcc7afd..f0ff5c5441 100644
  31. --- a/target/riscv/insn32.decode
  32. +++ b/target/riscv/insn32.decode
  33. @@ -711,8 +711,12 @@ bset 0010100 .......... 001 ..... 0110011 @r
  34. bclr 0100100 .......... 001 ..... 0110011 @r
  35. binv 0110100 .......... 001 ..... 0110011 @r
  36. bext 0100100 .......... 101 ..... 0110011 @r
  37. +slo 0010000 .......... 001 ..... 0110011 @r
  38. +sro 0010000 .......... 101 ..... 0110011 @r
  39. bseti 00101. ........... 001 ..... 0010011 @sh
  40. bclri 01001. ........... 001 ..... 0010011 @sh
  41. binvi 01101. ........... 001 ..... 0010011 @sh
  42. bexti 01001. ........... 101 ..... 0010011 @sh
  43. +sloi 00100. ........... 001 ..... 0010011 @sh
  44. +sroi 00100. ........... 101 ..... 0010011 @sh
  45. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  46. index 0c41f135dc..44f9f63924 100644
  47. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  48. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  49. @@ -155,6 +155,30 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
  50. return gen_shifti(ctx, a, gen_bext);
  51. }
  52. +static bool trans_slo(DisasContext *ctx, arg_slo *a)
  53. +{
  54. + REQUIRE_EXT(ctx, RVB);
  55. + return gen_shift(ctx, a, gen_slo);
  56. +}
  57. +
  58. +static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
  59. +{
  60. + REQUIRE_EXT(ctx, RVB);
  61. + return gen_shifti(ctx, a, gen_slo);
  62. +}
  63. +
  64. +static bool trans_sro(DisasContext *ctx, arg_sro *a)
  65. +{
  66. + REQUIRE_EXT(ctx, RVB);
  67. + return gen_shift(ctx, a, gen_sro);
  68. +}
  69. +
  70. +static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
  71. +{
  72. + REQUIRE_EXT(ctx, RVB);
  73. + return gen_shifti(ctx, a, gen_sro);
  74. +}
  75. +
  76. /* RV64-only instructions */
  77. #ifdef TARGET_RISCV64
  78. @@ -230,4 +254,28 @@ static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
  79. return gen_shiftw(ctx, a, gen_bext);
  80. }
  81. +static bool trans_slow(DisasContext *ctx, arg_slow *a)
  82. +{
  83. + REQUIRE_EXT(ctx, RVB);
  84. + return gen_shiftw(ctx, a, gen_slo);
  85. +}
  86. +
  87. +static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
  88. +{
  89. + REQUIRE_EXT(ctx, RVB);
  90. + return gen_shiftiw(ctx, a, gen_slo);
  91. +}
  92. +
  93. +static bool trans_srow(DisasContext *ctx, arg_srow *a)
  94. +{
  95. + REQUIRE_EXT(ctx, RVB);
  96. + return gen_shiftw(ctx, a, gen_sro);
  97. +}
  98. +
  99. +static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
  100. +{
  101. + REQUIRE_EXT(ctx, RVB);
  102. + return gen_shiftiw(ctx, a, gen_sro);
  103. +}
  104. +
  105. #endif
  106. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  107. index 5c70890333..f9dcdf8afe 100644
  108. --- a/target/riscv/translate.c
  109. +++ b/target/riscv/translate.c
  110. @@ -666,6 +666,20 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
  111. tcg_gen_andi_tl(ret, ret, 1);
  112. }
  113. +static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
  114. +{
  115. + tcg_gen_not_tl(ret, arg1);
  116. + tcg_gen_shl_tl(ret, ret, arg2);
  117. + tcg_gen_not_tl(ret, ret);
  118. +}
  119. +
  120. +static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
  121. +{
  122. + tcg_gen_not_tl(ret, arg1);
  123. + tcg_gen_shr_tl(ret, ret, arg2);
  124. + tcg_gen_not_tl(ret, ret);
  125. +}
  126. +
  127. #ifdef TARGET_RISCV64
  128. static void gen_ctzw(TCGv ret, TCGv arg1)
  129. --
  130. 2.33.1