0093-target-riscv-rvb-single-bit-instructions.patch 6.5 KB

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  1. From b3036a6cb051f2d8e2ed8e7be056205034fbf88f Mon Sep 17 00:00:00 2001
  2. From: Kito Cheng <kito.cheng@sifive.com>
  3. Date: Mon, 11 Jan 2021 23:31:03 +0800
  4. Subject: [PATCH 093/107] target/riscv: rvb: single-bit instructions
  5. Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. ---
  9. target/riscv/insn32-64.decode | 8 +++
  10. target/riscv/insn32.decode | 9 +++
  11. target/riscv/insn_trans/trans_rvb.c.inc | 90 +++++++++++++++++++++++++
  12. target/riscv/translate.c | 61 +++++++++++++++++
  13. 4 files changed, 168 insertions(+)
  14. diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
  15. index 722af2d144..3543342fca 100644
  16. --- a/target/riscv/insn32-64.decode
  17. +++ b/target/riscv/insn32-64.decode
  18. @@ -100,3 +100,11 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
  19. packw 0000100 .......... 100 ..... 0111011 @r
  20. packuw 0100100 .......... 100 ..... 0111011 @r
  21. +bsetw 0010100 .......... 001 ..... 0111011 @r
  22. +bclrw 0100100 .......... 001 ..... 0111011 @r
  23. +binvw 0110100 .......... 001 ..... 0111011 @r
  24. +bextw 0100100 .......... 101 ..... 0111011 @r
  25. +
  26. +bsetiw 0010100 .......... 001 ..... 0011011 @sh5
  27. +bclriw 0100100 .......... 001 ..... 0011011 @sh5
  28. +binviw 0110100 .......... 001 ..... 0011011 @sh5
  29. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  30. index 531de51c63..14ffcc7afd 100644
  31. --- a/target/riscv/insn32.decode
  32. +++ b/target/riscv/insn32.decode
  33. @@ -707,3 +707,12 @@ min 0000101 .......... 100 ..... 0110011 @r
  34. minu 0000101 .......... 101 ..... 0110011 @r
  35. max 0000101 .......... 110 ..... 0110011 @r
  36. maxu 0000101 .......... 111 ..... 0110011 @r
  37. +bset 0010100 .......... 001 ..... 0110011 @r
  38. +bclr 0100100 .......... 001 ..... 0110011 @r
  39. +binv 0110100 .......... 001 ..... 0110011 @r
  40. +bext 0100100 .......... 101 ..... 0110011 @r
  41. +
  42. +bseti 00101. ........... 001 ..... 0010011 @sh
  43. +bclri 01001. ........... 001 ..... 0010011 @sh
  44. +binvi 01101. ........... 001 ..... 0010011 @sh
  45. +bexti 01001. ........... 101 ..... 0010011 @sh
  46. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  47. index 1496996a66..0c41f135dc 100644
  48. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  49. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  50. @@ -107,6 +107,54 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
  51. return gen_unary(ctx, a, tcg_gen_ext16s_tl);
  52. }
  53. +static bool trans_bset(DisasContext *ctx, arg_bset *a)
  54. +{
  55. + REQUIRE_EXT(ctx, RVB);
  56. + return gen_shift(ctx, a, gen_bset);
  57. +}
  58. +
  59. +static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
  60. +{
  61. + REQUIRE_EXT(ctx, RVB);
  62. + return gen_shifti(ctx, a, gen_bset);
  63. +}
  64. +
  65. +static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
  66. +{
  67. + REQUIRE_EXT(ctx, RVB);
  68. + return gen_shift(ctx, a, gen_bclr);
  69. +}
  70. +
  71. +static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
  72. +{
  73. + REQUIRE_EXT(ctx, RVB);
  74. + return gen_shifti(ctx, a, gen_bclr);
  75. +}
  76. +
  77. +static bool trans_binv(DisasContext *ctx, arg_binv *a)
  78. +{
  79. + REQUIRE_EXT(ctx, RVB);
  80. + return gen_shift(ctx, a, gen_binv);
  81. +}
  82. +
  83. +static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
  84. +{
  85. + REQUIRE_EXT(ctx, RVB);
  86. + return gen_shifti(ctx, a, gen_binv);
  87. +}
  88. +
  89. +static bool trans_bext(DisasContext *ctx, arg_bext *a)
  90. +{
  91. + REQUIRE_EXT(ctx, RVB);
  92. + return gen_shift(ctx, a, gen_bext);
  93. +}
  94. +
  95. +static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
  96. +{
  97. + REQUIRE_EXT(ctx, RVB);
  98. + return gen_shifti(ctx, a, gen_bext);
  99. +}
  100. +
  101. /* RV64-only instructions */
  102. #ifdef TARGET_RISCV64
  103. @@ -140,4 +188,46 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
  104. return gen_arith(ctx, a, gen_packuw);
  105. }
  106. +static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
  107. +{
  108. + REQUIRE_EXT(ctx, RVB);
  109. + return gen_shiftw(ctx, a, gen_bset);
  110. +}
  111. +
  112. +static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
  113. +{
  114. + REQUIRE_EXT(ctx, RVB);
  115. + return gen_shiftiw(ctx, a, gen_bset);
  116. +}
  117. +
  118. +static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
  119. +{
  120. + REQUIRE_EXT(ctx, RVB);
  121. + return gen_shiftw(ctx, a, gen_bclr);
  122. +}
  123. +
  124. +static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
  125. +{
  126. + REQUIRE_EXT(ctx, RVB);
  127. + return gen_shiftiw(ctx, a, gen_bclr);
  128. +}
  129. +
  130. +static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
  131. +{
  132. + REQUIRE_EXT(ctx, RVB);
  133. + return gen_shiftw(ctx, a, gen_binv);
  134. +}
  135. +
  136. +static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
  137. +{
  138. + REQUIRE_EXT(ctx, RVB);
  139. + return gen_shiftiw(ctx, a, gen_binv);
  140. +}
  141. +
  142. +static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
  143. +{
  144. + REQUIRE_EXT(ctx, RVB);
  145. + return gen_shiftw(ctx, a, gen_bext);
  146. +}
  147. +
  148. #endif
  149. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  150. index a6e50f77d4..5c70890333 100644
  151. --- a/target/riscv/translate.c
  152. +++ b/target/riscv/translate.c
  153. @@ -624,6 +624,48 @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
  154. tcg_temp_free(t);
  155. }
  156. +static void gen_sbop_mask(TCGv ret, TCGv shamt)
  157. +{
  158. + tcg_gen_movi_tl(ret, 1);
  159. + tcg_gen_shl_tl(ret, ret, shamt);
  160. +}
  161. +
  162. +static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
  163. +{
  164. + TCGv t = tcg_temp_new();
  165. +
  166. + gen_sbop_mask(t, shamt);
  167. + tcg_gen_or_tl(ret, arg1, t);
  168. +
  169. + tcg_temp_free(t);
  170. +}
  171. +
  172. +static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
  173. +{
  174. + TCGv t = tcg_temp_new();
  175. +
  176. + gen_sbop_mask(t, shamt);
  177. + tcg_gen_andc_tl(ret, arg1, t);
  178. +
  179. + tcg_temp_free(t);
  180. +}
  181. +
  182. +static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
  183. +{
  184. + TCGv t = tcg_temp_new();
  185. +
  186. + gen_sbop_mask(t, shamt);
  187. + tcg_gen_xor_tl(ret, arg1, t);
  188. +
  189. + tcg_temp_free(t);
  190. +}
  191. +
  192. +static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
  193. +{
  194. + tcg_gen_shr_tl(ret, arg1, shamt);
  195. + tcg_gen_andi_tl(ret, ret, 1);
  196. +}
  197. +
  198. #ifdef TARGET_RISCV64
  199. static void gen_ctzw(TCGv ret, TCGv arg1)
  200. @@ -732,6 +774,25 @@ static bool gen_shifti(DisasContext *ctx, arg_shift *a,
  201. #ifdef TARGET_RISCV64
  202. +static bool gen_shiftw(DisasContext *ctx, arg_r *a,
  203. + void(*func)(TCGv, TCGv, TCGv))
  204. +{
  205. + TCGv source1 = tcg_temp_new();
  206. + TCGv source2 = tcg_temp_new();
  207. +
  208. + gen_get_gpr(source1, a->rs1);
  209. + gen_get_gpr(source2, a->rs2);
  210. +
  211. + tcg_gen_andi_tl(source2, source2, 31);
  212. + (*func)(source1, source1, source2);
  213. + tcg_gen_ext32s_tl(source1, source1);
  214. +
  215. + gen_set_gpr(a->rd, source1);
  216. + tcg_temp_free(source1);
  217. + tcg_temp_free(source2);
  218. + return true;
  219. +}
  220. +
  221. static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
  222. void(*func)(TCGv, TCGv, TCGv))
  223. {
  224. --
  225. 2.33.1