0091-target-riscv-rvb-sign-extend-instructions.patch 1.8 KB

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  1. From 6a354df65631f859834b2ef5533501248996b2e7 Mon Sep 17 00:00:00 2001
  2. From: Kito Cheng <kito.cheng@sifive.com>
  3. Date: Tue, 20 Oct 2020 17:55:54 +0800
  4. Subject: [PATCH 091/107] target/riscv: rvb: sign-extend instructions
  5. Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
  6. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  7. ---
  8. target/riscv/insn32.decode | 2 ++
  9. target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
  10. 2 files changed, 14 insertions(+)
  11. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  12. index 0d951f7f1a..531de51c63 100644
  13. --- a/target/riscv/insn32.decode
  14. +++ b/target/riscv/insn32.decode
  15. @@ -694,6 +694,8 @@ fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
  16. clz 011000 000000 ..... 001 ..... 0010011 @r2
  17. ctz 011000 000001 ..... 001 ..... 0010011 @r2
  18. cpop 011000 000010 ..... 001 ..... 0010011 @r2
  19. +sext_b 011000 000100 ..... 001 ..... 0010011 @r2
  20. +sext_h 011000 000101 ..... 001 ..... 0010011 @r2
  21. andn 0100000 .......... 111 ..... 0110011 @r
  22. orn 0100000 .......... 110 ..... 0110011 @r
  23. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  24. index 2aa4515fe3..1496996a66 100644
  25. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  26. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  27. @@ -95,6 +95,18 @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
  28. return gen_arith(ctx, a, tcg_gen_umax_tl);
  29. }
  30. +static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
  31. +{
  32. + REQUIRE_EXT(ctx, RVB);
  33. + return gen_unary(ctx, a, tcg_gen_ext8s_tl);
  34. +}
  35. +
  36. +static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
  37. +{
  38. + REQUIRE_EXT(ctx, RVB);
  39. + return gen_unary(ctx, a, tcg_gen_ext16s_tl);
  40. +}
  41. +
  42. /* RV64-only instructions */
  43. #ifdef TARGET_RISCV64
  44. --
  45. 2.33.1