0090-target-riscv-rvb-min-max-instructions.patch 2.0 KB

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  1. From 216a6e190232aabac13eea58f9be63c44194ece1 Mon Sep 17 00:00:00 2001
  2. From: Kito Cheng <kito.cheng@sifive.com>
  3. Date: Tue, 20 Oct 2020 17:54:26 +0800
  4. Subject: [PATCH 090/107] target/riscv: rvb: min/max instructions
  5. Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
  6. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  7. ---
  8. target/riscv/insn32.decode | 4 ++++
  9. target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++++++++++++
  10. 2 files changed, 28 insertions(+)
  11. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  12. index 28ac42d196..0d951f7f1a 100644
  13. --- a/target/riscv/insn32.decode
  14. +++ b/target/riscv/insn32.decode
  15. @@ -701,3 +701,7 @@ xnor 0100000 .......... 100 ..... 0110011 @r
  16. pack 0000100 .......... 100 ..... 0110011 @r
  17. packu 0100100 .......... 100 ..... 0110011 @r
  18. packh 0000100 .......... 111 ..... 0110011 @r
  19. +min 0000101 .......... 100 ..... 0110011 @r
  20. +minu 0000101 .......... 101 ..... 0110011 @r
  21. +max 0000101 .......... 110 ..... 0110011 @r
  22. +maxu 0000101 .......... 111 ..... 0110011 @r
  23. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  24. index 2d24dafac0..2aa4515fe3 100644
  25. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  26. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  27. @@ -71,6 +71,30 @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
  28. return gen_arith(ctx, a, gen_packh);
  29. }
  30. +static bool trans_min(DisasContext *ctx, arg_min *a)
  31. +{
  32. + REQUIRE_EXT(ctx, RVB);
  33. + return gen_arith(ctx, a, tcg_gen_smin_tl);
  34. +}
  35. +
  36. +static bool trans_max(DisasContext *ctx, arg_max *a)
  37. +{
  38. + REQUIRE_EXT(ctx, RVB);
  39. + return gen_arith(ctx, a, tcg_gen_smax_tl);
  40. +}
  41. +
  42. +static bool trans_minu(DisasContext *ctx, arg_minu *a)
  43. +{
  44. + REQUIRE_EXT(ctx, RVB);
  45. + return gen_arith(ctx, a, tcg_gen_umin_tl);
  46. +}
  47. +
  48. +static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
  49. +{
  50. + REQUIRE_EXT(ctx, RVB);
  51. + return gen_arith(ctx, a, tcg_gen_umax_tl);
  52. +}
  53. +
  54. /* RV64-only instructions */
  55. #ifdef TARGET_RISCV64
  56. --
  57. 2.33.1