0089-target-riscv-rvb-pack-two-words-into-one-register.patch 4.4 KB

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  1. From 2da595ddcf9da58be57803e12ac69d419a1f1cd9 Mon Sep 17 00:00:00 2001
  2. From: Kito Cheng <kito.cheng@sifive.com>
  3. Date: Tue, 20 Oct 2020 17:52:50 +0800
  4. Subject: [PATCH 089/107] target/riscv: rvb: pack two words into one register
  5. Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. ---
  9. target/riscv/insn32-64.decode | 3 ++
  10. target/riscv/insn32.decode | 3 ++
  11. target/riscv/insn_trans/trans_rvb.c.inc | 30 +++++++++++++++++++
  12. target/riscv/translate.c | 40 +++++++++++++++++++++++++
  13. 4 files changed, 76 insertions(+)
  14. diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
  15. index e4344c0c29..722af2d144 100644
  16. --- a/target/riscv/insn32-64.decode
  17. +++ b/target/riscv/insn32-64.decode
  18. @@ -97,3 +97,6 @@ fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
  19. clzw 0110000 00000 ..... 001 ..... 0011011 @r2
  20. ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
  21. cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
  22. +
  23. +packw 0000100 .......... 100 ..... 0111011 @r
  24. +packuw 0100100 .......... 100 ..... 0111011 @r
  25. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  26. index 770978993d..28ac42d196 100644
  27. --- a/target/riscv/insn32.decode
  28. +++ b/target/riscv/insn32.decode
  29. @@ -698,3 +698,6 @@ cpop 011000 000010 ..... 001 ..... 0010011 @r2
  30. andn 0100000 .......... 111 ..... 0110011 @r
  31. orn 0100000 .......... 110 ..... 0110011 @r
  32. xnor 0100000 .......... 100 ..... 0110011 @r
  33. +pack 0000100 .......... 100 ..... 0110011 @r
  34. +packu 0100100 .......... 100 ..... 0110011 @r
  35. +packh 0000100 .......... 111 ..... 0110011 @r
  36. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  37. index 73c4693a26..2d24dafac0 100644
  38. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  39. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  40. @@ -53,6 +53,24 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
  41. return gen_arith(ctx, a, tcg_gen_eqv_tl);
  42. }
  43. +static bool trans_pack(DisasContext *ctx, arg_pack *a)
  44. +{
  45. + REQUIRE_EXT(ctx, RVB);
  46. + return gen_arith(ctx, a, gen_pack);
  47. +}
  48. +
  49. +static bool trans_packu(DisasContext *ctx, arg_packu *a)
  50. +{
  51. + REQUIRE_EXT(ctx, RVB);
  52. + return gen_arith(ctx, a, gen_packu);
  53. +}
  54. +
  55. +static bool trans_packh(DisasContext *ctx, arg_packh *a)
  56. +{
  57. + REQUIRE_EXT(ctx, RVB);
  58. + return gen_arith(ctx, a, gen_packh);
  59. +}
  60. +
  61. /* RV64-only instructions */
  62. #ifdef TARGET_RISCV64
  63. @@ -74,4 +92,16 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
  64. return gen_unary(ctx, a, gen_cpopw);
  65. }
  66. +static bool trans_packw(DisasContext *ctx, arg_packw *a)
  67. +{
  68. + REQUIRE_EXT(ctx, RVB);
  69. + return gen_arith(ctx, a, gen_packw);
  70. +}
  71. +
  72. +static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
  73. +{
  74. + REQUIRE_EXT(ctx, RVB);
  75. + return gen_arith(ctx, a, gen_packuw);
  76. +}
  77. +
  78. #endif
  79. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  80. index aaef43c0e6..0152deef67 100644
  81. --- a/target/riscv/translate.c
  82. +++ b/target/riscv/translate.c
  83. @@ -601,6 +601,29 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
  84. #endif
  85. +static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
  86. +{
  87. + tcg_gen_deposit_tl(ret, arg1, arg2,
  88. + TARGET_LONG_BITS / 2,
  89. + TARGET_LONG_BITS / 2);
  90. +}
  91. +
  92. +static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
  93. +{
  94. + TCGv t = tcg_temp_new();
  95. + tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
  96. + tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
  97. + tcg_temp_free(t);
  98. +}
  99. +
  100. +static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
  101. +{
  102. + TCGv t = tcg_temp_new();
  103. + tcg_gen_ext8u_tl(t, arg2);
  104. + tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
  105. + tcg_temp_free(t);
  106. +}
  107. +
  108. #ifdef TARGET_RISCV64
  109. static void gen_ctzw(TCGv ret, TCGv arg1)
  110. @@ -622,6 +645,23 @@ static void gen_cpopw(TCGv ret, TCGv arg1)
  111. tcg_gen_ctpop_tl(ret, arg1);
  112. }
  113. +static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
  114. +{
  115. + TCGv t = tcg_temp_new();
  116. + tcg_gen_ext16s_i64(t, arg2);
  117. + tcg_gen_deposit_i64(ret, arg1, t, 16, 48);
  118. + tcg_temp_free(t);
  119. +}
  120. +
  121. +static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
  122. +{
  123. + TCGv t = tcg_temp_new();
  124. + tcg_gen_shri_i64(t, arg1, 16);
  125. + tcg_gen_deposit_i64(ret, arg2, t, 0, 16);
  126. + tcg_gen_ext32s_i64(ret, ret);
  127. + tcg_temp_free(t);
  128. +}
  129. +
  130. #endif
  131. static bool gen_arith(DisasContext *ctx, arg_r *a,
  132. --
  133. 2.33.1