0088-target-riscv-rvb-logic-with-negate.patch 1.9 KB

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  1. From 7c35ae0d4d1ca24009c00e4c2dfbe87a68baeef8 Mon Sep 17 00:00:00 2001
  2. From: Kito Cheng <kito.cheng@sifive.com>
  3. Date: Tue, 20 Oct 2020 17:48:49 +0800
  4. Subject: [PATCH 088/107] target/riscv: rvb: logic-with-negate
  5. Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. ---
  9. target/riscv/insn32.decode | 4 ++++
  10. target/riscv/insn_trans/trans_rvb.c.inc | 18 ++++++++++++++++++
  11. 2 files changed, 22 insertions(+)
  12. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  13. index 2d02cf5234..770978993d 100644
  14. --- a/target/riscv/insn32.decode
  15. +++ b/target/riscv/insn32.decode
  16. @@ -694,3 +694,7 @@ fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
  17. clz 011000 000000 ..... 001 ..... 0010011 @r2
  18. ctz 011000 000001 ..... 001 ..... 0010011 @r2
  19. cpop 011000 000010 ..... 001 ..... 0010011 @r2
  20. +
  21. +andn 0100000 .......... 111 ..... 0110011 @r
  22. +orn 0100000 .......... 110 ..... 0110011 @r
  23. +xnor 0100000 .......... 100 ..... 0110011 @r
  24. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  25. index dbbd94e101..73c4693a26 100644
  26. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  27. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  28. @@ -35,6 +35,24 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
  29. return gen_unary(ctx, a, tcg_gen_ctpop_tl);
  30. }
  31. +static bool trans_andn(DisasContext *ctx, arg_andn *a)
  32. +{
  33. + REQUIRE_EXT(ctx, RVB);
  34. + return gen_arith(ctx, a, tcg_gen_andc_tl);
  35. +}
  36. +
  37. +static bool trans_orn(DisasContext *ctx, arg_orn *a)
  38. +{
  39. + REQUIRE_EXT(ctx, RVB);
  40. + return gen_arith(ctx, a, tcg_gen_orc_tl);
  41. +}
  42. +
  43. +static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
  44. +{
  45. + REQUIRE_EXT(ctx, RVB);
  46. + return gen_arith(ctx, a, tcg_gen_eqv_tl);
  47. +}
  48. +
  49. /* RV64-only instructions */
  50. #ifdef TARGET_RISCV64
  51. --
  52. 2.33.1