0087-target-riscv-rvb-count-bits-set.patch 2.7 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980
  1. From 515cc3cc26a1f070f3a7c7f73a010f23f3b9f3f7 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Wed, 2 Dec 2020 03:36:16 +0800
  4. Subject: [PATCH 087/107] target/riscv: rvb: count bits set
  5. Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
  6. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  7. ---
  8. target/riscv/insn32-64.decode | 1 +
  9. target/riscv/insn32.decode | 1 +
  10. target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
  11. target/riscv/translate.c | 6 ++++++
  12. 4 files changed, 20 insertions(+)
  13. diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
  14. index 68ad4cee16..e4344c0c29 100644
  15. --- a/target/riscv/insn32-64.decode
  16. +++ b/target/riscv/insn32-64.decode
  17. @@ -96,3 +96,4 @@ fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
  18. # *** RV64B Standard Extension (in addition to RV32B) ***
  19. clzw 0110000 00000 ..... 001 ..... 0011011 @r2
  20. ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
  21. +cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
  22. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  23. index 58385becfe..2d02cf5234 100644
  24. --- a/target/riscv/insn32.decode
  25. +++ b/target/riscv/insn32.decode
  26. @@ -693,3 +693,4 @@ fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
  27. # *** RV32B Standard Extension ***
  28. clz 011000 000000 ..... 001 ..... 0010011 @r2
  29. ctz 011000 000001 ..... 001 ..... 0010011 @r2
  30. +cpop 011000 000010 ..... 001 ..... 0010011 @r2
  31. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  32. index 76788c2f35..dbbd94e101 100644
  33. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  34. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  35. @@ -29,6 +29,12 @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
  36. return gen_unary(ctx, a, gen_ctz);
  37. }
  38. +static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
  39. +{
  40. + REQUIRE_EXT(ctx, RVB);
  41. + return gen_unary(ctx, a, tcg_gen_ctpop_tl);
  42. +}
  43. +
  44. /* RV64-only instructions */
  45. #ifdef TARGET_RISCV64
  46. @@ -44,4 +50,10 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
  47. return gen_unary(ctx, a, gen_ctzw);
  48. }
  49. +static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
  50. +{
  51. + REQUIRE_EXT(ctx, RVB);
  52. + return gen_unary(ctx, a, gen_cpopw);
  53. +}
  54. +
  55. #endif
  56. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  57. index 4f33bfbfd1..aaef43c0e6 100644
  58. --- a/target/riscv/translate.c
  59. +++ b/target/riscv/translate.c
  60. @@ -616,6 +616,12 @@ static void gen_clzw(TCGv ret, TCGv arg1)
  61. tcg_gen_subi_i64(ret, ret, 32);
  62. }
  63. +static void gen_cpopw(TCGv ret, TCGv arg1)
  64. +{
  65. + tcg_gen_ext32u_tl(arg1, arg1);
  66. + tcg_gen_ctpop_tl(ret, arg1);
  67. +}
  68. +
  69. #endif
  70. static bool gen_arith(DisasContext *ctx, arg_r *a,
  71. --
  72. 2.33.1