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- From 515cc3cc26a1f070f3a7c7f73a010f23f3b9f3f7 Mon Sep 17 00:00:00 2001
- From: Frank Chang <frank.chang@sifive.com>
- Date: Wed, 2 Dec 2020 03:36:16 +0800
- Subject: [PATCH 087/107] target/riscv: rvb: count bits set
- Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
- Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
- ---
- target/riscv/insn32-64.decode | 1 +
- target/riscv/insn32.decode | 1 +
- target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
- target/riscv/translate.c | 6 ++++++
- 4 files changed, 20 insertions(+)
- diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
- index 68ad4cee16..e4344c0c29 100644
- --- a/target/riscv/insn32-64.decode
- +++ b/target/riscv/insn32-64.decode
- @@ -96,3 +96,4 @@ fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
- # *** RV64B Standard Extension (in addition to RV32B) ***
- clzw 0110000 00000 ..... 001 ..... 0011011 @r2
- ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
- +cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
- diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
- index 58385becfe..2d02cf5234 100644
- --- a/target/riscv/insn32.decode
- +++ b/target/riscv/insn32.decode
- @@ -693,3 +693,4 @@ fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
- # *** RV32B Standard Extension ***
- clz 011000 000000 ..... 001 ..... 0010011 @r2
- ctz 011000 000001 ..... 001 ..... 0010011 @r2
- +cpop 011000 000010 ..... 001 ..... 0010011 @r2
- diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
- index 76788c2f35..dbbd94e101 100644
- --- a/target/riscv/insn_trans/trans_rvb.c.inc
- +++ b/target/riscv/insn_trans/trans_rvb.c.inc
- @@ -29,6 +29,12 @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
- return gen_unary(ctx, a, gen_ctz);
- }
-
- +static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
- +{
- + REQUIRE_EXT(ctx, RVB);
- + return gen_unary(ctx, a, tcg_gen_ctpop_tl);
- +}
- +
- /* RV64-only instructions */
- #ifdef TARGET_RISCV64
-
- @@ -44,4 +50,10 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
- return gen_unary(ctx, a, gen_ctzw);
- }
-
- +static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
- +{
- + REQUIRE_EXT(ctx, RVB);
- + return gen_unary(ctx, a, gen_cpopw);
- +}
- +
- #endif
- diff --git a/target/riscv/translate.c b/target/riscv/translate.c
- index 4f33bfbfd1..aaef43c0e6 100644
- --- a/target/riscv/translate.c
- +++ b/target/riscv/translate.c
- @@ -616,6 +616,12 @@ static void gen_clzw(TCGv ret, TCGv arg1)
- tcg_gen_subi_i64(ret, ret, 32);
- }
-
- +static void gen_cpopw(TCGv ret, TCGv arg1)
- +{
- + tcg_gen_ext32u_tl(arg1, arg1);
- + tcg_gen_ctpop_tl(ret, arg1);
- +}
- +
- #endif
-
- static bool gen_arith(DisasContext *ctx, arg_r *a,
- --
- 2.33.1
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