0086-target-riscv-rvb-count-leading-trailing-zeros.patch 5.9 KB

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  1. From 8c7eb5e999228976b3a70f62b2a30e6e78b75d5f Mon Sep 17 00:00:00 2001
  2. From: Kito Cheng <kito.cheng@sifive.com>
  3. Date: Tue, 20 Oct 2020 16:54:22 +0800
  4. Subject: [PATCH 086/107] target/riscv: rvb: count leading/trailing zeros
  5. Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. ---
  9. target/riscv/insn32-64.decode | 4 +++
  10. target/riscv/insn32.decode | 7 +++-
  11. target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++++++++++++++++++++
  12. target/riscv/translate.c | 42 ++++++++++++++++++++++
  13. 4 files changed, 99 insertions(+), 1 deletion(-)
  14. create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
  15. diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
  16. index bf39c5064f..68ad4cee16 100644
  17. --- a/target/riscv/insn32-64.decode
  18. +++ b/target/riscv/insn32-64.decode
  19. @@ -92,3 +92,7 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
  20. fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
  21. fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
  22. fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
  23. +
  24. +# *** RV64B Standard Extension (in addition to RV32B) ***
  25. +clzw 0110000 00000 ..... 001 ..... 0011011 @r2
  26. +ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
  27. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  28. index eb4c75ad1f..58385becfe 100644
  29. --- a/target/riscv/insn32.decode
  30. +++ b/target/riscv/insn32.decode
  31. @@ -40,6 +40,7 @@
  32. &i imm rs1 rd
  33. &j imm rd
  34. &r rd rs1 rs2
  35. +&r2 rd rs1
  36. &s imm rs1 rs2
  37. &u imm rd
  38. &shift shamt rs1 rd
  39. @@ -67,7 +68,7 @@
  40. @r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
  41. @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
  42. @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
  43. -@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
  44. +@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
  45. @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
  46. @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
  47. @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
  48. @@ -688,3 +689,7 @@ fclass_h 1110010 00000 ..... 001 ..... 1010011 @r2
  49. fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm
  50. fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm
  51. fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
  52. +
  53. +# *** RV32B Standard Extension ***
  54. +clz 011000 000000 ..... 001 ..... 0010011 @r2
  55. +ctz 011000 000001 ..... 001 ..... 0010011 @r2
  56. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  57. new file mode 100644
  58. index 0000000000..76788c2f35
  59. --- /dev/null
  60. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  61. @@ -0,0 +1,47 @@
  62. +/*
  63. + * RISC-V translation routines for the RVB Standard Extension.
  64. + *
  65. + * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
  66. + * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
  67. + *
  68. + * This program is free software; you can redistribute it and/or modify it
  69. + * under the terms and conditions of the GNU General Public License,
  70. + * version 2 or later, as published by the Free Software Foundation.
  71. + *
  72. + * This program is distributed in the hope it will be useful, but WITHOUT
  73. + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  74. + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  75. + * more details.
  76. + *
  77. + * You should have received a copy of the GNU General Public License along with
  78. + * this program. If not, see <http://www.gnu.org/licenses/>.
  79. + */
  80. +
  81. +static bool trans_clz(DisasContext *ctx, arg_clz *a)
  82. +{
  83. + REQUIRE_EXT(ctx, RVB);
  84. + return gen_unary(ctx, a, gen_clz);
  85. +}
  86. +
  87. +static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
  88. +{
  89. + REQUIRE_EXT(ctx, RVB);
  90. + return gen_unary(ctx, a, gen_ctz);
  91. +}
  92. +
  93. +/* RV64-only instructions */
  94. +#ifdef TARGET_RISCV64
  95. +
  96. +static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
  97. +{
  98. + REQUIRE_EXT(ctx, RVB);
  99. + return gen_unary(ctx, a, gen_clzw);
  100. +}
  101. +
  102. +static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
  103. +{
  104. + REQUIRE_EXT(ctx, RVB);
  105. + return gen_unary(ctx, a, gen_ctzw);
  106. +}
  107. +
  108. +#endif
  109. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  110. index 15305a3096..4f33bfbfd1 100644
  111. --- a/target/riscv/translate.c
  112. +++ b/target/riscv/translate.c
  113. @@ -601,6 +601,23 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
  114. #endif
  115. +#ifdef TARGET_RISCV64
  116. +
  117. +static void gen_ctzw(TCGv ret, TCGv arg1)
  118. +{
  119. + tcg_gen_ori_i64(ret, arg1, MAKE_64BIT_MASK(32, 32));
  120. + tcg_gen_ctzi_i64(ret, ret, 64);
  121. +}
  122. +
  123. +static void gen_clzw(TCGv ret, TCGv arg1)
  124. +{
  125. + tcg_gen_ext32u_i64(ret, arg1);
  126. + tcg_gen_clzi_i64(ret, ret, 64);
  127. + tcg_gen_subi_i64(ret, ret, 32);
  128. +}
  129. +
  130. +#endif
  131. +
  132. static bool gen_arith(DisasContext *ctx, arg_r *a,
  133. void(*func)(TCGv, TCGv, TCGv))
  134. {
  135. @@ -646,6 +663,30 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
  136. return cpu_ldl_code(env, pc);
  137. }
  138. +static void gen_ctz(TCGv ret, TCGv arg1)
  139. +{
  140. + tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
  141. +}
  142. +
  143. +static void gen_clz(TCGv ret, TCGv arg1)
  144. +{
  145. + tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
  146. +}
  147. +
  148. +static bool gen_unary(DisasContext *ctx, arg_r2 *a,
  149. + void(*func)(TCGv, TCGv))
  150. +{
  151. + TCGv source = tcg_temp_new();
  152. +
  153. + gen_get_gpr(source, a->rs1);
  154. +
  155. + (*func)(source, source);
  156. +
  157. + gen_set_gpr(a->rd, source);
  158. + tcg_temp_free(source);
  159. + return true;
  160. +}
  161. +
  162. /* Include insn module translation function */
  163. #include "insn_trans/trans_rvi.c.inc"
  164. #include "insn_trans/trans_rvm.c.inc"
  165. @@ -654,6 +695,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
  166. #include "insn_trans/trans_rvd.c.inc"
  167. #include "insn_trans/trans_rvh.c.inc"
  168. #include "insn_trans/trans_rvv.c.inc"
  169. +#include "insn_trans/trans_rvb.c.inc"
  170. #include "insn_trans/trans_rvzfh.c.inc"
  171. #include "insn_trans/trans_privileged.c.inc"
  172. --
  173. 2.33.1