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- From deceb2c6b3ba82c259c57bda1226e0ac6cbb2757 Mon Sep 17 00:00:00 2001
- From: Frank Chang <frank.chang@sifive.com>
- Date: Mon, 17 Aug 2020 16:11:32 +0800
- Subject: [PATCH 084/107] target/riscv: rvv-1.0: patch floating-point reduction
- instructions
- In SiFive's RTL implementation:
- * vfredosum: Pass through the original NaN and set no exception flags
- if no elements are active and the scalar input is NaN.
- * vfredsum: Canonicalize the NaN and, if the NaN is signaling, set the
- invalid exception flag.
- Same principles are also applied to vfwredosum and vfwredsum
- instructions.
- Signed-off-by: Frank Chang <frank.chang@sifive.com>
- ---
- target/riscv/helper.h | 5 +
- target/riscv/insn32.decode | 6 +-
- target/riscv/insn_trans/trans_rvv.c.inc | 2 +
- target/riscv/vector_helper.c | 190 ++++++++++++++++++++----
- 4 files changed, 171 insertions(+), 32 deletions(-)
- diff --git a/target/riscv/helper.h b/target/riscv/helper.h
- index f085f2fbb5..38721ea5ee 100644
- --- a/target/riscv/helper.h
- +++ b/target/riscv/helper.h
- @@ -1079,6 +1079,9 @@ DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
- DEF_HELPER_6(vfredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
- DEF_HELPER_6(vfredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
- DEF_HELPER_6(vfredsum_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
- +DEF_HELPER_6(vfredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
- +DEF_HELPER_6(vfredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
- +DEF_HELPER_6(vfredosum_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
- DEF_HELPER_6(vfredmax_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
- DEF_HELPER_6(vfredmax_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
- DEF_HELPER_6(vfredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
- @@ -1088,6 +1091,8 @@ DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
-
- DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
- DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
- +DEF_HELPER_6(vfwredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
- +DEF_HELPER_6(vfwredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
-
- DEF_HELPER_6(vmand_mm, void, ptr, ptr, ptr, ptr, env, i32)
- DEF_HELPER_6(vmnand_mm, void, ptr, ptr, ptr, ptr, env, i32)
- diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
- index 12fbad1b6b..83cd63f831 100644
- --- a/target/riscv/insn32.decode
- +++ b/target/riscv/insn32.decode
- @@ -603,11 +603,13 @@ vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm
- vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm
- vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm
- # Vector ordered and unordered reduction sum
- -vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm
- +vfredsum_vs 000001 . ..... ..... 001 ..... 1010111 @r_vm
- +vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm
- vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
- vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
- # Vector widening ordered and unordered float reduction sum
- -vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm
- +vfwredsum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm
- +vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm
- vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r
- vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r
- vmandnot_mm 011000 - ..... ..... 010 ..... 1010111 @r
- diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
- index c7ef4fa0ac..84e81ffa4d 100644
- --- a/target/riscv/insn_trans/trans_rvv.c.inc
- +++ b/target/riscv/insn_trans/trans_rvv.c.inc
- @@ -3051,6 +3051,7 @@ static bool freduction_check(DisasContext *s, arg_rmrr *a)
- }
-
- GEN_OPFVV_TRANS(vfredsum_vs, freduction_check)
- +GEN_OPFVV_TRANS(vfredosum_vs, freduction_check)
- GEN_OPFVV_TRANS(vfredmax_vs, freduction_check)
- GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
-
- @@ -3063,6 +3064,7 @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
- }
-
- GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, freduction_widen_check)
- +GEN_OPFVV_WIDEN_TRANS(vfwredosum_vs, freduction_widen_check)
-
- /*
- *** Vector Mask Operations
- diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
- index aca8e63023..a77e315045 100644
- --- a/target/riscv/vector_helper.c
- +++ b/target/riscv/vector_helper.c
- @@ -4597,43 +4597,155 @@ GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD)
- GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD)
-
- /* Vector Single-Width Floating-Point Reduction Instructions */
- -#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP) \
- -void HELPER(NAME)(void *vd, void *v0, void *vs1, \
- - void *vs2, CPURISCVState *env, \
- - uint32_t desc) \
- -{ \
- - uint32_t vm = vext_vm(desc); \
- - uint32_t vl = env->vl; \
- - uint32_t i; \
- - TD s1 = *((TD *)vs1 + HD(0)); \
- - \
- - for (i = env->vstart; i < vl; i++) { \
- - TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
- - if (!vm && !vext_elem_mask(v0, i)) { \
- - continue; \
- - } \
- - s1 = OP(s1, (TD)s2, &env->fp_status); \
- - } \
- - *((TD *)vd + HD(0)) = s1; \
- - env->vstart = 0; \
- +/*
- + * If f is NaN, return SEW-bit canonical NaN.
- + * Set the invalid exception flag if f is a sNaN.
- + */
- +static uint64_t propagate_nan(uint64_t f, uint32_t sew, float_status *s)
- +{
- + target_ulong ret;
- +
- + switch (sew) {
- + case 16:
- + ret = fclass_h(f);
- + /* check if f is NaN */
- + if (ret & 0x300) {
- + /* check if f is a sNaN */
- + if (ret & 0x100) {
- + s->float_exception_flags |= float_flag_invalid;
- + }
- + /* return canonical NaN */
- + return float16_default_nan(s);
- + } else {
- + return f;
- + }
- + break;
- + case 32:
- + ret = fclass_s(f);
- + /* check if f is NaN */
- + if (ret & 0x300) {
- + /* check if f is a sNaN */
- + if (ret & 0x100) {
- + s->float_exception_flags |= float_flag_invalid;
- + }
- + /* return canonical NaN */
- + return float32_default_nan(s);
- + } else {
- + return f;
- + }
- + break;
- + case 64:
- + ret = fclass_d(f);
- + /* check if f is NaN */
- + if (ret & 0x300) {
- + /* check if f is a sNaN */
- + if (ret & 0x100) {
- + s->float_exception_flags |= float_flag_invalid;
- + }
- + /* return canonical NaN */
- + return float64_default_nan(s);
- + } else {
- + return f;
- + }
- + break;
- + default:
- + g_assert_not_reached();
- + }
- +}
- +
- +#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, PROPAGATE_NAN, OP) \
- +void HELPER(NAME)(void *vd, void *v0, void *vs1, \
- + void *vs2, CPURISCVState *env, \
- + uint32_t desc) \
- +{ \
- + uint32_t vm = vext_vm(desc); \
- + uint32_t vl = env->vl; \
- + uint32_t i; \
- + bool active = false; \
- + TD s1 = *((TD *)vs1 + HD(0)); \
- + \
- + for (i = env->vstart; i < vl; i++) { \
- + TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
- + if (!vm && !vext_elem_mask(v0, i)) { \
- + continue; \
- + } \
- + active = true; \
- + s1 = OP(s1, (TD)s2, &env->fp_status); \
- + } \
- + \
- + if (vl > 0) { \
- + if (PROPAGATE_NAN && !active) { \
- + *((TD *)vd + HD(0)) = propagate_nan(s1, sizeof(TD) * 8, \
- + &env->fp_status); \
- + } else { \
- + *((TD *)vd + HD(0)) = s1; \
- + } \
- + } \
- + env->vstart = 0; \
- }
-
- +/* Ordered sum */
- +GEN_VEXT_FRED(vfredosum_vs_h, uint16_t, uint16_t, H2, H2, false, float16_add)
- +GEN_VEXT_FRED(vfredosum_vs_w, uint32_t, uint32_t, H4, H4, false, float32_add)
- +GEN_VEXT_FRED(vfredosum_vs_d, uint64_t, uint64_t, H8, H8, false, float64_add)
- +
- /* Unordered sum */
- -GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add)
- -GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add)
- -GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add)
- +GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, true, float16_add)
- +GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, true, float32_add)
- +GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, true, float64_add)
-
- /* Maximum value */
- -GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum_noprop)
- -GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum_noprop)
- -GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum_noprop)
- +GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, false, float16_maxnum_noprop)
- +GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, false, float32_maxnum_noprop)
- +GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, false, float64_maxnum_noprop)
-
- /* Minimum value */
- -GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum_noprop)
- -GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum_noprop)
- -GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum_noprop)
- +GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, false, float16_minnum_noprop)
- +GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, false, float32_minnum_noprop)
- +GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, false, float64_minnum_noprop)
-
- /* Vector Widening Floating-Point Reduction Instructions */
- +/* Ordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
- +void HELPER(vfwredosum_vs_h)(void *vd, void *v0, void *vs1,
- + void *vs2, CPURISCVState *env, uint32_t desc)
- +{
- + uint32_t vm = vext_vm(desc);
- + uint32_t vl = env->vl;
- + uint32_t i;
- + uint32_t s1 = *((uint32_t *)vs1 + H4(0));
- +
- + for (i = env->vstart; i < vl; i++) {
- + uint16_t s2 = *((uint16_t *)vs2 + H2(i));
- + if (!vm && !vext_elem_mask(v0, i)) {
- + continue;
- + }
- + s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status),
- + &env->fp_status);
- + }
- + *((uint32_t *)vd + H4(0)) = s1;
- + env->vstart = 0;
- +}
- +
- +void HELPER(vfwredosum_vs_w)(void *vd, void *v0, void *vs1,
- + void *vs2, CPURISCVState *env, uint32_t desc)
- +{
- + uint32_t vm = vext_vm(desc);
- + uint32_t vl = env->vl;
- + uint32_t i;
- + uint64_t s1 = *((uint64_t *)vs1);
- +
- + for (i = env->vstart; i < vl; i++) {
- + uint32_t s2 = *((uint32_t *)vs2 + H4(i));
- + if (!vm && !vext_elem_mask(v0, i)) {
- + continue;
- + }
- + s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status),
- + &env->fp_status);
- + }
- + *((uint64_t *)vd) = s1;
- + env->vstart = 0;
- +}
- +
- /* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
- void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
- void *vs2, CPURISCVState *env, uint32_t desc)
- @@ -4642,16 +4754,25 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
- uint32_t vl = env->vl;
- uint32_t i;
- uint32_t s1 = *((uint32_t *)vs1 + H4(0));
- + bool active = false;
-
- for (i = env->vstart; i < vl; i++) {
- uint16_t s2 = *((uint16_t *)vs2 + H2(i));
- if (!vm && !vext_elem_mask(v0, i)) {
- continue;
- }
- + active = true;
- s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status),
- &env->fp_status);
- }
- - *((uint32_t *)vd + H4(0)) = s1;
- +
- + if (vl > 0) {
- + if (!active) {
- + *((uint32_t *)vd + H4(0)) = propagate_nan(s1, 32, &env->fp_status);
- + } else {
- + *((uint32_t *)vd + H4(0)) = s1;
- + }
- + }
- env->vstart = 0;
- }
-
- @@ -4662,16 +4783,25 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
- uint32_t vl = env->vl;
- uint32_t i;
- uint64_t s1 = *((uint64_t *)vs1);
- + bool active = false;
-
- for (i = env->vstart; i < vl; i++) {
- uint32_t s2 = *((uint32_t *)vs2 + H4(i));
- if (!vm && !vext_elem_mask(v0, i)) {
- continue;
- }
- + active = true;
- s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status),
- &env->fp_status);
- }
- - *((uint64_t *)vd) = s1;
- +
- + if (vl > 0) {
- + if (!active) {
- + *((uint64_t *)vd) = propagate_nan(s1, 64, &env->fp_status);
- + } else {
- + *((uint64_t *)vd) = s1;
- + }
- + }
- env->vstart = 0;
- }
-
- --
- 2.33.1
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