0083-target-riscv-rvv-1.0-add-vector-unit-stride-mask-loa.patch 4.5 KB

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  1. From 859e2c447049371276adb2af8c0724e5f0eaceb9 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Wed, 24 Feb 2021 16:16:12 +0800
  4. Subject: [PATCH 083/107] target/riscv: rvv-1.0: add vector unit-stride mask
  5. load/store insns
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. ---
  8. target/riscv/helper.h | 2 ++
  9. target/riscv/insn32.decode | 4 +++
  10. target/riscv/insn_trans/trans_rvv.c.inc | 40 +++++++++++++++++++++++++
  11. target/riscv/vector_helper.c | 21 +++++++++++++
  12. 4 files changed, 67 insertions(+)
  13. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  14. index a83a7c33c0..f085f2fbb5 100644
  15. --- a/target/riscv/helper.h
  16. +++ b/target/riscv/helper.h
  17. @@ -130,6 +130,8 @@ DEF_HELPER_5(vse8_v_mask, void, ptr, ptr, tl, env, i32)
  18. DEF_HELPER_5(vse16_v_mask, void, ptr, ptr, tl, env, i32)
  19. DEF_HELPER_5(vse32_v_mask, void, ptr, ptr, tl, env, i32)
  20. DEF_HELPER_5(vse64_v_mask, void, ptr, ptr, tl, env, i32)
  21. +DEF_HELPER_5(vlm_v, void, ptr, ptr, tl, env, i32)
  22. +DEF_HELPER_5(vsm_v, void, ptr, ptr, tl, env, i32)
  23. DEF_HELPER_6(vlse8_v, void, ptr, ptr, tl, tl, env, i32)
  24. DEF_HELPER_6(vlse16_v, void, ptr, ptr, tl, tl, env, i32)
  25. DEF_HELPER_6(vlse32_v, void, ptr, ptr, tl, tl, env, i32)
  26. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  27. index f6eec02d55..12fbad1b6b 100644
  28. --- a/target/riscv/insn32.decode
  29. +++ b/target/riscv/insn32.decode
  30. @@ -251,6 +251,10 @@ vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
  31. vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
  32. vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
  33. +# Vector unit-stride mask load/store insns.
  34. +vlm_v 000 000 1 01011 ..... 000 ..... 0000111 @r2
  35. +vsm_v 000 000 1 01011 ..... 000 ..... 0100111 @r2
  36. +
  37. # Vector strided insns.
  38. vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
  39. vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
  40. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  41. index 49f2eeee47..c7ef4fa0ac 100644
  42. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  43. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  44. @@ -747,6 +747,46 @@ GEN_VEXT_TRANS(vse16_v, MO_16, r2nfvm, st_us_op, st_us_check)
  45. GEN_VEXT_TRANS(vse32_v, MO_32, r2nfvm, st_us_op, st_us_check)
  46. GEN_VEXT_TRANS(vse64_v, MO_64, r2nfvm, st_us_op, st_us_check)
  47. +/*
  48. + *** unit stride mask load and store
  49. + */
  50. +static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a, uint8_t eew)
  51. +{
  52. + uint32_t data = 0;
  53. + gen_helper_ldst_us *fn = gen_helper_vlm_v;
  54. +
  55. + /* EMUL = 1, NFIELDS = 1 */
  56. + data = FIELD_DP32(data, VDATA, LMUL, 0);
  57. + data = FIELD_DP32(data, VDATA, NF, 1);
  58. + return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
  59. +}
  60. +
  61. +static bool ld_us_mask_check(DisasContext *s, arg_vlm_v *a, uint8_t eew)
  62. +{
  63. + /* EMUL = 1, NFIELDS = 1 */
  64. + return require_rvv(s) && vext_check_isa_ill(s);
  65. +}
  66. +
  67. +static bool st_us_mask_op(DisasContext *s, arg_vsm_v *a, uint8_t eew)
  68. +{
  69. + uint32_t data = 0;
  70. + gen_helper_ldst_us *fn = gen_helper_vsm_v;
  71. +
  72. + /* EMUL = 1, NFIELDS = 1 */
  73. + data = FIELD_DP32(data, VDATA, LMUL, 0);
  74. + data = FIELD_DP32(data, VDATA, NF, 1);
  75. + return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
  76. +}
  77. +
  78. +static bool st_us_mask_check(DisasContext *s, arg_vsm_v *a, uint8_t eew)
  79. +{
  80. + /* EMUL = 1, NFIELDS = 1 */
  81. + return require_rvv(s) && vext_check_isa_ill(s);
  82. +}
  83. +
  84. +GEN_VEXT_TRANS(vlm_v, MO_8, vlm_v, ld_us_mask_op, ld_us_mask_check)
  85. +GEN_VEXT_TRANS(vsm_v, MO_8, vsm_v, st_us_mask_op, st_us_mask_check)
  86. +
  87. /*
  88. *** stride load and store
  89. */
  90. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  91. index 0e0b392a27..aca8e63023 100644
  92. --- a/target/riscv/vector_helper.c
  93. +++ b/target/riscv/vector_helper.c
  94. @@ -361,6 +361,27 @@ GEN_VEXT_ST_US(vse16_v, int16_t, ste_h)
  95. GEN_VEXT_ST_US(vse32_v, int32_t, ste_w)
  96. GEN_VEXT_ST_US(vse64_v, int64_t, ste_d)
  97. +/*
  98. + *** unit stride mask load and store, EEW = 1
  99. + */
  100. +void HELPER(vlm_v)(void *vd, void *v0, target_ulong base,
  101. + CPURISCVState *env, uint32_t desc)
  102. +{
  103. + /* evl = ceil(vl/8) */
  104. + uint8_t evl = (env->vl + 7) >> 3;
  105. + vext_ldst_us(vd, base, env, desc, lde_b,
  106. + 0, evl, GETPC(), MMU_DATA_LOAD);
  107. +}
  108. +
  109. +void HELPER(vsm_v)(void *vd, void *v0, target_ulong base,
  110. + CPURISCVState *env, uint32_t desc)
  111. +{
  112. + /* evl = ceil(vl/8) */
  113. + uint8_t evl = (env->vl + 7) >> 3;
  114. + vext_ldst_us(vd, base, env, desc, ste_b,
  115. + 0, evl, GETPC(), MMU_DATA_STORE);
  116. +}
  117. +
  118. /*
  119. *** index: access vector element from indexed memory
  120. */
  121. --
  122. 2.33.1