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- From 2be237127e46c352e487c55800b779c694089aa8 Mon Sep 17 00:00:00 2001
- From: Frank Chang <frank.chang@sifive.com>
- Date: Thu, 19 Nov 2020 14:40:08 +0800
- Subject: [PATCH 078/107] target/riscv: rvv-1.0: floating-point reciprocal
- estimate instruction
- Implement the floating-point reciprocal estimate to 7 bits instruction.
- Signed-off-by: Frank Chang <frank.chang@sifive.com>
- ---
- target/riscv/helper.h | 4 +
- target/riscv/insn32.decode | 1 +
- target/riscv/insn_trans/trans_rvv.c.inc | 1 +
- target/riscv/vector_helper.c | 191 ++++++++++++++++++++++++
- 4 files changed, 197 insertions(+)
- diff --git a/target/riscv/helper.h b/target/riscv/helper.h
- index 807d1f7202..a83a7c33c0 100644
- --- a/target/riscv/helper.h
- +++ b/target/riscv/helper.h
- @@ -920,6 +920,10 @@ DEF_HELPER_5(vfrsqrt7_v_h, void, ptr, ptr, ptr, env, i32)
- DEF_HELPER_5(vfrsqrt7_v_w, void, ptr, ptr, ptr, env, i32)
- DEF_HELPER_5(vfrsqrt7_v_d, void, ptr, ptr, ptr, env, i32)
-
- +DEF_HELPER_5(vfrec7_v_h, void, ptr, ptr, ptr, env, i32)
- +DEF_HELPER_5(vfrec7_v_w, void, ptr, ptr, ptr, env, i32)
- +DEF_HELPER_5(vfrec7_v_d, void, ptr, ptr, ptr, env, i32)
- +
- DEF_HELPER_6(vfmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
- DEF_HELPER_6(vfmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
- DEF_HELPER_6(vfmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
- diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
- index 0c7fd17d56..c90d347af4 100644
- --- a/target/riscv/insn32.decode
- +++ b/target/riscv/insn32.decode
- @@ -536,6 +536,7 @@ vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
- vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
- vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
- vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm
- +vfrec7_v 010011 . ..... 00101 001 ..... 1010111 @r2_vm
- vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
- vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
- vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
- diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
- index a53f0158ee..f916f5d064 100644
- --- a/target/riscv/insn_trans/trans_rvv.c.inc
- +++ b/target/riscv/insn_trans/trans_rvv.c.inc
- @@ -2639,6 +2639,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
-
- GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN)
- GEN_OPFV_TRANS(vfrsqrt7_v, opfv_check, RISCV_FRM_DYN)
- +GEN_OPFV_TRANS(vfrec7_v, opfv_check, RISCV_FRM_DYN)
-
- /* Vector Floating-Point MIN/MAX Instructions */
- GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
- diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
- index 7d8f05ae21..78787af258 100644
- --- a/target/riscv/vector_helper.c
- +++ b/target/riscv/vector_helper.c
- @@ -3821,6 +3821,197 @@ GEN_VEXT_V_ENV(vfrsqrt7_v_h, 2, 2)
- GEN_VEXT_V_ENV(vfrsqrt7_v_w, 4, 4)
- GEN_VEXT_V_ENV(vfrsqrt7_v_d, 8, 8)
-
- +/*
- + * Vector Floating-Point Reciprocal Estimate Instruction
- + *
- + * Adapted from riscv-v-spec recip.c:
- + * https://github.com/riscv/riscv-v-spec/blob/master/recip.c
- + */
- +static uint64_t frec7(uint64_t f, int exp_size, int frac_size,
- + float_status *s)
- +{
- + uint64_t sign = extract64(f, frac_size + exp_size, 1);
- + uint64_t exp = extract64(f, frac_size, exp_size);
- + uint64_t frac = extract64(f, 0, frac_size);
- +
- + const uint8_t lookup_table[] = {
- + 127, 125, 123, 121, 119, 117, 116, 114,
- + 112, 110, 109, 107, 105, 104, 102, 100,
- + 99, 97, 96, 94, 93, 91, 90, 88,
- + 87, 85, 84, 83, 81, 80, 79, 77,
- + 76, 75, 74, 72, 71, 70, 69, 68,
- + 66, 65, 64, 63, 62, 61, 60, 59,
- + 58, 57, 56, 55, 54, 53, 52, 51,
- + 50, 49, 48, 47, 46, 45, 44, 43,
- + 42, 41, 40, 40, 39, 38, 37, 36,
- + 35, 35, 34, 33, 32, 31, 31, 30,
- + 29, 28, 28, 27, 26, 25, 25, 24,
- + 23, 23, 22, 21, 21, 20, 19, 19,
- + 18, 17, 17, 16, 15, 15, 14, 14,
- + 13, 12, 12, 11, 11, 10, 9, 9,
- + 8, 8, 7, 7, 6, 5, 5, 4,
- + 4, 3, 3, 2, 2, 1, 1, 0
- + };
- + const int precision = 7;
- +
- + if (exp == 0 && frac != 0) { /* subnormal */
- + /* Normalize the subnormal. */
- + while (extract64(frac, frac_size - 1, 1) == 0) {
- + exp--;
- + frac <<= 1;
- + }
- +
- + frac = (frac << 1) & MAKE_64BIT_MASK(0, frac_size);
- +
- + if (exp != 0 && exp != UINT64_MAX) {
- + /*
- + * Overflow to inf or max value of same sign,
- + * depending on sign and rounding mode.
- + */
- + s->float_exception_flags |= (float_flag_inexact |
- + float_flag_overflow);
- +
- + if ((s->float_rounding_mode == float_round_to_zero) ||
- + ((s->float_rounding_mode == float_round_down) && !sign) ||
- + ((s->float_rounding_mode == float_round_up) && sign)) {
- + /* Return greatest/negative finite value. */
- + return (sign << (exp_size + frac_size)) |
- + (MAKE_64BIT_MASK(frac_size, exp_size) - 1);
- + } else {
- + /* Return +-inf. */
- + return (sign << (exp_size + frac_size)) |
- + MAKE_64BIT_MASK(frac_size, exp_size);
- + }
- + }
- + }
- +
- + int idx = frac >> (frac_size - precision);
- + uint64_t out_frac = (uint64_t)(lookup_table[idx]) <<
- + (frac_size - precision);
- + uint64_t out_exp = 2 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp;
- +
- + if (out_exp == 0 || out_exp == UINT64_MAX) {
- + /*
- + * The result is subnormal, but don't raise the underflow exception,
- + * because there's no additional loss of precision.
- + */
- + out_frac = (out_frac >> 1) | MAKE_64BIT_MASK(frac_size - 1, 1);
- + if (out_exp == UINT64_MAX) {
- + out_frac >>= 1;
- + out_exp = 0;
- + }
- + }
- +
- + uint64_t val = 0;
- + val = deposit64(val, 0, frac_size, out_frac);
- + val = deposit64(val, frac_size, exp_size, out_exp);
- + val = deposit64(val, frac_size + exp_size, 1, sign);
- + return val;
- +}
- +
- +static float16 frec7_h(float16 f, float_status *s)
- +{
- + int exp_size = 5, frac_size = 10;
- + bool sign = float16_is_neg(f);
- +
- + /* frec7(+-inf) = +-0 */
- + if (float16_is_infinity(f)) {
- + return float16_set_sign(float16_zero, sign);
- + }
- +
- + /* frec7(+-0) = +-inf */
- + if (float16_is_zero(f)) {
- + s->float_exception_flags |= float_flag_divbyzero;
- + return float16_set_sign(float16_infinity, sign);
- + }
- +
- + /* frec7(sNaN) = canonical NaN */
- + if (float16_is_signaling_nan(f, s)) {
- + s->float_exception_flags |= float_flag_invalid;
- + return float16_default_nan(s);
- + }
- +
- + /* frec7(qNaN) = canonical NaN */
- + if (float16_is_quiet_nan(f, s)) {
- + return float16_default_nan(s);
- + }
- +
- + /* +-normal, +-subnormal */
- + uint64_t val = frec7(f, exp_size, frac_size, s);
- + return make_float16(val);
- +}
- +
- +static float32 frec7_s(float32 f, float_status *s)
- +{
- + int exp_size = 8, frac_size = 23;
- + bool sign = float32_is_neg(f);
- +
- + /* frec7(+-inf) = +-0 */
- + if (float32_is_infinity(f)) {
- + return float32_set_sign(float32_zero, sign);
- + }
- +
- + /* frec7(+-0) = +-inf */
- + if (float32_is_zero(f)) {
- + s->float_exception_flags |= float_flag_divbyzero;
- + return float32_set_sign(float32_infinity, sign);
- + }
- +
- + /* frec7(sNaN) = canonical NaN */
- + if (float32_is_signaling_nan(f, s)) {
- + s->float_exception_flags |= float_flag_invalid;
- + return float32_default_nan(s);
- + }
- +
- + /* frec7(qNaN) = canonical NaN */
- + if (float32_is_quiet_nan(f, s)) {
- + return float32_default_nan(s);
- + }
- +
- + /* +-normal, +-subnormal */
- + uint64_t val = frec7(f, exp_size, frac_size, s);
- + return make_float32(val);
- +}
- +
- +static float64 frec7_d(float64 f, float_status *s)
- +{
- + int exp_size = 11, frac_size = 52;
- + bool sign = float64_is_neg(f);
- +
- + /* frec7(+-inf) = +-0 */
- + if (float64_is_infinity(f)) {
- + return float64_set_sign(float64_zero, sign);
- + }
- +
- + /* frec7(+-0) = +-inf */
- + if (float64_is_zero(f)) {
- + s->float_exception_flags |= float_flag_divbyzero;
- + return float64_set_sign(float64_infinity, sign);
- + }
- +
- + /* frec7(sNaN) = canonical NaN */
- + if (float64_is_signaling_nan(f, s)) {
- + s->float_exception_flags |= float_flag_invalid;
- + return float64_default_nan(s);
- + }
- +
- + /* frec7(qNaN) = canonical NaN */
- + if (float64_is_quiet_nan(f, s)) {
- + return float64_default_nan(s);
- + }
- +
- + /* +-normal, +-subnormal */
- + uint64_t val = frec7(f, exp_size, frac_size, s);
- + return make_float64(val);
- +}
- +
- +RVVCALL(OPFVV1, vfrec7_v_h, OP_UU_H, H2, H2, frec7_h)
- +RVVCALL(OPFVV1, vfrec7_v_w, OP_UU_W, H4, H4, frec7_s)
- +RVVCALL(OPFVV1, vfrec7_v_d, OP_UU_D, H8, H8, frec7_d)
- +GEN_VEXT_V_ENV(vfrec7_v_h, 2, 2)
- +GEN_VEXT_V_ENV(vfrec7_v_w, 4, 4)
- +GEN_VEXT_V_ENV(vfrec7_v_d, 8, 8)
- +
- /* Vector Floating-Point MIN/MAX Instructions */
- RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum_noprop)
- RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum_noprop)
- --
- 2.33.1
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