0078-target-riscv-rvv-1.0-floating-point-reciprocal-estim.patch 9.0 KB

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  1. From 2be237127e46c352e487c55800b779c694089aa8 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Thu, 19 Nov 2020 14:40:08 +0800
  4. Subject: [PATCH 078/107] target/riscv: rvv-1.0: floating-point reciprocal
  5. estimate instruction
  6. Implement the floating-point reciprocal estimate to 7 bits instruction.
  7. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  8. ---
  9. target/riscv/helper.h | 4 +
  10. target/riscv/insn32.decode | 1 +
  11. target/riscv/insn_trans/trans_rvv.c.inc | 1 +
  12. target/riscv/vector_helper.c | 191 ++++++++++++++++++++++++
  13. 4 files changed, 197 insertions(+)
  14. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  15. index 807d1f7202..a83a7c33c0 100644
  16. --- a/target/riscv/helper.h
  17. +++ b/target/riscv/helper.h
  18. @@ -920,6 +920,10 @@ DEF_HELPER_5(vfrsqrt7_v_h, void, ptr, ptr, ptr, env, i32)
  19. DEF_HELPER_5(vfrsqrt7_v_w, void, ptr, ptr, ptr, env, i32)
  20. DEF_HELPER_5(vfrsqrt7_v_d, void, ptr, ptr, ptr, env, i32)
  21. +DEF_HELPER_5(vfrec7_v_h, void, ptr, ptr, ptr, env, i32)
  22. +DEF_HELPER_5(vfrec7_v_w, void, ptr, ptr, ptr, env, i32)
  23. +DEF_HELPER_5(vfrec7_v_d, void, ptr, ptr, ptr, env, i32)
  24. +
  25. DEF_HELPER_6(vfmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
  26. DEF_HELPER_6(vfmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
  27. DEF_HELPER_6(vfmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
  28. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  29. index 0c7fd17d56..c90d347af4 100644
  30. --- a/target/riscv/insn32.decode
  31. +++ b/target/riscv/insn32.decode
  32. @@ -536,6 +536,7 @@ vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
  33. vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
  34. vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
  35. vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm
  36. +vfrec7_v 010011 . ..... 00101 001 ..... 1010111 @r2_vm
  37. vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
  38. vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
  39. vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
  40. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  41. index a53f0158ee..f916f5d064 100644
  42. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  43. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  44. @@ -2639,6 +2639,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  45. GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN)
  46. GEN_OPFV_TRANS(vfrsqrt7_v, opfv_check, RISCV_FRM_DYN)
  47. +GEN_OPFV_TRANS(vfrec7_v, opfv_check, RISCV_FRM_DYN)
  48. /* Vector Floating-Point MIN/MAX Instructions */
  49. GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
  50. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  51. index 7d8f05ae21..78787af258 100644
  52. --- a/target/riscv/vector_helper.c
  53. +++ b/target/riscv/vector_helper.c
  54. @@ -3821,6 +3821,197 @@ GEN_VEXT_V_ENV(vfrsqrt7_v_h, 2, 2)
  55. GEN_VEXT_V_ENV(vfrsqrt7_v_w, 4, 4)
  56. GEN_VEXT_V_ENV(vfrsqrt7_v_d, 8, 8)
  57. +/*
  58. + * Vector Floating-Point Reciprocal Estimate Instruction
  59. + *
  60. + * Adapted from riscv-v-spec recip.c:
  61. + * https://github.com/riscv/riscv-v-spec/blob/master/recip.c
  62. + */
  63. +static uint64_t frec7(uint64_t f, int exp_size, int frac_size,
  64. + float_status *s)
  65. +{
  66. + uint64_t sign = extract64(f, frac_size + exp_size, 1);
  67. + uint64_t exp = extract64(f, frac_size, exp_size);
  68. + uint64_t frac = extract64(f, 0, frac_size);
  69. +
  70. + const uint8_t lookup_table[] = {
  71. + 127, 125, 123, 121, 119, 117, 116, 114,
  72. + 112, 110, 109, 107, 105, 104, 102, 100,
  73. + 99, 97, 96, 94, 93, 91, 90, 88,
  74. + 87, 85, 84, 83, 81, 80, 79, 77,
  75. + 76, 75, 74, 72, 71, 70, 69, 68,
  76. + 66, 65, 64, 63, 62, 61, 60, 59,
  77. + 58, 57, 56, 55, 54, 53, 52, 51,
  78. + 50, 49, 48, 47, 46, 45, 44, 43,
  79. + 42, 41, 40, 40, 39, 38, 37, 36,
  80. + 35, 35, 34, 33, 32, 31, 31, 30,
  81. + 29, 28, 28, 27, 26, 25, 25, 24,
  82. + 23, 23, 22, 21, 21, 20, 19, 19,
  83. + 18, 17, 17, 16, 15, 15, 14, 14,
  84. + 13, 12, 12, 11, 11, 10, 9, 9,
  85. + 8, 8, 7, 7, 6, 5, 5, 4,
  86. + 4, 3, 3, 2, 2, 1, 1, 0
  87. + };
  88. + const int precision = 7;
  89. +
  90. + if (exp == 0 && frac != 0) { /* subnormal */
  91. + /* Normalize the subnormal. */
  92. + while (extract64(frac, frac_size - 1, 1) == 0) {
  93. + exp--;
  94. + frac <<= 1;
  95. + }
  96. +
  97. + frac = (frac << 1) & MAKE_64BIT_MASK(0, frac_size);
  98. +
  99. + if (exp != 0 && exp != UINT64_MAX) {
  100. + /*
  101. + * Overflow to inf or max value of same sign,
  102. + * depending on sign and rounding mode.
  103. + */
  104. + s->float_exception_flags |= (float_flag_inexact |
  105. + float_flag_overflow);
  106. +
  107. + if ((s->float_rounding_mode == float_round_to_zero) ||
  108. + ((s->float_rounding_mode == float_round_down) && !sign) ||
  109. + ((s->float_rounding_mode == float_round_up) && sign)) {
  110. + /* Return greatest/negative finite value. */
  111. + return (sign << (exp_size + frac_size)) |
  112. + (MAKE_64BIT_MASK(frac_size, exp_size) - 1);
  113. + } else {
  114. + /* Return +-inf. */
  115. + return (sign << (exp_size + frac_size)) |
  116. + MAKE_64BIT_MASK(frac_size, exp_size);
  117. + }
  118. + }
  119. + }
  120. +
  121. + int idx = frac >> (frac_size - precision);
  122. + uint64_t out_frac = (uint64_t)(lookup_table[idx]) <<
  123. + (frac_size - precision);
  124. + uint64_t out_exp = 2 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp;
  125. +
  126. + if (out_exp == 0 || out_exp == UINT64_MAX) {
  127. + /*
  128. + * The result is subnormal, but don't raise the underflow exception,
  129. + * because there's no additional loss of precision.
  130. + */
  131. + out_frac = (out_frac >> 1) | MAKE_64BIT_MASK(frac_size - 1, 1);
  132. + if (out_exp == UINT64_MAX) {
  133. + out_frac >>= 1;
  134. + out_exp = 0;
  135. + }
  136. + }
  137. +
  138. + uint64_t val = 0;
  139. + val = deposit64(val, 0, frac_size, out_frac);
  140. + val = deposit64(val, frac_size, exp_size, out_exp);
  141. + val = deposit64(val, frac_size + exp_size, 1, sign);
  142. + return val;
  143. +}
  144. +
  145. +static float16 frec7_h(float16 f, float_status *s)
  146. +{
  147. + int exp_size = 5, frac_size = 10;
  148. + bool sign = float16_is_neg(f);
  149. +
  150. + /* frec7(+-inf) = +-0 */
  151. + if (float16_is_infinity(f)) {
  152. + return float16_set_sign(float16_zero, sign);
  153. + }
  154. +
  155. + /* frec7(+-0) = +-inf */
  156. + if (float16_is_zero(f)) {
  157. + s->float_exception_flags |= float_flag_divbyzero;
  158. + return float16_set_sign(float16_infinity, sign);
  159. + }
  160. +
  161. + /* frec7(sNaN) = canonical NaN */
  162. + if (float16_is_signaling_nan(f, s)) {
  163. + s->float_exception_flags |= float_flag_invalid;
  164. + return float16_default_nan(s);
  165. + }
  166. +
  167. + /* frec7(qNaN) = canonical NaN */
  168. + if (float16_is_quiet_nan(f, s)) {
  169. + return float16_default_nan(s);
  170. + }
  171. +
  172. + /* +-normal, +-subnormal */
  173. + uint64_t val = frec7(f, exp_size, frac_size, s);
  174. + return make_float16(val);
  175. +}
  176. +
  177. +static float32 frec7_s(float32 f, float_status *s)
  178. +{
  179. + int exp_size = 8, frac_size = 23;
  180. + bool sign = float32_is_neg(f);
  181. +
  182. + /* frec7(+-inf) = +-0 */
  183. + if (float32_is_infinity(f)) {
  184. + return float32_set_sign(float32_zero, sign);
  185. + }
  186. +
  187. + /* frec7(+-0) = +-inf */
  188. + if (float32_is_zero(f)) {
  189. + s->float_exception_flags |= float_flag_divbyzero;
  190. + return float32_set_sign(float32_infinity, sign);
  191. + }
  192. +
  193. + /* frec7(sNaN) = canonical NaN */
  194. + if (float32_is_signaling_nan(f, s)) {
  195. + s->float_exception_flags |= float_flag_invalid;
  196. + return float32_default_nan(s);
  197. + }
  198. +
  199. + /* frec7(qNaN) = canonical NaN */
  200. + if (float32_is_quiet_nan(f, s)) {
  201. + return float32_default_nan(s);
  202. + }
  203. +
  204. + /* +-normal, +-subnormal */
  205. + uint64_t val = frec7(f, exp_size, frac_size, s);
  206. + return make_float32(val);
  207. +}
  208. +
  209. +static float64 frec7_d(float64 f, float_status *s)
  210. +{
  211. + int exp_size = 11, frac_size = 52;
  212. + bool sign = float64_is_neg(f);
  213. +
  214. + /* frec7(+-inf) = +-0 */
  215. + if (float64_is_infinity(f)) {
  216. + return float64_set_sign(float64_zero, sign);
  217. + }
  218. +
  219. + /* frec7(+-0) = +-inf */
  220. + if (float64_is_zero(f)) {
  221. + s->float_exception_flags |= float_flag_divbyzero;
  222. + return float64_set_sign(float64_infinity, sign);
  223. + }
  224. +
  225. + /* frec7(sNaN) = canonical NaN */
  226. + if (float64_is_signaling_nan(f, s)) {
  227. + s->float_exception_flags |= float_flag_invalid;
  228. + return float64_default_nan(s);
  229. + }
  230. +
  231. + /* frec7(qNaN) = canonical NaN */
  232. + if (float64_is_quiet_nan(f, s)) {
  233. + return float64_default_nan(s);
  234. + }
  235. +
  236. + /* +-normal, +-subnormal */
  237. + uint64_t val = frec7(f, exp_size, frac_size, s);
  238. + return make_float64(val);
  239. +}
  240. +
  241. +RVVCALL(OPFVV1, vfrec7_v_h, OP_UU_H, H2, H2, frec7_h)
  242. +RVVCALL(OPFVV1, vfrec7_v_w, OP_UU_W, H4, H4, frec7_s)
  243. +RVVCALL(OPFVV1, vfrec7_v_d, OP_UU_D, H8, H8, frec7_d)
  244. +GEN_VEXT_V_ENV(vfrec7_v_h, 2, 2)
  245. +GEN_VEXT_V_ENV(vfrec7_v_w, 4, 4)
  246. +GEN_VEXT_V_ENV(vfrec7_v_d, 8, 8)
  247. +
  248. /* Vector Floating-Point MIN/MAX Instructions */
  249. RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum_noprop)
  250. RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum_noprop)
  251. --
  252. 2.33.1