0060-target-riscv-rvv-1.0-single-width-floating-point-red.patch 2.9 KB

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  1. From 0b0e6f66c2d99d2ab72663a649e8d0fbf98823c9 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Wed, 5 Aug 2020 18:06:00 +0800
  4. Subject: [PATCH 060/107] target/riscv: rvv-1.0: single-width floating-point
  5. reduction
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. ---
  9. target/riscv/insn_trans/trans_rvv.c.inc | 12 +++++++++---
  10. target/riscv/vector_helper.c | 12 ++++++------
  11. 2 files changed, 15 insertions(+), 9 deletions(-)
  12. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  13. index aac29a31a7..6273bef23a 100644
  14. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  15. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  16. @@ -2866,9 +2866,15 @@ GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
  17. GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
  18. /* Vector Single-Width Floating-Point Reduction Instructions */
  19. -GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
  20. -GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
  21. -GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
  22. +static bool freduction_check(DisasContext *s, arg_rmrr *a)
  23. +{
  24. + return reduction_check(s, a) &&
  25. + require_rvf(s);
  26. +}
  27. +
  28. +GEN_OPFVV_TRANS(vfredsum_vs, freduction_check)
  29. +GEN_OPFVV_TRANS(vfredmax_vs, freduction_check)
  30. +GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
  31. /* Vector Widening Floating-Point Reduction Instructions */
  32. GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
  33. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  34. index dd18ca26f8..fb01d126d7 100644
  35. --- a/target/riscv/vector_helper.c
  36. +++ b/target/riscv/vector_helper.c
  37. @@ -4382,14 +4382,14 @@ GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add)
  38. GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add)
  39. /* Maximum value */
  40. -GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum)
  41. -GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum)
  42. -GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum)
  43. +GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum_noprop)
  44. +GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum_noprop)
  45. +GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum_noprop)
  46. /* Minimum value */
  47. -GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum)
  48. -GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum)
  49. -GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum)
  50. +GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum_noprop)
  51. +GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum_noprop)
  52. +GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum_noprop)
  53. /* Vector Widening Floating-Point Reduction Instructions */
  54. /* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
  55. --
  56. 2.33.1