0004-RISCV-Add-customer-cache-instructions.patch 2.6 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667
  1. From bcd728e619143e082767170bfd7b255e521923db Mon Sep 17 00:00:00 2001
  2. From: "yilun.xie" <yilun.xie@starfivetech.com>
  3. Date: Fri, 29 Oct 2021 10:16:06 +0800
  4. Subject: [PATCH 4/9] [RISCV] Add customer cache instructions
  5. ---
  6. llvm/lib/Target/RISCV/RISCVInstrFormats.td | 12 ++++++++++++
  7. llvm/lib/Target/RISCV/RISCVInstrInfo.td | 13 +++++++++++++
  8. 2 files changed, 25 insertions(+)
  9. diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
  10. index e913edc47ec2..d3953227b0cd 100644
  11. --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
  12. +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
  13. @@ -377,6 +377,18 @@ class RVInstPref<RISCVOpcode opcode, dag outs, dag ins,
  14. let Opcode = opcode.Value;
  15. }
  16. +class RVInstCache<bits<12> cache, RISCVOpcode opcode, dag outs, dag ins,
  17. + string opcodestr, string argstr>
  18. + : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
  19. + bits<5> rs1;
  20. +
  21. + let Inst{31-20} = cache;
  22. + let Inst{19-15} = rs1;
  23. + let Inst{14-12} = 0;
  24. + let Inst{11-7} = 0;
  25. + let Opcode = opcode.Value;
  26. +}
  27. +
  28. class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
  29. dag outs, dag ins, string opcodestr, string argstr>
  30. : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
  31. diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
  32. index 5849327ca255..6bd3de20b807 100644
  33. --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
  34. +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
  35. @@ -586,6 +586,12 @@ class PREF_iir<string opcodestr>
  36. : RVInstPref<OPC_OP_IMM, (outs), (ins uimm4_pref:$imm4, simm8:$imm8, GPR:$rs1),
  37. opcodestr, "$imm4, ${imm8}(${rs1})">;
  38. +let hasNoSchedulingInfo = 1,
  39. + hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
  40. +class CSR_cache<bits<12> cache, string opcodestr>
  41. + : RVInstCache<cache, OPC_SYSTEM, (outs), (ins GPR:$rs1),
  42. + opcodestr, "$rs1">, Sched<[WriteCSR, ReadCSR]>;
  43. +
  44. let hasNoSchedulingInfo = 1,
  45. hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
  46. class CSR_ii<bits<3> funct3, string opcodestr>
  47. @@ -773,6 +779,13 @@ def WRS_STO : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "wrs.sto", "">,
  48. } // hasSideEffects = 1, mayLoad = 0, mayStore = 0
  49. +/* Custom instruction and CSRs */
  50. +def CFLUSH_D_L1 : CSR_cache<0b111111000000, "cflush.d.l1">;
  51. +def CDISCARD_D_L1 : CSR_cache<0b111111000010, "cdiscard.d.l1">;
  52. +def CFLUSH_D_L2 : CSR_cache<0b111111000100, "cflush.d.l2">;
  53. +def CDISCARD_D_L2 : CSR_cache<0b111111000110, "cdiscard.d.l2">;
  54. +/* End */
  55. +
  56. def CSRRW : CSR_ir<0b001, "csrrw">;
  57. def CSRRS : CSR_ir<0b010, "csrrs">;
  58. def CSRRC : CSR_ir<0b011, "csrrc">;
  59. --
  60. 2.25.1