0003-RISCV-Add-prefetch-instructions.patch 5.4 KB

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  1. From 4cd4084046f2dd3d57eb6bee0e88baecd66e49df Mon Sep 17 00:00:00 2001
  2. From: "max.ma" <max.ma@starfivetech.com>
  3. Date: Sun, 25 Jun 2023 19:36:20 -0700
  4. Subject: [PATCH 3/9] [RISCV] Add prefetch instructions
  5. ---
  6. .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 10 +++++++
  7. .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 2 ++
  8. llvm/lib/Target/RISCV/RISCVInstrFormats.td | 16 +++++++++++
  9. llvm/lib/Target/RISCV/RISCVInstrInfo.td | 27 +++++++++++++++++++
  10. 4 files changed, 55 insertions(+)
  11. diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  12. index 9752e398bd99..d577d83bf14e 100644
  13. --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  14. +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  15. @@ -566,6 +566,7 @@ public:
  16. bool isUImm2() { return IsUImm<2>(); }
  17. bool isUImm3() { return IsUImm<3>(); }
  18. + bool isUImm4() { return IsUImm<4>(); }
  19. bool isUImm5() { return IsUImm<5>(); }
  20. bool isUImm7() { return IsUImm<7>(); }
  21. @@ -597,6 +598,15 @@ public:
  22. return IsConstantImm && isInt<6>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
  23. }
  24. + bool isSImm8() const {
  25. + if (!isImm())
  26. + return false;
  27. + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
  28. + int64_t Imm;
  29. + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
  30. + return IsConstantImm && isInt<8>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
  31. + }
  32. +
  33. bool isSImm6NonZero() const {
  34. if (!isImm())
  35. return false;
  36. diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  37. index eb43f4bf0a02..a832f51bd517 100644
  38. --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  39. +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  40. @@ -244,11 +244,13 @@ enum OperandType : unsigned {
  41. OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM,
  42. OPERAND_UIMM3,
  43. OPERAND_UIMM4,
  44. + OPERAND_UIMM4_PREF,
  45. OPERAND_UIMM5,
  46. OPERAND_UIMM7,
  47. OPERAND_UIMM7_LSB00,
  48. OPERAND_UIMM8_LSB00,
  49. OPERAND_UIMM8_LSB000,
  50. + OPERAND_SIMM8,
  51. OPERAND_UIMM12,
  52. OPERAND_ZERO,
  53. OPERAND_SIMM5,
  54. diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
  55. index f2cd4ed8857f..e913edc47ec2 100644
  56. --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
  57. +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
  58. @@ -361,6 +361,22 @@ class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
  59. let Opcode = opcode.Value;
  60. }
  61. +class RVInstPref<RISCVOpcode opcode, dag outs, dag ins,
  62. + string opcodestr, string argstr>
  63. + : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
  64. +
  65. + bits<8> imm8;
  66. + bits<4> imm4;
  67. + bits<5> rs1;
  68. +
  69. + let Inst{31-24} = imm8;
  70. + let Inst{23-20} = imm4;
  71. + let Inst{19-15} = rs1;
  72. + let Inst{14-12} = 2;
  73. + let Inst{11-7} = 0;
  74. + let Opcode = opcode.Value;
  75. +}
  76. +
  77. class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
  78. dag outs, dag ins, string opcodestr, string argstr>
  79. : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
  80. diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
  81. index 75fee3f962d0..5849327ca255 100644
  82. --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
  83. +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
  84. @@ -205,6 +205,18 @@ def uimm3 : Operand<XLenVT> {
  85. let OperandNamespace = "RISCVOp";
  86. }
  87. +def uimm4_pref : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<4>(Imm);}]> {
  88. + let ParserMatchClass = UImmAsmOperand<4>;
  89. + let DecoderMethod = "decodeUImmOperand<4>";
  90. + let MCOperandPredicate = [{
  91. + int64_t Imm;
  92. + if (MCOp.evaluateAsConstantImm(Imm))
  93. + return isUInt<4>(Imm) && (imm == 0 || imm == 1 || imm == 2 || imm == 4 || imm == 8);
  94. + }];
  95. + let OperandType = "OPERAND_UIMM4_PREF";
  96. + let OperandNamespace = "RISCVOp";
  97. +}
  98. +
  99. def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
  100. let ParserMatchClass = UImmAsmOperand<5>;
  101. let DecoderMethod = "decodeUImmOperand<5>";
  102. @@ -212,6 +224,14 @@ def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
  103. let OperandNamespace = "RISCVOp";
  104. }
  105. +def simm8 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<8>(Imm);}]> {
  106. + let ParserMatchClass = SImmAsmOperand<8>;
  107. + let EncoderMethod = "getImmOpValue";
  108. + let DecoderMethod = "decodeSImmOperand<8>";
  109. + let OperandType = "OPERAND_SIMM8";
  110. + let OperandNamespace = "RISCVOp";
  111. +}
  112. +
  113. def InsnDirectiveOpcode : AsmOperandClass {
  114. let Name = "InsnDirectiveOpcode";
  115. let ParserMethod = "parseInsnDirectiveOpcode";
  116. @@ -560,6 +580,12 @@ class CSR_ir<bits<3> funct3, string opcodestr>
  117. : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1),
  118. opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR, ReadCSR]>;
  119. +let hasNoSchedulingInfo = 1,
  120. + hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
  121. +class PREF_iir<string opcodestr>
  122. + : RVInstPref<OPC_OP_IMM, (outs), (ins uimm4_pref:$imm4, simm8:$imm8, GPR:$rs1),
  123. + opcodestr, "$imm4, ${imm8}(${rs1})">;
  124. +
  125. let hasNoSchedulingInfo = 1,
  126. hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
  127. class CSR_ii<bits<3> funct3, string opcodestr>
  128. @@ -670,6 +696,7 @@ def SLT : ALU_rr<0b0000000, 0b010, "slt">,
  129. def SLTU : ALU_rr<0b0000000, 0b011, "sltu">,
  130. Sched<[WriteIALU, ReadIALU, ReadIALU]>;
  131. }
  132. +def PREF : PREF_iir<"pref">;
  133. def XOR : ALU_rr<0b0000000, 0b100, "xor", /*Commutable*/1>,
  134. Sched<[WriteIALU, ReadIALU, ReadIALU]>;
  135. def SRL : ALU_rr<0b0000000, 0b101, "srl">,
  136. --
  137. 2.25.1