0001-neon2rvv-support-type-convert-between-fixed-vector-a.patch 8.1 KB

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  1. From 51248b6c65c8809f27e84a56e43b00c88d473280 Mon Sep 17 00:00:00 2001
  2. From: Eric Tang <eric.tang@starfivetech.com>
  3. Date: Fri, 2 Jun 2023 09:07:44 +0800
  4. Subject: [PATCH 1/9] [neon2rvv] support type convert between fixed vector and
  5. scalable vector
  6. disable the default vectorize options on O1,O2,O3,Oz...
  7. Signed-off-by: Eric Tang <eric.tang@starfivetech.com>
  8. ---
  9. clang/include/clang/Basic/BuiltinsRISCV.def | 49 ++++++++++++++++++++
  10. clang/lib/CodeGen/CGBuiltin.cpp | 51 +++++++++++++++++++++
  11. clang/lib/Driver/ToolChains/Clang.cpp | 1 +
  12. 3 files changed, 101 insertions(+)
  13. diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def
  14. index c26e3b807370..cbeb29245aec 100644
  15. --- a/clang/include/clang/Basic/BuiltinsRISCV.def
  16. +++ b/clang/include/clang/Basic/BuiltinsRISCV.def
  17. @@ -79,5 +79,54 @@ TARGET_BUILTIN(__builtin_riscv_sm4ks, "LiLiLiIUc", "nc", "zksed")
  18. TARGET_BUILTIN(__builtin_riscv_sm3p0, "LiLi", "nc", "zksh")
  19. TARGET_BUILTIN(__builtin_riscv_sm3p1, "LiLi", "nc", "zksh")
  20. +// Scalable Vector type <-> Fixed Vector type
  21. +
  22. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_i8m1, "q8ScV8Sc", "nc", "v,64bit")
  23. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_i8m2, "q16ScV16Sc", "nc", "v,64bit")
  24. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_i16m1, "q4SsV4Ss", "nc", "v,64bit")
  25. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_i16m2, "q8SsV8Ss", "nc", "v,64bit")
  26. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_i32m1, "q2SiV2Si", "nc", "v,64bit")
  27. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_i32m2, "q4SiV4Si", "nc", "v,64bit")
  28. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_i64m1, "q1LSiV1LSi", "nc", "v,64bit")
  29. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_i64m2, "q2LSiV2LSi", "nc", "v,64bit")
  30. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_u8m1, "q8UcV8Uc", "nc", "v,64bit")
  31. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_u8m2, "q16UcV16Uc", "nc", "v,64bit")
  32. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_u16m1, "q4UsV4Us", "nc", "v,64bit")
  33. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_u16m2, "q8UsV8Us", "nc", "v,64bit")
  34. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_u32m1, "q2UiV2Ui", "nc", "v,64bit")
  35. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_u32m2, "q4UiV4Ui", "nc", "v,64bit")
  36. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_u64m1, "q1LUiV1LUi", "nc", "v,64bit")
  37. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_u64m2, "q2LUiV2LUi", "nc", "v,64bit")
  38. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_f16m1, "q4hV4h", "nc", "v,64bit")
  39. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_f16m2, "q8hV8h", "nc", "v,64bit")
  40. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_f32m1, "q2fV2f", "nc", "v,64bit")
  41. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_f32m2, "q4fV4f", "nc", "v,64bit")
  42. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_f64m1, "q1dV1d", "nc", "v,64bit")
  43. +TARGET_BUILTIN(__builtin_rvv_type_cast_from_f64m2, "q2dV2d", "nc", "v,64bit")
  44. +
  45. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_i8m1, "V8Scq8Sc", "nc", "v,64bit")
  46. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_i8m2, "V16Scq16Sc", "nc", "v,64bit")
  47. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_i16m1, "V4Ssq4Ss", "nc", "v,64bit")
  48. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_i16m2, "V8Ssq8Ss", "nc", "v,64bit")
  49. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_i32m1, "V2Siq2Si", "nc", "v,64bit")
  50. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_i32m2, "V4Siq4Si", "nc", "v,64bit")
  51. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_i64m1, "V1LSiq1LSi", "nc", "v,64bit")
  52. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_i64m2, "V2LSiq2LSi", "nc", "v,64bit")
  53. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_u8m1, "V8Ucq8Uc", "nc", "v,64bit")
  54. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_u8m2, "V16Ucq16Uc", "nc", "v,64bit")
  55. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_u16m1, "V4Usq4Us", "nc", "v,64bit")
  56. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_u16m2, "V8Usq8Us", "nc", "v,64bit")
  57. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_u32m1, "V2Uiq2Ui", "nc", "v,64bit")
  58. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_u32m2, "V4Uiq4Ui", "nc", "v,64bit")
  59. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_u64m1, "V1LUiq1LUi", "nc", "v,64bit")
  60. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_u64m2, "V2LUiq2LUi", "nc", "v,64bit")
  61. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_f16m1, "V4hq4h", "nc", "v,64bit")
  62. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_f16m2, "V8hq8h", "nc", "v,64bit")
  63. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_f32m1, "V2fq2f", "nc", "v,64bit")
  64. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_f32m2, "V4fq4f", "nc", "v,64bit")
  65. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_f64m1, "V1dq1d", "nc", "v,64bit")
  66. +TARGET_BUILTIN(__builtin_rvv_type_cast_to_f64m2, "V2dq2d", "nc", "v,64bit")
  67. +
  68. +
  69. #undef BUILTIN
  70. #undef TARGET_BUILTIN
  71. diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
  72. index f72e04a425d9..1e276bac4e54 100644
  73. --- a/clang/lib/CodeGen/CGBuiltin.cpp
  74. +++ b/clang/lib/CodeGen/CGBuiltin.cpp
  75. @@ -19666,6 +19666,57 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
  76. ID = Intrinsic::riscv_sm3p1;
  77. IntrinsicTypes = {ResultType};
  78. break;
  79. + //scalable vector type <-> fixed vector types
  80. + case RISCV::BI__builtin_rvv_type_cast_from_i8m1:
  81. + case RISCV::BI__builtin_rvv_type_cast_from_i8m2:
  82. + case RISCV::BI__builtin_rvv_type_cast_from_i16m1:
  83. + case RISCV::BI__builtin_rvv_type_cast_from_i16m2:
  84. + case RISCV::BI__builtin_rvv_type_cast_from_i32m1:
  85. + case RISCV::BI__builtin_rvv_type_cast_from_i32m2:
  86. + case RISCV::BI__builtin_rvv_type_cast_from_i64m1:
  87. + case RISCV::BI__builtin_rvv_type_cast_from_i64m2:
  88. + case RISCV::BI__builtin_rvv_type_cast_from_u8m1:
  89. + case RISCV::BI__builtin_rvv_type_cast_from_u8m2:
  90. + case RISCV::BI__builtin_rvv_type_cast_from_u16m1:
  91. + case RISCV::BI__builtin_rvv_type_cast_from_u16m2:
  92. + case RISCV::BI__builtin_rvv_type_cast_from_u32m1:
  93. + case RISCV::BI__builtin_rvv_type_cast_from_u32m2:
  94. + case RISCV::BI__builtin_rvv_type_cast_from_u64m1:
  95. + case RISCV::BI__builtin_rvv_type_cast_from_u64m2:
  96. + case RISCV::BI__builtin_rvv_type_cast_from_f16m1:
  97. + case RISCV::BI__builtin_rvv_type_cast_from_f16m2:
  98. + case RISCV::BI__builtin_rvv_type_cast_from_f32m1:
  99. + case RISCV::BI__builtin_rvv_type_cast_from_f32m2:
  100. + case RISCV::BI__builtin_rvv_type_cast_from_f64m1:
  101. + case RISCV::BI__builtin_rvv_type_cast_from_f64m2:
  102. + {
  103. + return Builder.CreateInsertVector(ResultType, UndefValue::get(ResultType), Ops[0], Builder.getInt64(0));
  104. + }
  105. + case RISCV::BI__builtin_rvv_type_cast_to_i8m1:
  106. + case RISCV::BI__builtin_rvv_type_cast_to_i8m2:
  107. + case RISCV::BI__builtin_rvv_type_cast_to_i16m1:
  108. + case RISCV::BI__builtin_rvv_type_cast_to_i16m2:
  109. + case RISCV::BI__builtin_rvv_type_cast_to_i32m1:
  110. + case RISCV::BI__builtin_rvv_type_cast_to_i32m2:
  111. + case RISCV::BI__builtin_rvv_type_cast_to_i64m1:
  112. + case RISCV::BI__builtin_rvv_type_cast_to_i64m2:
  113. + case RISCV::BI__builtin_rvv_type_cast_to_u8m1:
  114. + case RISCV::BI__builtin_rvv_type_cast_to_u8m2:
  115. + case RISCV::BI__builtin_rvv_type_cast_to_u16m1:
  116. + case RISCV::BI__builtin_rvv_type_cast_to_u16m2:
  117. + case RISCV::BI__builtin_rvv_type_cast_to_u32m1:
  118. + case RISCV::BI__builtin_rvv_type_cast_to_u32m2:
  119. + case RISCV::BI__builtin_rvv_type_cast_to_u64m1:
  120. + case RISCV::BI__builtin_rvv_type_cast_to_u64m2:
  121. + case RISCV::BI__builtin_rvv_type_cast_to_f16m1:
  122. + case RISCV::BI__builtin_rvv_type_cast_to_f16m2:
  123. + case RISCV::BI__builtin_rvv_type_cast_to_f32m1:
  124. + case RISCV::BI__builtin_rvv_type_cast_to_f32m2:
  125. + case RISCV::BI__builtin_rvv_type_cast_to_f64m1:
  126. + case RISCV::BI__builtin_rvv_type_cast_to_f64m2:
  127. + {
  128. + return Builder.CreateExtractVector(ResultType, Ops[0], Builder.getInt64(0));
  129. + }
  130. // Vector builtins are handled from here.
  131. #include "clang/Basic/riscv_vector_builtin_cg.inc"
  132. diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
  133. index 77554aa2c462..d207a636e07f 100644
  134. --- a/clang/lib/Driver/ToolChains/Clang.cpp
  135. +++ b/clang/lib/Driver/ToolChains/Clang.cpp
  136. @@ -635,6 +635,7 @@ static void addCoveragePrefixMapArg(const Driver &D, const ArgList &Args,
  137. /// For -Oz the loop vectorizer is disabled, while the slp vectorizer is
  138. /// enabled.
  139. static bool shouldEnableVectorizerAtOLevel(const ArgList &Args, bool isSlpVec) {
  140. + return false;
  141. if (Arg *A = Args.getLastArg(options::OPT_O_Group)) {
  142. if (A->getOption().matches(options::OPT_O4) ||
  143. A->getOption().matches(options::OPT_Ofast))
  144. --
  145. 2.25.1