From 410eaceb105782c98f8d9899c1b316f709a6be5e Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Mon, 19 Apr 2021 12:27:56 +0800 Subject: [PATCH 006/107] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions In IEEE 754-2008 spec: Invalid operation exception is signaled when doing: fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c) unless c is a quiet NaN; if c is a quiet NaN then it is implementation defined whether the invalid operation exception is signaled. In RISC-V Unprivileged ISA spec: The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are Inf and zero, even when the addend is a quiet NaN. This commit set invalid operation execption flag for RISC-V when multiplicands of muladd instructions are Inf and zero. Signed-off-by: Frank Chang --- fpu/softfloat-specialize.c.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index c2f87addb2..12f29fbfc5 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -624,6 +624,12 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { return 1; } +#elif defined(TARGET_RISCV) + /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ + if (infzero) { + float_raise(float_flag_invalid, status); + } + return 3; /* deafult NaN */ #elif defined(TARGET_XTENSA) /* * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns -- 2.33.1