From c1eaf07b4e8a7ea6c3f053003a8ebd9a1e933f22 Mon Sep 17 00:00:00 2001 From: "yilun.xie" Date: Thu, 18 Nov 2021 15:37:45 +0800 Subject: [PATCH 20/26] Cost model for zbb extension --- gcc/config/riscv/riscv.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 7d5e22d9fe2..bf91d8c7371 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -1684,6 +1684,16 @@ riscv_extend_cost (rtx op, bool unsigned_p) if (TARGET_ZBA && TARGET_64BIT && unsigned_p && GET_MODE (op) == SImode) return COSTS_N_INSNS (1); + /* ZBB provide zext.h, sext.b and sext.h. */ + if (TARGET_ZBB) + { + if (!unsigned_p && GET_MODE (op) == QImode) + return COSTS_N_INSNS (1); + + if (GET_MODE (op) == HImode) + return COSTS_N_INSNS (1); + } + if (!unsigned_p && GET_MODE (op) == SImode) /* We can use SEXT.W. */ return COSTS_N_INSNS (1); @@ -1775,6 +1785,14 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN case IOR: case XOR: + /* orn, andn and xorn pattern for zbb. */ + if (TARGET_ZBB + && GET_CODE (XEXP (x, 0)) == NOT) + { + *total = riscv_binary_cost (x, 1, 2); + return true; + } + /* Double-word operations use two single-word operations. */ *total = riscv_binary_cost (x, 1, 2); return false; -- 2.33.1