From 2441e7b302dc5f3805b61b3a675adb80de35fb4b Mon Sep 17 00:00:00 2001 From: "yilun.xie" Date: Sat, 9 Oct 2021 10:41:17 +0800 Subject: [PATCH 07/15] merge from riscv-gcc-10.2.0 to support bitmanip --- gcc/common/config/riscv/riscv-common.c | 32 ++++++++++++++++++++++++++ gcc/config/riscv/riscv-opts.h | 22 ++++++++++++++++++ gcc/config/riscv/riscv.opt | 5 ++++ 3 files changed, 59 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c index 34b74e52a2d..c7b6158af4b 100644 --- a/gcc/common/config/riscv/riscv-common.c +++ b/gcc/common/config/riscv/riscv-common.c @@ -50,6 +50,16 @@ static const riscv_implied_info_t riscv_implied_info[] = {"d", "f"}, {"f", "zicsr"}, {"d", "zicsr"}, + {"b", "zbb"}, + {"b", "zbs"}, + {"b", "zba"}, + {"b", "zbp"}, + {"b", "zbe"}, + {"b", "zbf"}, + {"b", "zbc"}, + {"b", "zbm"}, + {"b", "zbr"}, + {"b", "zbt"}, {NULL, NULL} }; @@ -101,6 +111,17 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0}, {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0}, + {"b", ISA_SPEC_CLASS_NONE, 0, 93}, + {"zba", ISA_SPEC_CLASS_NONE, 0, 93}, + {"zbb", ISA_SPEC_CLASS_NONE, 0, 93}, + {"zbc", ISA_SPEC_CLASS_NONE, 0, 93}, + {"zbe", ISA_SPEC_CLASS_NONE, 0, 93}, + {"zbf", ISA_SPEC_CLASS_NONE, 0, 93}, + {"zbr", ISA_SPEC_CLASS_NONE, 0, 93}, + {"zbm", ISA_SPEC_CLASS_NONE, 0, 93}, + {"zbs", ISA_SPEC_CLASS_NONE, 0, 93}, + {"zbt", ISA_SPEC_CLASS_NONE, 0, 93}, + {"zbp", ISA_SPEC_CLASS_NONE, 0, 93}, /* Terminate the list. */ {NULL, ISA_SPEC_CLASS_NONE, 0, 0} }; @@ -900,10 +921,21 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"f", &gcc_options::x_target_flags, MASK_HARD_FLOAT}, {"d", &gcc_options::x_target_flags, MASK_DOUBLE_FLOAT}, {"c", &gcc_options::x_target_flags, MASK_RVC}, + {"b", &gcc_options::x_target_flags, MASK_BITMANIP}, {"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR}, {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI}, + {"zba", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBA}, + {"zbb", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBB}, + {"zbs", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBS}, + {"zbp", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBP}, + {"zbr", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBR}, + {"zbe", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBE}, + {"zbf", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBF}, + {"zbc", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBC}, + {"zbm", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBM}, + {"zbt", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBT}, {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index f4cf6ca4b82..ca3190b6414 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -67,6 +67,28 @@ enum stack_protector_guard { SSP_GLOBAL /* global canary */ }; +#define MASK_ZBA (1 << 0) +#define MASK_ZBB (1 << 1) +#define MASK_ZBS (1 << 2) +#define MASK_ZBP (1 << 3) +#define MASK_ZBE (1 << 4) +#define MASK_ZBF (1 << 5) +#define MASK_ZBC (1 << 6) +#define MASK_ZBR (1 << 7) +#define MASK_ZBM (1 << 8) +#define MASK_ZBT (1 << 9) + +#define TARGET_ZBA ((riscv_bitmanip_subext & MASK_ZBA) != 0) +#define TARGET_ZBB ((riscv_bitmanip_subext & MASK_ZBB) != 0) +#define TARGET_ZBS ((riscv_bitmanip_subext & MASK_ZBS) != 0) +#define TARGET_ZBP ((riscv_bitmanip_subext & MASK_ZBP) != 0) +#define TARGET_ZBE ((riscv_bitmanip_subext & MASK_ZBE) != 0) +#define TARGET_ZBF ((riscv_bitmanip_subext & MASK_ZBF) != 0) +#define TARGET_ZBC ((riscv_bitmanip_subext & MASK_ZBC) != 0) +#define TARGET_ZBR ((riscv_bitmanip_subext & MASK_ZBR) != 0) +#define TARGET_ZBM ((riscv_bitmanip_subext & MASK_ZBM) != 0) +#define TARGET_ZBT ((riscv_bitmanip_subext & MASK_ZBT) != 0) + #define MASK_ZICSR (1 << 0) #define MASK_ZIFENCEI (1 << 1) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index e294e223151..0e73e2ab758 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -136,6 +136,8 @@ Mask(64BIT) Mask(MUL) +Mask(BITMANIP) + Mask(ATOMIC) Mask(HARD_FLOAT) @@ -195,6 +197,9 @@ long riscv_stack_protector_guard_offset = 0 TargetVariable int riscv_zi_subext +TargetVariable +int riscv_bitmanip_subext + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option): -- 2.33.1