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dubhe: clang: Upgrade version to 17.0.0
Forked from meta-clang master branch with version change (17.0.1 to 17.0.0), SRCREV change and patches.
Dropped e7b3acb82f4c4422e57884ad9427fba6bd020e8b from meta-clang as the suffix "-crosssdk" is still needed in Kirkstone version.
Revert 384e8d169a2c408e2cef03ea2deb88fb82058011 patch in clang_17.0.0.bbappend.

Signed-off-by: weiheng.cheng <weiheng.cheng@starfivetech.com>

weiheng.cheng 4 months ago
parent
commit
ea96ada6d2
70 changed files with 1198 additions and 2012 deletions
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      recipes-devtools/clang/clang-cross-canadian_17.0.0.bb
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      recipes-devtools/clang/clang-cross_17.0.0.bb
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      recipes-devtools/clang/clang-crosssdk_17.0.0.bb
  4. 4 5
      recipes-devtools/clang/clang.inc
  5. 655 0
      recipes-devtools/clang/clang/0001-Handle-seteq-setne-conditions-for-CZERO_NEZ-CZERO_EQ.patch
  6. 9 9
      recipes-devtools/clang/clang/0001-libcxxabi-Find-libunwind-headers-when-LIBCXXABI_LIBU.patch
  7. 1 1
      recipes-devtools/clang/clang/0002-compiler-rt-support-a-new-embedded-linux-target.patch
  8. 0 1278
      recipes-devtools/clang/clang/0002-neon2rvv-Model-vxrm-in-LLVM-intrinsics-and-add-optim.patch
  9. 13 13
      recipes-devtools/clang/clang/0002-neon2rvv-support-type-convert-between-fixed-vector-a.patch
  10. 51 0
      recipes-devtools/clang/clang/0003-Add-an-optional-for-optimizing-Insert-Read-Write-CSR.patch
  11. 3 3
      recipes-devtools/clang/clang/0003-compiler-rt-Simplify-cross-compilation.-Don-t-use-na.patch
  12. 38 35
      recipes-devtools/clang/clang/0004-RISCV-Add-prefetch-instructions.patch
  13. 9 9
      recipes-devtools/clang/clang/0004-llvm-TargetLibraryInfo-Undefine-libc-functions-if-th.patch
  14. 10 10
      recipes-devtools/clang/clang/0005-RISCV-Add-customer-cache-instructions.patch
  15. 2 2
      recipes-devtools/clang/clang/0005-llvm-allow-env-override-of-exe-and-libdir-path.patch
  16. 10 13
      recipes-devtools/clang/clang/0006-RISCV-Add-multilib-v-b-support-for-baremetal-toolcha.patch
  17. 20 7
      recipes-devtools/clang/clang/0006-clang-driver-Check-sysroot-for-ldso-path.patch
  18. 0 25
      recipes-devtools/clang/clang/0007-Driver-Set-clang-default-dwarf-version-to-4.patch
  19. 7 7
      recipes-devtools/clang/clang/0007-RISCV-Change-baremetal-multilib-directory-name-to-al.patch
  20. 3 3
      recipes-devtools/clang/clang/0007-clang-Driver-tools.cpp-Add-lssp_nonshared-on-musl.patch
  21. 22 14
      recipes-devtools/clang/clang/0008-RISCV-Support-b-letter-in-march-string.patch
  22. 4 4
      recipes-devtools/clang/clang/0008-clang-Prepend-trailing-to-sysroot.patch
  23. 0 38
      recipes-devtools/clang/clang/0009-RISCV-Align-default-march-with-dubhe-gcc-toolchain.patch
  24. 5 5
      recipes-devtools/clang/clang/0009-clang-Look-inside-the-target-sysroot-for-compiler-ru.patch
  25. 3 4
      recipes-devtools/clang/clang/0010-clang-Define-releative-gcc-installation-dir.patch
  26. 3 3
      recipes-devtools/clang/clang/0011-clang-Add-lpthread-and-ldl-along-with-lunwind-for-st.patch
  27. 2 2
      recipes-devtools/clang/clang/0012-Pass-PYTHON_EXECUTABLE-when-cross-compiling-for-nati.patch
  28. 1 1
      recipes-devtools/clang/clang/0013-Check-for-atomic-double-intrinsics.patch
  29. 4 4
      recipes-devtools/clang/clang/0014-libcxx-Add-compiler-runtime-library-to-link-step-for.patch
  30. 9 9
      recipes-devtools/clang/clang/0015-clang-llvm-cmake-Fix-configure-for-packages-using-fi.patch
  31. 5 3
      recipes-devtools/clang/clang/0016-clang-Fix-resource-dir-location-for-cross-toolchains.patch
  32. 19 8
      recipes-devtools/clang/clang/0017-clang-driver-Add-dyld-prefix-when-checking-sysroot-f.patch
  33. 5 16
      recipes-devtools/clang/clang/0018-clang-Use-python3-in-python-scripts.patch
  34. 3 3
      recipes-devtools/clang/clang/0019-For-x86_64-set-Yocto-based-GCC-install-search-path.patch
  35. 3 3
      recipes-devtools/clang/clang/0020-llvm-Do-not-use-find_library-for-ncurses.patch
  36. 3 3
      recipes-devtools/clang/clang/0021-llvm-Insert-anchor-for-adding-OE-distro-vendor-names.patch
  37. 1 1
      recipes-devtools/clang/clang/0022-compiler-rt-Do-not-use-backtrace-APIs-on-non-glibc-l.patch
  38. 3 3
      recipes-devtools/clang/clang/0023-clang-Fix-x86-triple-for-non-debian-multiarch-linux-.patch
  39. 10 9
      recipes-devtools/clang/clang/0024-libunwind-Added-unw_backtrace-method.patch
  40. 3 3
      recipes-devtools/clang/clang/0025-clang-Do-not-use-install-relative-libc-headers.patch
  41. 44 28
      recipes-devtools/clang/clang/0026-clang-Fix-how-driver-finds-GCC-installation-path-on-.patch
  42. 6 6
      recipes-devtools/clang/clang/0027-Fix-lib-paths-for-OpenEmbedded-Host.patch
  43. 5 5
      recipes-devtools/clang/clang/0028-Correct-library-search-path-for-OpenEmbedded-Host.patch
  44. 2 2
      recipes-devtools/clang/clang/0029-lldb-Link-with-libatomic-on-x86.patch
  45. 0 35
      recipes-devtools/clang/clang/0030-clang-exclude-openembedded-distributions-from-settin.patch
  46. 8 8
      recipes-devtools/clang/clang/0030-compiler-rt-Enable-__int128-for-ppc32.patch
  47. 4 4
      recipes-devtools/clang/clang/0031-llvm-Do-not-use-cmake-infra-to-detect-libzstd.patch
  48. 3 3
      recipes-devtools/clang/clang/0032-compiler-rt-Fix-stat-struct-s-size-for-O32-ABI.patch
  49. 0 53
      recipes-devtools/clang/clang/0033-build-Enable-64bit-off_t-on-32bit-glibc-systems.patch
  50. 3 3
      recipes-devtools/clang/clang/0033-compiler-rt-Undef-_TIME_BITS-along-with-_FILE_OFFSET.patch
  51. 32 0
      recipes-devtools/clang/clang/0034-ToolChains-Gnu.cpp-ARMLibDirs-search-also-in-lib32.patch
  52. 0 36
      recipes-devtools/clang/clang/0034-compiler-rt-Undef-_TIME_BITS-along-with-_FILE_OFFSET.patch
  53. 0 70
      recipes-devtools/clang/clang/0037-clang-Call-printName-to-get-name-of-Decl.patch
  54. 14 5
      recipes-devtools/clang/clang/llvm-config
  55. 3 6
      recipes-devtools/clang/clang_17.0.0.bb
  56. 3 0
      recipes-devtools/clang/clang_17.0.0.bbappend
  57. 5 9
      recipes-devtools/clang/common.inc
  58. 1 1
      recipes-devtools/clang/compiler-rt-sanitizers_17.0.0.bb
  59. 1 1
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  60. 0 0
      recipes-devtools/clang/libclc_17.0.0.bb
  61. 0 0
      recipes-devtools/clang/libcxx_17.0.0.bb
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  63. 1 0
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  64. 14 19
      recipes-devtools/clang/llvm-project-source.bbappend
  65. 1 1
      recipes-devtools/clang/llvm-project-source.inc
  66. 0 0
      recipes-devtools/clang/openmp_17.0.0.bb
  67. 0 90
      recipes-devtools/llvm/llvm/0006-llvm-TargetLibraryInfo-Undefine-libc-functions-if-th.patch
  68. 9 9
      recipes-devtools/llvm/llvm/0007-llvm-allow-env-override-of-exe-path.patch
  69. 51 0
      recipes-devtools/llvm/llvm/llvm-config
  70. 45 62
      recipes-devtools/llvm/llvm_git.bb

+ 0 - 0
recipes-devtools/clang/clang-cross-canadian_16.0.5.bb → recipes-devtools/clang/clang-cross-canadian_17.0.0.bb


+ 0 - 0
recipes-devtools/clang/clang-cross_16.0.5.bb → recipes-devtools/clang/clang-cross_17.0.0.bb


+ 0 - 0
recipes-devtools/clang/clang-crosssdk_16.0.5.bb → recipes-devtools/clang/clang-crosssdk_17.0.0.bb


+ 4 - 5
recipes-devtools/clang/clang.inc

@@ -4,15 +4,14 @@ LLVM_DIR = "llvm${LLVM_RELEASE}"
 LLVM_GIT ?= "git://github.com/llvm"
 LLVM_GIT_PROTOCOL ?= "https"
 
-MAJOR_VER = "16"
+MAJOR_VER = "17"
 MINOR_VER = "0"
-PATCH_VER = "5"
+PATCH_VER = "0"
 
-SRCREV ?= "185b81e034ba60081023b6e59504dfffb560f3e3"
+SRCREV ?= "e19b7dc36bc047b9eb72078d034596be766da350"
 
 PV = "${MAJOR_VER}.${MINOR_VER}.${PATCH_VER}"
-#BRANCH = "release/15.x"
-BRANCH = "release/16.x"
+BRANCH = "release/17.x"
 
 LLVMMD5SUM = "8a15a0759ef07f2682d2ba4b893c9afe"
 CLANGMD5SUM = "ff42885ed2ab98f1ecb8c1fc41205343"

+ 655 - 0
recipes-devtools/clang/clang/0001-Handle-seteq-setne-conditions-for-CZERO_NEZ-CZERO_EQ.patch

@@ -0,0 +1,655 @@
+From eff753f5734bebb607696079ff7865cd292db7f7 Mon Sep 17 00:00:00 2001
+From: Craig Topper <craig.topper@sifive.com>
+Date: Wed, 26 Jul 2023 09:47:50 -0700
+Subject: [PATCH 1/8] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ
+ during isel.
+
+This removes selectSETCC and adds isel patterns for seteq/setne
+conditions.
+
+This removes the duplication of selectSETCC between lowering and
+isel. This also gets some cases in xaluo.ll that we missed previously.
+
+Reviewed By: wangpc
+
+Differential Revision: https://reviews.llvm.org/D156250
+---
+ llvm/lib/Target/RISCV/RISCVISelLowering.cpp   |  79 --------
+ .../Target/RISCV/RISCVInstrInfoXVentana.td    |   9 +
+ llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td |   9 +
+ llvm/test/CodeGen/RISCV/condops.ll            | 170 +++++++++---------
+ llvm/test/CodeGen/RISCV/xaluo.ll              |  24 ++-
+ 5 files changed, 113 insertions(+), 178 deletions(-)
+
+diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+index f030982cb815..9f702873c9aa 100644
+--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
++++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+@@ -5904,56 +5904,6 @@ static SDValue combineSelectToBinOp(SDNode *N, SelectionDAG &DAG,
+   return SDValue();
+ }
+ 
+-/// RISC-V doesn't have general instructions for integer setne/seteq, but we can
+-/// check for equality with 0. This function emits nodes that convert the
+-/// seteq/setne into something that can be compared with 0.
+-/// Based on RISCVDAGToDAGISel::selectSETCC but modified to produce
+-/// target-independent SelectionDAG nodes rather than machine nodes.
+-static SDValue selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal,
+-                           SelectionDAG &DAG) {
+-  assert(ISD::isIntEqualitySetCC(ExpectedCCVal) &&
+-         "Unexpected condition code!");
+-
+-  // We're looking for a setcc.
+-  if (N->getOpcode() != ISD::SETCC)
+-    return SDValue();
+-
+-  // Must be an equality comparison.
+-  ISD::CondCode CCVal = cast<CondCodeSDNode>(N->getOperand(2))->get();
+-  if (CCVal != ExpectedCCVal)
+-    return SDValue();
+-
+-  SDValue LHS = N->getOperand(0);
+-  SDValue RHS = N->getOperand(1);
+-
+-  if (!LHS.getValueType().isScalarInteger())
+-    return SDValue();
+-
+-  // If the RHS side is 0, we don't need any extra instructions, return the LHS.
+-  if (isNullConstant(RHS))
+-    return LHS;
+-
+-  SDLoc DL(N);
+-
+-  if (auto *C = dyn_cast<ConstantSDNode>(RHS)) {
+-    int64_t CVal = C->getSExtValue();
+-    // If the RHS is -2048, we can use xori to produce 0 if the LHS is -2048 and
+-    // non-zero otherwise.
+-    if (CVal == -2048)
+-      return DAG.getNode(ISD::XOR, DL, N->getValueType(0), LHS,
+-                         DAG.getConstant(CVal, DL, N->getValueType(0)));
+-    // If the RHS is [-2047,2048], we can use addi with -RHS to produce 0 if the
+-    // LHS is equal to the RHS and non-zero otherwise.
+-    if (isInt<12>(CVal) || CVal == 2048)
+-      return DAG.getNode(ISD::ADD, DL, N->getValueType(0), LHS,
+-                         DAG.getConstant(-CVal, DL, N->getValueType(0)));
+-  }
+-
+-  // If nothing else we can XOR the LHS and RHS to produce zero if they are
+-  // equal and a non-zero value if they aren't.
+-  return DAG.getNode(ISD::XOR, DL, N->getValueType(0), LHS, RHS);
+-}
+-
+ // Transform `binOp (select cond, x, c0), c1` where `c0` and `c1` are constants
+ // into `select cond, binOp(x, c1), binOp(c0, c1)` if profitable.
+ // For now we only consider transformation profitable if `binOp(c0, c1)` ends up
+@@ -6041,35 +5991,6 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
+   // sequence or RISCVISD::SELECT_CC node (branch-based select).
+   if ((Subtarget.hasStdExtZicond() || Subtarget.hasVendorXVentanaCondOps()) &&
+       VT.isScalarInteger()) {
+-    if (SDValue NewCondV = selectSETCC(CondV, ISD::SETNE, DAG)) {
+-      // (select (riscv_setne c), t, 0) -> (czero_eqz t, c)
+-      if (isNullConstant(FalseV))
+-        return DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, NewCondV);
+-      // (select (riscv_setne c), 0, f) -> (czero_nez f, c)
+-      if (isNullConstant(TrueV))
+-        return DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, FalseV, NewCondV);
+-      // (select (riscv_setne c), t, f) -> (or (czero_eqz t, c), (czero_nez f,
+-      // c)
+-      return DAG.getNode(
+-          ISD::OR, DL, VT,
+-          DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, NewCondV),
+-          DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, FalseV, NewCondV));
+-    }
+-    if (SDValue NewCondV =  selectSETCC(CondV, ISD::SETEQ, DAG)) {
+-      // (select (riscv_seteq c), t, 0) -> (czero_nez t, c)
+-      if (isNullConstant(FalseV))
+-        return DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, TrueV, NewCondV);
+-      // (select (riscv_seteq c), 0, f) -> (czero_eqz f, c)
+-      if (isNullConstant(TrueV))
+-        return DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, FalseV, NewCondV);
+-      // (select (riscv_seteq c), t, f) -> (or (czero_eqz f, c), (czero_nez t,
+-      // c)
+-      return DAG.getNode(
+-          ISD::OR, DL, VT,
+-          DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, FalseV, NewCondV),
+-          DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, TrueV, NewCondV));
+-    }
+-
+     // (select c, t, 0) -> (czero_eqz t, c)
+     if (isNullConstant(FalseV))
+       return DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, CondV);
+diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
+index f6b0feaf7628..b82321f94e90 100644
+--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
++++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
+@@ -33,4 +33,13 @@ def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, GPR:$rc)),
+           (VT_MASKC GPR:$rs1, GPR:$rc)>;
+ def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, GPR:$rc)),
+           (VT_MASKCN GPR:$rs1, GPR:$rc)>;
++
++def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
++          (VT_MASKC GPR:$rs1, GPR:$rc)>;
++def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
++          (VT_MASKCN GPR:$rs1, GPR:$rc)>;
++def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
++          (VT_MASKCN GPR:$rs1, GPR:$rc)>;
++def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
++          (VT_MASKC GPR:$rs1, GPR:$rc)>;
+ } // Predicates = [IsRV64, HasVendorXVentanaCondOps]
+diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
+index ab0b93d62af5..0790a941823b 100644
+--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
++++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
+@@ -40,4 +40,13 @@ def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, GPR:$rc)),
+           (CZERO_EQZ GPR:$rs1, GPR:$rc)>;
+ def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, GPR:$rc)),
+           (CZERO_NEZ GPR:$rs1, GPR:$rc)>;
++
++def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
++          (CZERO_EQZ GPR:$rs1, GPR:$rc)>;
++def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
++          (CZERO_NEZ GPR:$rs1, GPR:$rc)>;
++def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
++          (CZERO_NEZ GPR:$rs1, GPR:$rc)>;
++def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
++          (CZERO_EQZ GPR:$rs1, GPR:$rc)>;
+ } // Predicates = [HasStdExtZicond]
+diff --git a/llvm/test/CodeGen/RISCV/condops.ll b/llvm/test/CodeGen/RISCV/condops.ll
+index 19018a3e461b..a1403fc1e2e7 100644
+--- a/llvm/test/CodeGen/RISCV/condops.ll
++++ b/llvm/test/CodeGen/RISCV/condops.ll
+@@ -1086,8 +1086,8 @@ define i64 @seteq(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
+ ; RV64XVENTANACONDOPS-LABEL: seteq:
+ ; RV64XVENTANACONDOPS:       # %bb.0:
+ ; RV64XVENTANACONDOPS-NEXT:    xor a0, a0, a1
+-; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a2, a0
+-; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a3, a0
++; RV64XVENTANACONDOPS-NEXT:    vt.maskc a1, a3, a0
++; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a2, a0
+ ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
+ ; RV64XVENTANACONDOPS-NEXT:    ret
+ ;
+@@ -1103,19 +1103,19 @@ define i64 @seteq(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
+ ; RV32ZICOND-NEXT:    xor a1, a1, a3
+ ; RV32ZICOND-NEXT:    xor a0, a0, a2
+ ; RV32ZICOND-NEXT:    or a1, a0, a1
+-; RV32ZICOND-NEXT:    czero.nez a0, a4, a1
+-; RV32ZICOND-NEXT:    czero.eqz a2, a6, a1
++; RV32ZICOND-NEXT:    czero.eqz a0, a6, a1
++; RV32ZICOND-NEXT:    czero.nez a2, a4, a1
+ ; RV32ZICOND-NEXT:    or a0, a2, a0
+-; RV32ZICOND-NEXT:    czero.nez a2, a5, a1
+-; RV32ZICOND-NEXT:    czero.eqz a1, a7, a1
++; RV32ZICOND-NEXT:    czero.eqz a2, a7, a1
++; RV32ZICOND-NEXT:    czero.nez a1, a5, a1
+ ; RV32ZICOND-NEXT:    or a1, a1, a2
+ ; RV32ZICOND-NEXT:    ret
+ ;
+ ; RV64ZICOND-LABEL: seteq:
+ ; RV64ZICOND:       # %bb.0:
+ ; RV64ZICOND-NEXT:    xor a0, a0, a1
+-; RV64ZICOND-NEXT:    czero.nez a1, a2, a0
+-; RV64ZICOND-NEXT:    czero.eqz a0, a3, a0
++; RV64ZICOND-NEXT:    czero.eqz a1, a3, a0
++; RV64ZICOND-NEXT:    czero.nez a0, a2, a0
+ ; RV64ZICOND-NEXT:    or a0, a0, a1
+ ; RV64ZICOND-NEXT:    ret
+   %rc = icmp eq i64 %a, %b
+@@ -1233,11 +1233,11 @@ define i64 @setgt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
+ ; RV32ZICOND-LABEL: setgt:
+ ; RV32ZICOND:       # %bb.0:
+ ; RV32ZICOND-NEXT:    xor t0, a1, a3
+-; RV32ZICOND-NEXT:    sltu a0, a2, a0
+-; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
+ ; RV32ZICOND-NEXT:    slt a1, a3, a1
+ ; RV32ZICOND-NEXT:    czero.eqz a1, a1, t0
+-; RV32ZICOND-NEXT:    or a1, a1, a0
++; RV32ZICOND-NEXT:    sltu a0, a2, a0
++; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
++; RV32ZICOND-NEXT:    or a1, a0, a1
+ ; RV32ZICOND-NEXT:    czero.nez a0, a6, a1
+ ; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
+ ; RV32ZICOND-NEXT:    or a0, a2, a0
+@@ -1306,13 +1306,13 @@ define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
+ ; RV32ZICOND-LABEL: setge:
+ ; RV32ZICOND:       # %bb.0:
+ ; RV32ZICOND-NEXT:    xor t0, a1, a3
+-; RV32ZICOND-NEXT:    sltu a0, a0, a2
+-; RV32ZICOND-NEXT:    xori a0, a0, 1
+-; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
+ ; RV32ZICOND-NEXT:    slt a1, a1, a3
+ ; RV32ZICOND-NEXT:    xori a1, a1, 1
+ ; RV32ZICOND-NEXT:    czero.eqz a1, a1, t0
+-; RV32ZICOND-NEXT:    or a1, a1, a0
++; RV32ZICOND-NEXT:    sltu a0, a0, a2
++; RV32ZICOND-NEXT:    xori a0, a0, 1
++; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
++; RV32ZICOND-NEXT:    or a1, a0, a1
+ ; RV32ZICOND-NEXT:    czero.nez a0, a6, a1
+ ; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
+ ; RV32ZICOND-NEXT:    or a0, a2, a0
+@@ -1379,11 +1379,11 @@ define i64 @setlt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
+ ; RV32ZICOND-LABEL: setlt:
+ ; RV32ZICOND:       # %bb.0:
+ ; RV32ZICOND-NEXT:    xor t0, a1, a3
+-; RV32ZICOND-NEXT:    sltu a0, a0, a2
+-; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
+ ; RV32ZICOND-NEXT:    slt a1, a1, a3
+ ; RV32ZICOND-NEXT:    czero.eqz a1, a1, t0
+-; RV32ZICOND-NEXT:    or a1, a1, a0
++; RV32ZICOND-NEXT:    sltu a0, a0, a2
++; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
++; RV32ZICOND-NEXT:    or a1, a0, a1
+ ; RV32ZICOND-NEXT:    czero.nez a0, a6, a1
+ ; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
+ ; RV32ZICOND-NEXT:    or a0, a2, a0
+@@ -1452,13 +1452,13 @@ define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
+ ; RV32ZICOND-LABEL: setle:
+ ; RV32ZICOND:       # %bb.0:
+ ; RV32ZICOND-NEXT:    xor t0, a1, a3
+-; RV32ZICOND-NEXT:    sltu a0, a2, a0
+-; RV32ZICOND-NEXT:    xori a0, a0, 1
+-; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
+ ; RV32ZICOND-NEXT:    slt a1, a3, a1
+ ; RV32ZICOND-NEXT:    xori a1, a1, 1
+ ; RV32ZICOND-NEXT:    czero.eqz a1, a1, t0
+-; RV32ZICOND-NEXT:    or a1, a1, a0
++; RV32ZICOND-NEXT:    sltu a0, a2, a0
++; RV32ZICOND-NEXT:    xori a0, a0, 1
++; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
++; RV32ZICOND-NEXT:    or a1, a0, a1
+ ; RV32ZICOND-NEXT:    czero.nez a0, a6, a1
+ ; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
+ ; RV32ZICOND-NEXT:    or a0, a2, a0
+@@ -1525,11 +1525,11 @@ define i64 @setugt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
+ ; RV32ZICOND-LABEL: setugt:
+ ; RV32ZICOND:       # %bb.0:
+ ; RV32ZICOND-NEXT:    xor t0, a1, a3
+-; RV32ZICOND-NEXT:    sltu a0, a2, a0
+-; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
+ ; RV32ZICOND-NEXT:    sltu a1, a3, a1
+ ; RV32ZICOND-NEXT:    czero.eqz a1, a1, t0
+-; RV32ZICOND-NEXT:    or a1, a1, a0
++; RV32ZICOND-NEXT:    sltu a0, a2, a0
++; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
++; RV32ZICOND-NEXT:    or a1, a0, a1
+ ; RV32ZICOND-NEXT:    czero.nez a0, a6, a1
+ ; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
+ ; RV32ZICOND-NEXT:    or a0, a2, a0
+@@ -1598,13 +1598,13 @@ define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
+ ; RV32ZICOND-LABEL: setuge:
+ ; RV32ZICOND:       # %bb.0:
+ ; RV32ZICOND-NEXT:    xor t0, a1, a3
+-; RV32ZICOND-NEXT:    sltu a0, a0, a2
+-; RV32ZICOND-NEXT:    xori a0, a0, 1
+-; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
+ ; RV32ZICOND-NEXT:    sltu a1, a1, a3
+ ; RV32ZICOND-NEXT:    xori a1, a1, 1
+ ; RV32ZICOND-NEXT:    czero.eqz a1, a1, t0
+-; RV32ZICOND-NEXT:    or a1, a1, a0
++; RV32ZICOND-NEXT:    sltu a0, a0, a2
++; RV32ZICOND-NEXT:    xori a0, a0, 1
++; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
++; RV32ZICOND-NEXT:    or a1, a0, a1
+ ; RV32ZICOND-NEXT:    czero.nez a0, a6, a1
+ ; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
+ ; RV32ZICOND-NEXT:    or a0, a2, a0
+@@ -1671,11 +1671,11 @@ define i64 @setult(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
+ ; RV32ZICOND-LABEL: setult:
+ ; RV32ZICOND:       # %bb.0:
+ ; RV32ZICOND-NEXT:    xor t0, a1, a3
+-; RV32ZICOND-NEXT:    sltu a0, a0, a2
+-; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
+ ; RV32ZICOND-NEXT:    sltu a1, a1, a3
+ ; RV32ZICOND-NEXT:    czero.eqz a1, a1, t0
+-; RV32ZICOND-NEXT:    or a1, a1, a0
++; RV32ZICOND-NEXT:    sltu a0, a0, a2
++; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
++; RV32ZICOND-NEXT:    or a1, a0, a1
+ ; RV32ZICOND-NEXT:    czero.nez a0, a6, a1
+ ; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
+ ; RV32ZICOND-NEXT:    or a0, a2, a0
+@@ -1744,13 +1744,13 @@ define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
+ ; RV32ZICOND-LABEL: setule:
+ ; RV32ZICOND:       # %bb.0:
+ ; RV32ZICOND-NEXT:    xor t0, a1, a3
+-; RV32ZICOND-NEXT:    sltu a0, a2, a0
+-; RV32ZICOND-NEXT:    xori a0, a0, 1
+-; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
+ ; RV32ZICOND-NEXT:    sltu a1, a3, a1
+ ; RV32ZICOND-NEXT:    xori a1, a1, 1
+ ; RV32ZICOND-NEXT:    czero.eqz a1, a1, t0
+-; RV32ZICOND-NEXT:    or a1, a1, a0
++; RV32ZICOND-NEXT:    sltu a0, a2, a0
++; RV32ZICOND-NEXT:    xori a0, a0, 1
++; RV32ZICOND-NEXT:    czero.nez a0, a0, t0
++; RV32ZICOND-NEXT:    or a1, a0, a1
+ ; RV32ZICOND-NEXT:    czero.nez a0, a6, a1
+ ; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
+ ; RV32ZICOND-NEXT:    or a0, a2, a0
+@@ -1795,9 +1795,9 @@ define i64 @seteq_zero(i64 %a, i64 %rs1, i64 %rs2) {
+ ;
+ ; RV64XVENTANACONDOPS-LABEL: seteq_zero:
+ ; RV64XVENTANACONDOPS:       # %bb.0:
+-; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a1, a0
+-; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
+-; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
++; RV64XVENTANACONDOPS-NEXT:    vt.maskc a2, a2, a0
++; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a1, a0
++; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a2
+ ; RV64XVENTANACONDOPS-NEXT:    ret
+ ;
+ ; RV64XTHEADCONDMOV-LABEL: seteq_zero:
+@@ -1809,19 +1809,19 @@ define i64 @seteq_zero(i64 %a, i64 %rs1, i64 %rs2) {
+ ; RV32ZICOND-LABEL: seteq_zero:
+ ; RV32ZICOND:       # %bb.0:
+ ; RV32ZICOND-NEXT:    or a1, a0, a1
+-; RV32ZICOND-NEXT:    czero.nez a0, a2, a1
+-; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
++; RV32ZICOND-NEXT:    czero.eqz a0, a4, a1
++; RV32ZICOND-NEXT:    czero.nez a2, a2, a1
+ ; RV32ZICOND-NEXT:    or a0, a2, a0
+-; RV32ZICOND-NEXT:    czero.nez a2, a3, a1
+-; RV32ZICOND-NEXT:    czero.eqz a1, a5, a1
++; RV32ZICOND-NEXT:    czero.eqz a2, a5, a1
++; RV32ZICOND-NEXT:    czero.nez a1, a3, a1
+ ; RV32ZICOND-NEXT:    or a1, a1, a2
+ ; RV32ZICOND-NEXT:    ret
+ ;
+ ; RV64ZICOND-LABEL: seteq_zero:
+ ; RV64ZICOND:       # %bb.0:
+-; RV64ZICOND-NEXT:    czero.nez a1, a1, a0
+-; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+-; RV64ZICOND-NEXT:    or a0, a0, a1
++; RV64ZICOND-NEXT:    czero.eqz a2, a2, a0
++; RV64ZICOND-NEXT:    czero.nez a0, a1, a0
++; RV64ZICOND-NEXT:    or a0, a0, a2
+ ; RV64ZICOND-NEXT:    ret
+   %rc = icmp eq i64 %a, 0
+   %sel = select i1 %rc, i64 %rs1, i64 %rs2
+@@ -1912,9 +1912,9 @@ define i64 @seteq_constant(i64 %a, i64 %rs1, i64 %rs2) {
+ ; RV64XVENTANACONDOPS-LABEL: seteq_constant:
+ ; RV64XVENTANACONDOPS:       # %bb.0:
+ ; RV64XVENTANACONDOPS-NEXT:    addi a0, a0, -123
+-; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a1, a0
+-; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
+-; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
++; RV64XVENTANACONDOPS-NEXT:    vt.maskc a2, a2, a0
++; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a1, a0
++; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a2
+ ; RV64XVENTANACONDOPS-NEXT:    ret
+ ;
+ ; RV64XTHEADCONDMOV-LABEL: seteq_constant:
+@@ -1928,20 +1928,20 @@ define i64 @seteq_constant(i64 %a, i64 %rs1, i64 %rs2) {
+ ; RV32ZICOND:       # %bb.0:
+ ; RV32ZICOND-NEXT:    xori a0, a0, 123
+ ; RV32ZICOND-NEXT:    or a1, a0, a1
+-; RV32ZICOND-NEXT:    czero.nez a0, a2, a1
+-; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
++; RV32ZICOND-NEXT:    czero.eqz a0, a4, a1
++; RV32ZICOND-NEXT:    czero.nez a2, a2, a1
+ ; RV32ZICOND-NEXT:    or a0, a2, a0
+-; RV32ZICOND-NEXT:    czero.nez a2, a3, a1
+-; RV32ZICOND-NEXT:    czero.eqz a1, a5, a1
++; RV32ZICOND-NEXT:    czero.eqz a2, a5, a1
++; RV32ZICOND-NEXT:    czero.nez a1, a3, a1
+ ; RV32ZICOND-NEXT:    or a1, a1, a2
+ ; RV32ZICOND-NEXT:    ret
+ ;
+ ; RV64ZICOND-LABEL: seteq_constant:
+ ; RV64ZICOND:       # %bb.0:
+ ; RV64ZICOND-NEXT:    addi a0, a0, -123
+-; RV64ZICOND-NEXT:    czero.nez a1, a1, a0
+-; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+-; RV64ZICOND-NEXT:    or a0, a0, a1
++; RV64ZICOND-NEXT:    czero.eqz a2, a2, a0
++; RV64ZICOND-NEXT:    czero.nez a0, a1, a0
++; RV64ZICOND-NEXT:    or a0, a0, a2
+ ; RV64ZICOND-NEXT:    ret
+   %rc = icmp eq i64 %a, 123
+   %sel = select i1 %rc, i64 %rs1, i64 %rs2
+@@ -2041,9 +2041,9 @@ define i64 @seteq_2048(i64 %a, i64 %rs1, i64 %rs2) {
+ ; RV64XVENTANACONDOPS-LABEL: seteq_2048:
+ ; RV64XVENTANACONDOPS:       # %bb.0:
+ ; RV64XVENTANACONDOPS-NEXT:    addi a0, a0, -2048
+-; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a1, a0
+-; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
+-; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
++; RV64XVENTANACONDOPS-NEXT:    vt.maskc a2, a2, a0
++; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a1, a0
++; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a2
+ ; RV64XVENTANACONDOPS-NEXT:    ret
+ ;
+ ; RV64XTHEADCONDMOV-LABEL: seteq_2048:
+@@ -2059,20 +2059,20 @@ define i64 @seteq_2048(i64 %a, i64 %rs1, i64 %rs2) {
+ ; RV32ZICOND-NEXT:    slli a6, a6, 11
+ ; RV32ZICOND-NEXT:    xor a0, a0, a6
+ ; RV32ZICOND-NEXT:    or a1, a0, a1
+-; RV32ZICOND-NEXT:    czero.nez a0, a2, a1
+-; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
++; RV32ZICOND-NEXT:    czero.eqz a0, a4, a1
++; RV32ZICOND-NEXT:    czero.nez a2, a2, a1
+ ; RV32ZICOND-NEXT:    or a0, a2, a0
+-; RV32ZICOND-NEXT:    czero.nez a2, a3, a1
+-; RV32ZICOND-NEXT:    czero.eqz a1, a5, a1
++; RV32ZICOND-NEXT:    czero.eqz a2, a5, a1
++; RV32ZICOND-NEXT:    czero.nez a1, a3, a1
+ ; RV32ZICOND-NEXT:    or a1, a1, a2
+ ; RV32ZICOND-NEXT:    ret
+ ;
+ ; RV64ZICOND-LABEL: seteq_2048:
+ ; RV64ZICOND:       # %bb.0:
+ ; RV64ZICOND-NEXT:    addi a0, a0, -2048
+-; RV64ZICOND-NEXT:    czero.nez a1, a1, a0
+-; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+-; RV64ZICOND-NEXT:    or a0, a0, a1
++; RV64ZICOND-NEXT:    czero.eqz a2, a2, a0
++; RV64ZICOND-NEXT:    czero.nez a0, a1, a0
++; RV64ZICOND-NEXT:    or a0, a0, a2
+ ; RV64ZICOND-NEXT:    ret
+   %rc = icmp eq i64 %a, 2048
+   %sel = select i1 %rc, i64 %rs1, i64 %rs2
+@@ -2107,9 +2107,9 @@ define i64 @seteq_neg2048(i64 %a, i64 %rs1, i64 %rs2) {
+ ; RV64XVENTANACONDOPS-LABEL: seteq_neg2048:
+ ; RV64XVENTANACONDOPS:       # %bb.0:
+ ; RV64XVENTANACONDOPS-NEXT:    xori a0, a0, -2048
+-; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a1, a0
+-; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a2, a0
+-; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
++; RV64XVENTANACONDOPS-NEXT:    vt.maskc a2, a2, a0
++; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a1, a0
++; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a2
+ ; RV64XVENTANACONDOPS-NEXT:    ret
+ ;
+ ; RV64XTHEADCONDMOV-LABEL: seteq_neg2048:
+@@ -2124,20 +2124,20 @@ define i64 @seteq_neg2048(i64 %a, i64 %rs1, i64 %rs2) {
+ ; RV32ZICOND-NEXT:    not a1, a1
+ ; RV32ZICOND-NEXT:    xori a0, a0, -2048
+ ; RV32ZICOND-NEXT:    or a1, a0, a1
+-; RV32ZICOND-NEXT:    czero.nez a0, a2, a1
+-; RV32ZICOND-NEXT:    czero.eqz a2, a4, a1
++; RV32ZICOND-NEXT:    czero.eqz a0, a4, a1
++; RV32ZICOND-NEXT:    czero.nez a2, a2, a1
+ ; RV32ZICOND-NEXT:    or a0, a2, a0
+-; RV32ZICOND-NEXT:    czero.nez a2, a3, a1
+-; RV32ZICOND-NEXT:    czero.eqz a1, a5, a1
++; RV32ZICOND-NEXT:    czero.eqz a2, a5, a1
++; RV32ZICOND-NEXT:    czero.nez a1, a3, a1
+ ; RV32ZICOND-NEXT:    or a1, a1, a2
+ ; RV32ZICOND-NEXT:    ret
+ ;
+ ; RV64ZICOND-LABEL: seteq_neg2048:
+ ; RV64ZICOND:       # %bb.0:
+ ; RV64ZICOND-NEXT:    xori a0, a0, -2048
+-; RV64ZICOND-NEXT:    czero.nez a1, a1, a0
+-; RV64ZICOND-NEXT:    czero.eqz a0, a2, a0
+-; RV64ZICOND-NEXT:    or a0, a0, a1
++; RV64ZICOND-NEXT:    czero.eqz a2, a2, a0
++; RV64ZICOND-NEXT:    czero.nez a0, a1, a0
++; RV64ZICOND-NEXT:    or a0, a0, a2
+ ; RV64ZICOND-NEXT:    ret
+   %rc = icmp eq i64 %a, -2048
+   %sel = select i1 %rc, i64 %rs1, i64 %rs2
+@@ -3466,9 +3466,9 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2,
+ ; RV64XVENTANACONDOPS-NEXT:    addi sp, sp, -16
+ ; RV64XVENTANACONDOPS-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+ ; RV64XVENTANACONDOPS-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
+-; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a3, a3, a0
+-; RV64XVENTANACONDOPS-NEXT:    vt.maskc s0, a2, a0
+-; RV64XVENTANACONDOPS-NEXT:    or s0, s0, a3
++; RV64XVENTANACONDOPS-NEXT:    vt.maskc a2, a2, a0
++; RV64XVENTANACONDOPS-NEXT:    vt.maskcn s0, a3, a0
++; RV64XVENTANACONDOPS-NEXT:    or s0, s0, a2
+ ; RV64XVENTANACONDOPS-NEXT:    beqz a1, .LBB58_2
+ ; RV64XVENTANACONDOPS-NEXT:  # %bb.1:
+ ; RV64XVENTANACONDOPS-NEXT:    mv a0, s0
+@@ -3503,9 +3503,9 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2,
+ ; RV32ZICOND-NEXT:    addi sp, sp, -16
+ ; RV32ZICOND-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+ ; RV32ZICOND-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+-; RV32ZICOND-NEXT:    czero.nez a3, a3, a0
+-; RV32ZICOND-NEXT:    czero.eqz s0, a2, a0
+-; RV32ZICOND-NEXT:    or s0, s0, a3
++; RV32ZICOND-NEXT:    czero.eqz a2, a2, a0
++; RV32ZICOND-NEXT:    czero.nez s0, a3, a0
++; RV32ZICOND-NEXT:    or s0, s0, a2
+ ; RV32ZICOND-NEXT:    beqz a1, .LBB58_2
+ ; RV32ZICOND-NEXT:  # %bb.1:
+ ; RV32ZICOND-NEXT:    mv a0, s0
+@@ -3522,9 +3522,9 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2,
+ ; RV64ZICOND-NEXT:    addi sp, sp, -16
+ ; RV64ZICOND-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+ ; RV64ZICOND-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
+-; RV64ZICOND-NEXT:    czero.nez a3, a3, a0
+-; RV64ZICOND-NEXT:    czero.eqz s0, a2, a0
+-; RV64ZICOND-NEXT:    or s0, s0, a3
++; RV64ZICOND-NEXT:    czero.eqz a2, a2, a0
++; RV64ZICOND-NEXT:    czero.nez s0, a3, a0
++; RV64ZICOND-NEXT:    or s0, s0, a2
+ ; RV64ZICOND-NEXT:    beqz a1, .LBB58_2
+ ; RV64ZICOND-NEXT:  # %bb.1:
+ ; RV64ZICOND-NEXT:    mv a0, s0
+diff --git a/llvm/test/CodeGen/RISCV/xaluo.ll b/llvm/test/CodeGen/RISCV/xaluo.ll
+index 5d47ea4e9a6c..6786f440e713 100644
+--- a/llvm/test/CodeGen/RISCV/xaluo.ll
++++ b/llvm/test/CodeGen/RISCV/xaluo.ll
+@@ -664,7 +664,7 @@ define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, ptr %res) {
+ ; RV32ZICOND-NEXT:    sltu a1, a3, a1
+ ; RV32ZICOND-NEXT:    czero.eqz a1, a1, a5
+ ; RV32ZICOND-NEXT:    czero.nez a0, a0, a5
+-; RV32ZICOND-NEXT:    or a0, a1, a0
++; RV32ZICOND-NEXT:    or a0, a0, a1
+ ; RV32ZICOND-NEXT:    sw a2, 0(a4)
+ ; RV32ZICOND-NEXT:    sw a3, 4(a4)
+ ; RV32ZICOND-NEXT:    ret
+@@ -1159,7 +1159,7 @@ define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, ptr %res) {
+ ; RV32ZICOND-NEXT:    sub a2, a0, a2
+ ; RV32ZICOND-NEXT:    sltu a0, a0, a2
+ ; RV32ZICOND-NEXT:    czero.nez a0, a0, a5
+-; RV32ZICOND-NEXT:    or a0, a1, a0
++; RV32ZICOND-NEXT:    or a0, a0, a1
+ ; RV32ZICOND-NEXT:    sw a2, 0(a4)
+ ; RV32ZICOND-NEXT:    sw a3, 4(a4)
+ ; RV32ZICOND-NEXT:    ret
+@@ -2529,7 +2529,7 @@ define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
+ ; RV32ZICOND-NEXT:    sltu a4, a4, a1
+ ; RV32ZICOND-NEXT:    czero.eqz a4, a4, a6
+ ; RV32ZICOND-NEXT:    czero.nez a5, a5, a6
+-; RV32ZICOND-NEXT:    or a4, a4, a5
++; RV32ZICOND-NEXT:    or a4, a5, a4
+ ; RV32ZICOND-NEXT:    czero.nez a2, a2, a4
+ ; RV32ZICOND-NEXT:    czero.eqz a0, a0, a4
+ ; RV32ZICOND-NEXT:    or a0, a0, a2
+@@ -2604,7 +2604,7 @@ define i1 @uaddo.not.i64(i64 %v1, i64 %v2) {
+ ; RV32ZICOND-NEXT:    sltu a1, a3, a1
+ ; RV32ZICOND-NEXT:    czero.eqz a1, a1, a2
+ ; RV32ZICOND-NEXT:    czero.nez a0, a0, a2
+-; RV32ZICOND-NEXT:    or a0, a1, a0
++; RV32ZICOND-NEXT:    or a0, a0, a1
+ ; RV32ZICOND-NEXT:    xori a0, a0, 1
+ ; RV32ZICOND-NEXT:    ret
+ ;
+@@ -3086,7 +3086,7 @@ define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
+ ; RV32ZICOND-NEXT:    sub a6, a0, a2
+ ; RV32ZICOND-NEXT:    sltu a6, a0, a6
+ ; RV32ZICOND-NEXT:    czero.nez a4, a6, a4
+-; RV32ZICOND-NEXT:    or a4, a5, a4
++; RV32ZICOND-NEXT:    or a4, a4, a5
+ ; RV32ZICOND-NEXT:    czero.nez a2, a2, a4
+ ; RV32ZICOND-NEXT:    czero.eqz a0, a0, a4
+ ; RV32ZICOND-NEXT:    or a0, a0, a2
+@@ -3168,7 +3168,7 @@ define i1 @usubo.not.i64(i64 %v1, i64 %v2) {
+ ; RV32ZICOND-NEXT:    sub a2, a0, a2
+ ; RV32ZICOND-NEXT:    sltu a0, a0, a2
+ ; RV32ZICOND-NEXT:    czero.nez a0, a0, a4
+-; RV32ZICOND-NEXT:    or a0, a1, a0
++; RV32ZICOND-NEXT:    or a0, a0, a1
+ ; RV32ZICOND-NEXT:    xori a0, a0, 1
+ ; RV32ZICOND-NEXT:    ret
+ ;
+@@ -3234,7 +3234,6 @@ define i32 @smulo.select.i32(i32 signext %v1, i32 signext %v2) {
+ ; RV32ZICOND-NEXT:    mul a3, a0, a1
+ ; RV32ZICOND-NEXT:    srai a3, a3, 31
+ ; RV32ZICOND-NEXT:    xor a2, a2, a3
+-; RV32ZICOND-NEXT:    snez a2, a2
+ ; RV32ZICOND-NEXT:    czero.nez a1, a1, a2
+ ; RV32ZICOND-NEXT:    czero.eqz a0, a0, a2
+ ; RV32ZICOND-NEXT:    or a0, a0, a1
+@@ -3518,7 +3517,6 @@ define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
+ ; RV64ZICOND-NEXT:    mul a3, a0, a1
+ ; RV64ZICOND-NEXT:    srai a3, a3, 63
+ ; RV64ZICOND-NEXT:    xor a2, a2, a3
+-; RV64ZICOND-NEXT:    snez a2, a2
+ ; RV64ZICOND-NEXT:    czero.nez a1, a1, a2
+ ; RV64ZICOND-NEXT:    czero.eqz a0, a0, a2
+ ; RV64ZICOND-NEXT:    or a0, a0, a1
+@@ -3772,7 +3770,6 @@ define i32 @umulo.select.i32(i32 signext %v1, i32 signext %v2) {
+ ; RV32ZICOND-LABEL: umulo.select.i32:
+ ; RV32ZICOND:       # %bb.0: # %entry
+ ; RV32ZICOND-NEXT:    mulhu a2, a0, a1
+-; RV32ZICOND-NEXT:    snez a2, a2
+ ; RV32ZICOND-NEXT:    czero.nez a1, a1, a2
+ ; RV32ZICOND-NEXT:    czero.eqz a0, a0, a2
+ ; RV32ZICOND-NEXT:    or a0, a0, a1
+@@ -3945,7 +3942,6 @@ define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
+ ; RV64ZICOND-LABEL: umulo.select.i64:
+ ; RV64ZICOND:       # %bb.0: # %entry
+ ; RV64ZICOND-NEXT:    mulhu a2, a0, a1
+-; RV64ZICOND-NEXT:    snez a2, a2
+ ; RV64ZICOND-NEXT:    czero.nez a1, a1, a2
+ ; RV64ZICOND-NEXT:    czero.eqz a0, a0, a2
+ ; RV64ZICOND-NEXT:    or a0, a0, a1
+@@ -4394,7 +4390,7 @@ define zeroext i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
+ ; RV32ZICOND-NEXT:    sltu a1, a3, a1
+ ; RV32ZICOND-NEXT:    czero.eqz a1, a1, a2
+ ; RV32ZICOND-NEXT:    czero.nez a0, a0, a2
+-; RV32ZICOND-NEXT:    or a0, a1, a0
++; RV32ZICOND-NEXT:    or a0, a0, a1
+ ; RV32ZICOND-NEXT:    beqz a0, .LBB55_2
+ ; RV32ZICOND-NEXT:  # %bb.1: # %overflow
+ ; RV32ZICOND-NEXT:    li a0, 0
+@@ -4767,7 +4763,7 @@ define zeroext i1 @usubo.br.i64(i64 %v1, i64 %v2) {
+ ; RV32ZICOND-NEXT:    sub a2, a0, a2
+ ; RV32ZICOND-NEXT:    sltu a0, a0, a2
+ ; RV32ZICOND-NEXT:    czero.nez a0, a0, a4
+-; RV32ZICOND-NEXT:    or a0, a1, a0
++; RV32ZICOND-NEXT:    or a0, a0, a1
+ ; RV32ZICOND-NEXT:    beqz a0, .LBB59_2
+ ; RV32ZICOND-NEXT:  # %bb.1: # %overflow
+ ; RV32ZICOND-NEXT:    li a0, 0
+@@ -5596,10 +5592,10 @@ define zeroext i1 @umulo2.br.i64(i64 %v1) {
+ ; RV32ZICOND-NEXT:    add a2, a1, a1
+ ; RV32ZICOND-NEXT:    add a2, a2, a0
+ ; RV32ZICOND-NEXT:    xor a3, a2, a1
+-; RV32ZICOND-NEXT:    czero.nez a0, a0, a3
+ ; RV32ZICOND-NEXT:    sltu a1, a2, a1
+ ; RV32ZICOND-NEXT:    czero.eqz a1, a1, a3
+-; RV32ZICOND-NEXT:    or a0, a1, a0
++; RV32ZICOND-NEXT:    czero.nez a0, a0, a3
++; RV32ZICOND-NEXT:    or a0, a0, a1
+ ; RV32ZICOND-NEXT:    beqz a0, .LBB65_2
+ ; RV32ZICOND-NEXT:  # %bb.1: # %overflow
+ ; RV32ZICOND-NEXT:    li a0, 0
+-- 
+2.25.1
+

+ 9 - 9
recipes-devtools/clang/clang/0001-libcxxabi-Find-libunwind-headers-when-LIBCXXABI_LIBU.patch

@@ -1,4 +1,4 @@
-From 60d418bdd291f061e32a73ffee7ad7acc27a4768 Mon Sep 17 00:00:00 2001
+From 6a743f488230aa025016396208d1760835495264 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Sun, 27 Aug 2017 10:37:49 -0700
 Subject: [PATCH] libcxxabi: Find libunwind headers when
@@ -18,10 +18,10 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 11 insertions(+), 5 deletions(-)
 
 diff --git a/libcxxabi/CMakeLists.txt b/libcxxabi/CMakeLists.txt
-index 8f48d402bc22..c2470267d8e3 100644
+index f380fe6b6b92..145cb9d7ee88 100644
 --- a/libcxxabi/CMakeLists.txt
 +++ b/libcxxabi/CMakeLists.txt
-@@ -483,7 +483,7 @@ set(LIBCXXABI_LIBUNWIND_PATH "${LIBCXXABI_LIBUNWIND_PATH}" CACHE PATH
+@@ -426,7 +426,7 @@ set(LIBCXXABI_LIBUNWIND_PATH "${LIBCXXABI_LIBUNWIND_PATH}" CACHE PATH
      "Specify path to libunwind source." FORCE)
  
  if (LIBCXXABI_USE_LLVM_UNWINDER OR LLVM_NATIVE_ARCH MATCHES ARM)
@@ -30,7 +30,7 @@ index 8f48d402bc22..c2470267d8e3 100644
      PATHS ${LIBCXXABI_LIBUNWIND_INCLUDES}
            ${LIBCXXABI_LIBUNWIND_PATH}/include
            ${CMAKE_BINARY_DIR}/${LIBCXXABI_LIBUNWIND_INCLUDES}
-@@ -494,15 +494,21 @@ if (LIBCXXABI_USE_LLVM_UNWINDER OR LLVM_NATIVE_ARCH MATCHES ARM)
+@@ -437,15 +437,21 @@ if (LIBCXXABI_USE_LLVM_UNWINDER OR LLVM_NATIVE_ARCH MATCHES ARM)
      NO_CMAKE_FIND_ROOT_PATH
    )
  
@@ -39,12 +39,12 @@ index 8f48d402bc22..c2470267d8e3 100644
 +  if (LIBCXXABI_LIBUNWIND_INCLUDES STREQUAL "LIBCXXABI_LIBUNWIND_INCLUDES-NOTFOUND")
 +    set(LIBCXXABI_LIBUNWIND_INCLUDES "")
    endif()
+ endif()
  
--  if (NOT LIBCXXABI_LIBUNWIND_INCLUDES_INTERNAL STREQUAL "")
--    include_directories("${LIBCXXABI_LIBUNWIND_INCLUDES_INTERNAL}")
-+  if (NOT LIBCXXABI_LIBUNWIND_INCLUDES STREQUAL "")
-+    include_directories("${LIBCXXABI_LIBUNWIND_INCLUDES}")
-   endif()
+-if (NOT "${LIBCXXABI_LIBUNWIND_INCLUDES_INTERNAL}" STREQUAL "")
+-  include_directories("${LIBCXXABI_LIBUNWIND_INCLUDES_INTERNAL}")
++if (NOT "${LIBCXXABI_LIBUNWIND_INCLUDES}" STREQUAL "")
++  include_directories("${LIBCXXABI_LIBUNWIND_INCLUDES}")
  endif()
  
 +set(LIBCXXABI_LIBUNWIND_INCLUDES "${LIBCXXABI_LIBUNWIND_INCLUDES}" CACHE PATH

+ 1 - 1
recipes-devtools/clang/clang/0002-compiler-rt-support-a-new-embedded-linux-target.patch

@@ -1,4 +1,4 @@
-From f205cf35a9ad116b291b2b36a50800e4573e6ac6 Mon Sep 17 00:00:00 2001
+From 25b8166b829bc987832a7c7b41581f193a4fabe9 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Sun, 19 Apr 2015 15:16:23 -0700
 Subject: [PATCH] compiler-rt: support a new embedded linux target

+ 0 - 1278
recipes-devtools/clang/clang/0002-neon2rvv-Model-vxrm-in-LLVM-intrinsics-and-add-optim.patch

@@ -1,1278 +0,0 @@
-From 29318f779da9c962af60d574b19159ecc10cfdd7 Mon Sep 17 00:00:00 2001
-From: Eric Tang <eric.tang@starfivetech.com>
-Date: Thu, 15 Jun 2023 09:30:16 +0800
-Subject: [PATCH 2/9] [neon2rvv] Model vxrm in LLVM intrinsics and add
- optimization for removing redundant csrwi
-
-Signed-off-by: Eric Tang <eric.tang@starfivetech.com>
----
- clang/include/clang/Basic/riscv_vector.td     | 134 +++++-
- llvm/include/llvm/IR/IntrinsicsRISCV.td       |  94 +++-
- llvm/lib/Target/RISCV/CMakeLists.txt          |   1 +
- .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |   8 +
- llvm/lib/Target/RISCV/RISCV.h                 |   3 +
- .../Target/RISCV/RISCVInsertReadWriteCSR.cpp  | 115 +++++
- llvm/lib/Target/RISCV/RISCVInstrFormats.td    |   3 +
- llvm/lib/Target/RISCV/RISCVInstrInfo.td       |   2 +
- .../Target/RISCV/RISCVInstrInfoVPseudos.td    | 428 +++++++++++++++++-
- llvm/lib/Target/RISCV/RISCVMCInstLower.cpp    |   2 +
- llvm/lib/Target/RISCV/RISCVSystemOperands.td  |   2 +-
- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp  |   2 +
- 12 files changed, 747 insertions(+), 47 deletions(-)
- create mode 100644 llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
-
-diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
-index b23e26ecaa57..9d443be0403c 100644
---- a/clang/include/clang/Basic/riscv_vector.td
-+++ b/clang/include/clang/Basic/riscv_vector.td
-@@ -316,11 +316,21 @@ multiclass RVVSignedBinBuiltinSet
-                           [["vv", "v", "vvv"],
-                            ["vx", "v", "vve"]]>;
- 
-+multiclass RVVSignedBinBuiltinSetRoundingMode
-+    : RVVOutOp1BuiltinSet<NAME, "csil",
-+                          [["vv", "v", "vvvu"],
-+                           ["vx", "v", "vveu"]]>;
-+
- multiclass RVVUnsignedBinBuiltinSet
-     : RVVOutOp1BuiltinSet<NAME, "csil",
-                           [["vv", "Uv", "UvUvUv"],
-                            ["vx", "Uv", "UvUvUe"]]>;
- 
-+multiclass RVVUnsignedBinBuiltinSetRoundingMode
-+    : RVVOutOp1BuiltinSet<NAME, "csil",
-+                          [["vv", "Uv", "UvUvUvu"],
-+                           ["vx", "Uv", "UvUvUeu"]]>;
-+
- multiclass RVVIntBinBuiltinSet
-     : RVVSignedBinBuiltinSet,
-       RVVUnsignedBinBuiltinSet;
-@@ -335,11 +345,21 @@ multiclass RVVSignedShiftBuiltinSet
-                           [["vv", "v", "vvUv"],
-                            ["vx", "v", "vvz"]]>;
- 
-+multiclass RVVSignedShiftBuiltinSetRoundingMode
-+    : RVVOutOp1BuiltinSet<NAME, "csil",
-+                          [["vv", "v", "vvUvu"],
-+                           ["vx", "v", "vvzu"]]>;
-+
- multiclass RVVUnsignedShiftBuiltinSet
-     : RVVOutOp1BuiltinSet<NAME, "csil",
-                           [["vv", "Uv", "UvUvUv"],
-                            ["vx", "Uv", "UvUvz"]]>;
- 
-+multiclass RVVUnsignedShiftBuiltinSetRoundingMode
-+    : RVVOutOp1BuiltinSet<NAME, "csil",
-+                          [["vv", "Uv", "UvUvUvu"],
-+                           ["vx", "Uv", "UvUvzu"]]>;
-+
- multiclass RVVShiftBuiltinSet
-     : RVVSignedShiftBuiltinSet,
-       RVVUnsignedShiftBuiltinSet;
-@@ -349,10 +369,18 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
-       : RVVOutOp0Op1BuiltinSet<NAME, "csil",
-                                      [["wv", "v", "vwUv"],
-                                       ["wx", "v", "vwz"]]>;
-+  multiclass RVVSignedNShiftBuiltinSetRoundingMode
-+      : RVVOutOp0Op1BuiltinSet<NAME, "csil",
-+                                     [["wv", "v", "vwUvu"],
-+                                      ["wx", "v", "vwzu"]]>;
-   multiclass RVVUnsignedNShiftBuiltinSet
-       : RVVOutOp0Op1BuiltinSet<NAME, "csil",
-                                      [["wv", "Uv", "UvUwUv"],
-                                       ["wx", "Uv", "UvUwz"]]>;
-+  multiclass RVVUnsignedNShiftBuiltinSetRoundingMode
-+      : RVVOutOp0Op1BuiltinSet<NAME, "csil",
-+                                     [["wv", "Uv", "UvUwUvu"],
-+                                      ["wx", "Uv", "UvUwzu"]]>;
- }
- 
- multiclass RVVCarryinBuiltinSet
-@@ -1928,6 +1956,17 @@ let HasMasked = false,
- }
- 
- // 13. Vector Fixed-Point Arithmetic Instructions
-+let HeaderCode =
-+[{
-+enum __RISCV_VXRM {
-+  __RISCV_VXRM_RNU = 0,
-+  __RISCV_VXRM_RNE = 1,
-+  __RISCV_VXRM_RDN = 2,
-+  __RISCV_VXRM_ROD = 3,
-+};
-+}] in
-+def vxrm_enum : RVVHeader;
-+
- // 13.1. Vector Single-Width Saturating Add and Subtract
- let UnMaskedPolicyScheme = HasPassthruOperand in {
- defm vsaddu : RVVUnsignedBinBuiltinSet;
-@@ -1936,23 +1975,94 @@ defm vssubu : RVVUnsignedBinBuiltinSet;
- defm vssub : RVVSignedBinBuiltinSet;
- 
- // 13.2. Vector Single-Width Averaging Add and Subtract
--defm vaaddu : RVVUnsignedBinBuiltinSet;
--defm vaadd : RVVSignedBinBuiltinSet;
--defm vasubu : RVVUnsignedBinBuiltinSet;
--defm vasub : RVVSignedBinBuiltinSet;
-+let ManualCodegen = [{
-+  {
-+    // LLVM intrinsic
-+    // Unmasked: (passthru, op0, op1, round_mode, vl)
-+    // Masked:   (passthru, vector_in, vector_in/scalar_in, mask, vxrm, vl, policy)
-+
-+    SmallVector<llvm::Value*, 7> Operands;
-+    bool HasMaskedOff = !(
-+        (IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
-+        (!IsMasked && PolicyAttrs & RVV_VTA));
-+    unsigned Offset = IsMasked ?
-+        (HasMaskedOff ? 2 : 1) : (HasMaskedOff ? 1 : 0);
-+
-+    if (!HasMaskedOff)
-+      Operands.push_back(llvm::PoisonValue::get(ResultType));
-+    else
-+      Operands.push_back(Ops[Offset]);
-+
-+    Operands.push_back(Ops[Offset]); // op0
-+    Operands.push_back(Ops[Offset + 1]); // op1
-+
-+    if (IsMasked)
-+      Operands.push_back(Ops[0]); // mask
-+
-+    Operands.push_back(Ops[Offset + 2]); // vxrm
-+    Operands.push_back(Ops[Offset + 3]); // vl
-+
-+    if (IsMasked)
-+      Operands.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
-+
-+    IntrinsicTypes = {ResultType, Ops[Offset + 1]->getType(), Ops.back()->getType()};
-+    llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
-+    return Builder.CreateCall(F, Operands, "");
-+  }
-+}] in {
-+  defm vaaddu : RVVUnsignedBinBuiltinSetRoundingMode;
-+  defm vaadd : RVVSignedBinBuiltinSetRoundingMode;
-+  defm vasubu : RVVUnsignedBinBuiltinSetRoundingMode;
-+  defm vasub : RVVSignedBinBuiltinSetRoundingMode;
- 
- // 13.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
--let RequiredFeatures = ["FullMultiply"] in {
--defm vsmul : RVVSignedBinBuiltinSet;
--}
-+  let RequiredFeatures = ["FullMultiply"] in {
-+    defm vsmul : RVVSignedBinBuiltinSetRoundingMode;
-+  }
- 
- // 13.4. Vector Single-Width Scaling Shift Instructions
--defm vssrl : RVVUnsignedShiftBuiltinSet;
--defm vssra : RVVSignedShiftBuiltinSet;
--
-+  defm vssrl : RVVUnsignedShiftBuiltinSetRoundingMode;
-+  defm vssra : RVVSignedShiftBuiltinSetRoundingMode;
-+}
-+let ManualCodegen = [{
-+  {
-+    // LLVM intrinsic
-+    // Unmasked: (passthru, op0, op1, round_mode, vl)
-+    // Masked:   (passthru, vector_in, vector_in/scalar_in, mask, vxrm, vl, policy)
-+
-+    SmallVector<llvm::Value*, 7> Operands;
-+    bool HasMaskedOff = !(
-+        (IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
-+        (!IsMasked && PolicyAttrs & RVV_VTA));
-+    unsigned Offset = IsMasked ?
-+        (HasMaskedOff ? 2 : 1) : (HasMaskedOff ? 1 : 0);
-+
-+    if (!HasMaskedOff)
-+      Operands.push_back(llvm::PoisonValue::get(ResultType));
-+    else
-+      Operands.push_back(Ops[Offset - 1]);
-+
-+    Operands.push_back(Ops[Offset]); // op0
-+    Operands.push_back(Ops[Offset + 1]); // op1
-+
-+    if (IsMasked)
-+      Operands.push_back(Ops[0]); // mask
-+
-+    Operands.push_back(Ops[Offset + 2]); // vxrm
-+    Operands.push_back(Ops[Offset + 3]); // vl
-+
-+    if (IsMasked)
-+      Operands.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
-+
-+    IntrinsicTypes = {ResultType, Ops[Offset]->getType(), Ops[Offset + 1]->getType(), Ops.back()->getType()};
-+    llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
-+    return Builder.CreateCall(F, Operands, "");
-+  }
-+}] in {
- // 13.5. Vector Narrowing Fixed-Point Clip Instructions
--defm vnclipu : RVVUnsignedNShiftBuiltinSet;
--defm vnclip : RVVSignedNShiftBuiltinSet;
-+  defm vnclipu : RVVUnsignedNShiftBuiltinSetRoundingMode;
-+  defm vnclip : RVVSignedNShiftBuiltinSetRoundingMode;
-+}
- 
- // 14. Vector Floating-Point Instructions
- // 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
-diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
-index e9c88f468076..7103bb5f5e39 100644
---- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
-+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
-@@ -586,6 +586,17 @@ let TargetPrefix = "riscv" in {
-     let ScalarOperand = 2;
-     let VLOperand = 3;
-   }
-+  // For Saturating binary operations with rounding-mode operand
-+  // The destination vector type is the same as first source vector.
-+  // Input: (passthru, vector_in, vector_in/scalar_in, vxrm, vl)
-+  class RISCVSaturatingBinaryAAXUnMaskedRoundingMode
-+        : Intrinsic<[llvm_anyvector_ty],
-+                    [LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
-+                     llvm_anyint_ty, LLVMMatchType<2>],
-+                    [ImmArg<ArgIndex<3>>, IntrNoMem]>, RISCVVIntrinsic {
-+    let ScalarOperand = 2;
-+    let VLOperand = 4;
-+  }
-   // For Saturating binary operations with mask.
-   // The destination vector type is the same as first source vector.
-   // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl, policy)
-@@ -598,6 +609,18 @@ let TargetPrefix = "riscv" in {
-     let ScalarOperand = 2;
-     let VLOperand = 4;
-   }
-+  // For Saturating binary operations with mask and rounding-mode operand
-+  // The destination vector type is the same as first source vector.
-+  // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vxrm, vl, policy)
-+  class RISCVSaturatingBinaryAAXMaskedRoundingMode
-+        : Intrinsic<[llvm_anyvector_ty],
-+                    [LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
-+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
-+                     LLVMMatchType<2>, LLVMMatchType<2>],
-+                    [ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<6>>, IntrNoMem]>, RISCVVIntrinsic {
-+    let ScalarOperand = 2;
-+    let VLOperand = 5;
-+  }
-   // For Saturating binary operations.
-   // The destination vector type is the same as first source vector.
-   // The second source operand matches the destination type or is an XLen scalar.
-@@ -609,6 +632,15 @@ let TargetPrefix = "riscv" in {
-                     [IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic {
-     let VLOperand = 3;
-   }
-+
-+  // Input: (passthru, vector_in, vector_in/scalar_in, vxrm, vl)
-+  class RISCVSaturatingBinaryAAShiftUnMaskedRoundingMode
-+        : Intrinsic<[llvm_anyvector_ty],
-+                    [LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
-+                     llvm_anyint_ty, LLVMMatchType<2>],
-+                    [ImmArg<ArgIndex<3>>, IntrNoMem]>, RISCVVIntrinsic {
-+    let VLOperand = 4;
-+  }
-   // For Saturating binary operations with mask.
-   // The destination vector type is the same as first source vector.
-   // The second source operand matches the destination type or is an XLen scalar.
-@@ -621,6 +653,17 @@ let TargetPrefix = "riscv" in {
-                     [ImmArg<ArgIndex<5>>, IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic {
-     let VLOperand = 4;
-   }
-+
-+  // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vxrm, vl, policy)
-+  class RISCVSaturatingBinaryAAShiftMaskedRoundingMode
-+        : Intrinsic<[llvm_anyvector_ty],
-+                    [LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
-+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
-+                     LLVMMatchType<2>, LLVMMatchType<2>],
-+                    [ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<6>>, IntrNoMem]>, RISCVVIntrinsic {
-+    let VLOperand = 5;
-+  }
-+
-   // For Saturating binary operations.
-   // The destination vector type is NOT the same as first source vector.
-   // The second source operand matches the destination type or is an XLen scalar.
-@@ -632,6 +675,16 @@ let TargetPrefix = "riscv" in {
-                     [IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic {
-     let VLOperand = 3;
-   }
-+
-+  // Input: (passthru, vector_in, vector_in/scalar_in, vxrm, vl)
-+  class RISCVSaturatingBinaryABShiftUnMaskedRoundingMode
-+        : Intrinsic<[llvm_anyvector_ty],
-+                    [LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
-+                     llvm_anyint_ty, LLVMMatchType<3>],
-+                    [ImmArg<ArgIndex<3>>, IntrNoMem]>, RISCVVIntrinsic {
-+    let VLOperand = 4;
-+  }
-+
-   // For Saturating binary operations with mask.
-   // The destination vector type is NOT the same as first source vector (with mask).
-   // The second source operand matches the destination type or is an XLen scalar.
-@@ -644,6 +697,17 @@ let TargetPrefix = "riscv" in {
-                     [ImmArg<ArgIndex<5>>, IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic {
-     let VLOperand = 4;
-   }
-+
-+  // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vxrm, vl, policy)
-+  class RISCVSaturatingBinaryABShiftMaskedRoundingMode
-+        : Intrinsic<[llvm_anyvector_ty],
-+                    [LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
-+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
-+                     LLVMMatchType<3>, LLVMMatchType<3>],
-+                    [ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<6>>, IntrNoMem]>, RISCVVIntrinsic {
-+    let VLOperand = 5;
-+  }
-+
-   // Input: (vector_in, vector_in, scalar_in, vl, policy)
-   class RVVSlideUnMasked
-         : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
-@@ -1074,14 +1138,26 @@ let TargetPrefix = "riscv" in {
-     def "int_riscv_" # NAME : RISCVSaturatingBinaryAAXUnMasked;
-     def "int_riscv_" # NAME # "_mask" : RISCVSaturatingBinaryAAXMasked;
-   }
-+  multiclass RISCVSaturatingBinaryAAXRoundingMode {
-+    def "int_riscv_" # NAME : RISCVSaturatingBinaryAAXUnMaskedRoundingMode;
-+    def "int_riscv_" # NAME # "_mask" : RISCVSaturatingBinaryAAXMaskedRoundingMode;
-+  }
-   multiclass RISCVSaturatingBinaryAAShift {
-     def "int_riscv_" # NAME : RISCVSaturatingBinaryAAShiftUnMasked;
-     def "int_riscv_" # NAME # "_mask" : RISCVSaturatingBinaryAAShiftMasked;
-   }
-+  multiclass RISCVSaturatingBinaryAAShiftRoundingMode {
-+    def "int_riscv_" # NAME : RISCVSaturatingBinaryAAShiftUnMaskedRoundingMode;
-+    def "int_riscv_" # NAME # "_mask" : RISCVSaturatingBinaryAAShiftMaskedRoundingMode;
-+  }
-   multiclass RISCVSaturatingBinaryABShift {
-     def "int_riscv_" # NAME : RISCVSaturatingBinaryABShiftUnMasked;
-     def "int_riscv_" # NAME # "_mask" : RISCVSaturatingBinaryABShiftMasked;
-   }
-+  multiclass RISCVSaturatingBinaryABShiftRoundingMode {
-+    def "int_riscv_" # NAME : RISCVSaturatingBinaryABShiftUnMaskedRoundingMode;
-+    def "int_riscv_" # NAME # "_mask" : RISCVSaturatingBinaryABShiftMaskedRoundingMode;
-+  }
-   multiclass RVVSlide {
-     def "int_riscv_" # NAME : RVVSlideUnMasked;
-     def "int_riscv_" # NAME # "_mask" : RVVSlideMasked;
-@@ -1350,18 +1426,18 @@ let TargetPrefix = "riscv" in {
- 
-   def "int_riscv_vcompress" : RISCVCompress;
- 
--  defm vaaddu : RISCVSaturatingBinaryAAX;
--  defm vaadd : RISCVSaturatingBinaryAAX;
--  defm vasubu : RISCVSaturatingBinaryAAX;
--  defm vasub : RISCVSaturatingBinaryAAX;
-+  defm vaaddu : RISCVSaturatingBinaryAAXRoundingMode;
-+  defm vaadd : RISCVSaturatingBinaryAAXRoundingMode;
-+  defm vasubu : RISCVSaturatingBinaryAAXRoundingMode;
-+  defm vasub : RISCVSaturatingBinaryAAXRoundingMode;
- 
--  defm vsmul : RISCVSaturatingBinaryAAX;
-+  defm vsmul : RISCVSaturatingBinaryAAXRoundingMode;
- 
--  defm vssrl : RISCVSaturatingBinaryAAShift;
--  defm vssra : RISCVSaturatingBinaryAAShift;
-+  defm vssrl : RISCVSaturatingBinaryAAShiftRoundingMode;
-+  defm vssra : RISCVSaturatingBinaryAAShiftRoundingMode;
- 
--  defm vnclipu : RISCVSaturatingBinaryABShift;
--  defm vnclip : RISCVSaturatingBinaryABShift;
-+  defm vnclipu : RISCVSaturatingBinaryABShiftRoundingMode;
-+  defm vnclip : RISCVSaturatingBinaryABShiftRoundingMode;
- 
-   defm vmfeq : RISCVCompare;
-   defm vmfne : RISCVCompare;
-diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
-index f909e0017e2b..db84f0504f21 100644
---- a/llvm/lib/Target/RISCV/CMakeLists.txt
-+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
-@@ -27,6 +27,7 @@ add_llvm_target(RISCVCodeGen
-   RISCVFrameLowering.cpp
-   RISCVGatherScatterLowering.cpp
-   RISCVInsertVSETVLI.cpp
-+  RISCVInsertReadWriteCSR.cpp
-   RISCVInstrInfo.cpp
-   RISCVISelDAGToDAG.cpp
-   RISCVISelLowering.cpp
-diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
-index 2cf2045c1719..eb43f4bf0a02 100644
---- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
-+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
-@@ -102,6 +102,9 @@ enum {
-   // in bits 63:31. Used by the SExtWRemoval pass.
-   IsSignExtendingOpWShift = UsesMaskPolicyShift + 1,
-   IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift,
-+
-+  HasRoundModeOpShift = IsSignExtendingOpWShift + 1,
-+  HasRoundModeOpMask = 1 << HasRoundModeOpShift,
- };
- 
- // Match with the definitions in RISCVInstrFormats.td
-@@ -176,6 +179,11 @@ static inline bool usesMaskPolicy(uint64_t TSFlags) {
-   return TSFlags & UsesMaskPolicyMask;
- }
- 
-+/// \returns true if there is a rounding mode operand for this instruction
-+static inline bool hasRoundModeOp(uint64_t TSFlags) {
-+  return TSFlags & HasRoundModeOpMask;
-+}
-+
- static inline unsigned getMergeOpNum(const MCInstrDesc &Desc) {
-   assert(hasMergeOp(Desc.TSFlags));
-   assert(!Desc.isVariadic());
-diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
-index c42fb070aade..f629bd2faea9 100644
---- a/llvm/lib/Target/RISCV/RISCV.h
-+++ b/llvm/lib/Target/RISCV/RISCV.h
-@@ -68,6 +68,9 @@ void initializeRISCVExpandAtomicPseudoPass(PassRegistry &);
- FunctionPass *createRISCVInsertVSETVLIPass();
- void initializeRISCVInsertVSETVLIPass(PassRegistry &);
- 
-+FunctionPass *createRISCVInsertReadWriteCSRPass();
-+void initializeRISCVInsertReadWriteCSRPass(PassRegistry &);
-+
- FunctionPass *createRISCVRedundantCopyEliminationPass();
- void initializeRISCVRedundantCopyEliminationPass(PassRegistry &);
- 
-diff --git a/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp b/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
-new file mode 100644
-index 000000000000..9cc06adf658c
---- /dev/null
-+++ b/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
-@@ -0,0 +1,115 @@
-+//===-- RISCVInsertReadWriteCSR.cpp - Insert Read/Write of RISC-V CSR -----===//
-+//
-+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-+// See https://llvm.org/LICENSE.txt for license information.
-+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-+//
-+//===----------------------------------------------------------------------===//
-+// This file implements the machine function pass to insert read/write of CSR-s
-+// of the RISC-V instructions.
-+//
-+// Currently the pass implements naive insertion of a write to vxrm before an
-+// RVV fixed-point instruction.
-+//
-+//===----------------------------------------------------------------------===//
-+
-+#include "RISCV.h"
-+#include "RISCVSubtarget.h"
-+#include "llvm/CodeGen/MachineFunctionPass.h"
-+using namespace llvm;
-+
-+#define DEBUG_TYPE "riscv-insert-read-write-csr"
-+#define RISCV_INSERT_READ_WRITE_CSR_NAME "RISC-V Insert Read/Write CSR Pass"
-+
-+namespace {
-+
-+class RISCVInsertReadWriteCSR : public MachineFunctionPass {
-+  const TargetInstrInfo *TII;
-+
-+public:
-+  static char ID;
-+
-+  RISCVInsertReadWriteCSR() : MachineFunctionPass(ID) {
-+    initializeRISCVInsertReadWriteCSRPass(*PassRegistry::getPassRegistry());
-+  }
-+
-+  bool runOnMachineFunction(MachineFunction &MF) override;
-+
-+  void getAnalysisUsage(AnalysisUsage &AU) const override {
-+    AU.setPreservesCFG();
-+    MachineFunctionPass::getAnalysisUsage(AU);
-+  }
-+
-+  StringRef getPassName() const override {
-+    return RISCV_INSERT_READ_WRITE_CSR_NAME;
-+  }
-+
-+private:
-+  bool emitWriteVXRM(MachineBasicBlock &MBB);
-+  std::optional<unsigned> getRoundModeIdx(const MachineInstr &MI);
-+};
-+
-+} // end anonymous namespace
-+
-+char RISCVInsertReadWriteCSR::ID = 0;
-+
-+static unsigned PreVXRMValue = 4;
-+
-+INITIALIZE_PASS(RISCVInsertReadWriteCSR, DEBUG_TYPE,
-+                RISCV_INSERT_READ_WRITE_CSR_NAME, false, false)
-+
-+// This function returns the index to the rounding mode immediate value if any,
-+// otherwise the function will return None.
-+std::optional<unsigned>
-+RISCVInsertReadWriteCSR::getRoundModeIdx(const MachineInstr &MI) {
-+  uint64_t TSFlags = MI.getDesc().TSFlags;
-+  if (!RISCVII::hasRoundModeOp(TSFlags))
-+    return std::nullopt;
-+
-+  // The operand order
-+  // -------------------------------------
-+  // | n-1 (if any)   | n-2  | n-3 | n-4 |
-+  // | policy         | sew  | vl  | rm  |
-+  // -------------------------------------
-+  return MI.getNumExplicitOperands() - RISCVII::hasVecPolicyOp(TSFlags) - 3;
-+}
-+
-+// This function inserts a write to vxrm when encountering an RVV fixed-point
-+// instruction.
-+bool RISCVInsertReadWriteCSR::emitWriteVXRM(MachineBasicBlock &MBB) {
-+  bool Changed = false;
-+  for (MachineInstr &MI : MBB) {
-+    if (auto RoundModeIdx = getRoundModeIdx(MI)) {
-+      unsigned VXRMImm = MI.getOperand(*RoundModeIdx).getImm();
-+      if (VXRMImm == PreVXRMValue)
-+          continue;
-+      PreVXRMValue = VXRMImm;
-+      Changed = true;
-+      BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteVXRMImm))
-+          .addImm(VXRMImm);
-+      MI.addOperand(MachineOperand::CreateReg(RISCV::VXRM, /*IsDef*/ false,
-+                                              /*IsImp*/ true));
-+    }
-+  }
-+  return Changed;
-+}
-+
-+bool RISCVInsertReadWriteCSR::runOnMachineFunction(MachineFunction &MF) {
-+  // Skip if the vector extension is not enabled.
-+  const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
-+  if (!ST.hasVInstructions())
-+    return false;
-+
-+  TII = ST.getInstrInfo();
-+
-+  bool Changed = false;
-+
-+  for (MachineBasicBlock &MBB : MF)
-+    Changed |= emitWriteVXRM(MBB);
-+
-+  return Changed;
-+}
-+
-+FunctionPass *llvm::createRISCVInsertReadWriteCSRPass() {
-+  return new RISCVInsertReadWriteCSR();
-+}
-diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
-index 3a494a5e3b58..f2cd4ed8857f 100644
---- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
-+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
-@@ -211,6 +211,9 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
-   // in bits 63:31. Used by the SExtWRemoval pass.
-   bit IsSignExtendingOpW = 0;
-   let TSFlags{19} = IsSignExtendingOpW;
-+
-+  bit HasRoundModeOp = 0;
-+  let TSFlags{20} =  HasRoundModeOp;
- }
- 
- // Pseudo instructions
-diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
-index c699a94943d8..75fee3f962d0 100644
---- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
-+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
-@@ -1693,6 +1693,8 @@ def WriteFRM : WriteSysReg<SysRegFRM, [FRM]>;
- def WriteFRMImm : WriteSysRegImm<SysRegFRM, [FRM]>;
- def SwapFRMImm : SwapSysRegImm<SysRegFRM, [FRM]>;
- 
-+def WriteVXRMImm : WriteSysRegImm<SysRegVXRM, [VXRM]>;
-+
- let hasSideEffects = true in {
- def ReadFFLAGS : ReadSysReg<SysRegFFLAGS, [FFLAGS]>;
- def WriteFFLAGS : WriteSysReg<SysRegFFLAGS, [FFLAGS]>;
-diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
-index 3f69b5e41cf1..ec7af31a23e2 100644
---- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
-+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
-@@ -1139,6 +1139,65 @@ class VPseudoBinaryNoMaskTU<VReg RetClass,
-   let HasMergeOp = 1;
- }
- 
-+class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
-+                                      VReg Op1Class,
-+                                      DAGOperand Op2Class,
-+                                      string Constraint,
-+                                      int DummyMask = 1> :
-+        Pseudo<(outs RetClass:$rd),
-+               (ins Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm, AVL:$vl, ixlenimm:$sew), []>,
-+        RISCVVPseudo {
-+  let mayLoad = 0;
-+  let mayStore = 0;
-+  let hasSideEffects = 0;
-+  let Constraints = Constraint;
-+  let HasVLOp = 1;
-+  let HasSEWOp = 1;
-+  let HasDummyMask = DummyMask;
-+  let HasRoundModeOp = 1;
-+}
-+
-+class VPseudoBinaryNoMaskTURoundingMode<VReg RetClass,
-+                                        VReg Op1Class,
-+                                        DAGOperand Op2Class,
-+                                        string Constraint> :
-+        Pseudo<(outs RetClass:$rd),
-+               (ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm,
-+                    AVL:$vl, ixlenimm:$sew), []>,
-+        RISCVVPseudo {
-+  let mayLoad = 0;
-+  let mayStore = 0;
-+  let hasSideEffects = 0;
-+  let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
-+  let HasVLOp = 1;
-+  let HasSEWOp = 1;
-+  let HasDummyMask = 1;
-+  let HasMergeOp = 1;
-+  let HasRoundModeOp = 1;
-+}
-+
-+class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,
-+                                          RegisterClass Op1Class,
-+                                          DAGOperand Op2Class,
-+                                          string Constraint> :
-+        Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
-+                (ins GetVRegNoV0<RetClass>.R:$merge,
-+                     Op1Class:$rs2, Op2Class:$rs1,
-+                     VMaskOp:$vm, ixlenimm:$rm, AVL:$vl,
-+                     ixlenimm:$sew, ixlenimm:$policy), []>,
-+        RISCVVPseudo {
-+  let mayLoad = 0;
-+  let mayStore = 0;
-+  let hasSideEffects = 0;
-+  let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
-+  let HasVLOp = 1;
-+  let HasSEWOp = 1;
-+  let HasMergeOp = 1;
-+  let HasVecPolicyOp = 1;
-+  let UsesMaskPolicy = 1;
-+  let HasRoundModeOp = 1;
-+}
-+
- // Special version of VPseudoBinaryNoMask where we pretend the first source is
- // tied to the destination.
- // This allows maskedoff and rs2 to be the same register.
-@@ -1923,6 +1982,24 @@ multiclass VPseudoBinary<VReg RetClass,
-   }
- }
- 
-+multiclass VPseudoBinaryRoundingMode<VReg RetClass,
-+                                     VReg Op1Class,
-+                                     DAGOperand Op2Class,
-+                                     LMULInfo MInfo,
-+                                     string Constraint = ""> {
-+  let VLMul = MInfo.value in {
-+    def "_" # MInfo.MX :
-+      VPseudoBinaryNoMaskRoundingMode<RetClass, Op1Class, Op2Class, Constraint>;
-+    def "_" # MInfo.MX # "_TU" :
-+      VPseudoBinaryNoMaskTURoundingMode<RetClass, Op1Class, Op2Class,
-+                                        Constraint>;
-+    def "_" # MInfo.MX # "_MASK" :
-+      VPseudoBinaryMaskPolicyRoundingMode<RetClass, Op1Class, Op2Class,
-+                                          Constraint>,
-+                                          RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
-+  }
-+}
-+
- multiclass VPseudoBinaryM<VReg RetClass,
-                           VReg Op1Class,
-                           DAGOperand Op2Class,
-@@ -1971,6 +2048,10 @@ multiclass VPseudoBinaryV_VV<LMULInfo m, string Constraint = ""> {
-   defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
- }
- 
-+multiclass VPseudoBinaryV_VV_RM<LMULInfo m, string Constraint = ""> {
-+  defm _VV : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
-+}
-+
- // Similar to VPseudoBinaryV_VV, but uses MxListF.
- multiclass VPseudoBinaryFV_VV<LMULInfo m, string Constraint = ""> {
-   defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
-@@ -2000,6 +2081,10 @@ multiclass VPseudoBinaryV_VX<LMULInfo m, string Constraint = ""> {
-   defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>;
- }
- 
-+multiclass VPseudoBinaryV_VX_RM<LMULInfo m, string Constraint = ""> {
-+  defm "_VX" : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, GPR, m, Constraint>;
-+}
-+
- multiclass VPseudoVSLD1_VX<string Constraint = ""> {
-   foreach m = MxList in {
-     defvar mx = m.MX;
-@@ -2036,6 +2121,10 @@ multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, LMULInfo m, string Constra
-   defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
- }
- 
-+multiclass VPseudoBinaryV_VI_RM<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
-+  defm _VI : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, ImmType, m, Constraint>;
-+}
-+
- multiclass VPseudoVALU_MM {
-   foreach m = MxList in {
-     defvar mx = m.MX;
-@@ -2098,16 +2187,31 @@ multiclass VPseudoBinaryV_WV<LMULInfo m> {
-                            !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
- }
- 
-+multiclass VPseudoBinaryV_WV_RM<LMULInfo m> {
-+  defm _WV : VPseudoBinaryRoundingMode<m.vrclass, m.wvrclass, m.vrclass, m,
-+                                       !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
-+}
-+
- multiclass VPseudoBinaryV_WX<LMULInfo m> {
-   defm _WX : VPseudoBinary<m.vrclass, m.wvrclass, GPR, m,
-                            !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
- }
- 
-+multiclass VPseudoBinaryV_WX_RM<LMULInfo m> {
-+  defm _WX : VPseudoBinaryRoundingMode<m.vrclass, m.wvrclass, GPR, m,
-+                                       !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
-+}
-+
- multiclass VPseudoBinaryV_WI<LMULInfo m> {
-   defm _WI : VPseudoBinary<m.vrclass, m.wvrclass, uimm5, m,
-                            !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
- }
- 
-+multiclass VPseudoBinaryV_WI_RM<LMULInfo m> {
-+  defm _WI : VPseudoBinaryRoundingMode<m.vrclass, m.wvrclass, uimm5, m,
-+                                       !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
-+}
-+
- // For vadc and vsbc, the instruction encoding is reserved if the destination
- // vector register is v0.
- // For vadc and vsbc, CarryIn == 1 and CarryOut == 0
-@@ -2419,6 +2523,23 @@ multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""
-   }
- }
- 
-+multiclass VPseudoVSALU_VV_VX_VI_RM<Operand ImmType = simm5, string Constraint = ""> {
-+  foreach m = MxList in {
-+    defvar mx = m.MX;
-+    defvar WriteVSALUV_MX = !cast<SchedWrite>("WriteVSALUV_" # mx);
-+    defvar WriteVSALUX_MX = !cast<SchedWrite>("WriteVSALUX_" # mx);
-+    defvar WriteVSALUI_MX = !cast<SchedWrite>("WriteVSALUI_" # mx);
-+    defvar ReadVSALUV_MX = !cast<SchedRead>("ReadVSALUV_" # mx);
-+    defvar ReadVSALUX_MX = !cast<SchedRead>("ReadVSALUX_" # mx);
-+
-+    defm "" : VPseudoBinaryV_VV_RM<m, Constraint>,
-+              Sched<[WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX, ReadVMask]>;
-+    defm "" : VPseudoBinaryV_VX_RM<m, Constraint>,
-+              Sched<[WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX, ReadVMask]>;
-+    defm "" : VPseudoBinaryV_VI_RM<ImmType, m, Constraint>,
-+              Sched<[WriteVSALUI_MX, ReadVSALUV_MX, ReadVMask]>;
-+  }
-+}
- 
- multiclass VPseudoVSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
-   foreach m = MxList in {
-@@ -2456,6 +2577,24 @@ multiclass VPseudoVSSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""
-   }
- }
- 
-+multiclass VPseudoVSSHT_VV_VX_VI_RM<Operand ImmType = simm5, string Constraint = ""> {
-+  foreach m = MxList in {
-+    defvar mx = m.MX;
-+    defvar WriteVSShiftV_MX = !cast<SchedWrite>("WriteVSShiftV_" # mx);
-+    defvar WriteVSShiftX_MX = !cast<SchedWrite>("WriteVSShiftX_" # mx);
-+    defvar WriteVSShiftI_MX = !cast<SchedWrite>("WriteVSShiftI_" # mx);
-+    defvar ReadVSShiftV_MX = !cast<SchedRead>("ReadVSShiftV_" # mx);
-+    defvar ReadVSShiftX_MX = !cast<SchedRead>("ReadVSShiftX_" # mx);
-+
-+    defm "" : VPseudoBinaryV_VV_RM<m, Constraint>,
-+              Sched<[WriteVSShiftV_MX, ReadVSShiftV_MX, ReadVSShiftV_MX, ReadVMask]>;
-+    defm "" : VPseudoBinaryV_VX_RM<m, Constraint>,
-+              Sched<[WriteVSShiftX_MX, ReadVSShiftV_MX, ReadVSShiftX_MX, ReadVMask]>;
-+    defm "" : VPseudoBinaryV_VI_RM<ImmType, m, Constraint>,
-+              Sched<[WriteVSShiftI_MX, ReadVSShiftV_MX, ReadVMask]>;
-+  }
-+}
-+
- multiclass VPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
-   foreach m = MxList in {
-     defvar mx = m.MX;
-@@ -2489,6 +2628,21 @@ multiclass VPseudoVSALU_VV_VX {
-   }
- }
- 
-+multiclass VPseudoVSALU_VV_VX_RM {
-+  foreach m = MxList in {
-+    defvar mx = m.MX;
-+    defvar WriteVSALUV_MX = !cast<SchedWrite>("WriteVSALUV_" # mx);
-+    defvar WriteVSALUX_MX = !cast<SchedWrite>("WriteVSALUX_" # mx);
-+    defvar ReadVSALUV_MX = !cast<SchedRead>("ReadVSALUV_" # mx);
-+    defvar ReadVSALUX_MX = !cast<SchedRead>("ReadVSALUX_" # mx);
-+
-+    defm "" : VPseudoBinaryV_VV_RM<m>,
-+              Sched<[WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX, ReadVMask]>;
-+    defm "" : VPseudoBinaryV_VX_RM<m>,
-+              Sched<[WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX, ReadVMask]>;
-+  }
-+}
-+
- multiclass VPseudoVSMUL_VV_VX {
-   foreach m = MxList in {
-     defvar mx = m.MX;
-@@ -2504,6 +2658,21 @@ multiclass VPseudoVSMUL_VV_VX {
-   }
- }
- 
-+multiclass VPseudoVSMUL_VV_VX_RM {
-+  foreach m = MxList in {
-+    defvar mx = m.MX;
-+    defvar WriteVSMulV_MX = !cast<SchedWrite>("WriteVSMulV_" # mx);
-+    defvar WriteVSMulX_MX = !cast<SchedWrite>("WriteVSMulX_" # mx);
-+    defvar ReadVSMulV_MX = !cast<SchedRead>("ReadVSMulV_" # mx);
-+    defvar ReadVSMulX_MX = !cast<SchedRead>("ReadVSMulX_" # mx);
-+
-+    defm "" : VPseudoBinaryV_VV_RM<m>,
-+              Sched<[WriteVSMulV_MX, ReadVSMulV_MX, ReadVSMulV_MX, ReadVMask]>;
-+    defm "" : VPseudoBinaryV_VX_RM<m>,
-+              Sched<[WriteVSMulX_MX, ReadVSMulV_MX, ReadVSMulX_MX, ReadVMask]>;
-+  }
-+}
-+
- multiclass VPseudoVAALU_VV_VX {
-   foreach m = MxList in {
-     defvar mx = m.MX;
-@@ -2519,6 +2688,21 @@ multiclass VPseudoVAALU_VV_VX {
-   }
- }
- 
-+multiclass VPseudoVAALU_VV_VX_RM {
-+  foreach m = MxList in {
-+    defvar mx = m.MX;
-+    defvar WriteVAALUV_MX = !cast<SchedWrite>("WriteVAALUV_" # mx);
-+    defvar WriteVAALUX_MX = !cast<SchedWrite>("WriteVAALUX_" # mx);
-+    defvar ReadVAALUV_MX = !cast<SchedRead>("ReadVAALUV_" # mx);
-+    defvar ReadVAALUX_MX = !cast<SchedRead>("ReadVAALUX_" # mx);
-+
-+    defm "" : VPseudoBinaryV_VV_RM<m>,
-+              Sched<[WriteVAALUV_MX, ReadVAALUV_MX, ReadVAALUV_MX, ReadVMask]>;
-+    defm "" : VPseudoBinaryV_VX_RM<m>,
-+              Sched<[WriteVAALUX_MX, ReadVAALUV_MX, ReadVAALUX_MX, ReadVMask]>;
-+  }
-+}
-+
- multiclass VPseudoVMINMAX_VV_VX {
-   foreach m = MxList in {
-     defvar mx = m.MX;
-@@ -3002,6 +3186,24 @@ multiclass VPseudoVNCLP_WV_WX_WI {
-   }
- }
- 
-+multiclass VPseudoVNCLP_WV_WX_WI_RM {
-+  foreach m = MxListW in {
-+    defvar mx = m.MX;
-+    defvar WriteVNClipV_MX = !cast<SchedWrite>("WriteVNClipV_" # mx);
-+    defvar WriteVNClipX_MX = !cast<SchedWrite>("WriteVNClipX_" # mx);
-+    defvar WriteVNClipI_MX = !cast<SchedWrite>("WriteVNClipI_" # mx);
-+    defvar ReadVNClipV_MX = !cast<SchedRead>("ReadVNClipV_" # mx);
-+    defvar ReadVNClipX_MX = !cast<SchedRead>("ReadVNClipX_" # mx);
-+
-+    defm "" : VPseudoBinaryV_WV_RM<m>,
-+              Sched<[WriteVNClipV_MX, ReadVNClipV_MX, ReadVNClipV_MX, ReadVMask]>;
-+    defm "" : VPseudoBinaryV_WX_RM<m>,
-+              Sched<[WriteVNClipX_MX, ReadVNClipV_MX, ReadVNClipX_MX, ReadVMask]>;
-+    defm "" : VPseudoBinaryV_WI_RM<m>,
-+              Sched<[WriteVNClipI_MX, ReadVNClipV_MX, ReadVMask]>;
-+  }
-+}
-+
- multiclass VPseudoVNSHT_WV_WX_WI {
-   foreach m = MxListW in {
-     defvar mx = m.MX;
-@@ -3881,6 +4083,48 @@ class VPatBinaryNoMaskTU<string intrinsic_name,
-                    (op2_type op2_kind:$rs2),
-                    GPR:$vl, sew)>;
- 
-+class VPatBinaryNoMaskTARoundingMode<string intrinsic_name,
-+                                     string inst,
-+                                     ValueType result_type,
-+                                     ValueType op1_type,
-+                                     ValueType op2_type,
-+                                     int sew,
-+                                     VReg op1_reg_class,
-+                                     DAGOperand op2_kind> :
-+  Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
-+                   (result_type (undef)),
-+                   (op1_type op1_reg_class:$rs1),
-+                   (op2_type op2_kind:$rs2),
-+                   (XLenVT timm:$round),
-+                   VLOpFrag)),
-+                   (!cast<Instruction>(inst)
-+                   (op1_type op1_reg_class:$rs1),
-+                   (op2_type op2_kind:$rs2),
-+                   (XLenVT timm:$round),
-+                   GPR:$vl, sew)>;
-+
-+class VPatBinaryNoMaskTURoundingMode<string intrinsic_name,
-+                                     string inst,
-+                                     ValueType result_type,
-+                                     ValueType op1_type,
-+                                     ValueType op2_type,
-+                                     int sew,
-+                                     VReg result_reg_class,
-+                                     VReg op1_reg_class,
-+                                     DAGOperand op2_kind> :
-+  Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
-+                   (result_type result_reg_class:$merge),
-+                   (op1_type op1_reg_class:$rs1),
-+                   (op2_type op2_kind:$rs2),
-+                   (XLenVT timm:$round),
-+                   VLOpFrag)),
-+                   (!cast<Instruction>(inst#"_TU")
-+                   (result_type result_reg_class:$merge),
-+                   (op1_type op1_reg_class:$rs1),
-+                   (op2_type op2_kind:$rs2),
-+                   (XLenVT timm:$round),
-+                   GPR:$vl, sew)>;
-+
- // Same as above but source operands are swapped.
- class VPatBinaryNoMaskSwapped<string intrinsic_name,
-                               string inst,
-@@ -3943,6 +4187,31 @@ class VPatBinaryMaskTA<string intrinsic_name,
-                    (op2_type op2_kind:$rs2),
-                    (mask_type V0), GPR:$vl, sew, (XLenVT timm:$policy))>;
- 
-+class VPatBinaryMaskTARoundingMode<string intrinsic_name,
-+                                   string inst,
-+                                   ValueType result_type,
-+                                   ValueType op1_type,
-+                                   ValueType op2_type,
-+                                   ValueType mask_type,
-+                                   int sew,
-+                                   VReg result_reg_class,
-+                                   VReg op1_reg_class,
-+                                   DAGOperand op2_kind> :
-+  Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")
-+                   (result_type result_reg_class:$merge),
-+                   (op1_type op1_reg_class:$rs1),
-+                   (op2_type op2_kind:$rs2),
-+                   (mask_type V0),
-+                   (XLenVT timm:$round),
-+                   VLOpFrag, (XLenVT timm:$policy))),
-+                   (!cast<Instruction>(inst#"_MASK")
-+                   (result_type result_reg_class:$merge),
-+                   (op1_type op1_reg_class:$rs1),
-+                   (op2_type op2_kind:$rs2),
-+                   (mask_type V0),
-+                   (XLenVT timm:$round),
-+                   GPR:$vl, sew, (XLenVT timm:$policy))>;
-+
- // Same as above but source operands are swapped.
- class VPatBinaryMaskSwapped<string intrinsic_name,
-                             string inst,
-@@ -4261,6 +4530,26 @@ multiclass VPatBinaryTA<string intrinsic,
-                          op2_kind>;
- }
- 
-+multiclass VPatBinaryTARoundingMode<string intrinsic,
-+                                    string inst,
-+                                    ValueType result_type,
-+                                    ValueType op1_type,
-+                                    ValueType op2_type,
-+                                    ValueType mask_type,
-+                                    int sew,
-+                                    VReg result_reg_class,
-+                                    VReg op1_reg_class,
-+                                    DAGOperand op2_kind>
-+{
-+  def : VPatBinaryNoMaskTARoundingMode<intrinsic, inst, result_type, op1_type, op2_type,
-+                                       sew, op1_reg_class, op2_kind>;
-+  def : VPatBinaryNoMaskTURoundingMode<intrinsic, inst, result_type, op1_type, op2_type,
-+                                       sew, result_reg_class, op1_reg_class, op2_kind>;
-+  def : VPatBinaryMaskTARoundingMode<intrinsic, inst, result_type, op1_type, op2_type,
-+                                     mask_type, sew, result_reg_class, op1_reg_class,
-+                                     op2_kind>;
-+}
-+
- multiclass VPatBinarySwapped<string intrinsic,
-                       string inst,
-                       ValueType result_type,
-@@ -4387,6 +4676,15 @@ multiclass VPatBinaryV_VV<string intrinsic, string instruction,
-                         vti.RegClass, vti.RegClass>;
- }
- 
-+multiclass VPatBinaryV_VVRoundingMode<string intrinsic, string instruction,
-+                                      list<VTypeInfo> vtilist> {
-+  foreach vti = vtilist in
-+    defm : VPatBinaryTARoundingMode<intrinsic, instruction # "_VV_" # vti.LMul.MX,
-+                                    vti.Vector, vti.Vector, vti.Vector,vti.Mask,
-+                                    vti.Log2SEW, vti.RegClass,
-+                                    vti.RegClass, vti.RegClass>;
-+}
-+
- multiclass VPatBinaryV_VV_INT<string intrinsic, string instruction,
-                           list<VTypeInfo> vtilist> {
-   foreach vti = vtilist in {
-@@ -4428,6 +4726,17 @@ multiclass VPatBinaryV_VX<string intrinsic, string instruction,
-   }
- }
- 
-+multiclass VPatBinaryV_VXRoundingMode<string intrinsic, string instruction,
-+                                      list<VTypeInfo> vtilist> {
-+  foreach vti = vtilist in {
-+    defvar kind = "V"#vti.ScalarSuffix;
-+    defm : VPatBinaryTARoundingMode<intrinsic, instruction#"_"#kind#"_"#vti.LMul.MX,
-+                                    vti.Vector, vti.Vector, vti.Scalar, vti.Mask,
-+                                    vti.Log2SEW, vti.RegClass,
-+                                    vti.RegClass, vti.ScalarRegClass>;
-+  }
-+}
-+
- multiclass VPatBinaryV_VX_INT<string intrinsic, string instruction,
-                           list<VTypeInfo> vtilist> {
-   foreach vti = vtilist in
-@@ -4446,6 +4755,15 @@ multiclass VPatBinaryV_VI<string intrinsic, string instruction,
-                         vti.RegClass, imm_type>;
- }
- 
-+multiclass VPatBinaryV_VIRoundingMode<string intrinsic, string instruction,
-+                                      list<VTypeInfo> vtilist, Operand imm_type> {
-+  foreach vti = vtilist in
-+    defm : VPatBinaryTARoundingMode<intrinsic, instruction # "_VI_" # vti.LMul.MX,
-+                                    vti.Vector, vti.Vector, XLenVT, vti.Mask,
-+                                    vti.Log2SEW, vti.RegClass,
-+                                    vti.RegClass, imm_type>;
-+}
-+
- multiclass VPatBinaryM_MM<string intrinsic, string instruction> {
-   foreach mti = AllMasks in
-     def : VPatBinaryM<intrinsic, instruction # "_MM_" # mti.LMul.MX,
-@@ -4529,6 +4847,18 @@ multiclass VPatBinaryV_WV<string intrinsic, string instruction,
-   }
- }
- 
-+multiclass VPatBinaryV_WVRoundingMode<string intrinsic, string instruction,
-+                                      list<VTypeInfoToWide> vtilist> {
-+  foreach VtiToWti = vtilist in {
-+    defvar Vti = VtiToWti.Vti;
-+    defvar Wti = VtiToWti.Wti;
-+    defm : VPatBinaryTARoundingMode<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
-+                                    Vti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,
-+                                    Vti.Log2SEW, Vti.RegClass,
-+                                    Wti.RegClass, Vti.RegClass>;
-+  }
-+}
-+
- multiclass VPatBinaryV_WX<string intrinsic, string instruction,
-                           list<VTypeInfoToWide> vtilist> {
-   foreach VtiToWti = vtilist in {
-@@ -4542,6 +4872,19 @@ multiclass VPatBinaryV_WX<string intrinsic, string instruction,
-   }
- }
- 
-+multiclass VPatBinaryV_WXRoundingMode<string intrinsic, string instruction,
-+                          list<VTypeInfoToWide> vtilist> {
-+  foreach VtiToWti = vtilist in {
-+    defvar Vti = VtiToWti.Vti;
-+    defvar Wti = VtiToWti.Wti;
-+    defvar kind = "W"#Vti.ScalarSuffix;
-+    defm : VPatBinaryTARoundingMode<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,
-+                                    Vti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask,
-+                                    Vti.Log2SEW, Vti.RegClass,
-+                                    Wti.RegClass, Vti.ScalarRegClass>;
-+  }
-+}
-+
- multiclass VPatBinaryV_WI<string intrinsic, string instruction,
-                           list<VTypeInfoToWide> vtilist> {
-   foreach VtiToWti = vtilist in {
-@@ -4554,6 +4897,18 @@ multiclass VPatBinaryV_WI<string intrinsic, string instruction,
-   }
- }
- 
-+multiclass VPatBinaryV_WIRoundingMode<string intrinsic, string instruction,
-+                          list<VTypeInfoToWide> vtilist> {
-+  foreach VtiToWti = vtilist in {
-+    defvar Vti = VtiToWti.Vti;
-+    defvar Wti = VtiToWti.Wti;
-+    defm : VPatBinaryTARoundingMode<intrinsic, instruction # "_WI_" # Vti.LMul.MX,
-+                                    Vti.Vector, Wti.Vector, XLenVT, Vti.Mask,
-+                                    Vti.Log2SEW, Vti.RegClass,
-+                                    Wti.RegClass, uimm5>;
-+  }
-+}
-+
- multiclass VPatBinaryV_VM<string intrinsic, string instruction,
-                           bit CarryOut = 0,
-                           list<VTypeInfo> vtilist = AllIntegerVectors> {
-@@ -4688,11 +5043,22 @@ multiclass VPatBinaryV_VV_VX_VI<string intrinsic, string instruction,
-       VPatBinaryV_VX<intrinsic, instruction, vtilist>,
-       VPatBinaryV_VI<intrinsic, instruction, vtilist, ImmType>;
- 
-+multiclass VPatBinaryV_VV_VX_VIRoundingMode<string intrinsic, string instruction,
-+                                            list<VTypeInfo> vtilist, Operand ImmType = simm5>
-+    : VPatBinaryV_VVRoundingMode<intrinsic, instruction, vtilist>,
-+      VPatBinaryV_VXRoundingMode<intrinsic, instruction, vtilist>,
-+      VPatBinaryV_VIRoundingMode<intrinsic, instruction, vtilist, ImmType>;
-+
- multiclass VPatBinaryV_VV_VX<string intrinsic, string instruction,
-                              list<VTypeInfo> vtilist>
-     : VPatBinaryV_VV<intrinsic, instruction, vtilist>,
-       VPatBinaryV_VX<intrinsic, instruction, vtilist>;
- 
-+multiclass VPatBinaryV_VV_VXRoundingMode<string intrinsic, string instruction,
-+                             list<VTypeInfo> vtilist>
-+    : VPatBinaryV_VVRoundingMode<intrinsic, instruction, vtilist>,
-+      VPatBinaryV_VXRoundingMode<intrinsic, instruction, vtilist>;
-+
- multiclass VPatBinaryV_VX_VI<string intrinsic, string instruction,
-                              list<VTypeInfo> vtilist>
-     : VPatBinaryV_VX<intrinsic, instruction, vtilist>,
-@@ -4714,6 +5080,12 @@ multiclass VPatBinaryV_WV_WX_WI<string intrinsic, string instruction,
-       VPatBinaryV_WX<intrinsic, instruction, vtilist>,
-       VPatBinaryV_WI<intrinsic, instruction, vtilist>;
- 
-+multiclass VPatBinaryV_WV_WX_WIRoundingMode<string intrinsic, string instruction,
-+                                            list<VTypeInfoToWide> vtilist>
-+    : VPatBinaryV_WVRoundingMode<intrinsic, instruction, vtilist>,
-+      VPatBinaryV_WXRoundingMode<intrinsic, instruction, vtilist>,
-+      VPatBinaryV_WIRoundingMode<intrinsic, instruction, vtilist>;
-+
- multiclass VPatBinaryV_VM_XM_IM<string intrinsic, string instruction>
-     : VPatBinaryV_VM_TAIL<intrinsic, instruction>,
-       VPatBinaryV_XM_TAIL<intrinsic, instruction>,
-@@ -5382,34 +5754,34 @@ let Defs = [VXSAT], hasSideEffects = 1 in {
- //===----------------------------------------------------------------------===//
- // 12.2. Vector Single-Width Averaging Add and Subtract
- //===----------------------------------------------------------------------===//
--let Uses = [VXRM], hasSideEffects = 1 in {
--  defm PseudoVAADDU : VPseudoVAALU_VV_VX;
--  defm PseudoVAADD  : VPseudoVAALU_VV_VX;
--  defm PseudoVASUBU : VPseudoVAALU_VV_VX;
--  defm PseudoVASUB  : VPseudoVAALU_VV_VX;
-+let hasSideEffects = 1 in {
-+  defm PseudoVAADDU : VPseudoVAALU_VV_VX_RM;
-+  defm PseudoVAADD  : VPseudoVAALU_VV_VX_RM;
-+  defm PseudoVASUBU : VPseudoVAALU_VV_VX_RM;
-+  defm PseudoVASUB  : VPseudoVAALU_VV_VX_RM;
- }
- 
- //===----------------------------------------------------------------------===//
- // 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
- //===----------------------------------------------------------------------===//
--let Uses = [VXRM], Defs = [VXSAT], hasSideEffects = 1 in {
--  defm PseudoVSMUL : VPseudoVSMUL_VV_VX;
-+let Defs = [VXSAT], hasSideEffects = 1 in {
-+  defm PseudoVSMUL : VPseudoVSMUL_VV_VX_RM;
- }
- 
- //===----------------------------------------------------------------------===//
- // 12.4. Vector Single-Width Scaling Shift Instructions
- //===----------------------------------------------------------------------===//
--let Uses = [VXRM], hasSideEffects = 1 in {
--  defm PseudoVSSRL : VPseudoVSSHT_VV_VX_VI<uimm5>;
--  defm PseudoVSSRA : VPseudoVSSHT_VV_VX_VI<uimm5>;
-+let hasSideEffects = 1 in {
-+  defm PseudoVSSRL : VPseudoVSSHT_VV_VX_VI_RM<uimm5>;
-+  defm PseudoVSSRA : VPseudoVSSHT_VV_VX_VI_RM<uimm5>;
- }
- 
- //===----------------------------------------------------------------------===//
- // 12.5. Vector Narrowing Fixed-Point Clip Instructions
- //===----------------------------------------------------------------------===//
--let Uses = [VXRM], Defs = [VXSAT], hasSideEffects = 1 in {
--  defm PseudoVNCLIP  : VPseudoVNCLP_WV_WX_WI;
--  defm PseudoVNCLIPU : VPseudoVNCLP_WV_WX_WI;
-+let Defs = [VXSAT], hasSideEffects = 1 in {
-+  defm PseudoVNCLIP  : VPseudoVNCLP_WV_WX_WI_RM;
-+  defm PseudoVNCLIPU : VPseudoVNCLP_WV_WX_WI_RM;
- }
- 
- } // Predicates = [HasVInstructions]
-@@ -6040,30 +6412,36 @@ defm : VPatBinaryV_VV_VX<"int_riscv_vssub", "PseudoVSSUB", AllIntegerVectors>;
- //===----------------------------------------------------------------------===//
- // 12.2. Vector Single-Width Averaging Add and Subtract
- //===----------------------------------------------------------------------===//
--defm : VPatBinaryV_VV_VX<"int_riscv_vaaddu", "PseudoVAADDU", AllIntegerVectors>;
--defm : VPatBinaryV_VV_VX<"int_riscv_vaadd", "PseudoVAADD", AllIntegerVectors>;
--defm : VPatBinaryV_VV_VX<"int_riscv_vasubu", "PseudoVASUBU", AllIntegerVectors>;
--defm : VPatBinaryV_VV_VX<"int_riscv_vasub", "PseudoVASUB", AllIntegerVectors>;
-+defm : VPatBinaryV_VV_VXRoundingMode<"int_riscv_vaaddu", "PseudoVAADDU",
-+                                     AllIntegerVectors>;
-+defm : VPatBinaryV_VV_VXRoundingMode<"int_riscv_vasubu", "PseudoVASUBU",
-+                                     AllIntegerVectors>;
-+defm : VPatBinaryV_VV_VXRoundingMode<"int_riscv_vasub", "PseudoVASUB",
-+                                     AllIntegerVectors>;
-+defm : VPatBinaryV_VV_VXRoundingMode<"int_riscv_vaadd", "PseudoVAADD",
-+                                     AllIntegerVectors>;
- 
- //===----------------------------------------------------------------------===//
- // 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
- //===----------------------------------------------------------------------===//
--defm : VPatBinaryV_VV_VX<"int_riscv_vsmul", "PseudoVSMUL", AllIntegerVectors>;
-+defm : VPatBinaryV_VV_VXRoundingMode<"int_riscv_vsmul", "PseudoVSMUL",
-+                                     AllIntegerVectors>;
- 
- //===----------------------------------------------------------------------===//
- // 12.4. Vector Single-Width Scaling Shift Instructions
- //===----------------------------------------------------------------------===//
--defm : VPatBinaryV_VV_VX_VI<"int_riscv_vssrl", "PseudoVSSRL", AllIntegerVectors,
--                            uimm5>;
--defm : VPatBinaryV_VV_VX_VI<"int_riscv_vssra", "PseudoVSSRA", AllIntegerVectors,
--                            uimm5>;
-+defm : VPatBinaryV_VV_VX_VIRoundingMode<"int_riscv_vssrl", "PseudoVSSRL",
-+                                        AllIntegerVectors, uimm5>;
-+defm : VPatBinaryV_VV_VX_VIRoundingMode<"int_riscv_vssra", "PseudoVSSRA",
-+                                        AllIntegerVectors, uimm5>;
- 
- //===----------------------------------------------------------------------===//
- // 12.5. Vector Narrowing Fixed-Point Clip Instructions
- //===----------------------------------------------------------------------===//
--defm : VPatBinaryV_WV_WX_WI<"int_riscv_vnclipu", "PseudoVNCLIPU", AllWidenableIntVectors>;
--defm : VPatBinaryV_WV_WX_WI<"int_riscv_vnclip", "PseudoVNCLIP", AllWidenableIntVectors>;
--
-+defm : VPatBinaryV_WV_WX_WIRoundingMode<"int_riscv_vnclipu", "PseudoVNCLIPU",
-+                                        AllWidenableIntVectors>;
-+defm : VPatBinaryV_WV_WX_WIRoundingMode<"int_riscv_vnclip", "PseudoVNCLIP",
-+                                        AllWidenableIntVectors>;
- } // Predicates = [HasVInstructions]
- 
- //===----------------------------------------------------------------------===//
-diff --git a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
-index 281918259cdb..7455df64c38a 100644
---- a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
-+++ b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
-@@ -159,6 +159,8 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
-     --NumOps;
-   if (RISCVII::hasVLOp(TSFlags))
-     --NumOps;
-+  if (RISCVII::hasRoundModeOp(TSFlags))
-+    --NumOps;
-   if (RISCVII::hasSEWOp(TSFlags))
-     --NumOps;
- 
-diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
-index b9aa25b321b0..ced58fbb2a6d 100644
---- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
-+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
-@@ -350,7 +350,7 @@ def : SysReg<"dscratch1", 0x7B3>;
- //===----------------------------------------------------------------------===//
- def : SysReg<"vstart", 0x008>;
- def : SysReg<"vxsat", 0x009>;
--def : SysReg<"vxrm", 0x00A>;
-+def SysRegVXRM : SysReg<"vxrm", 0x00A>;
- def : SysReg<"vcsr", 0x00F>;
- def : SysReg<"vl", 0xC20>;
- def : SysReg<"vtype", 0xC21>;
-diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
-index cc881406666c..28908e88f39f 100644
---- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
-+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
-@@ -81,6 +81,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
-   initializeRISCVPreRAExpandPseudoPass(*PR);
-   initializeRISCVExpandPseudoPass(*PR);
-   initializeRISCVInsertVSETVLIPass(*PR);
-+  initializeRISCVInsertReadWriteCSRPass(*PR);
-   initializeRISCVDAGToDAGISelPass(*PR);
- }
- 
-@@ -354,6 +355,7 @@ void RISCVPassConfig::addPreRegAlloc() {
-   if (TM->getOptLevel() != CodeGenOpt::None)
-     addPass(createRISCVMergeBaseOffsetOptPass());
-   addPass(createRISCVInsertVSETVLIPass());
-+  addPass(createRISCVInsertReadWriteCSRPass());
- }
- 
- void RISCVPassConfig::addPostRegAlloc() {
--- 
-2.25.1
-

+ 13 - 13
recipes-devtools/clang/clang/0001-neon2rvv-support-type-convert-between-fixed-vector-a.patch → recipes-devtools/clang/clang/0002-neon2rvv-support-type-convert-between-fixed-vector-a.patch

@@ -1,7 +1,7 @@
-From 51248b6c65c8809f27e84a56e43b00c88d473280 Mon Sep 17 00:00:00 2001
+From da348addac39388d474b73ea596077087c29b228 Mon Sep 17 00:00:00 2001
 From: Eric Tang <eric.tang@starfivetech.com>
 Date: Fri, 2 Jun 2023 09:07:44 +0800
-Subject: [PATCH 1/9] [neon2rvv] support type convert between fixed vector and
+Subject: [PATCH 2/8] [neon2rvv] support type convert between fixed vector and
  scalable vector
 
   disable the default vectorize options on O1,O2,O3,Oz...
@@ -14,12 +14,12 @@ Signed-off-by: Eric Tang <eric.tang@starfivetech.com>
  3 files changed, 101 insertions(+)
 
 diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def
-index c26e3b807370..cbeb29245aec 100644
+index 50e912c2c1c7..a08e81dd4820 100644
 --- a/clang/include/clang/Basic/BuiltinsRISCV.def
 +++ b/clang/include/clang/Basic/BuiltinsRISCV.def
-@@ -79,5 +79,54 @@ TARGET_BUILTIN(__builtin_riscv_sm4ks, "LiLiLiIUc", "nc", "zksed")
- TARGET_BUILTIN(__builtin_riscv_sm3p0, "LiLi", "nc", "zksh")
- TARGET_BUILTIN(__builtin_riscv_sm3p1, "LiLi", "nc", "zksh")
+@@ -89,5 +89,54 @@ TARGET_BUILTIN(__builtin_riscv_sm3p1, "UiUi", "nc", "zksh")
+ TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "experimental-zihintntl")
+ TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "experimental-zihintntl")
  
 +// Scalable Vector type <-> Fixed Vector type
 +
@@ -73,12 +73,12 @@ index c26e3b807370..cbeb29245aec 100644
  #undef BUILTIN
  #undef TARGET_BUILTIN
 diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
-index f72e04a425d9..1e276bac4e54 100644
+index 30f5f4e7061c..aa6f59802ef3 100644
 --- a/clang/lib/CodeGen/CGBuiltin.cpp
 +++ b/clang/lib/CodeGen/CGBuiltin.cpp
-@@ -19666,6 +19666,57 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
+@@ -20358,6 +20358,57 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
+   case RISCV::BI__builtin_riscv_sm3p1:
      ID = Intrinsic::riscv_sm3p1;
-     IntrinsicTypes = {ResultType};
      break;
 +  //scalable vector type <-> fixed vector types
 +  case RISCV::BI__builtin_rvv_type_cast_from_i8m1:
@@ -132,13 +132,13 @@ index f72e04a425d9..1e276bac4e54 100644
 +    return Builder.CreateExtractVector(ResultType, Ops[0], Builder.getInt64(0));
 +  }
  
-   // Vector builtins are handled from here.
- #include "clang/Basic/riscv_vector_builtin_cg.inc"
+   // Zihintntl
+   case RISCV::BI__builtin_riscv_ntl_load: {
 diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
-index 77554aa2c462..d207a636e07f 100644
+index 47ec36b3a8ff..393a310f669f 100644
 --- a/clang/lib/Driver/ToolChains/Clang.cpp
 +++ b/clang/lib/Driver/ToolChains/Clang.cpp
-@@ -635,6 +635,7 @@ static void addCoveragePrefixMapArg(const Driver &D, const ArgList &Args,
+@@ -645,6 +645,7 @@ static void addCoveragePrefixMapArg(const Driver &D, const ArgList &Args,
  /// For -Oz the loop vectorizer is disabled, while the slp vectorizer is
  /// enabled.
  static bool shouldEnableVectorizerAtOLevel(const ArgList &Args, bool isSlpVec) {

+ 51 - 0
recipes-devtools/clang/clang/0003-Add-an-optional-for-optimizing-Insert-Read-Write-CSR.patch

@@ -0,0 +1,51 @@
+From d21645695ea772387ffeb96289de2aa931f1eb2b Mon Sep 17 00:00:00 2001
+From: Eric Tang <eric.tang@starfivetech.com>
+Date: Fri, 22 Dec 2023 17:00:42 +0800
+Subject: [PATCH 3/8] Add an optional for optimizing Insert Read/Write CSR pass
+
+Signed-off-by: Eric Tang <eric.tang@starfivetech.com>
+---
+ llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp b/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
+index 4b26c27bb4f8..3981747c00cb 100644
+--- a/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
++++ b/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
+@@ -22,6 +22,10 @@ using namespace llvm;
+ #define DEBUG_TYPE "riscv-insert-read-write-csr"
+ #define RISCV_INSERT_READ_WRITE_CSR_NAME "RISC-V Insert Read/Write CSR Pass"
+ 
++static cl::opt<bool> EnableInsertCSROpt(
++    "riscv-enable-insert-read-write-csr-opt", cl::init(false), cl::Hidden,
++    cl::desc("enable insert Read/Write CSR when inserting CSR."));
++
+ namespace {
+ 
+ class RISCVInsertReadWriteCSR : public MachineFunctionPass {
+@@ -53,6 +57,8 @@ private:
+ 
+ char RISCVInsertReadWriteCSR::ID = 0;
+ 
++static unsigned PreVXRMValue = 4;
++
+ INITIALIZE_PASS(RISCVInsertReadWriteCSR, DEBUG_TYPE,
+                 RISCV_INSERT_READ_WRITE_CSR_NAME, false, false)
+ 
+@@ -80,6 +86,13 @@ bool RISCVInsertReadWriteCSR::emitWriteRoundingMode(MachineBasicBlock &MBB) {
+       if (RISCVII::usesVXRM(MI.getDesc().TSFlags)) {
+         unsigned VXRMImm = MI.getOperand(*RoundModeIdx).getImm();
+ 
++        if (EnableInsertCSROpt) {
++          if (VXRMImm == PreVXRMValue)
++            continue;
++
++          PreVXRMValue = VXRMImm;
++        }
++
+         Changed = true;
+ 
+         BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteVXRMImm))
+-- 
+2.25.1
+

+ 3 - 3
recipes-devtools/clang/clang/0003-compiler-rt-Simplify-cross-compilation.-Don-t-use-na.patch

@@ -1,4 +1,4 @@
-From e1031fdbe63c6065b89e1e15f9bbc62cd36cd898 Mon Sep 17 00:00:00 2001
+From fb844bcda4ed86c4f7246b4249d217dca534bc25 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Thu, 19 May 2016 23:11:45 -0700
 Subject: [PATCH] compiler-rt: Simplify cross-compilation. Don't use
@@ -21,10 +21,10 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 10 insertions(+), 1 deletion(-)
 
 diff --git a/compiler-rt/CMakeLists.txt b/compiler-rt/CMakeLists.txt
-index 8a13508fcb98..2c2bda5befa5 100644
+index 1545340aa8a8..73fad3284810 100644
 --- a/compiler-rt/CMakeLists.txt
 +++ b/compiler-rt/CMakeLists.txt
-@@ -89,7 +89,16 @@ if (COMPILER_RT_STANDALONE_BUILD)
+@@ -80,7 +80,16 @@ if (COMPILER_RT_STANDALONE_BUILD)
    set(CMAKE_CXX_EXTENSIONS NO)
  
    if (NOT LLVM_RUNTIMES_BUILD)

+ 38 - 35
recipes-devtools/clang/clang/0003-RISCV-Add-prefetch-instructions.patch → recipes-devtools/clang/clang/0004-RISCV-Add-prefetch-instructions.patch

@@ -1,29 +1,21 @@
-From 4cd4084046f2dd3d57eb6bee0e88baecd66e49df Mon Sep 17 00:00:00 2001
+From cb5af57ef9b5cff4ed5aa9fa7a5f59cb32b86569 Mon Sep 17 00:00:00 2001
 From: "max.ma" <max.ma@starfivetech.com>
-Date: Sun, 25 Jun 2023 19:36:20 -0700
-Subject: [PATCH 3/9] [RISCV] Add prefetch instructions
+Date: Fri, 22 Dec 2023 02:23:33 -0800
+Subject: [PATCH 4/8] [RISCV] Add prefetch instructions
 
 ---
- .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 10 +++++++
+ .../Target/RISCV/AsmParser/RISCVAsmParser.cpp |  9 ++++++
  .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |  2 ++
- llvm/lib/Target/RISCV/RISCVInstrFormats.td    | 16 +++++++++++
- llvm/lib/Target/RISCV/RISCVInstrInfo.td       | 27 +++++++++++++++++++
- 4 files changed, 55 insertions(+)
+ llvm/lib/Target/RISCV/RISCVInstrFormats.td    | 16 ++++++++++
+ llvm/lib/Target/RISCV/RISCVInstrInfo.td       | 29 +++++++++++++++++++
+ 4 files changed, 56 insertions(+)
 
 diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
-index 9752e398bd99..d577d83bf14e 100644
+index 046a208921ae..ca57a9ba529d 100644
 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
 +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
-@@ -566,6 +566,7 @@ public:
- 
-   bool isUImm2() { return IsUImm<2>(); }
-   bool isUImm3() { return IsUImm<3>(); }
-+  bool isUImm4() { return IsUImm<4>(); }
-   bool isUImm5() { return IsUImm<5>(); }
-   bool isUImm7() { return IsUImm<7>(); }
- 
-@@ -597,6 +598,15 @@ public:
-     return IsConstantImm && isInt<6>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
+@@ -731,6 +731,15 @@ public:
+            VK == RISCVMCExpr::VK_RISCV_None;
    }
  
 +  bool isSImm8() const {
@@ -39,29 +31,31 @@ index 9752e398bd99..d577d83bf14e 100644
      if (!isImm())
        return false;
 diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
-index eb43f4bf0a02..a832f51bd517 100644
+index f86419319dd3..eb9941865261 100644
 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
 +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
-@@ -244,11 +244,13 @@ enum OperandType : unsigned {
-   OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM,
+@@ -243,6 +243,7 @@ enum OperandType : unsigned {
+   OPERAND_UIMM2_LSB0,
    OPERAND_UIMM3,
    OPERAND_UIMM4,
 +  OPERAND_UIMM4_PREF,
    OPERAND_UIMM5,
+   OPERAND_UIMM6,
    OPERAND_UIMM7,
-   OPERAND_UIMM7_LSB00,
-   OPERAND_UIMM8_LSB00,
-   OPERAND_UIMM8_LSB000,
+@@ -253,6 +254,7 @@ enum OperandType : unsigned {
+   OPERAND_UIMM8_GE32,
+   OPERAND_UIMM9_LSB000,
+   OPERAND_UIMM10_LSB00_NONZERO,
 +  OPERAND_SIMM8,
    OPERAND_UIMM12,
    OPERAND_ZERO,
    OPERAND_SIMM5,
 diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
-index f2cd4ed8857f..e913edc47ec2 100644
+index 504952b6bd2f..cdea63fbe26b 100644
 --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
 +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
-@@ -361,6 +361,22 @@ class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
-   let Opcode = opcode.Value;
+@@ -371,6 +371,22 @@ class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+   let Inst{6-0} = opcode.Value;
  }
  
 +class RVInstPref<RISCVOpcode opcode, dag outs, dag ins,
@@ -77,17 +71,17 @@ index f2cd4ed8857f..e913edc47ec2 100644
 +  let Inst{19-15} = rs1;
 +  let Inst{14-12} = 2;
 +  let Inst{11-7} = 0;
-+  let Opcode = opcode.Value;
++  let Inst{6-0} = opcode.Value;
 +}
 +
  class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
                     dag outs, dag ins, string opcodestr, string argstr>
      : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
 diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
-index 75fee3f962d0..5849327ca255 100644
+index e58e3412aea3..0e036728442a 100644
 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
 +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
-@@ -205,6 +205,18 @@ def uimm3 : Operand<XLenVT> {
+@@ -223,6 +223,18 @@ def uimm4 : Operand<XLenVT> {
    let OperandNamespace = "RISCVOp";
  }
  
@@ -106,7 +100,7 @@ index 75fee3f962d0..5849327ca255 100644
  def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
    let ParserMatchClass = UImmAsmOperand<5>;
    let DecoderMethod = "decodeUImmOperand<5>";
-@@ -212,6 +224,14 @@ def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
+@@ -230,6 +242,14 @@ def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
    let OperandNamespace = "RISCVOp";
  }
  
@@ -121,7 +115,7 @@ index 75fee3f962d0..5849327ca255 100644
  def InsnDirectiveOpcode : AsmOperandClass {
    let Name = "InsnDirectiveOpcode";
    let ParserMethod = "parseInsnDirectiveOpcode";
-@@ -560,6 +580,12 @@ class CSR_ir<bits<3> funct3, string opcodestr>
+@@ -593,6 +613,12 @@ class CSR_ir<bits<3> funct3, string opcodestr>
      : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1),
                opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR, ReadCSR]>;
  
@@ -134,14 +128,23 @@ index 75fee3f962d0..5849327ca255 100644
  let hasNoSchedulingInfo = 1,
      hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
  class CSR_ii<bits<3> funct3, string opcodestr>
-@@ -670,6 +696,7 @@ def SLT  : ALU_rr<0b0000000, 0b010, "slt">,
+@@ -701,6 +727,7 @@ def SLT  : ALU_rr<0b0000000, 0b010, "slt">,
  def SLTU : ALU_rr<0b0000000, 0b011, "sltu">,
             Sched<[WriteIALU, ReadIALU, ReadIALU]>;
  }
-+def PREF : PREF_iir<"pref">;
- def XOR  : ALU_rr<0b0000000, 0b100, "xor", /*Commutable*/1>,
++
+ def XOR  : ALU_rr<0b0000000, 0b100, "xor", Commutable=1>,
             Sched<[WriteIALU, ReadIALU, ReadIALU]>;
  def SRL  : ALU_rr<0b0000000, 0b101, "srl">,
+@@ -712,6 +739,8 @@ def OR   : ALU_rr<0b0000000, 0b110, "or", Commutable=1>,
+ def AND  : ALU_rr<0b0000000, 0b111, "and", Commutable=1>,
+            Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+ 
++def PREF : PREF_iir<"pref">;
++
+ let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
+ def FENCE : RVInstI<0b000, OPC_MISC_MEM, (outs),
+                     (ins fencearg:$pred, fencearg:$succ),
 -- 
 2.25.1
 

+ 9 - 9
recipes-devtools/clang/clang/0004-llvm-TargetLibraryInfo-Undefine-libc-functions-if-th.patch

@@ -1,4 +1,4 @@
-From 1279fd32e3809fe9b8f0bddab69042a92637282b Mon Sep 17 00:00:00 2001
+From f258983025dd6a1d8a72f244ac97893c895e5b21 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Sat, 21 May 2016 00:33:20 +0000
 Subject: [PATCH] llvm: TargetLibraryInfo: Undefine libc functions if they are
@@ -14,10 +14,10 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 21 insertions(+), 1 deletion(-)
 
 diff --git a/llvm/include/llvm/Analysis/TargetLibraryInfo.def b/llvm/include/llvm/Analysis/TargetLibraryInfo.def
-index 5f6af3514fc2..9ac2e912590f 100644
+index 03ac422d3e6b..3080b4758894 100644
 --- a/llvm/include/llvm/Analysis/TargetLibraryInfo.def
 +++ b/llvm/include/llvm/Analysis/TargetLibraryInfo.def
-@@ -1303,6 +1303,9 @@ TLI_DEFINE_STRING_INTERNAL("fopen")
+@@ -1348,6 +1348,9 @@ TLI_DEFINE_STRING_INTERNAL("fopen")
  TLI_DEFINE_SIG_INTERNAL(Ptr, Ptr, Ptr)
  
  /// FILE *fopen64(const char *filename, const char *opentype)
@@ -27,7 +27,7 @@ index 5f6af3514fc2..9ac2e912590f 100644
  TLI_DEFINE_ENUM_INTERNAL(fopen64)
  TLI_DEFINE_STRING_INTERNAL("fopen64")
  TLI_DEFINE_SIG_INTERNAL(Ptr, Ptr, Ptr)
-@@ -1381,7 +1384,9 @@ TLI_DEFINE_SIG_INTERNAL(Int, Ptr, Long, Int)
+@@ -1426,7 +1429,9 @@ TLI_DEFINE_SIG_INTERNAL(Int, Ptr, Long, Int)
  TLI_DEFINE_ENUM_INTERNAL(fseeko)
  TLI_DEFINE_STRING_INTERNAL("fseeko")
  TLI_DEFINE_SIG_INTERNAL(Int, Ptr, IntX, Int)
@@ -38,7 +38,7 @@ index 5f6af3514fc2..9ac2e912590f 100644
  /// int fseeko64(FILE *stream, off64_t offset, int whence)
  TLI_DEFINE_ENUM_INTERNAL(fseeko64)
  TLI_DEFINE_STRING_INTERNAL("fseeko64")
-@@ -1398,6 +1403,9 @@ TLI_DEFINE_STRING_INTERNAL("fstat")
+@@ -1443,6 +1448,9 @@ TLI_DEFINE_STRING_INTERNAL("fstat")
  TLI_DEFINE_SIG_INTERNAL(Int, Int, Ptr)
  
  /// int fstat64(int filedes, struct stat64 *buf)
@@ -48,7 +48,7 @@ index 5f6af3514fc2..9ac2e912590f 100644
  TLI_DEFINE_ENUM_INTERNAL(fstat64)
  TLI_DEFINE_STRING_INTERNAL("fstat64")
  TLI_DEFINE_SIG_INTERNAL(Int, Int, Ptr)
-@@ -1423,6 +1431,9 @@ TLI_DEFINE_STRING_INTERNAL("ftello")
+@@ -1468,6 +1476,9 @@ TLI_DEFINE_STRING_INTERNAL("ftello")
  TLI_DEFINE_SIG_INTERNAL(IntPlus, Ptr)
  
  /// off64_t ftello64(FILE *stream)
@@ -58,7 +58,7 @@ index 5f6af3514fc2..9ac2e912590f 100644
  TLI_DEFINE_ENUM_INTERNAL(ftello64)
  TLI_DEFINE_STRING_INTERNAL("ftello64")
  TLI_DEFINE_SIG_INTERNAL(Int64, Ptr)
-@@ -1633,6 +1644,9 @@ TLI_DEFINE_STRING_INTERNAL("lstat")
+@@ -1678,6 +1689,9 @@ TLI_DEFINE_STRING_INTERNAL("lstat")
  TLI_DEFINE_SIG_INTERNAL(Int, Ptr, Ptr)
  
  /// int lstat64(const char *path, struct stat64 *buf);
@@ -68,7 +68,7 @@ index 5f6af3514fc2..9ac2e912590f 100644
  TLI_DEFINE_ENUM_INTERNAL(lstat64)
  TLI_DEFINE_STRING_INTERNAL("lstat64")
  TLI_DEFINE_SIG_INTERNAL(Int, Ptr, Ptr)
-@@ -2045,6 +2059,9 @@ TLI_DEFINE_STRING_INTERNAL("stat")
+@@ -2090,6 +2104,9 @@ TLI_DEFINE_STRING_INTERNAL("stat")
  TLI_DEFINE_SIG_INTERNAL(Int, Ptr, Ptr)
  
  /// int stat64(const char *path, struct stat64 *buf);
@@ -78,7 +78,7 @@ index 5f6af3514fc2..9ac2e912590f 100644
  TLI_DEFINE_ENUM_INTERNAL(stat64)
  TLI_DEFINE_STRING_INTERNAL("stat64")
  TLI_DEFINE_SIG_INTERNAL(Int, Ptr, Ptr)
-@@ -2270,6 +2287,9 @@ TLI_DEFINE_STRING_INTERNAL("tmpfile")
+@@ -2315,6 +2332,9 @@ TLI_DEFINE_STRING_INTERNAL("tmpfile")
  TLI_DEFINE_SIG_INTERNAL(Ptr)
  
  /// FILE *tmpfile64(void)

+ 10 - 10
recipes-devtools/clang/clang/0004-RISCV-Add-customer-cache-instructions.patch → recipes-devtools/clang/clang/0005-RISCV-Add-customer-cache-instructions.patch

@@ -1,7 +1,7 @@
-From bcd728e619143e082767170bfd7b255e521923db Mon Sep 17 00:00:00 2001
+From 89088497bdbe65b231ed1c59ce5d07b3fa3f42d5 Mon Sep 17 00:00:00 2001
 From: "yilun.xie" <yilun.xie@starfivetech.com>
-Date: Fri, 29 Oct 2021 10:16:06 +0800
-Subject: [PATCH 4/9] [RISCV] Add customer cache instructions
+Date: Fri, 22 Dec 2023 17:48:39 -0800
+Subject: [PATCH 5/8] [RISCV] Add customer cache instructions
 
 ---
  llvm/lib/Target/RISCV/RISCVInstrFormats.td | 12 ++++++++++++
@@ -9,11 +9,11 @@ Subject: [PATCH 4/9] [RISCV] Add customer cache instructions
  2 files changed, 25 insertions(+)
 
 diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
-index e913edc47ec2..d3953227b0cd 100644
+index cdea63fbe26b..42cfdbc7b886 100644
 --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
 +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
-@@ -377,6 +377,18 @@ class RVInstPref<RISCVOpcode opcode, dag outs, dag ins,
-   let Opcode = opcode.Value;
+@@ -387,6 +387,18 @@ class RVInstPref<RISCVOpcode opcode, dag outs, dag ins,
+   let Inst{6-0} = opcode.Value;
  }
  
 +class RVInstCache<bits<12> cache, RISCVOpcode opcode, dag outs, dag ins,
@@ -25,17 +25,17 @@ index e913edc47ec2..d3953227b0cd 100644
 +  let Inst{19-15} = rs1;
 +  let Inst{14-12} = 0;
 +  let Inst{11-7} = 0;
-+  let Opcode = opcode.Value;
++  let Inst{6-0} = opcode.Value;
 +}
 +
  class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
                     dag outs, dag ins, string opcodestr, string argstr>
      : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
 diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
-index 5849327ca255..6bd3de20b807 100644
+index 0e036728442a..fe2f2ce6a277 100644
 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
 +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
-@@ -586,6 +586,12 @@ class PREF_iir<string opcodestr>
+@@ -619,6 +619,12 @@ class PREF_iir<string opcodestr>
      : RVInstPref<OPC_OP_IMM, (outs), (ins uimm4_pref:$imm4, simm8:$imm8, GPR:$rs1),
                opcodestr, "$imm4, ${imm8}(${rs1})">;
  
@@ -48,7 +48,7 @@ index 5849327ca255..6bd3de20b807 100644
  let hasNoSchedulingInfo = 1,
      hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
  class CSR_ii<bits<3> funct3, string opcodestr>
-@@ -773,6 +779,13 @@ def WRS_STO : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "wrs.sto", "">,
+@@ -806,6 +812,13 @@ def WRS_STO : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "wrs.sto", "">,
  
  } // hasSideEffects = 1, mayLoad = 0, mayStore = 0
  

+ 2 - 2
recipes-devtools/clang/clang/0005-llvm-allow-env-override-of-exe-and-libdir-path.patch

@@ -1,4 +1,4 @@
-From 8f8e25be1822d93341b0e32ba42d22c8c54016d4 Mon Sep 17 00:00:00 2001
+From 588a8694c6540e31140c7e242bfb5e279d6ca08c Mon Sep 17 00:00:00 2001
 From: Martin Kelly <mkelly@xevo.com>
 Date: Fri, 19 May 2017 00:22:57 -0700
 Subject: [PATCH] llvm: allow env override of exe and libdir path
@@ -19,7 +19,7 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 19 insertions(+), 6 deletions(-)
 
 diff --git a/llvm/tools/llvm-config/llvm-config.cpp b/llvm/tools/llvm-config/llvm-config.cpp
-index b1d795a0a349..dbeddeb2152e 100644
+index e86eb2b44b10..7b2abf318dbe 100644
 --- a/llvm/tools/llvm-config/llvm-config.cpp
 +++ b/llvm/tools/llvm-config/llvm-config.cpp
 @@ -246,6 +246,13 @@ Typical components:\n\

+ 10 - 13
recipes-devtools/clang/clang/0005-RISCV-Add-multilib-v-b-support-for-baremetal-toolcha.patch → recipes-devtools/clang/clang/0006-RISCV-Add-multilib-v-b-support-for-baremetal-toolcha.patch

@@ -1,17 +1,17 @@
-From f24280ce4b015090f4da8de03d5b57bfc6756de8 Mon Sep 17 00:00:00 2001
+From f4613904612d3c145b8a044adb0bad78c6b1bcb3 Mon Sep 17 00:00:00 2001
 From: "max.ma" <max.ma@starfivetech.com>
 Date: Wed, 5 Jan 2022 19:27:39 -0800
-Subject: [PATCH 5/9] [RISCV] Add multilib v&b support for baremetal toolchain
+Subject: [PATCH 6/8] [RISCV] Add multilib v&b support for baremetal toolchain
 
 ---
- clang/lib/Driver/ToolChains/Gnu.cpp | 30 +++++++++++++++++++++++++++--
- 1 file changed, 28 insertions(+), 2 deletions(-)
+ clang/lib/Driver/ToolChains/Gnu.cpp | 28 +++++++++++++++++++++++++++-
+ 1 file changed, 27 insertions(+), 1 deletion(-)
 
 diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp
-index 4f2340316654..c1737fe56635 100644
+index 40038dce47d8..8aa483ccd4f3 100644
 --- a/clang/lib/Driver/ToolChains/Gnu.cpp
 +++ b/clang/lib/Driver/ToolChains/Gnu.cpp
-@@ -1695,7 +1695,8 @@ static void findRISCVBareMetalMultilibs(const Driver &D,
+@@ -1739,7 +1739,8 @@ static void findRISCVBareMetalMultilibs(const Driver &D,
    constexpr RiscvMultilib RISCVMultilibSet[] = {
        {"rv32i", "ilp32"},     {"rv32im", "ilp32"},     {"rv32iac", "ilp32"},
        {"rv32imac", "ilp32"},  {"rv32imafc", "ilp32f"}, {"rv64imac", "lp64"},
@@ -19,9 +19,9 @@ index 4f2340316654..c1737fe56635 100644
 +      {"rv64imafdc", "lp64d"}, {"rv64imafdc_zba_zbb_zbc_zbs", "lp64d"},
 +      {"rv64imafdcv_zba_zbb_zbc_zbs", "lp64d"}, {"rv64imafdcv", "lp64d"},};
  
-   std::vector<Multilib> Ms;
+   std::vector<MultilibBuilder> Ms;
    for (auto Element : RISCVMultilibSet) {
-@@ -1721,8 +1722,33 @@ static void findRISCVBareMetalMultilibs(const Driver &D,
+@@ -1766,6 +1767,31 @@ static void findRISCVBareMetalMultilibs(const Driver &D,
    llvm::StringSet<> Added_ABIs;
    StringRef ABIName = tools::riscv::getRISCVABI(Args, TargetTriple);
    StringRef MArch = tools::riscv::getRISCVArch(Args, TargetTriple);
@@ -51,11 +51,8 @@ index 4f2340316654..c1737fe56635 100644
 +  Ext += Extra;  
 +  
    for (auto Element : RISCVMultilibSet) {
--    addMultilibFlag(MArch == Element.march,
-+    addMultilibFlag(Ext == Element.march,
-                     Twine("march=", Element.march).str().c_str(), Flags);
-     if (!Added_ABIs.count(Element.mabi)) {
-       Added_ABIs.insert(Element.mabi);
+     addMultilibFlag(MArch == Element.march,
+                     Twine("-march=", Element.march).str().c_str(), Flags);
 -- 
 2.25.1
 

+ 20 - 7
recipes-devtools/clang/clang/0006-clang-driver-Check-sysroot-for-ldso-path.patch

@@ -1,4 +1,4 @@
-From 953b9d2c5a7ef4224dec304154feceb30e2b836f Mon Sep 17 00:00:00 2001
+From f033c3e6da2f09e627cf8cf8fbd753e07e0ebacd Mon Sep 17 00:00:00 2001
 From: Dan McGregor <dan.mcgregor@usask.ca>
 Date: Wed, 26 Apr 2017 20:29:41 -0600
 Subject: [PATCH] clang: driver: Check sysroot for ldso path
@@ -11,14 +11,27 @@ Upstream-Status: Pending
 Signed-off-by: Dan McGregor <dan.mcgregor@usask.ca>
 Signed-off-by: Khem Raj <raj.khem@gmail.com>
 ---
- clang/lib/Driver/ToolChains/Linux.cpp | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
+ clang/lib/Driver/ToolChains/Linux.cpp | 22 +++++++++++++++++++++-
+ 1 file changed, 21 insertions(+), 1 deletion(-)
 
 diff --git a/clang/lib/Driver/ToolChains/Linux.cpp b/clang/lib/Driver/ToolChains/Linux.cpp
-index c6fb290ffdb4..2a58f876a68d 100644
+index 1ba222bf83b1..b2ed29621879 100644
 --- a/clang/lib/Driver/ToolChains/Linux.cpp
 +++ b/clang/lib/Driver/ToolChains/Linux.cpp
-@@ -518,11 +518,19 @@ std::string Linux::getDynamicLinker(const ArgList &Args) const {
+@@ -495,7 +495,11 @@ std::string Linux::getDynamicLinker(const ArgList &Args) const {
+         Triple.getEnvironment() == llvm::Triple::GNUEABIHF ||
+         tools::arm::getARMFloatABI(*this, Args) == tools::arm::FloatABI::Hard;
+ 
+-    LibDir = "lib";
++    LibDir = "lib32";
++    if (!getVFS().exists(getDriver().SysRoot + "/" + LibDir + "/" + Loader) &&
++         getVFS().exists(getDriver().SysRoot + "/lib/" + Loader)) {
++        LibDir = "lib";
++    }
+     Loader = HF ? "ld-linux-armhf.so.3" : "ld-linux.so.3";
+     break;
+   }
+@@ -550,11 +554,19 @@ std::string Linux::getDynamicLinker(const ArgList &Args) const {
      LibDir = "lib64";
      Loader =
          (tools::ppc::hasPPCAbiArg(Args, "elfv2")) ? "ld64.so.2" : "ld64.so.1";
@@ -38,7 +51,7 @@ index c6fb290ffdb4..2a58f876a68d 100644
      break;
    case llvm::Triple::riscv32: {
      StringRef ABIName = tools::riscv::getRISCVABI(Args, Triple);
-@@ -544,6 +552,10 @@ std::string Linux::getDynamicLinker(const ArgList &Args) const {
+@@ -576,6 +588,10 @@ std::string Linux::getDynamicLinker(const ArgList &Args) const {
    case llvm::Triple::sparcv9:
      LibDir = "lib64";
      Loader = "ld-linux.so.2";
@@ -49,7 +62,7 @@ index c6fb290ffdb4..2a58f876a68d 100644
      break;
    case llvm::Triple::systemz:
      LibDir = "lib";
-@@ -558,6 +570,10 @@ std::string Linux::getDynamicLinker(const ArgList &Args) const {
+@@ -590,6 +606,10 @@ std::string Linux::getDynamicLinker(const ArgList &Args) const {
  
      LibDir = X32 ? "libx32" : "lib64";
      Loader = X32 ? "ld-linux-x32.so.2" : "ld-linux-x86-64.so.2";

+ 0 - 25
recipes-devtools/clang/clang/0007-Driver-Set-clang-default-dwarf-version-to-4.patch

@@ -1,25 +0,0 @@
-From a10e0f315a96f4b7f2458f377fd9a8de9288f829 Mon Sep 17 00:00:00 2001
-From: "max.ma" <max.ma@starfivetech.com>
-Date: Sun, 1 May 2022 05:51:37 -0700
-Subject: [PATCH 7/9] [Driver] Set clang default dwarf version to 4
-
----
- clang/include/clang/Driver/ToolChain.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/clang/include/clang/Driver/ToolChain.h b/clang/include/clang/Driver/ToolChain.h
-index f75f35dc9e65..a70ae2b17833 100644
---- a/clang/include/clang/Driver/ToolChain.h
-+++ b/clang/include/clang/Driver/ToolChain.h
-@@ -547,7 +547,7 @@ public:
- 
-   // Return the DWARF version to emit, in the absence of arguments
-   // to the contrary.
--  virtual unsigned GetDefaultDwarfVersion() const { return 5; }
-+  virtual unsigned GetDefaultDwarfVersion() const { return 4; }
- 
-   // Some toolchains may have different restrictions on the DWARF version and
-   // may need to adjust it. E.g. NVPTX may need to enforce DWARF2 even when host
--- 
-2.25.1
-

+ 7 - 7
recipes-devtools/clang/clang/0006-RISCV-Change-baremetal-multilib-directory-name-to-al.patch → recipes-devtools/clang/clang/0007-RISCV-Change-baremetal-multilib-directory-name-to-al.patch

@@ -1,7 +1,7 @@
-From 6c56523d3583772c5e4e9102e42ed41abe902dff Mon Sep 17 00:00:00 2001
+From ba7d02560d82733577dd9926663f033496386c27 Mon Sep 17 00:00:00 2001
 From: "max.ma" <max.ma@starfivetech.com>
 Date: Sun, 9 Oct 2022 00:19:02 -0700
-Subject: [PATCH 6/9] [RISCV] Change baremetal multilib directory name to align
+Subject: [PATCH 7/8] [RISCV] Change baremetal multilib directory name to align
  with gcc 12.1
 
 ---
@@ -9,10 +9,10 @@ Subject: [PATCH 6/9] [RISCV] Change baremetal multilib directory name to align
  1 file changed, 14 insertions(+), 2 deletions(-)
 
 diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp
-index c1737fe56635..06aec80f366a 100644
+index 8aa483ccd4f3..462b0ad1a748 100644
 --- a/clang/lib/Driver/ToolChains/Gnu.cpp
 +++ b/clang/lib/Driver/ToolChains/Gnu.cpp
-@@ -1696,7 +1696,11 @@ static void findRISCVBareMetalMultilibs(const Driver &D,
+@@ -1740,7 +1740,11 @@ static void findRISCVBareMetalMultilibs(const Driver &D,
        {"rv32i", "ilp32"},     {"rv32im", "ilp32"},     {"rv32iac", "ilp32"},
        {"rv32imac", "ilp32"},  {"rv32imafc", "ilp32f"}, {"rv64imac", "lp64"},
        {"rv64imafdc", "lp64d"}, {"rv64imafdc_zba_zbb_zbc_zbs", "lp64d"},
@@ -23,9 +23,9 @@ index c1737fe56635..06aec80f366a 100644
 +      {"rv64imafdcv_zicsr_zifencei_zba_zbb_zbc_zbs_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b", "lp64d"},
 +      };   
  
-   std::vector<Multilib> Ms;
+   std::vector<MultilibBuilder> Ms;
    for (auto Element : RISCVMultilibSet) {
-@@ -1722,8 +1726,10 @@ static void findRISCVBareMetalMultilibs(const Driver &D,
+@@ -1767,8 +1771,10 @@ static void findRISCVBareMetalMultilibs(const Driver &D,
    llvm::StringSet<> Added_ABIs;
    StringRef ABIName = tools::riscv::getRISCVABI(Args, TargetTriple);
    StringRef MArch = tools::riscv::getRISCVArch(Args, TargetTriple);
@@ -37,7 +37,7 @@ index c1737fe56635..06aec80f366a 100644
      char c = *I;
      switch (c) {
        default: 
-@@ -1732,12 +1738,18 @@ static void findRISCVBareMetalMultilibs(const Driver &D,
+@@ -1777,12 +1783,18 @@ static void findRISCVBareMetalMultilibs(const Driver &D,
  
        case 'g':
        Ext += "imafd";

+ 3 - 3
recipes-devtools/clang/clang/0007-clang-Driver-tools.cpp-Add-lssp_nonshared-on-musl.patch

@@ -1,4 +1,4 @@
-From c35e16f856192a090696b033bc5a32af18f592ac Mon Sep 17 00:00:00 2001
+From b497f95862cfe82aa2d581798182d2c2112796ae Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Thu, 19 May 2016 21:11:06 -0700
 Subject: [PATCH] clang: Driver/tools.cpp: Add -lssp_nonshared on musl
@@ -14,10 +14,10 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 6 insertions(+)
 
 diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp
-index 4f2340316654..cc9ed4f6b8ac 100644
+index 40038dce47d8..c642946c5cfb 100644
 --- a/clang/lib/Driver/ToolChains/Gnu.cpp
 +++ b/clang/lib/Driver/ToolChains/Gnu.cpp
-@@ -653,6 +653,12 @@ void tools::gnutools::Linker::ConstructJob(Compilation &C, const JobAction &JA,
+@@ -636,6 +636,12 @@ void tools::gnutools::Linker::ConstructJob(Compilation &C, const JobAction &JA,
        if (IsIAMCU)
          CmdArgs.push_back("-lgloss");
  

+ 22 - 14
recipes-devtools/clang/clang/0008-RISCV-Support-b-letter-in-march-string.patch

@@ -1,45 +1,53 @@
-From 7f3eaa0f7b494f9091b1916f208d78ba681b19a3 Mon Sep 17 00:00:00 2001
+From 08bff38b37acf7c5d9b47d7ebc3d90ca7705cbea Mon Sep 17 00:00:00 2001
 From: "max.ma" <max.ma@starfivetech.com>
 Date: Fri, 15 Apr 2022 02:16:43 -0700
-Subject: [PATCH 8/9] [RISCV] Support "b" letter in march string
+Subject: [PATCH 8/8] [RISCV] Support "b" letter in march string
 
 ---
- llvm/lib/Support/RISCVISAInfo.cpp      |  9 ++++++++-
+ llvm/lib/Support/RISCVISAInfo.cpp      | 10 +++++++++-
  llvm/lib/Target/RISCV/RISCVFeatures.td | 12 ++++++++++++
- 2 files changed, 20 insertions(+), 1 deletion(-)
+ 2 files changed, 21 insertions(+), 1 deletion(-)
 
 diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
-index 7cb1147d4265..8b3dcc91746b 100644
+index 70fab8010831..bbebcda64b83 100644
 --- a/llvm/lib/Support/RISCVISAInfo.cpp
 +++ b/llvm/lib/Support/RISCVISAInfo.cpp
-@@ -64,6 +64,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
+@@ -51,6 +51,7 @@ static const char *RISCVGImplications[] = {
+ // NOTE: This table should be sorted alphabetically by extension name.
+ static const RISCVSupportedExtension SupportedExtensions[] = {
+     {"a", RISCVExtensionVersion{2, 1}},
++    {"b", RISCVExtensionVersion{1, 0}},
+     {"c", RISCVExtensionVersion{2, 0}},
+     {"d", RISCVExtensionVersion{2, 2}},
+     {"e", RISCVExtensionVersion{2, 0}},
+@@ -88,6 +89,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
+     {"zba", RISCVExtensionVersion{1, 0}},
      {"zbb", RISCVExtensionVersion{1, 0}},
      {"zbc", RISCVExtensionVersion{1, 0}},
-     {"zbs", RISCVExtensionVersion{1, 0}},
-+    {"b", RISCVExtensionVersion{1, 0}},
- 
++
      {"zbkb", RISCVExtensionVersion{1, 0}},
      {"zbkc", RISCVExtensionVersion{1, 0}},
-@@ -707,7 +708,13 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
+     {"zbkx", RISCVExtensionVersion{1, 0}},
+@@ -806,7 +808,13 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
                                 "unsupported standard user-level extension '%c'",
                                 C);
      }
--    ISAInfo->addExtension(std::string(1, C), Major, Minor);
+-    ISAInfo->addExtension(StringRef(&C, 1), Major, Minor);
 +    if (C == 'b') {
 +      ISAInfo->addExtension("zba", Major, Minor);
 +      ISAInfo->addExtension("zbb", Major, Minor);
 +      ISAInfo->addExtension("zbc", Major, Minor);
 +      ISAInfo->addExtension("zbs", Major, Minor);
 +    } else
-+      ISAInfo->addExtension(std::string(1, C), Major, Minor);
++      ISAInfo->addExtension(StringRef(&C, 1), Major, Minor);
  
      // Consume full extension name and version, including any optional '_'
      // between this extension and the next
 diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
-index be8834fd4c2f..c0443eddeb90 100644
+index 4ce9c41eaf5c..da49f73bdbf7 100644
 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td
 +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
-@@ -547,3 +547,15 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
+@@ -891,3 +891,15 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
      "AllowTaggedGlobals",
      "true", "Use an instruction sequence for taking the address of a global "
      "that allows a memory tag in the upper address bits">;

+ 4 - 4
recipes-devtools/clang/clang/0008-clang-Prepend-trailing-to-sysroot.patch

@@ -1,4 +1,4 @@
-From 51b99c1b9836f2e6967f1192f16fb639e127df2e Mon Sep 17 00:00:00 2001
+From acfefc5462044827ba3b7d0ac7512a9d9461a833 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Thu, 16 Mar 2017 09:02:13 -0700
 Subject: [PATCH] clang: Prepend trailing '/' to sysroot
@@ -25,12 +25,12 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/clang/lib/Driver/ToolChains/Linux.cpp b/clang/lib/Driver/ToolChains/Linux.cpp
-index 2a58f876a68d..c68a842b45e0 100644
+index b2ed29621879..d2fa4b2f11cf 100644
 --- a/clang/lib/Driver/ToolChains/Linux.cpp
 +++ b/clang/lib/Driver/ToolChains/Linux.cpp
-@@ -184,7 +184,7 @@ Linux::Linux(const Driver &D, const llvm::Triple &Triple, const ArgList &Args)
+@@ -215,7 +215,7 @@ Linux::Linux(const Driver &D, const llvm::Triple &Triple, const ArgList &Args)
    Multilibs = GCCInstallation.getMultilibs();
-   SelectedMultilib = GCCInstallation.getMultilib();
+   SelectedMultilibs.assign({GCCInstallation.getMultilib()});
    llvm::Triple::ArchType Arch = Triple.getArch();
 -  std::string SysRoot = computeSysRoot();
 +  std::string SysRoot = computeSysRoot() + "/";

+ 0 - 38
recipes-devtools/clang/clang/0009-RISCV-Align-default-march-with-dubhe-gcc-toolchain.patch

@@ -1,38 +0,0 @@
-From a108ed8c2f32b4c5929b3bd72f1b4d1830ddcd4a Mon Sep 17 00:00:00 2001
-From: "max.ma" <max.ma@starfivetech.com>
-Date: Mon, 26 Jun 2023 03:04:07 -0700
-Subject: [PATCH 9/9] [RISCV] Align default march with dubhe gcc toolchain
-
----
- clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 8 ++------
- 1 file changed, 2 insertions(+), 6 deletions(-)
-
-diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
-index 4c34c09d5589..dddf8d7cd168 100644
---- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
-+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
-@@ -220,9 +220,7 @@ StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
-     else
-       return "ilp32d";
-   } else {
--    if (Triple.getOS() == llvm::Triple::UnknownOS)
--      return "lp64";
--    else
-+      //align default march with dubhe gcc toolchain
-       return "lp64d";
-   }
- }
-@@ -299,9 +297,7 @@ StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args,
-     else
-       return "rv32imafdc";
-   } else {
--    if (Triple.getOS() == llvm::Triple::UnknownOS)
--      return "rv64imac";
--    else
-+      //align default march with dubhe gcc toolchain
-       return "rv64imafdc";
-   }
- }
--- 
-2.25.1
-

+ 5 - 5
recipes-devtools/clang/clang/0009-clang-Look-inside-the-target-sysroot-for-compiler-ru.patch

@@ -1,4 +1,4 @@
-From 243f40f492fbbbc3104de0fc77eef3122a4a42c4 Mon Sep 17 00:00:00 2001
+From 9069a7f709cdb5392c9e0ecd863d62176d080a91 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Thu, 16 Mar 2017 19:06:26 -0700
 Subject: [PATCH] clang: Look inside the target sysroot for compiler runtime
@@ -16,10 +16,10 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 5 insertions(+), 1 deletion(-)
 
 diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp
-index bc70205a6c01..527efd421e01 100644
+index 8dafc3d481c2..3e0f7b64b0db 100644
 --- a/clang/lib/Driver/ToolChain.cpp
 +++ b/clang/lib/Driver/ToolChain.cpp
-@@ -13,6 +13,7 @@
+@@ -15,6 +15,7 @@
  #include "ToolChains/InterfaceStubs.h"
  #include "clang/Basic/ObjCRuntime.h"
  #include "clang/Basic/Sanitizers.h"
@@ -27,7 +27,7 @@ index bc70205a6c01..527efd421e01 100644
  #include "clang/Config/config.h"
  #include "clang/Driver/Action.h"
  #include "clang/Driver/Driver.h"
-@@ -488,7 +489,10 @@ StringRef ToolChain::getOSLibName() const {
+@@ -595,7 +596,10 @@ StringRef ToolChain::getOSLibName() const {
  }
  
  std::string ToolChain::getCompilerRTPath() const {
@@ -38,4 +38,4 @@ index bc70205a6c01..527efd421e01 100644
 +                            CLANG_VERSION_STRING);
    if (isBareMetal()) {
      llvm::sys::path::append(Path, "lib", getOSLibName());
-     Path += SelectedMultilib.gccSuffix();
+     if (!SelectedMultilibs.empty()) {

+ 3 - 4
recipes-devtools/clang/clang/0010-clang-Define-releative-gcc-installation-dir.patch

@@ -1,4 +1,4 @@
-From d1fdcd76fc759e644d697c967ddfbeae279aa7ac Mon Sep 17 00:00:00 2001
+From fcc667e02238ad83e5db2ecc1f060af6dcc618f1 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Sat, 20 Mar 2021 16:09:16 -0700
 Subject: [PATCH] clang: Define / releative gcc installation dir
@@ -9,17 +9,16 @@ and other standard headers and libraries from gcc
 installation in OE
 
 Upstream-Status: Pending
-
 Signed-off-by: Khem Raj <raj.khem@gmail.com>
 ---
  clang/lib/Driver/ToolChains/Gnu.cpp | 14 +++++++-------
  1 file changed, 7 insertions(+), 7 deletions(-)
 
 diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp
-index cc9ed4f6b8ac..846163329d92 100644
+index c642946c5cfb..e1c2cdc0e93b 100644
 --- a/clang/lib/Driver/ToolChains/Gnu.cpp
 +++ b/clang/lib/Driver/ToolChains/Gnu.cpp
-@@ -2681,19 +2681,19 @@ void Generic_GCC::GCCInstallationDetector::ScanLibDirForGCCTriple(
+@@ -2744,19 +2744,19 @@ void Generic_GCC::GCCInstallationDetector::ScanLibDirForGCCTriple(
      // Whether this library suffix is relevant for the triple.
      bool Active;
    } Suffixes[] = {

+ 3 - 3
recipes-devtools/clang/clang/0011-clang-Add-lpthread-and-ldl-along-with-lunwind-for-st.patch

@@ -1,4 +1,4 @@
-From 16ec16d11424040b83b360199ab785650bd1fb65 Mon Sep 17 00:00:00 2001
+From 85230d89fc000068097599df6c8750d75cf84c72 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Wed, 31 Jul 2019 22:51:39 -0700
 Subject: [PATCH] clang: Add -lpthread and -ldl along with -lunwind for static
@@ -21,10 +21,10 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 2 insertions(+)
 
 diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp
-index 0883631dfe98..dfab4075e03e 100644
+index 0d6907b8e5c7..778da2b7b4a5 100644
 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
 +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
-@@ -1718,6 +1718,8 @@ static void AddUnwindLibrary(const ToolChain &TC, const Driver &D,
+@@ -1820,6 +1820,8 @@ static void AddUnwindLibrary(const ToolChain &TC, const Driver &D,
          CmdArgs.push_back("-lunwind");
      } else if (LGT == LibGccType::StaticLibGcc) {
        CmdArgs.push_back("-l:libunwind.a");

+ 2 - 2
recipes-devtools/clang/clang/0012-Pass-PYTHON_EXECUTABLE-when-cross-compiling-for-nati.patch

@@ -1,4 +1,4 @@
-From e9e65cc455973c05ae3502b84bc90b3f8b70b438 Mon Sep 17 00:00:00 2001
+From 84a2bee19c577eb56c381903959c77271a4368e5 Mon Sep 17 00:00:00 2001
 From: Anuj Mittal <anuj.mittal@intel.com>
 Date: Thu, 26 Dec 2019 12:56:16 -0800
 Subject: [PATCH] Pass PYTHON_EXECUTABLE when cross compiling for native build
@@ -11,7 +11,7 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 1 insertion(+)
 
 diff --git a/llvm/cmake/modules/CrossCompile.cmake b/llvm/cmake/modules/CrossCompile.cmake
-index a46a0fd630b0..55f6dba2901a 100644
+index 6af47b51d4c6..bf9adea6814a 100644
 --- a/llvm/cmake/modules/CrossCompile.cmake
 +++ b/llvm/cmake/modules/CrossCompile.cmake
 @@ -86,6 +86,7 @@ function(llvm_create_cross_target project_name target_name toolchain buildtype)

+ 1 - 1
recipes-devtools/clang/clang/0013-Check-for-atomic-double-intrinsics.patch

@@ -1,4 +1,4 @@
-From b0310dcff11cade76add2b84f9d694fc626284ee Mon Sep 17 00:00:00 2001
+From 129d994b584cab112d39916075eef8c833813677 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Mon, 18 Nov 2019 17:00:29 -0800
 Subject: [PATCH] Check for atomic<double> intrinsics

+ 4 - 4
recipes-devtools/clang/clang/0014-libcxx-Add-compiler-runtime-library-to-link-step-for.patch

@@ -1,4 +1,4 @@
-From fbe1464c92e5b4e078390c040f0a7f446cda81f0 Mon Sep 17 00:00:00 2001
+From c646fe1dd7b9fcb80de27c8b4da916bd9e0adb7f Mon Sep 17 00:00:00 2001
 From: Jeremy Puhlman <jpuhlman@mvista.com>
 Date: Thu, 16 Jan 2020 21:16:10 +0000
 Subject: [PATCH] libcxx: Add compiler runtime library to link step for libcxx
@@ -14,10 +14,10 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/libcxx/src/CMakeLists.txt b/libcxx/src/CMakeLists.txt
-index 9ff2a62e9394..e76625d5a5ac 100644
+index 35b466527096..f261c1def1ca 100644
 --- a/libcxx/src/CMakeLists.txt
 +++ b/libcxx/src/CMakeLists.txt
-@@ -200,7 +200,7 @@ if (LIBCXX_ENABLE_SHARED)
+@@ -189,7 +189,7 @@ if (LIBCXX_ENABLE_SHARED)
    add_library(cxx_shared SHARED ${exclude_from_all} ${LIBCXX_SOURCES} ${LIBCXX_HEADERS})
    target_include_directories(cxx_shared PRIVATE ${CMAKE_CURRENT_SOURCE_DIR})
    target_link_libraries(cxx_shared PUBLIC cxx-headers
@@ -26,7 +26,7 @@ index 9ff2a62e9394..e76625d5a5ac 100644
    set_target_properties(cxx_shared
      PROPERTIES
        COMPILE_FLAGS "${LIBCXX_COMPILE_FLAGS}"
-@@ -294,7 +294,7 @@ if (LIBCXX_ENABLE_STATIC)
+@@ -282,7 +282,7 @@ if (LIBCXX_ENABLE_STATIC)
    add_library(cxx_static STATIC ${exclude_from_all} ${LIBCXX_SOURCES} ${LIBCXX_HEADERS})
    target_include_directories(cxx_static PRIVATE ${CMAKE_CURRENT_SOURCE_DIR})
    target_link_libraries(cxx_static PUBLIC cxx-headers

+ 9 - 9
recipes-devtools/clang/clang/0015-clang-llvm-cmake-Fix-configure-for-packages-using-fi.patch

@@ -1,4 +1,4 @@
-From f16083f3436f1286941547b3036787f128c9d8a4 Mon Sep 17 00:00:00 2001
+From ae428248f697ccf8b98c0da5a9983a1f0ff89bd5 Mon Sep 17 00:00:00 2001
 From: Ovidiu Panait <ovidiu.panait@windriver.com>
 Date: Fri, 31 Jan 2020 10:56:11 +0200
 Subject: [PATCH] clang,llvm: cmake: Fix configure for packages using
@@ -52,10 +52,10 @@ index 75b0080f6715..ddf446a13eca 100644
    endif()
  endmacro()
 diff --git a/llvm/cmake/modules/AddLLVM.cmake b/llvm/cmake/modules/AddLLVM.cmake
-index 94fc83db9344..5155b0222d87 100644
+index 230620c37027..cb5a9bd41ee8 100644
 --- a/llvm/cmake/modules/AddLLVM.cmake
 +++ b/llvm/cmake/modules/AddLLVM.cmake
-@@ -1335,7 +1335,6 @@ macro(llvm_add_tool project name)
+@@ -1353,7 +1353,6 @@ macro(llvm_add_tool project name)
        if( LLVM_BUILD_TOOLS )
          get_target_export_arg(${name} LLVM export_to_llvmexports)
          install(TARGETS ${name}
@@ -63,7 +63,7 @@ index 94fc83db9344..5155b0222d87 100644
                  RUNTIME DESTINATION ${${project}_TOOLS_INSTALL_DIR}
                  COMPONENT ${name})
  
-@@ -1346,9 +1345,6 @@ macro(llvm_add_tool project name)
+@@ -1364,9 +1363,6 @@ macro(llvm_add_tool project name)
          endif()
        endif()
      endif()
@@ -73,7 +73,7 @@ index 94fc83db9344..5155b0222d87 100644
      set_target_properties(${name} PROPERTIES FOLDER "Tools")
    endif()
  endmacro(llvm_add_tool project name)
-@@ -1393,7 +1389,6 @@ macro(add_llvm_utility name)
+@@ -1411,7 +1407,6 @@ macro(add_llvm_utility name)
      if (LLVM_INSTALL_UTILS AND LLVM_BUILD_UTILS)
        get_target_export_arg(${name} LLVM export_to_llvmexports)
        install(TARGETS ${name}
@@ -81,7 +81,7 @@ index 94fc83db9344..5155b0222d87 100644
                RUNTIME DESTINATION ${LLVM_UTILS_INSTALL_DIR}
                COMPONENT ${name})
  
-@@ -1402,7 +1397,6 @@ macro(add_llvm_utility name)
+@@ -1420,7 +1415,6 @@ macro(add_llvm_utility name)
                                   DEPENDS ${name}
                                   COMPONENT ${name})
        endif()
@@ -90,10 +90,10 @@ index 94fc83db9344..5155b0222d87 100644
        set_property(GLOBAL APPEND PROPERTY LLVM_EXPORTS_BUILDTREE_ONLY ${name})
      endif()
 diff --git a/llvm/cmake/modules/TableGen.cmake b/llvm/cmake/modules/TableGen.cmake
-index 70c2edb8c833..e012fea08982 100644
+index 7fd6628ef55d..57a996d03755 100644
 --- a/llvm/cmake/modules/TableGen.cmake
 +++ b/llvm/cmake/modules/TableGen.cmake
-@@ -189,12 +189,7 @@ macro(add_tablegen target project)
+@@ -195,12 +195,7 @@ macro(add_tablegen target project)
  
    if (ADD_TABLEGEN_DESTINATION AND NOT LLVM_INSTALL_TOOLCHAIN_ONLY AND
        (LLVM_BUILD_UTILS OR ${target} IN_LIST LLVM_DISTRIBUTION_COMPONENTS))
@@ -106,7 +106,7 @@ index 70c2edb8c833..e012fea08982 100644
              COMPONENT ${target}
              RUNTIME DESTINATION "${ADD_TABLEGEN_DESTINATION}")
      if(NOT LLVM_ENABLE_IDE)
-@@ -205,6 +200,5 @@ macro(add_tablegen target project)
+@@ -211,6 +206,5 @@ macro(add_tablegen target project)
    endif()
    if(ADD_TABLEGEN_EXPORT)
      string(TOUPPER ${ADD_TABLEGEN_EXPORT} export_upper)

+ 5 - 3
recipes-devtools/clang/clang/0016-clang-Fix-resource-dir-location-for-cross-toolchains.patch

@@ -1,4 +1,4 @@
-From 3b58bf71bf2908d1c7361e420b13330366402ea6 Mon Sep 17 00:00:00 2001
+From f45ef34d9d5a3ff049c39dd2d3d6aed72eb5b0bc Mon Sep 17 00:00:00 2001
 From: Jim Broadus <jbroadus@xevo.com>
 Date: Thu, 26 Mar 2020 16:05:53 -0700
 Subject: [PATCH] clang: Fix resource dir location for cross toolchains
@@ -20,15 +20,17 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 7 insertions(+), 1 deletion(-)
 
 diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
-index a268f2fa8fc5..ab813044dc8c 100644
+index bdbdad9362e1..a0d4a04b42bb 100644
 --- a/clang/lib/Driver/Driver.cpp
 +++ b/clang/lib/Driver/Driver.cpp
-@@ -181,7 +181,13 @@ std::string Driver::GetResourcesPath(StringRef BinaryPath,
+@@ -183,9 +183,15 @@ std::string Driver::GetResourcesPath(StringRef BinaryPath,
      // With a static-library build of libclang, LibClangPath will contain the
      // path of the embedding binary, which for LLVM binaries will be in bin/.
      // ../lib gets us to lib/ in both cases.
 -    P = llvm::sys::path::parent_path(Dir);
 +    Dir = std::string(llvm::sys::path::parent_path(Dir));
+     // This search path is also created in the COFF driver of lld, so any
+     // changes here also needs to happen in lld/COFF/Driver.cpp
 +
 +    // OE cross toolchains are installed, by default, in a subdir of bin.
 +    if (llvm::sys::path::filename(Dir) == "bin") {

+ 19 - 8
recipes-devtools/clang/clang/0017-clang-driver-Add-dyld-prefix-when-checking-sysroot-f.patch

@@ -1,4 +1,4 @@
-From a9127817f4ceb0f19e99c89c08ffb1d9d256d1a2 Mon Sep 17 00:00:00 2001
+From 53138d6a7fe341821a73719f776ee5535d759c3b Mon Sep 17 00:00:00 2001
 From: Oleksandr Ocheretnyi <oocheret@cisco.com>
 Date: Wed, 15 Apr 2020 00:08:39 +0300
 Subject: [PATCH] clang: driver: Add dyld-prefix when checking sysroot for ldso
@@ -15,14 +15,25 @@ Upstream-Status: Pending
 Signed-off-by: Oleksandr Ocheretnyi <oocheret@cisco.com>
 Signed-off-by: Khem Raj <raj.khem@gmail.com>
 ---
- clang/lib/Driver/ToolChains/Linux.cpp | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
+ clang/lib/Driver/ToolChains/Linux.cpp | 20 ++++++++++----------
+ 1 file changed, 10 insertions(+), 10 deletions(-)
 
 diff --git a/clang/lib/Driver/ToolChains/Linux.cpp b/clang/lib/Driver/ToolChains/Linux.cpp
-index c68a842b45e0..ca9f5f2e4f74 100644
+index d2fa4b2f11cf..42b88e76a9d5 100644
 --- a/clang/lib/Driver/ToolChains/Linux.cpp
 +++ b/clang/lib/Driver/ToolChains/Linux.cpp
-@@ -518,8 +518,8 @@ std::string Linux::getDynamicLinker(const ArgList &Args) const {
+@@ -496,8 +496,8 @@ std::string Linux::getDynamicLinker(const ArgList &Args) const {
+         tools::arm::getARMFloatABI(*this, Args) == tools::arm::FloatABI::Hard;
+ 
+     LibDir = "lib32";
+-    if (!getVFS().exists(getDriver().SysRoot + "/" + LibDir + "/" + Loader) &&
+-         getVFS().exists(getDriver().SysRoot + "/lib/" + Loader)) {
++    if (!getVFS().exists(getDriver().SysRoot + getDriver().DyldPrefix + "/" + LibDir + "/" + Loader) &&
++         getVFS().exists(getDriver().SysRoot + getDriver().DyldPrefix + "/lib/" + Loader)) {
+         LibDir = "lib";
+     }
+     Loader = HF ? "ld-linux-armhf.so.3" : "ld-linux.so.3";
+@@ -554,8 +554,8 @@ std::string Linux::getDynamicLinker(const ArgList &Args) const {
      LibDir = "lib64";
      Loader =
          (tools::ppc::hasPPCAbiArg(Args, "elfv2")) ? "ld64.so.2" : "ld64.so.1";
@@ -33,7 +44,7 @@ index c68a842b45e0..ca9f5f2e4f74 100644
          LibDir = "lib";
      }
      break;
-@@ -527,8 +527,8 @@ std::string Linux::getDynamicLinker(const ArgList &Args) const {
+@@ -563,8 +563,8 @@ std::string Linux::getDynamicLinker(const ArgList &Args) const {
      LibDir = "lib64";
      Loader =
          (tools::ppc::hasPPCAbiArg(Args, "elfv1")) ? "ld64.so.1" : "ld64.so.2";
@@ -44,7 +55,7 @@ index c68a842b45e0..ca9f5f2e4f74 100644
          LibDir = "lib";
      }
      break;
-@@ -552,8 +552,8 @@ std::string Linux::getDynamicLinker(const ArgList &Args) const {
+@@ -588,8 +588,8 @@ std::string Linux::getDynamicLinker(const ArgList &Args) const {
    case llvm::Triple::sparcv9:
      LibDir = "lib64";
      Loader = "ld-linux.so.2";
@@ -55,7 +66,7 @@ index c68a842b45e0..ca9f5f2e4f74 100644
          LibDir = "lib";
      }
      break;
-@@ -570,8 +570,8 @@ std::string Linux::getDynamicLinker(const ArgList &Args) const {
+@@ -606,8 +606,8 @@ std::string Linux::getDynamicLinker(const ArgList &Args) const {
  
      LibDir = X32 ? "libx32" : "lib64";
      Loader = X32 ? "ld-linux-x32.so.2" : "ld-linux-x86-64.so.2";

+ 5 - 16
recipes-devtools/clang/clang/0018-clang-Use-python3-in-python-scripts.patch

@@ -1,4 +1,4 @@
-From 5b8fe61522fbf453b514fc1c9f317742cf34cbcd Mon Sep 17 00:00:00 2001
+From 61de53f94868705c7a0379c3f20e6b9de76c6198 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Wed, 14 Oct 2020 22:19:57 -0700
 Subject: [PATCH] clang: Use python3 in python scripts
@@ -10,32 +10,21 @@ Upstream-Status: Pending
 Signed-off-by: Khem Raj <raj.khem@gmail.com>
 ---
  .../find-all-symbols/tool/run-find-all-symbols.py               | 2 +-
- clang-tools-extra/clang-tidy/tool/clang-tidy-diff.py            | 2 +-
  clang/tools/scan-view/bin/scan-view                             | 2 +-
- 3 files changed, 3 insertions(+), 3 deletions(-)
+ 2 files changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/clang-tools-extra/clang-include-fixer/find-all-symbols/tool/run-find-all-symbols.py b/clang-tools-extra/clang-include-fixer/find-all-symbols/tool/run-find-all-symbols.py
-index a0fa64592e62..27aa97a35571 100755
+index 471dbf8c110b..f98385dc6651 100755
 --- a/clang-tools-extra/clang-include-fixer/find-all-symbols/tool/run-find-all-symbols.py
 +++ b/clang-tools-extra/clang-include-fixer/find-all-symbols/tool/run-find-all-symbols.py
 @@ -1,4 +1,4 @@
 -#!/usr/bin/env python
 +#!/usr/bin/env python3
  #
- #=- run-find-all-symbols.py - Parallel find-all-symbols runner -*- python  -*-=#
- #
-diff --git a/clang-tools-extra/clang-tidy/tool/clang-tidy-diff.py b/clang-tools-extra/clang-tidy/tool/clang-tidy-diff.py
-index a26d2144b7f9..396a201b667e 100755
---- a/clang-tools-extra/clang-tidy/tool/clang-tidy-diff.py
-+++ b/clang-tools-extra/clang-tidy/tool/clang-tidy-diff.py
-@@ -1,4 +1,4 @@
--#!/usr/bin/env python
-+#!/usr/bin/env python3
- #
- #===- clang-tidy-diff.py - ClangTidy Diff Checker -----------*- python -*--===#
+ # =- run-find-all-symbols.py - Parallel find-all-symbols runner -*- python  -*-=#
  #
 diff --git a/clang/tools/scan-view/bin/scan-view b/clang/tools/scan-view/bin/scan-view
-index 6165432e7af8..07effbca5969 100755
+index d01aebb4029a..f3375804654d 100755
 --- a/clang/tools/scan-view/bin/scan-view
 +++ b/clang/tools/scan-view/bin/scan-view
 @@ -1,4 +1,4 @@

+ 3 - 3
recipes-devtools/clang/clang/0019-For-x86_64-set-Yocto-based-GCC-install-search-path.patch

@@ -1,4 +1,4 @@
-From ca344d46711d5ce6b5e0f7862b98bbfc7abb7d4c Mon Sep 17 00:00:00 2001
+From 83fc70ac26c2412382341be61978e51bbd2e6c4f Mon Sep 17 00:00:00 2001
 From: Hongxu Jia <hongxu.jia@windriver.com>
 Date: Mon, 25 Jan 2021 16:14:35 +0800
 Subject: [PATCH] For x86_64, set Yocto based GCC install search path
@@ -57,10 +57,10 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 1 insertion(+)
 
 diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp
-index 846163329d92..0db37c6ef1a8 100644
+index e1c2cdc0e93b..0b355d9a3f4b 100644
 --- a/clang/lib/Driver/ToolChains/Gnu.cpp
 +++ b/clang/lib/Driver/ToolChains/Gnu.cpp
-@@ -2254,6 +2254,7 @@ void Generic_GCC::GCCInstallationDetector::AddDefaultGCCPrefixes(
+@@ -2334,6 +2334,7 @@ void Generic_GCC::GCCInstallationDetector::AddDefaultGCCPrefixes(
        "x86_64-redhat-linux",    "x86_64-suse-linux",
        "x86_64-manbo-linux-gnu", "x86_64-linux-gnu",
        "x86_64-slackware-linux", "x86_64-unknown-linux",

+ 3 - 3
recipes-devtools/clang/clang/0020-llvm-Do-not-use-find_library-for-ncurses.patch

@@ -1,4 +1,4 @@
-From 20208fe7aaaf65837d06bd00a5550134075a2b22 Mon Sep 17 00:00:00 2001
+From 45a0c6817175c12aac685b4d45badf761bd7f4fc Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Sun, 7 Feb 2021 23:58:41 -0800
 Subject: [PATCH] llvm: Do not use find_library for ncurses
@@ -18,10 +18,10 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  2 files changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/compiler-rt/cmake/config-ix.cmake b/compiler-rt/cmake/config-ix.cmake
-index 5f51befc1973..55c04b76908e 100644
+index 8d3dc8d208b2..14dfbe147bdd 100644
 --- a/compiler-rt/cmake/config-ix.cmake
 +++ b/compiler-rt/cmake/config-ix.cmake
-@@ -179,7 +179,7 @@ else()
+@@ -177,7 +177,7 @@ else()
    set(MAYBE_REQUIRED)
  endif()
  if(LLVM_ENABLE_TERMINFO)

+ 3 - 3
recipes-devtools/clang/clang/0021-llvm-Insert-anchor-for-adding-OE-distro-vendor-names.patch

@@ -1,4 +1,4 @@
-From c63accf38a7c7db518e01311b23e661392af916d Mon Sep 17 00:00:00 2001
+From 3ee6071f459375e0534db3bd84b1a71a5694daef Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Thu, 11 Feb 2021 16:42:49 -0800
 Subject: [PATCH] llvm: Insert anchor for adding OE distro vendor names
@@ -18,10 +18,10 @@ Signed-off-by: Martin Jansa <martin.jansa@gmail.com>
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp
-index a68035989a93..ab1fef23d6fc 100644
+index a3d6a06af976..953132c543cd 100644
 --- a/llvm/lib/TargetParser/Triple.cpp
 +++ b/llvm/lib/TargetParser/Triple.cpp
-@@ -551,7 +551,7 @@ static Triple::VendorType parseVendor(StringRef VendorName) {
+@@ -569,7 +569,7 @@ static Triple::VendorType parseVendor(StringRef VendorName) {
      .Case("amd", Triple::AMD)
      .Case("mesa", Triple::Mesa)
      .Case("suse", Triple::SUSE)

+ 1 - 1
recipes-devtools/clang/clang/0022-compiler-rt-Do-not-use-backtrace-APIs-on-non-glibc-l.patch

@@ -1,4 +1,4 @@
-From f8ee0a66ba5b81f5489d8954dfc521f6b2612c6d Mon Sep 17 00:00:00 2001
+From 073a80b1f50e27c88c931bedea516effcff0945e Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Wed, 19 May 2021 17:32:13 -0700
 Subject: [PATCH] compiler-rt: Do not use backtrace APIs on non-glibc linux

+ 3 - 3
recipes-devtools/clang/clang/0023-clang-Fix-x86-triple-for-non-debian-multiarch-linux-.patch

@@ -1,4 +1,4 @@
-From 013ee27a17e32ddf078bf33a82293a9f9980512e Mon Sep 17 00:00:00 2001
+From 64bf8ed61750e9139851c866d9cfbed9a3fb5bb9 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Wed, 19 May 2021 17:56:03 -0700
 Subject: [PATCH] clang: Fix x86 triple for non-debian multiarch linux distros
@@ -13,10 +13,10 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 3 insertions(+)
 
 diff --git a/clang/lib/Driver/ToolChains/Linux.cpp b/clang/lib/Driver/ToolChains/Linux.cpp
-index ca9f5f2e4f74..20c7c7a745be 100644
+index 42b88e76a9d5..ef8435385130 100644
 --- a/clang/lib/Driver/ToolChains/Linux.cpp
 +++ b/clang/lib/Driver/ToolChains/Linux.cpp
-@@ -667,6 +667,9 @@ void Linux::addLibStdCxxIncludePaths(const llvm::opt::ArgList &DriverArgs,
+@@ -703,6 +703,9 @@ void Linux::addLibStdCxxIncludePaths(const llvm::opt::ArgList &DriverArgs,
        GCCInstallation.getTriple().getArch() == llvm::Triple::x86
            ? "i386-linux-gnu"
            : TripleStr;

+ 10 - 9
recipes-devtools/clang/clang/0024-libunwind-Added-unw_backtrace-method.patch

@@ -1,4 +1,4 @@
-From 959667047a6d92e3912762c8db5695a945c564b4 Mon Sep 17 00:00:00 2001
+From 755f0c575bb3efa82703eda87df3c37aeb6f96b0 Mon Sep 17 00:00:00 2001
 From: Maksim Kita <maksim-kita@yandex-team.ru>
 Date: Sun, 23 May 2021 10:27:29 +0000
 Subject: [PATCH] libunwind: Added unw_backtrace method
@@ -8,8 +8,8 @@ Upstream-Status: Pending
 Signed-off-by: Khem Raj <raj.khem@gmail.com>
 ---
  libunwind/include/libunwind.h |  1 +
- libunwind/src/libunwind.cpp   | 18 ++++++++++++++++++
- 2 files changed, 19 insertions(+)
+ libunwind/src/libunwind.cpp   | 20 ++++++++++++++++++++
+ 2 files changed, 21 insertions(+)
 
 diff --git a/libunwind/include/libunwind.h b/libunwind/include/libunwind.h
 index d2ad5ab87122..d735d955aee2 100644
@@ -24,12 +24,12 @@ index d2ad5ab87122..d735d955aee2 100644
  extern unw_addr_space_t unw_local_addr_space;
  
 diff --git a/libunwind/src/libunwind.cpp b/libunwind/src/libunwind.cpp
-index 0faea2b78570..14bf07d8f470 100644
+index 1bd18659b786..64819826cfea 100644
 --- a/libunwind/src/libunwind.cpp
 +++ b/libunwind/src/libunwind.cpp
-@@ -349,7 +349,25 @@ void __unw_remove_dynamic_eh_frame_section(unw_word_t eh_frame_start) {
- #endif // defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND)
- #endif // !defined(__USING_SJLJ_EXCEPTIONS__)
+@@ -431,6 +431,26 @@ int __unw_remove_find_dynamic_unwind_sections(
+ 
+ #endif // __APPLE__
  
 +int unw_backtrace(void **buffer, int size) {
 +  unw_context_t context;
@@ -44,12 +44,13 @@ index 0faea2b78570..14bf07d8f470 100644
 +    if (current >= size || unw_get_reg(&cursor, UNW_REG_IP, &ip)) {
 +      break;
 +    }
- 
++
 +    buffer[current++] = reinterpret_cast<void *>(static_cast<uintptr_t>(ip));
 +  }
 +
 +  return current;
 +}
- 
++
  // Add logging hooks in Debug builds only
  #ifndef NDEBUG
+ #include <stdlib.h>

+ 3 - 3
recipes-devtools/clang/clang/0025-clang-Do-not-use-install-relative-libc-headers.patch

@@ -1,4 +1,4 @@
-From d249ebabcd4e0350acf3595f80160110cb0ab56d Mon Sep 17 00:00:00 2001
+From 6fd8342c1b41a5d3f2aad1e8b215d1d9c70df800 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Wed, 11 Aug 2021 18:37:11 -0700
 Subject: [PATCH] clang: Do not use install relative libc++ headers
@@ -16,10 +16,10 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 3 insertions(+), 1 deletion(-)
 
 diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp
-index 0db37c6ef1a8..80a21d58c86c 100644
+index 0b355d9a3f4b..f228bd14e8a8 100644
 --- a/clang/lib/Driver/ToolChains/Gnu.cpp
 +++ b/clang/lib/Driver/ToolChains/Gnu.cpp
-@@ -3093,7 +3093,9 @@ Generic_GCC::addLibCxxIncludePaths(const llvm::opt::ArgList &DriverArgs,
+@@ -3128,7 +3128,9 @@ Generic_GCC::addLibCxxIncludePaths(const llvm::opt::ArgList &DriverArgs,
  
    // Android never uses the libc++ headers installed alongside the toolchain,
    // which are generally incompatible with the NDK libraries anyway.

+ 44 - 28
recipes-devtools/clang/clang/0026-clang-Fix-how-driver-finds-GCC-installation-path-on-.patch

@@ -1,4 +1,4 @@
-From 1801fad99e1dedbe8d40931b18c37d326a1d532c Mon Sep 17 00:00:00 2001
+From b00d9692a5337fdbbb5635cc9077061c47c7b741 Mon Sep 17 00:00:00 2001
 From: David Abdurachmanov <david.abdurachmanov@sifive.com>
 Date: Wed, 20 Oct 2021 17:30:36 -0700
 Subject: [PATCH] clang: Fix how driver finds GCC installation path on
@@ -27,54 +27,70 @@ Upstream-Status: Pending
 Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
 Signed-off-by: Khem Raj <raj.khem@gmail.com>
 ---
- clang/lib/Driver/ToolChains/Gnu.cpp | 39 +++++++++++++++++++++--------
- 1 file changed, 28 insertions(+), 11 deletions(-)
+ clang/lib/Driver/ToolChains/Gnu.cpp | 57 ++++++++++++++++++++---------
+ 1 file changed, 39 insertions(+), 18 deletions(-)
 
 diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp
-index 80a21d58c86c..77f5c3f58a8b 100644
+index f228bd14e8a8..d746db487e1f 100644
 --- a/clang/lib/Driver/ToolChains/Gnu.cpp
 +++ b/clang/lib/Driver/ToolChains/Gnu.cpp
-@@ -1748,18 +1748,29 @@ static void findRISCVMultilibs(const Driver &D,
+@@ -1793,23 +1793,38 @@ static void findRISCVMultilibs(const Driver &D,
      return findRISCVBareMetalMultilibs(D, TargetTriple, Path, Args, Result);
  
    FilterNonExistent NonExistent(Path, "/crtbegin.o", D.getVFS());
--  Multilib Ilp32 = makeMultilib("lib32/ilp32").flag("+m32").flag("+mabi=ilp32");
--  Multilib Ilp32f =
+-  MultilibBuilder Ilp32 =
+-      MultilibBuilder("lib32/ilp32").flag("-m32").flag("-mabi=ilp32");
+-  MultilibBuilder Ilp32f =
+-      MultilibBuilder("lib32/ilp32f").flag("-m32").flag("-mabi=ilp32f");
+-  MultilibBuilder Ilp32d =
+-      MultilibBuilder("lib32/ilp32d").flag("-m32").flag("-mabi=ilp32d");
+-  MultilibBuilder Lp64 =
+-      MultilibBuilder("lib64/lp64").flag("-m64").flag("-mabi=lp64");
+-  MultilibBuilder Lp64f =
+-      MultilibBuilder("lib64/lp64f").flag("-m64").flag("-mabi=lp64f");
+-  MultilibBuilder Lp64d =
+-      MultilibBuilder("lib64/lp64d").flag("-m64").flag("-mabi=lp64d");
+-  MultilibSet RISCVMultilibs =
+-      MultilibSetBuilder()
+-          .Either({Ilp32, Ilp32f, Ilp32d, Lp64, Lp64f, Lp64d})
+-          .makeMultilibSet()
+-          .FilterOut(NonExistent);
++
 +  MultilibSet RISCVMultilibs;
 +
 +  if (TargetTriple.getVendor() == llvm::Triple::OpenEmbedded) {
-+    Multilib OpenEmbeddedIlp32d = makeMultilib("").flag("+m32").flag("+mabi=ilp32d");
-+    Multilib OpenEmbeddedLp64d = makeMultilib("").flag("+m64").flag("+mabi=lp64d");
++    MultilibBuilder OpenEmbeddedIlp32d =
++        MultilibBuilder("").flag("+m32").flag("+mabi=ilp32d");
++    MultilibBuilder OpenEmbeddedLp64d =
++        MultilibBuilder("").flag("+m64").flag("+mabi=lp64d");
 +    RISCVMultilibs =
-+        MultilibSet()
++        MultilibSetBuilder()
 +            .Either({OpenEmbeddedIlp32d, OpenEmbeddedLp64d})
++            .makeMultilibSet()
 +            .FilterOut(NonExistent);
 +  } else {
-+    Multilib Ilp32 = makeMultilib("lib32/ilp32").flag("+m32").flag("+mabi=ilp32");
-+    Multilib Ilp32f =
-       makeMultilib("lib32/ilp32f").flag("+m32").flag("+mabi=ilp32f");
--  Multilib Ilp32d =
-+    Multilib Ilp32d =
-       makeMultilib("lib32/ilp32d").flag("+m32").flag("+mabi=ilp32d");
--  Multilib Lp64 = makeMultilib("lib64/lp64").flag("+m64").flag("+mabi=lp64");
--  Multilib Lp64f = makeMultilib("lib64/lp64f").flag("+m64").flag("+mabi=lp64f");
--  Multilib Lp64d = makeMultilib("lib64/lp64d").flag("+m64").flag("+mabi=lp64d");
--  MultilibSet RISCVMultilibs =
--      MultilibSet()
--          .Either({Ilp32, Ilp32f, Ilp32d, Lp64, Lp64f, Lp64d})
--          .FilterOut(NonExistent);
-+    Multilib Lp64 = makeMultilib("lib64/lp64").flag("+m64").flag("+mabi=lp64");
-+    Multilib Lp64f = makeMultilib("lib64/lp64f").flag("+m64").flag("+mabi=lp64f");
-+    Multilib Lp64d = makeMultilib("lib64/lp64d").flag("+m64").flag("+mabi=lp64d");
++    MultilibBuilder Ilp32 =
++        MultilibBuilder("lib32/ilp32").flag("-m32").flag("-mabi=ilp32");
++    MultilibBuilder Ilp32f =
++        MultilibBuilder("lib32/ilp32f").flag("-m32").flag("-mabi=ilp32f");
++    MultilibBuilder Ilp32d =
++        MultilibBuilder("lib32/ilp32d").flag("-m32").flag("-mabi=ilp32d");
++    MultilibBuilder Lp64 =
++        MultilibBuilder("lib64/lp64").flag("-m64").flag("-mabi=lp64");
++    MultilibBuilder Lp64f =
++        MultilibBuilder("lib64/lp64f").flag("-m64").flag("-mabi=lp64f");
++    MultilibBuilder Lp64d =
++        MultilibBuilder("lib64/lp64d").flag("-m64").flag("-mabi=lp64d");
 +    RISCVMultilibs =
-+        MultilibSet()
++        MultilibSetBuilder()
 +            .Either({Ilp32, Ilp32f, Ilp32d, Lp64, Lp64f, Lp64d})
++            .makeMultilibSet()
 +            .FilterOut(NonExistent);
 +  }
  
    Multilib::flags_list Flags;
    bool IsRV64 = TargetTriple.getArch() == llvm::Triple::riscv64;
-@@ -2713,13 +2724,19 @@ void Generic_GCC::GCCInstallationDetector::ScanLibDirForGCCTriple(
+@@ -2776,13 +2791,19 @@ void Generic_GCC::GCCInstallationDetector::ScanLibDirForGCCTriple(
            continue; // Saw this path before; no need to look at it again.
        if (CandidateVersion.isOlderThan(4, 1, 1))
          continue;

+ 6 - 6
recipes-devtools/clang/clang/0027-Fix-lib-paths-for-OpenEmbedded-Host.patch

@@ -1,4 +1,4 @@
-From b8dd608a9ca83b9c321dce3ca0d18e8aeea987af Mon Sep 17 00:00:00 2001
+From f910a403e898d42d589b694bc9856f052386136e Mon Sep 17 00:00:00 2001
 From: Changqing Li <changqing.li@windriver.com>
 Date: Tue, 7 Dec 2021 04:08:22 +0000
 Subject: [PATCH] Fix lib paths for OpenEmbedded Host
@@ -48,18 +48,18 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 4 insertions(+), 1 deletion(-)
 
 diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp
-index 77f5c3f58a8b..0ec2dadafc05 100644
+index d746db487e1f..020fd106a629 100644
 --- a/clang/lib/Driver/ToolChains/Gnu.cpp
 +++ b/clang/lib/Driver/ToolChains/Gnu.cpp
-@@ -18,6 +18,7 @@
+@@ -19,6 +19,7 @@
  #include "Linux.h"
  #include "clang/Config/config.h" // for GCC_INSTALL_PREFIX
  #include "clang/Driver/Compilation.h"
 +#include "clang/Driver/Distro.h"
  #include "clang/Driver/Driver.h"
  #include "clang/Driver/DriverDiagnostic.h"
- #include "clang/Driver/Options.h"
-@@ -2682,6 +2683,7 @@ void Generic_GCC::GCCInstallationDetector::ScanLibDirForGCCTriple(
+ #include "clang/Driver/MultilibBuilder.h"
+@@ -2749,6 +2750,7 @@ void Generic_GCC::GCCInstallationDetector::ScanLibDirForGCCTriple(
      const llvm::Triple &TargetTriple, const ArgList &Args,
      const std::string &LibDir, StringRef CandidateTriple,
      bool NeedsBiarchSuffix, bool GCCDirExists, bool GCCCrossDirExists) {
@@ -67,7 +67,7 @@ index 77f5c3f58a8b..0ec2dadafc05 100644
    // Locations relative to the system lib directory where GCC's triple-specific
    // directories might reside.
    struct GCCLibSuffix {
-@@ -2699,7 +2701,8 @@ void Generic_GCC::GCCInstallationDetector::ScanLibDirForGCCTriple(
+@@ -2766,7 +2768,8 @@ void Generic_GCC::GCCInstallationDetector::ScanLibDirForGCCTriple(
        // files in that location, not just GCC installation data.
        {CandidateTriple.str(), "..",
         TargetTriple.getVendor() == llvm::Triple::Freescale ||

+ 5 - 5
recipes-devtools/clang/clang/0028-Correct-library-search-path-for-OpenEmbedded-Host.patch

@@ -1,4 +1,4 @@
-From a4574f3cfd55c014d0e09956fe413835debe1b87 Mon Sep 17 00:00:00 2001
+From 9ed567b3fcce1759947621765199f13261c615a4 Mon Sep 17 00:00:00 2001
 From: Changqing Li <changqing.li@windriver.com>
 Date: Tue, 7 Dec 2021 04:55:48 +0000
 Subject: [PATCH] Correct library search path for OpenEmbedded Host
@@ -39,7 +39,7 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  3 files changed, 4 insertions(+)
 
 diff --git a/clang/include/clang/Driver/Distro.h b/clang/include/clang/Driver/Distro.h
-index 1aaf93ddb7c4..31f03e327b78 100644
+index 8291f6575a71..7ce64b9a2c25 100644
 --- a/clang/include/clang/Driver/Distro.h
 +++ b/clang/include/clang/Driver/Distro.h
 @@ -45,6 +45,7 @@ public:
@@ -50,7 +50,7 @@ index 1aaf93ddb7c4..31f03e327b78 100644
      OpenSUSE,
      UbuntuHardy,
      UbuntuIntrepid,
-@@ -135,6 +136,7 @@ public:
+@@ -136,6 +137,7 @@ public:
  
    bool IsGentoo() const { return DistroVal == Gentoo; }
  
@@ -59,7 +59,7 @@ index 1aaf93ddb7c4..31f03e327b78 100644
  };
  
 diff --git a/clang/lib/Driver/Distro.cpp b/clang/lib/Driver/Distro.cpp
-index 87a0c5a58511..b607a3f18d1e 100644
+index 6e0087565941..13e45b1ea088 100644
 --- a/clang/lib/Driver/Distro.cpp
 +++ b/clang/lib/Driver/Distro.cpp
 @@ -44,6 +44,7 @@ static Distro::DistroType DetectOsRelease(llvm::vfs::FileSystem &VFS) {
@@ -71,7 +71,7 @@ index 87a0c5a58511..b607a3f18d1e 100644
    return Version;
  }
 diff --git a/clang/lib/Driver/ToolChains/Linux.cpp b/clang/lib/Driver/ToolChains/Linux.cpp
-index 20c7c7a745be..f5d9b3187cf5 100644
+index ef8435385130..8bd21eebfed3 100644
 --- a/clang/lib/Driver/ToolChains/Linux.cpp
 +++ b/clang/lib/Driver/ToolChains/Linux.cpp
 @@ -78,6 +78,7 @@ std::string Linux::getMultiarchTriple(const Driver &D,

+ 2 - 2
recipes-devtools/clang/clang/0029-lldb-Link-with-libatomic-on-x86.patch

@@ -1,4 +1,4 @@
-From e9c06e4994d4cd52d8783838186df8c93ffd0052 Mon Sep 17 00:00:00 2001
+From 374f62b718dbb04a88764cdfa747cd42ebf57829 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Tue, 8 Feb 2022 01:31:26 -0800
 Subject: [PATCH] lldb: Link with libatomic on x86
@@ -17,7 +17,7 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 4 insertions(+)
 
 diff --git a/lldb/source/Utility/CMakeLists.txt b/lldb/source/Utility/CMakeLists.txt
-index 89acd7cd2eaf..6aa84f9d284d 100644
+index b376ace0ebe3..b9bb39220524 100644
 --- a/lldb/source/Utility/CMakeLists.txt
 +++ b/lldb/source/Utility/CMakeLists.txt
 @@ -19,6 +19,10 @@ if (CMAKE_SYSTEM_NAME MATCHES "Windows")

+ 0 - 35
recipes-devtools/clang/clang/0030-clang-exclude-openembedded-distributions-from-settin.patch

@@ -1,35 +0,0 @@
-From b34b67256aa36ceb6bce1b6f657ad129ecf90313 Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Fri, 11 Feb 2022 12:29:14 -0800
-Subject: [PATCH] clang: exclude openembedded distributions from setting rpath
- on openmp executables
-
-OpenEmbedded based SDKs stage toolchains outsides the target rootfs and
-libomp.so is part of the target rootfs and not part of compiler
-toolchain install or relative to it. It finds the libraries via
---sysroot during compile. This ensures that -rpath is not added for such
-systems, since it is adding cross-compile paths to rpath which is not
-correct when the binaries are run on real targets.
-
-Upstream-Status: Submitted [https://reviews.llvm.org/D119590]
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
----
- clang/lib/Driver/ToolChains/CommonArgs.cpp | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp
-index dfab4075e03e..14c6f0a3b21d 100644
---- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
-+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
-@@ -794,6 +794,11 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const ArgList &Args,
- void tools::addOpenMPRuntimeSpecificRPath(const ToolChain &TC,
-                                           const ArgList &Args,
-                                           ArgStringList &CmdArgs) {
-+  // OpenEmbedded/Yocto installs libomp.so into <sysroot>/usr/lib
-+  // therefore using -rpath is not needed, on the contrary it adds
-+  // paths from cross compiler install location which is not correct
-+  if (TC.getTriple().getVendor() == llvm::Triple::OpenEmbedded)
-+    return;
- 
-   if (Args.hasFlag(options::OPT_fopenmp_implicit_rpath,
-                    options::OPT_fno_openmp_implicit_rpath, true)) {

+ 8 - 8
recipes-devtools/clang/clang/0031-compiler-rt-Enable-__int128-for-ppc32.patch → recipes-devtools/clang/clang/0030-compiler-rt-Enable-__int128-for-ppc32.patch

@@ -1,4 +1,4 @@
-From 2a622188e62705f20d7806926a99f47f727d8858 Mon Sep 17 00:00:00 2001
+From b907dbdce5520eaf841ae041fcca6941a8529456 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Wed, 9 Mar 2022 16:28:16 -0800
 Subject: [PATCH] compiler-rt: Enable __int128 for ppc32
@@ -11,10 +11,10 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  2 files changed, 8 insertions(+), 9 deletions(-)
 
 diff --git a/compiler-rt/lib/builtins/CMakeLists.txt b/compiler-rt/lib/builtins/CMakeLists.txt
-index 2fc70522895f..55f0ecb20a1f 100644
+index d62fa0432e2a..126505bd8921 100644
 --- a/compiler-rt/lib/builtins/CMakeLists.txt
 +++ b/compiler-rt/lib/builtins/CMakeLists.txt
-@@ -668,11 +668,9 @@ set(mips64_SOURCES ${GENERIC_TF_SOURCES}
+@@ -669,11 +669,9 @@ set(mips64_SOURCES ${GENERIC_TF_SOURCES}
  set(mips64el_SOURCES ${GENERIC_TF_SOURCES}
                       ${mips_SOURCES})
  
@@ -27,10 +27,10 @@ index 2fc70522895f..55f0ecb20a1f 100644
    ppc/divtc3.c
    ppc/fixtfdi.c
    ppc/fixunstfdi.c
-@@ -687,14 +685,15 @@ set(powerpc64_SOURCES
+@@ -688,14 +686,15 @@ set(powerpc64_SOURCES
  )
  # These routines require __int128, which isn't supported on AIX.
- if (NOT ${CMAKE_SYSTEM_NAME} MATCHES "AIX")
+ if (NOT OS_NAME MATCHES "AIX")
 -  set(powerpc64_SOURCES
 +  set(powerpc_SOURCES
      ppc/floattitf.c
@@ -46,15 +46,15 @@ index 2fc70522895f..55f0ecb20a1f 100644
  
  set(riscv_SOURCES
    riscv/fp_mode.c
-@@ -818,9 +817,9 @@ else ()
+@@ -823,9 +822,9 @@ else ()
          list(APPEND BUILTIN_CFLAGS_${arch} -fomit-frame-pointer -DCOMPILER_RT_ARMHF_TARGET)
        endif()
  
 -      # For RISCV32, we must force enable int128 for compiling long
 +      # For RISCV32/PPC32, we must force enable int128 for compiling long
        # double routines.
--      if("${arch}" STREQUAL "riscv32")
-+      if("${arch}" STREQUAL "riscv32" OR "${arch}" STREQUAL "powerpc" )
+-      if(COMPILER_RT_ENABLE_SOFTWARE_INT128 OR "${arch}" STREQUAL "riscv32")
++      if(COMPILER_RT_ENABLE_SOFTWARE_INT128 OR "${arch}" STREQUAL "riscv32" OR "${arch}" STREQUAL "powerpc")
          list(APPEND BUILTIN_CFLAGS_${arch} -fforce-enable-int128)
        endif()
  

+ 4 - 4
recipes-devtools/clang/clang/0032-llvm-Do-not-use-cmake-infra-to-detect-libzstd.patch → recipes-devtools/clang/clang/0031-llvm-Do-not-use-cmake-infra-to-detect-libzstd.patch

@@ -1,4 +1,4 @@
-From ab07bcf103432f49aeff486e2898110c879e8bc0 Mon Sep 17 00:00:00 2001
+From fc268457a7ef1a8481a1d563550cc8e9a8a5afcb Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Fri, 12 Aug 2022 11:50:57 -0700
 Subject: [PATCH] llvm: Do not use cmake infra to detect libzstd
@@ -21,7 +21,7 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 4 insertions(+), 4 deletions(-)
 
 diff --git a/llvm/lib/Support/CMakeLists.txt b/llvm/lib/Support/CMakeLists.txt
-index 8fbb2ca4c164..a6daa7c9f20f 100644
+index 87fe7bebf688..e12e292fdfbf 100644
 --- a/llvm/lib/Support/CMakeLists.txt
 +++ b/llvm/lib/Support/CMakeLists.txt
 @@ -22,7 +22,7 @@ if (HAS_WERROR_GLOBAL_CTORS)
@@ -42,7 +42,7 @@ index 8fbb2ca4c164..a6daa7c9f20f 100644
  endif()
  
  if( MSVC OR MINGW )
-@@ -291,7 +291,7 @@ if(LLVM_ENABLE_ZLIB)
+@@ -292,7 +292,7 @@ if(LLVM_ENABLE_ZLIB)
      get_property(zlib_library TARGET ZLIB::ZLIB PROPERTY LOCATION)
    endif()
    get_library_name(${zlib_library} zlib_library)
@@ -51,7 +51,7 @@ index 8fbb2ca4c164..a6daa7c9f20f 100644
  endif()
  
  if(LLVM_ENABLE_ZSTD)
-@@ -304,7 +304,7 @@ if(LLVM_ENABLE_ZSTD)
+@@ -305,7 +305,7 @@ if(LLVM_ENABLE_ZSTD)
      get_property(zstd_library TARGET ${zstd_target} PROPERTY LOCATION)
    endif()
    get_library_name(${zstd_library} zstd_library)

+ 3 - 3
recipes-devtools/clang/clang/0035-compiler-rt-Fix-stat-struct-s-size-for-O32-ABI.patch → recipes-devtools/clang/clang/0032-compiler-rt-Fix-stat-struct-s-size-for-O32-ABI.patch

@@ -1,4 +1,4 @@
-From 577a70fd39778fb7e3bcd22b6c6713fcb516c365 Mon Sep 17 00:00:00 2001
+From b5be1155dbe4d82fef53960f5df8a25770cd8bfc Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Tue, 3 Jan 2023 18:44:34 -0800
 Subject: [PATCH] compiler-rt: Fix stat struct's size for O32 ABI
@@ -14,10 +14,10 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 13 insertions(+)
 
 diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h b/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
-index fdc69b8a5fba..d2246893f8a5 100644
+index 58244c9944a0..70daaf279f4a 100644
 --- a/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
 +++ b/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
-@@ -97,11 +97,24 @@ const unsigned struct_kernel_stat64_sz = 104;
+@@ -98,11 +98,24 @@ const unsigned struct_kernel_stat64_sz = 104;
  const unsigned struct_kernel_stat_sz = 144;
  const unsigned struct_kernel_stat64_sz = 104;
  #elif defined(__mips__)

+ 0 - 53
recipes-devtools/clang/clang/0033-build-Enable-64bit-off_t-on-32bit-glibc-systems.patch

@@ -1,53 +0,0 @@
-From 48cf70c06ae6085ff3d1f8b28e323f153cff23c6 Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Sun, 25 Dec 2022 15:13:41 -0800
-Subject: [PATCH] build: Enable 64bit off_t on 32bit glibc systems
-
-Pass -D_FILE_OFFSET_BITS=64 to compiler flags on 32bit glibc based
-systems. This will make sure that 64bit versions of LFS functions are
-used e.g. lseek will behave same as lseek64. Also revert [1] partially
-because this added a cmake test to detect lseek64 but then forgot to
-pass the needed macro during actual compile, this test was incomplete too
-since libc implementations like musl has 64-bit off_t by default on 32-bit
-systems and does not bundle -D_LARGEFILE64_SOURCE [2] under -D_GNU_SOURCE
-like glibc, which means the compile now fails on musl because the cmake
-check passes but we do not have _LARGEFILE64_SOURCE defined. Moreover,
-Using the *64 function was transitional anyways so use
--D_FILE_OFFSET_BITS=64 instead
-
-[1] https://github.com/llvm/llvm-project/commit/8db7e5e4eed4c4e697dc3164f2c9351d8c3e942b
-[2] https://git.musl-libc.org/cgit/musl/commit/?id=25e6fee27f4a293728dd15b659170e7b9c7db9bc
-
-Upstream-Status: Pending
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
----
- utils/bazel/llvm-project-overlay/llvm/config.bzl               | 1 -
- .../llvm-project-overlay/llvm/include/llvm/Config/config.h     | 3 ---
- 2 files changed, 4 deletions(-)
-
-diff --git a/utils/bazel/llvm-project-overlay/llvm/config.bzl b/utils/bazel/llvm-project-overlay/llvm/config.bzl
-index 5507f80efa0b..b15ec9e1bb39 100644
---- a/utils/bazel/llvm-project-overlay/llvm/config.bzl
-+++ b/utils/bazel/llvm-project-overlay/llvm/config.bzl
-@@ -48,7 +48,6 @@ posix_defines = [
- linux_defines = posix_defines + [
-     "_GNU_SOURCE",
-     "HAVE_LINK_H=1",
--    "HAVE_LSEEK64=1",
-     "HAVE_MALLINFO=1",
-     "HAVE_SBRK=1",
-     "HAVE_STRUCT_STAT_ST_MTIM_TV_NSEC=1",
-diff --git a/utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h b/utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h
-index 8a30957b6120..6a68ac040bb8 100644
---- a/utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h
-+++ b/utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h
-@@ -144,9 +144,6 @@
- /* Define to 1 if you have the <link.h> header file. */
- /* HAVE_LINK_H defined in Bazel */
- 
--/* Define to 1 if you have the `lseek64' function. */
--/* HAVE_LSEEK64 defined in Bazel */
--
- /* Define to 1 if you have the <mach/mach.h> header file. */
- /* HAVE_MACH_MACH_H defined in Bazel */
- 

+ 3 - 3
recipes-devtools/clang/clang/0036-compiler-rt-Undef-_TIME_BITS-along-with-_FILE_OFFSET.patch → recipes-devtools/clang/clang/0033-compiler-rt-Undef-_TIME_BITS-along-with-_FILE_OFFSET.patch

@@ -1,4 +1,4 @@
-From c62140c7e116fabe7bccf9b55848c74e5beefccd Mon Sep 17 00:00:00 2001
+From e8ecd192495c092dcee4fdb1ee5514222a8aa0c1 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Tue, 21 Feb 2023 12:46:10 -0800
 Subject: [PATCH] compiler-rt: Undef _TIME_BITS along with _FILE_OFFSET_BITS in
@@ -22,7 +22,7 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 9 insertions(+)
 
 diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_platform.h b/compiler-rt/lib/sanitizer_common/sanitizer_platform.h
-index 764996e57355..df3d165ecdb6 100644
+index 764996e57355..99024169f925 100644
 --- a/compiler-rt/lib/sanitizer_common/sanitizer_platform.h
 +++ b/compiler-rt/lib/sanitizer_common/sanitizer_platform.h
 @@ -22,6 +22,15 @@
@@ -34,7 +34,7 @@ index 764996e57355..df3d165ecdb6 100644
 +// 32-bit architectures using 64-bit time_t and users passing _TIME_BITS=64
 +// from build environment, therefore both _FILE_OFFSET_BITS and _TIME_BITS
 +// need to be undefined together since features.h will check for both being 64
-+// if one is set to 64
++// if one is set to 64.
 +#  if !defined(_FILE_OFFSET_BITS)
 +#    undef _TIME_BITS
 +#  endif

File diff suppressed because it is too large
+ 32 - 0
recipes-devtools/clang/clang/0034-ToolChains-Gnu.cpp-ARMLibDirs-search-also-in-lib32.patch


+ 0 - 36
recipes-devtools/clang/clang/0034-compiler-rt-Undef-_TIME_BITS-along-with-_FILE_OFFSET.patch

@@ -1,36 +0,0 @@
-From 3c7ebde16bea113e119b2ef7134b10cd8d7e3b1c Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Sat, 31 Dec 2022 15:03:24 -0800
-Subject: [PATCH] compiler-rt: Undef _TIME_BITS along with _FILE_OFFSET_BITS on
- linux
-
-On 32bit systems using 64bit time_t build fails because
-_FILE_OFFSET_BITS is undefined here but _TIME_BITS is still set to 64
-
-Fixes
-/usr/include/features-time64.h:26:5: error: "_TIME_BITS=64 is allowed
- only with _FILE_OFFSET_BITS=64"
-| #   error "_TIME_BITS=64 is allowed only with _FILE_OFFSET_BITS=64"
-|     ^
-| 1 error generated.
-
-Also avoid LFS64 functions on musl
-
-Upstream-Status: Pending
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
----
- .../lib/sanitizer_common/sanitizer_platform_limits_posix.cpp     | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp
-index fc01498aa228..eb2ee78c2f45 100644
---- a/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp
-+++ b/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp
-@@ -18,6 +18,7 @@
- // depends on _FILE_OFFSET_BITS setting.
- // To get this "true" dirent definition, we undefine _FILE_OFFSET_BITS below.
- #undef _FILE_OFFSET_BITS
-+#undef _TIME_BITS
- #endif
- 
- // Must go after undef _FILE_OFFSET_BITS.

+ 0 - 70
recipes-devtools/clang/clang/0037-clang-Call-printName-to-get-name-of-Decl.patch

@@ -1,70 +0,0 @@
-From d33d6a8c4f43907cb53130730a2bc48624a34b74 Mon Sep 17 00:00:00 2001
-From: Dan McGregor <dan.mcgregor@usask.ca>
-Date: Tue, 21 Mar 2023 13:04:51 -0600
-Subject: [PATCH] [clang] Call printName to get name of Decl
-
-Rather than sending a name directly to the stream, use printName
-to preserve any PrintingPolicy. This ensures that names are properly
-affected by path remapping.
-
-Differential Revision: https://reviews.llvm.org/D149272
-
-Upstream-Status: Pending
----
- clang/lib/AST/Decl.cpp                  |  4 ++--
- clang/lib/AST/DeclarationName.cpp       |  4 ++--
- clang/test/CodeGen/debug-prefix-map.cpp | 11 +++++++++++
- 3 files changed, 15 insertions(+), 4 deletions(-)
- create mode 100644 clang/test/CodeGen/debug-prefix-map.cpp
-
-diff --git a/clang/lib/AST/Decl.cpp b/clang/lib/AST/Decl.cpp
-index e60cc28f6e0f..24de6156c0f5 100644
---- a/clang/lib/AST/Decl.cpp
-+++ b/clang/lib/AST/Decl.cpp
-@@ -1626,8 +1626,8 @@ Module *Decl::getOwningModuleForLinkage(bool IgnoreLinkage) const {
-   llvm_unreachable("unknown module kind");
- }
- 
--void NamedDecl::printName(raw_ostream &OS, const PrintingPolicy&) const {
--  OS << Name;
-+void NamedDecl::printName(raw_ostream &OS, const PrintingPolicy &Policy) const {
-+  Name.print(OS, Policy);
- }
- 
- void NamedDecl::printName(raw_ostream &OS) const {
-diff --git a/clang/lib/AST/DeclarationName.cpp b/clang/lib/AST/DeclarationName.cpp
-index c1219041a466..da8b3886c340 100644
---- a/clang/lib/AST/DeclarationName.cpp
-+++ b/clang/lib/AST/DeclarationName.cpp
-@@ -117,12 +117,12 @@ static void printCXXConstructorDestructorName(QualType ClassType,
-   Policy.adjustForCPlusPlus();
- 
-   if (const RecordType *ClassRec = ClassType->getAs<RecordType>()) {
--    OS << *ClassRec->getDecl();
-+    ClassRec->getDecl()->printName(OS, Policy);
-     return;
-   }
-   if (Policy.SuppressTemplateArgsInCXXConstructors) {
-     if (auto *InjTy = ClassType->getAs<InjectedClassNameType>()) {
--      OS << *InjTy->getDecl();
-+      InjTy->getDecl()->printName(OS, Policy);
-       return;
-     }
-   }
-diff --git a/clang/test/CodeGen/debug-prefix-map.cpp b/clang/test/CodeGen/debug-prefix-map.cpp
-new file mode 100644
-index 000000000000..7ddaee531282
---- /dev/null
-+++ b/clang/test/CodeGen/debug-prefix-map.cpp
-@@ -0,0 +1,11 @@
-+// RUN: %clang_cc1 -debug-info-kind=standalone -fdebug-prefix-map=%p=./UNLIKELY_PATH/empty -S %s -emit-llvm -o - | FileCheck %s
-+
-+struct alignas(64) an {
-+  struct {
-+    unsigned char x{0};
-+  } arr[64];
-+};
-+
-+struct an *pan = new an;
-+
-+// CHECK: !DISubprogram(name: "(unnamed struct at ./UNLIKELY_PATH/empty{{/|\\\\}}{{.*}}",

+ 14 - 5
recipes-devtools/clang/clang/llvm-config

@@ -8,7 +8,11 @@
 SCRIPT_DIR="$(dirname "$(readlink -f "$0")")"
 NEXT_LLVM_CONFIG="$(which -a llvm-config | sed -n 2p)"
 export YOCTO_ALTERNATE_EXE_PATH="${YOCTO_ALTERNATE_EXE_PATH:="$(readlink -f "$SCRIPT_DIR/../llvm-config")"}"
-export YOCTO_ALTERNATE_LIBDIR="${YOCTO_ALTERNATE_LIBDIR:="/lib"}"
+if [ -n "$( echo $base_libdir | sed -n '/lib64/p')" ]; then
+    export YOCTO_ALTERNATE_LIBDIR="${YOCTO_ALTERNATE_LIBDIR:="/lib64"}"
+else
+    export YOCTO_ALTERNATE_LIBDIR="${YOCTO_ALTERNATE_LIBDIR:="/lib"}"
+fi
 if [[ $# == 0 ]]; then
   exec "$NEXT_LLVM_CONFIG"
 fi
@@ -22,19 +26,24 @@ if [[ $1 == "--bindir" ]]; then
   exec "$NEXT_LLVM_CONFIG" $@
 fi
 
+if [[ $1 == "--libfiles" ]]; then
+  exec "$NEXT_LLVM_CONFIG" $@
+fi
+
+
 for arg in "$@"; do
   case "$arg" in
     --cppflags)
-      echo $TARGET_CPPFLAGS
+      echo $CPPFLAGS
       ;;
     --cflags)
-      echo $TARGET_CFLAGS
+      echo $CFLAGS
       ;;
     --cxxflags)
-      echo $TARGET_CXXFLAGS
+      echo $CXXFLAGS
       ;;
     --ldflags)
-      echo $TARGET_LDFLAGS
+      echo $LDFLAGS
       ;;
     *)
       echo "$("$NEXT_LLVM_CONFIG" "$arg")"

+ 3 - 6
recipes-devtools/clang/clang_16.0.5.bb → recipes-devtools/clang/clang_17.0.0.bb

@@ -251,9 +251,9 @@ endif()\n" ${D}${libdir}/cmake/llvm/LLVMExports-release.cmake
 
 do_install:append:class-native () {
     install -Dm 0755 ${B}${BINPATHPREFIX}/bin/clang-tblgen ${D}${bindir}/clang-tblgen
-    install -Dm 0755 ${B}/bin/clang-pseudo-gen ${D}${bindir}/clang-pseudo-gen
-    install -Dm 0755 ${B}/bin/lldb-tblgen ${D}${bindir}/lldb-tblgen
-    install -Dm 0755 ${B}/bin/clang-tidy-confusable-chars-gen ${D}${bindir}/clang-tidy-confusable-chars-gen
+    install -Dm 0755 ${B}${BINPATHPREFIX}/bin/clang-pseudo-gen ${D}${bindir}/clang-pseudo-gen
+    install -Dm 0755 ${B}${BINPATHPREFIX}/bin/lldb-tblgen ${D}${bindir}/lldb-tblgen
+    install -Dm 0755 ${B}${BINPATHPREFIX}/bin/clang-tidy-confusable-chars-gen ${D}${bindir}/clang-tidy-confusable-chars-gen
     for f in `find ${D}${bindir} -executable -type f -not -type l`; do
         test -n "`file -b $f|grep -i ELF`" && ${STRIP} $f
         echo "stripped $f"
@@ -281,9 +281,6 @@ do_install:append:class-nativesdk () {
 PACKAGES =+ "${PN}-libllvm ${PN}-lldb-python ${PN}-libclang-cpp ${PN}-tidy ${PN}-format ${PN}-tools \
              libclang lldb lldb-server liblldb llvm-linker-tools"
 
-PROVIDES += "llvm llvm${PV}"
-PROVIDES:append:class-native = " llvm-native"
-
 BBCLASSEXTEND = "native nativesdk"
 
 RDEPENDS:lldb += "${PN}-lldb-python lldb-server"

+ 3 - 0
recipes-devtools/clang/clang_16.0.5.bbappend → recipes-devtools/clang/clang_17.0.0.bbappend

@@ -26,3 +26,6 @@ EXTRA_OECMAKE:append:class-native = " \
 			-DLLDB_PYTHON_RELATIVE_PATH="recipe-sysroot-native/usr/bin/python3-native/" \
                         -DLLDB_PYTHON_EXT_SUFFIX=".so" \
 			"
+
+PROVIDES += "llvm llvm${PV}"
+PROVIDES:append:class-native = " llvm-native"

+ 5 - 9
recipes-devtools/clang/common.inc

@@ -35,18 +35,14 @@ SRC_URI = "\
     file://0023-clang-Fix-x86-triple-for-non-debian-multiarch-linux-.patch \
     file://0024-libunwind-Added-unw_backtrace-method.patch \
     file://0025-clang-Do-not-use-install-relative-libc-headers.patch \
-    file://0026-clang-Fix-how-driver-finds-GCC-installation-path-on-.patch \
     file://0027-Fix-lib-paths-for-OpenEmbedded-Host.patch \
     file://0028-Correct-library-search-path-for-OpenEmbedded-Host.patch \
     file://0029-lldb-Link-with-libatomic-on-x86.patch \
-    file://0030-clang-exclude-openembedded-distributions-from-settin.patch \
-    file://0031-compiler-rt-Enable-__int128-for-ppc32.patch \
-    file://0032-llvm-Do-not-use-cmake-infra-to-detect-libzstd.patch \
-    file://0033-build-Enable-64bit-off_t-on-32bit-glibc-systems.patch \
-    file://0034-compiler-rt-Undef-_TIME_BITS-along-with-_FILE_OFFSET.patch \
-    file://0035-compiler-rt-Fix-stat-struct-s-size-for-O32-ABI.patch \
-    file://0036-compiler-rt-Undef-_TIME_BITS-along-with-_FILE_OFFSET.patch \
-    file://0037-clang-Call-printName-to-get-name-of-Decl.patch \
+    file://0030-compiler-rt-Enable-__int128-for-ppc32.patch \
+    file://0031-llvm-Do-not-use-cmake-infra-to-detect-libzstd.patch \
+    file://0032-compiler-rt-Fix-stat-struct-s-size-for-O32-ABI.patch \
+    file://0033-compiler-rt-Undef-_TIME_BITS-along-with-_FILE_OFFSET.patch \
+    file://0034-ToolChains-Gnu.cpp-ARMLibDirs-search-also-in-lib32.patch \
     "
 # Fallback to no-PIE if not set
 GCCPIE ??= ""

+ 1 - 1
recipes-devtools/clang/compiler-rt-sanitizers_16.0.5.bb → recipes-devtools/clang/compiler-rt-sanitizers_17.0.0.bb

@@ -37,7 +37,7 @@ EXTRA_OECMAKE += "-DCMAKE_BUILD_TYPE=RelWithDebInfo \
                   -DCOMPILER_RT_STANDALONE_BUILD=OFF \
                   -DCOMPILER_RT_DEFAULT_TARGET_ONLY=ON \
                   -DCOMPILER_RT_USE_BUILTINS_LIBRARY=ON \
-                  -DCMAKE_C_COMPILER_TARGET=${HOST_ARCH}${HF}${HOST_VENDOR}-${HOST_OS} \
+                  -DCMAKE_C_COMPILER_TARGET=${HOST_ARCH}${HOST_VENDOR}-${HOST_OS}${HF} \
                   -DCOMPILER_RT_BUILD_BUILTINS=OFF \
                   -DCOMPILER_RT_INCLUDE_TESTS=OFF \
                   -DSANITIZER_CXX_ABI_LIBNAME=${@bb.utils.contains("RUNTIME", "llvm", "libc++", "libstdc++", d)} \

+ 1 - 1
recipes-devtools/clang/compiler-rt_16.0.5.bb → recipes-devtools/clang/compiler-rt_17.0.0.bb

@@ -61,7 +61,7 @@ EXTRA_OECMAKE += "-DCMAKE_BUILD_TYPE=RelWithDebInfo \
                   -DCOMPILER_RT_STANDALONE_BUILD=OFF \
                   -DCOMPILER_RT_DEFAULT_TARGET_ONLY=ON \
                   -DCOMPILER_RT_INCLUDE_TESTS=OFF \
-                  -DCMAKE_C_COMPILER_TARGET=${HOST_ARCH}${HF}${HOST_VENDOR}-${HOST_OS} \
+                  -DCMAKE_C_COMPILER_TARGET=${HOST_ARCH}${HOST_VENDOR}-${HOST_OS}${HF} \
                   -DCOMPILER_RT_BUILD_XRAY=OFF \
                   -DCOMPILER_RT_BUILD_SANITIZERS=OFF \
                   -DCOMPILER_RT_BUILD_MEMPROF=OFF \

+ 0 - 0
recipes-devtools/clang/libclc_16.0.5.bb → recipes-devtools/clang/libclc_17.0.0.bb


+ 0 - 0
recipes-devtools/clang/libcxx_16.0.5.bb → recipes-devtools/clang/libcxx_17.0.0.bb


+ 0 - 0
recipes-devtools/clang/libcxx_16.0.5.bbappend → recipes-devtools/clang/libcxx_17.0.0.bbappend


+ 1 - 0
recipes-devtools/clang/llvm-project-source.bb

@@ -1,6 +1,7 @@
 # Copyright (C) 2018 Khem Raj <raj.khem@gmail.com>
 # Released under the MIT license (see COPYING.MIT for the terms)
 
+FILESEXTRAPATHS:prepend := "${THISDIR}/clang:"
 SUMMARY = "This is the canonical git mirror of the LLVM subversion repository."
 HOMEPAGE = "https://github.com/llvm/llvm-project"
 

+ 14 - 19
recipes-devtools/clang/llvm-project-source.bbappend

@@ -1,21 +1,20 @@
 FILESEXTRAPATHS:prepend := "${THISDIR}/clang:"
 
-SRCREV = "35bd94a4b791787e7f3938e10ce80f409831dd7e"
-BRANCH = "release/16.x"
+SRCREV = "092b6c5ee3707ea10b9f10d0a674e8d12395369b"
+BRANCH = "release/17.x"
 
 SRC_URI = "\
     ${BASEURI} \
     file://llvm-config \
     file://libunwind.pc.in \
-    file://0001-neon2rvv-support-type-convert-between-fixed-vector-a.patch \
-    file://0002-neon2rvv-Model-vxrm-in-LLVM-intrinsics-and-add-optim.patch \
-    file://0003-RISCV-Add-prefetch-instructions.patch \
-    file://0004-RISCV-Add-customer-cache-instructions.patch \
-    file://0005-RISCV-Add-multilib-v-b-support-for-baremetal-toolcha.patch \
-    file://0006-RISCV-Change-baremetal-multilib-directory-name-to-al.patch \
-    file://0007-Driver-Set-clang-default-dwarf-version-to-4.patch \
+    file://0001-Handle-seteq-setne-conditions-for-CZERO_NEZ-CZERO_EQ.patch \
+    file://0002-neon2rvv-support-type-convert-between-fixed-vector-a.patch \
+    file://0003-Add-an-optional-for-optimizing-Insert-Read-Write-CSR.patch \
+    file://0004-RISCV-Add-prefetch-instructions.patch \
+    file://0005-RISCV-Add-customer-cache-instructions.patch \
+    file://0006-RISCV-Add-multilib-v-b-support-for-baremetal-toolcha.patch \
+    file://0007-RISCV-Change-baremetal-multilib-directory-name-to-al.patch \
     file://0008-RISCV-Support-b-letter-in-march-string.patch \
-    file://0009-RISCV-Align-default-march-with-dubhe-gcc-toolchain.patch \
     file://0001-libcxxabi-Find-libunwind-headers-when-LIBCXXABI_LIBU.patch \
     file://0002-compiler-rt-support-a-new-embedded-linux-target.patch \
     file://0003-compiler-rt-Simplify-cross-compilation.-Don-t-use-na.patch \
@@ -41,16 +40,12 @@ SRC_URI = "\
     file://0023-clang-Fix-x86-triple-for-non-debian-multiarch-linux-.patch \
     file://0024-libunwind-Added-unw_backtrace-method.patch \
     file://0025-clang-Do-not-use-install-relative-libc-headers.patch \
-    file://0026-clang-Fix-how-driver-finds-GCC-installation-path-on-.patch \
     file://0027-Fix-lib-paths-for-OpenEmbedded-Host.patch \
     file://0028-Correct-library-search-path-for-OpenEmbedded-Host.patch \
     file://0029-lldb-Link-with-libatomic-on-x86.patch \
-    file://0030-clang-exclude-openembedded-distributions-from-settin.patch \
-    file://0031-compiler-rt-Enable-__int128-for-ppc32.patch \
-    file://0032-llvm-Do-not-use-cmake-infra-to-detect-libzstd.patch \
-    file://0033-build-Enable-64bit-off_t-on-32bit-glibc-systems.patch \
-    file://0034-compiler-rt-Undef-_TIME_BITS-along-with-_FILE_OFFSET.patch \
-    file://0035-compiler-rt-Fix-stat-struct-s-size-for-O32-ABI.patch \
-    file://0036-compiler-rt-Undef-_TIME_BITS-along-with-_FILE_OFFSET.patch \
-    file://0037-clang-Call-printName-to-get-name-of-Decl.patch \
+    file://0030-compiler-rt-Enable-__int128-for-ppc32.patch \
+    file://0031-llvm-Do-not-use-cmake-infra-to-detect-libzstd.patch \
+    file://0032-compiler-rt-Fix-stat-struct-s-size-for-O32-ABI.patch \
+    file://0033-compiler-rt-Undef-_TIME_BITS-along-with-_FILE_OFFSET.patch \
+    file://0034-ToolChains-Gnu.cpp-ARMLibDirs-search-also-in-lib32.patch \
     "

+ 1 - 1
recipes-devtools/clang/llvm-project-source.inc

@@ -91,6 +91,6 @@ python add_distro_vendor() {
     subprocess.check_output(cmd, stderr=subprocess.STDOUT, shell=True)
 }
 
+do_patch[vardepsexclude] = "MULTILIBS"
 do_patch[postfuncs] += "add_distro_vendor"
 do_create_spdx[depends] += "${PN}:do_patch"
-

+ 0 - 0
recipes-devtools/clang/openmp_16.0.5.bb → recipes-devtools/clang/openmp_17.0.0.bb


+ 0 - 90
recipes-devtools/llvm/llvm/0006-llvm-TargetLibraryInfo-Undefine-libc-functions-if-th.patch

@@ -1,90 +0,0 @@
-Upstream-Status: Pending
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
-
-From dbeecdb307be8b783b42cbc89dcb9c5e7f528989 Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Sat, 21 May 2016 00:33:20 +0000
-Subject: [PATCH] llvm: TargetLibraryInfo: Undefine libc functions if they are macros
-
-musl defines some functions as macros and not inline functions
-if this is the case then make sure to undefine them
-
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
----
- .../llvm/Analysis/TargetLibraryInfo.def       | 21 +++++++++++++++++++
- 1 file changed, 21 insertions(+)
-
-diff --git a/llvm/include/llvm/Analysis/TargetLibraryInfo.def b/llvm/include/llvm/Analysis/TargetLibraryInfo.def
-index afed404f04c..876888656f2 100644
---- a/llvm/include/llvm/Analysis/TargetLibraryInfo.def
-+++ b/llvm/include/llvm/Analysis/TargetLibraryInfo.def
-@@ -782,6 +782,9 @@ TLI_DEFINE_STRING_INTERNAL("fmodl")
- TLI_DEFINE_ENUM_INTERNAL(fopen)
- TLI_DEFINE_STRING_INTERNAL("fopen")
- /// FILE *fopen64(const char *filename, const char *opentype)
-+#ifdef fopen64
-+#undef fopen64
-+#endif
- TLI_DEFINE_ENUM_INTERNAL(fopen64)
- TLI_DEFINE_STRING_INTERNAL("fopen64")
- /// int fork();
-@@ -829,6 +832,9 @@ TLI_DEFINE_STRING_INTERNAL("fseek")
- /// int fseeko(FILE *stream, off_t offset, int whence);
- TLI_DEFINE_ENUM_INTERNAL(fseeko)
- TLI_DEFINE_STRING_INTERNAL("fseeko")
-+#ifdef fseeko64
-+#undef fseeko64
-+#endif
- /// int fseeko64(FILE *stream, off64_t offset, int whence)
- TLI_DEFINE_ENUM_INTERNAL(fseeko64)
- TLI_DEFINE_STRING_INTERNAL("fseeko64")
-@@ -839,6 +845,9 @@ TLI_DEFINE_STRING_INTERNAL("fsetpos")
- TLI_DEFINE_ENUM_INTERNAL(fstat)
- TLI_DEFINE_STRING_INTERNAL("fstat")
- /// int fstat64(int filedes, struct stat64 *buf)
-+#ifdef fstat64
-+#undef fstat64
-+#endif
- TLI_DEFINE_ENUM_INTERNAL(fstat64)
- TLI_DEFINE_STRING_INTERNAL("fstat64")
- /// int fstatvfs(int fildes, struct statvfs *buf);
-@@ -854,6 +863,9 @@ TLI_DEFINE_STRING_INTERNAL("ftell")
- TLI_DEFINE_ENUM_INTERNAL(ftello)
- TLI_DEFINE_STRING_INTERNAL("ftello")
- /// off64_t ftello64(FILE *stream)
-+#ifdef ftello64
-+#undef ftello64
-+#endif
- TLI_DEFINE_ENUM_INTERNAL(ftello64)
- TLI_DEFINE_STRING_INTERNAL("ftello64")
- /// int ftrylockfile(FILE *file);
-@@ -980,6 +992,9 @@ TLI_DEFINE_STRING_INTERNAL("logl")
- TLI_DEFINE_ENUM_INTERNAL(lstat)
- TLI_DEFINE_STRING_INTERNAL("lstat")
- /// int lstat64(const char *path, struct stat64 *buf);
-+#ifdef lstat64
-+#undef lstat64
-+#endif
- TLI_DEFINE_ENUM_INTERNAL(lstat64)
- TLI_DEFINE_STRING_INTERNAL("lstat64")
- /// void *malloc(size_t size);
-@@ -1205,6 +1220,9 @@ TLI_DEFINE_STRING_INTERNAL("sscanf")
- TLI_DEFINE_ENUM_INTERNAL(stat)
- TLI_DEFINE_STRING_INTERNAL("stat")
- /// int stat64(const char *path, struct stat64 *buf);
-+#ifdef stat64
-+#undef stat64
-+#endif
- TLI_DEFINE_ENUM_INTERNAL(stat64)
- TLI_DEFINE_STRING_INTERNAL("stat64")
- /// int statvfs(const char *path, struct statvfs *buf);
-@@ -1340,6 +1358,9 @@ TLI_DEFINE_STRING_INTERNAL("times")
- TLI_DEFINE_ENUM_INTERNAL(tmpfile)
- TLI_DEFINE_STRING_INTERNAL("tmpfile")
- /// FILE *tmpfile64(void)
-+#ifdef tmpfile64
-+#undef tmpfile64
-+#endif
- TLI_DEFINE_ENUM_INTERNAL(tmpfile64)
- TLI_DEFINE_STRING_INTERNAL("tmpfile64")
- /// int toascii(int c);

+ 9 - 9
recipes-devtools/llvm/llvm/0007-llvm-allow-env-override-of-exe-path.patch

@@ -1,27 +1,26 @@
-Upstream-Status: Pending
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
-
-From 61b00e1e051e367f5483d7b5253b6c85a9e8a90f Mon Sep 17 00:00:00 2001
+From 588a8694c6540e31140c7e242bfb5e279d6ca08c Mon Sep 17 00:00:00 2001
 From: Martin Kelly <mkelly@xevo.com>
 Date: Fri, 19 May 2017 00:22:57 -0700
-Subject: [PATCH] llvm: allow env override of exe path
+Subject: [PATCH] llvm: allow env override of exe and libdir path
 
 When using a native llvm-config from inside a sysroot, we need llvm-config to
 return the libraries, include directories, etc. from inside the sysroot rather
 than from the native sysroot. Thus provide an env override for calling
 llvm-config from a target sysroot.
 
+Upstream-Status: Inappropriate [OE-specific]
+
 Signed-off-by: Martin Kelly <mkelly@xevo.com>
 Signed-off-by: Khem Raj <raj.khem@gmail.com>
 ---
- llvm/tools/llvm-config/llvm-config.cpp | 7 +++++++
- 1 file changed, 7 insertions(+)
+ llvm/tools/llvm-config/llvm-config.cpp | 25 +++++++++++++++++++------
+ 1 file changed, 19 insertions(+), 6 deletions(-)
 
 diff --git a/llvm/tools/llvm-config/llvm-config.cpp b/llvm/tools/llvm-config/llvm-config.cpp
-index 7ef7c46a262..a4f7ed82c7b 100644
+index e86eb2b44b10..7b2abf318dbe 100644
 --- a/llvm/tools/llvm-config/llvm-config.cpp
 +++ b/llvm/tools/llvm-config/llvm-config.cpp
-@@ -225,6 +225,13 @@ Typical components:\n\
+@@ -246,6 +246,13 @@ Typical components:\n\
  
  /// Compute the path to the main executable.
  std::string GetExecutablePath(const char *Argv0) {
@@ -35,3 +34,4 @@ index 7ef7c46a262..a4f7ed82c7b 100644
    // This just needs to be some symbol in the binary; C++ doesn't
    // allow taking the address of ::main however.
    void *P = (void *)(intptr_t)GetExecutablePath;
+ 

+ 51 - 0
recipes-devtools/llvm/llvm/llvm-config

@@ -0,0 +1,51 @@
+#!/bin/bash
+#
+# Copyright OpenEmbedded Contributors
+#
+# SPDX-License-Identifier: MIT
+#
+# Wrap llvm-config since the native llvm-config will remap some values correctly
+# if placed in the target sysroot but for flags, it would provide the native ones.
+# Provide ours from the environment instead.
+
+NEXT_LLVM_CONFIG="$(which -a llvm-config | sed -n 2p)"
+if [[ $# == 0 ]]; then
+  exec "$NEXT_LLVM_CONFIG"
+fi
+
+remain=""
+output=""
+for arg in "$@"; do
+  case "$arg" in
+    --cppflags)
+      output="${output} ${CPPFLAGS}"
+      ;;
+    --cflags)
+      output="${output} ${CFLAGS}"
+      ;;
+    --cxxflags)
+      output="${output} ${CXXFLAGS}"
+      ;;
+    --ldflags)
+      output="${output} ${LDFLAGS}"
+      ;;
+    --shared-mode)
+      output="${output} shared"
+      ;;
+    --libs)
+      output="${output} -lLLVM"
+      ;;
+    --link-shared)
+      break
+      ;;
+    *)
+      remain="${remain} ${arg}"
+      ;;
+  esac
+done
+
+if [ "${remain}" != "" ]; then
+      output="${output} "$("$NEXT_LLVM_CONFIG" ${remain})
+fi
+
+echo "${output}"

+ 45 - 62
recipes-devtools/llvm/llvm_git.bb

@@ -1,39 +1,31 @@
 # Copyright (C) 2017 Khem Raj <raj.khem@gmail.com>
 # Released under the MIT license (see COPYING.MIT for the terms)
 
-DESCRIPTION = "The LLVM Compiler Infrastructure"
+SUMMARY = "The LLVM Compiler Infrastructure"
 HOMEPAGE = "http://llvm.org"
 LICENSE = "Apache-2.0-with-LLVM-exception"
 SECTION = "devel"
 
 LIC_FILES_CHKSUM = "file://LICENSE.TXT;md5=8a15a0759ef07f2682d2ba4b893c9afe"
 
-DEPENDS = "libffi libxml2 zlib libedit ninja-native llvm-native"
+DEPENDS = "libffi libxml2 zlib zstd libedit ninja-native llvm-native"
 
 RDEPENDS:${PN}:append:class-target = " ncurses-terminfo"
 
 inherit cmake pkgconfig
 
-PROVIDES += "llvm${PV}"
-
-PV = "16.0.5"
+PV = "17.0.0"
 
 MAJOR_VERSION = "${@oe.utils.trim_version("${PV}", 1)}"
 
 LLVM_RELEASE = "${PV}"
-LLVM_DIR = "llvm${LLVM_RELEASE}"
-
-FILES:${PN}:class-nativesdk += "/usr/local/oe-sdk-hardcoded-buildpath/sysroots/x86_64-oesdk-linux/usr/lib/llvm14.0.0/libLLVM-14git.so \
-  /usr/local/oe-sdk-hardcoded-buildpath/sysroots/x86_64-oesdk-linux/usr/lib/llvm14.0.0/libLLVM-14.0.0git.so \
-  /usr/local/oe-sdk-hardcoded-buildpath/sysroots/x86_64-oesdk-linux/usr/bin/llvm14.0.0/* \
-  "
 
-BRANCH = "main"
-SRCREV = "afab3c488f0c86af87e262cc7454e04de18e3e6a"
+BRANCH = "release/${MAJOR_VERSION}.x"
+SRCREV = "092b6c5ee3707ea10b9f10d0a674e8d12395369b"
 SRC_URI = "git://github.com/llvm/llvm-project.git;branch=${BRANCH};protocol=https \
-           file://0006-llvm-TargetLibraryInfo-Undefine-libc-functions-if-th.patch;striplevel=2 \
            file://0007-llvm-allow-env-override-of-exe-path.patch;striplevel=2 \
            file://0001-AsmMatcherEmitter-sort-ClassInfo-lists-by-name-as-we.patch;striplevel=2 \
+           file://llvm-config \
            "
 
 UPSTREAM_CHECK_GITTAGREGEX = "llvmorg-(?P<pver>\d+(\.\d+)+)"
@@ -59,6 +51,12 @@ def get_llvm_arch(bb, d, arch_var):
 def get_llvm_host_arch(bb, d):
     return get_llvm_arch(bb, d, 'HOST_ARCH')
 
+PACKAGECONFIG ??= "libllvm"
+PACKAGECONFIG:class-native = "${@bb.utils.contains('DISTRO_FEATURES', 'opengl', 'libllvm', '', d)}"
+# if optviewer OFF, force the modules to be not found or the ones on the host would be found
+PACKAGECONFIG[optviewer] = ",-DPY_PYGMENTS_FOUND=OFF -DPY_PYGMENTS_LEXERS_C_CPP_FOUND=OFF -DPY_YAML_FOUND=OFF,python3-pygments python3-pyyaml,python3-pygments python3-pyyaml"
+PACKAGECONFIG[libllvm] = ""
+
 #
 # Default to build all OE-Core supported target arches (user overridable).
 #
@@ -78,8 +76,8 @@ EXTRA_OECMAKE += "-DLLVM_ENABLE_ASSERTIONS=OFF \
                   -DLLVM_OPTIMIZED_TABLEGEN=ON \
                   -DLLVM_TARGETS_TO_BUILD='${LLVM_TARGETS}' \
                   -DLLVM_TEMPORARILY_ALLOW_OLD_TOOLCHAIN=ON \
-                  -DPYTHON_EXECUTABLE=${HOSTTOOLS_DIR}/python3 \
-                  -G Ninja"
+                  -DCMAKE_BUILD_TYPE=Release \
+                 "
 
 EXTRA_OECMAKE:append:class-target = "\
                   -DCMAKE_CROSSCOMPILING:BOOL=ON \
@@ -93,61 +91,47 @@ EXTRA_OECMAKE:append:class-nativesdk = "\
                   -DLLVM_CONFIG_PATH=${STAGING_BINDIR_NATIVE}/llvm-config${PV} \
                  "
 
-do_configure:prepend() {
-# Fix paths in llvm-config
-	sed -i "s|sys::path::parent_path(CurrentPath))\.str()|sys::path::parent_path(sys::path::parent_path(CurrentPath))).str()|g" ${S}/tools/llvm-config/llvm-config.cpp
-	sed -ri "s#/(bin|include|lib)(/?\")#/\1/${LLVM_DIR}\2#g" ${S}/tools/llvm-config/llvm-config.cpp
-	sed -ri "s#lib/${LLVM_DIR}#${baselib}/${LLVM_DIR}#g" ${S}/tools/llvm-config/llvm-config.cpp
-}
-
 # patch out build host paths for reproducibility
 do_compile:prepend:class-target() {
         sed -i -e "s,${WORKDIR},,g" ${B}/tools/llvm-config/BuildVariables.inc
 }
 
 do_compile() {
+    if ${@bb.utils.contains('PACKAGECONFIG', 'libllvm', 'true', 'false', d)}; then
 	ninja -v ${PARALLEL_MAKE}
-}
-
-do_compile:class-native() {
+    else
 	ninja -v ${PARALLEL_MAKE} llvm-config llvm-tblgen
+    fi
 }
 
 do_install() {
-	DESTDIR=${LLVM_INSTALL_DIR} ninja -v install
-	install -D -m 0755 ${B}/bin/llvm-config ${D}${libdir}/${LLVM_DIR}/llvm-config
+    if ${@bb.utils.contains('PACKAGECONFIG', 'libllvm', 'true', 'false', d)}; then
+	DESTDIR=${D} ninja -v install
 
-	install -d ${D}${bindir}/${LLVM_DIR}
-	cp -r ${LLVM_INSTALL_DIR}${bindir}/* ${D}${bindir}/${LLVM_DIR}/
+        # llvm harcodes usr/lib as install path, so this corrects it to actual libdir
+        mv -T -n ${D}/${prefix}/lib ${D}/${libdir} || true
 
-	install -d ${D}${includedir}/${LLVM_DIR}
-	cp -r ${LLVM_INSTALL_DIR}${includedir}/* ${D}${includedir}/${LLVM_DIR}/
+        # Remove opt-viewer: https://llvm.org/docs/Remarks.html
+        rm -rf ${D}${datadir}/opt-viewer
+        rmdir ${D}${datadir}
 
-	install -d ${D}${libdir}/${LLVM_DIR}
-
-	# The LLVM sources have "/lib" embedded and so we cannot completely rely on the ${libdir} variable
-	if [ -d ${LLVM_INSTALL_DIR}${libdir}/ ]; then
-		cp -r ${LLVM_INSTALL_DIR}${libdir}/* ${D}${libdir}/${LLVM_DIR}/
-	elif [ -d ${LLVM_INSTALL_DIR}${prefix}/lib ]; then
-		cp -r ${LLVM_INSTALL_DIR}${prefix}/lib/* ${D}${libdir}/${LLVM_DIR}/
-	elif [ -d ${LLVM_INSTALL_DIR}${prefix}/lib64 ]; then
-		cp -r ${LLVM_INSTALL_DIR}${prefix}/lib64/* ${D}${libdir}/${LLVM_DIR}/
-	fi
-
-	# Remove unnecessary cmake files
-	rm -rf ${D}${libdir}/${LLVM_DIR}/cmake
-
-	ln -s ${LLVM_DIR}/libLLVM-${MAJOR_VERSION}${SOLIBSDEV} ${D}${libdir}/libLLVM-${MAJOR_VERSION}${SOLIBSDEV}
-
-	# We'll have to delete the libLLVM.so due to multiple reasons...
-	rm -rf ${D}${libdir}/${LLVM_DIR}/libLLVM.so
-	rm -rf ${D}${libdir}/${LLVM_DIR}/libLTO.so
+        # reproducibility
+        sed -i -e 's,${WORKDIR},,g' ${D}/${libdir}/cmake/llvm/LLVMConfig.cmake
+    fi
 }
 
-do_install:class-native() {
+do_install:append:class-native() {
 	install -D -m 0755 ${B}/bin/llvm-tblgen ${D}${bindir}/llvm-tblgen${PV}
 	install -D -m 0755 ${B}/bin/llvm-config ${D}${bindir}/llvm-config${PV}
-	install -D -m 0755 ${B}/lib/libLLVM-${MAJOR_VERSION}.so ${D}${libdir}/libLLVM-${MAJOR_VERSION}.so
+	ln -sf llvm-config${PV} ${D}${bindir}/llvm-config
+}
+
+SYSROOT_PREPROCESS_FUNCS:append:class-target = " llvm_sysroot_preprocess"
+
+llvm_sysroot_preprocess() {
+	install -d ${SYSROOT_DESTDIR}${bindir_crossscripts}/
+	install -m 0755 ${WORKDIR}/llvm-config ${SYSROOT_DESTDIR}${bindir_crossscripts}/
+	ln -sf llvm-config ${SYSROOT_DESTDIR}${bindir_crossscripts}/llvm-config${PV}
 }
 
 PACKAGES =+ "${PN}-bugpointpasses ${PN}-llvmhello ${PN}-libllvm ${PN}-liboptremarks ${PN}-liblto"
@@ -155,34 +139,33 @@ PACKAGES =+ "${PN}-bugpointpasses ${PN}-llvmhello ${PN}-libllvm ${PN}-liboptrema
 RRECOMMENDS:${PN}-dev += "${PN}-bugpointpasses ${PN}-llvmhello ${PN}-liboptremarks"
 
 FILES:${PN}-bugpointpasses = "\
-    ${libdir}/${LLVM_DIR}/BugpointPasses.so \
+    ${libdir}/BugpointPasses.so \
 "
 
 FILES:${PN}-libllvm = "\
-    ${libdir}/${LLVM_DIR}/libLLVM-${MAJOR_VERSION}.so \
     ${libdir}/libLLVM-${MAJOR_VERSION}.so \
 "
 
 FILES:${PN}-liblto += "\
-    ${libdir}/${LLVM_DIR}/libLTO.so.* \
+    ${libdir}/libLTO.so.* \
 "
 
 FILES:${PN}-liboptremarks += "\
-    ${libdir}/${LLVM_DIR}/libRemarks.so.* \
+    ${libdir}/libRemarks.so.* \
 "
 
 FILES:${PN}-llvmhello = "\
-    ${libdir}/${LLVM_DIR}/LLVMHello.so \
+    ${libdir}/LLVMHello.so \
 "
 
 FILES:${PN}-dev += " \
-    ${libdir}/${LLVM_DIR}/llvm-config \
-    ${libdir}/${LLVM_DIR}/libRemarks.so \
-    ${libdir}/${LLVM_DIR}/libLLVM-${PV}.so \
+    ${libdir}/llvm-config \
+    ${libdir}/libRemarks.so \
+    ${libdir}/libLLVM-${PV}.so \
 "
 
 FILES:${PN}-staticdev += "\
-    ${libdir}/${LLVM_DIR}/*.a \
+    ${libdir}/*.a \
 "
 
 INSANE_SKIP:${PN}-libllvm += "dev-so"

Some files were not shown because too many files changed in this diff