Browse Source

dubhe: gcc: Update & patch gcc toolchain (11.1 -> 12.1).

Signed-off-by: weiheng.cheng <weiheng.cheng@starfivetech.com>
weiheng.cheng 1 year ago
parent
commit
67047978ba
100 changed files with 2439 additions and 5945 deletions
  1. 0 148
      recipes-devtools/gcc/gcc-11.1.inc
  2. 129 0
      recipes-devtools/gcc/gcc-12.1.inc
  3. 2 6
      recipes-devtools/gcc/gcc-common.inc
  4. 10 1
      recipes-devtools/gcc/gcc-configure-common.inc
  5. 6 6
      recipes-devtools/gcc/gcc-cross-canadian.inc
  6. 0 4
      recipes-devtools/gcc/gcc-cross-canadian_11.1.bb
  7. 5 0
      recipes-devtools/gcc/gcc-cross-canadian_12.1.bb
  8. 10 8
      recipes-devtools/gcc/gcc-cross.inc
  9. 0 4
      recipes-devtools/gcc/gcc-cross_11.1.bb
  10. 5 0
      recipes-devtools/gcc/gcc-cross_12.1.bb
  11. 0 4
      recipes-devtools/gcc/gcc-crosssdk_11.1.bb
  12. 5 0
      recipes-devtools/gcc/gcc-crosssdk_12.1.bb
  13. 23 9
      recipes-devtools/gcc/gcc-multilib-config.inc
  14. 10 19
      recipes-devtools/gcc/gcc-runtime.inc
  15. 0 0
      recipes-devtools/gcc/gcc-runtime_12.1.bb
  16. 3 1
      recipes-devtools/gcc/gcc-sanitizers.inc
  17. 0 0
      recipes-devtools/gcc/gcc-sanitizers_12.1.bb
  18. 1 0
      recipes-devtools/gcc/gcc-source.inc
  19. 0 6
      recipes-devtools/gcc/gcc-source_11.1.bb
  20. 7 0
      recipes-devtools/gcc/gcc-source_12.1.bb
  21. 1 2
      recipes-devtools/gcc/gcc-target.inc
  22. 0 96
      recipes-devtools/gcc/gcc/0001-Upstream-Status-Backport.patch
  23. 0 25
      recipes-devtools/gcc/gcc/0001-Yocto-patch-for-arch-canonicalize-to-use-python3.patch
  24. 5 5
      recipes-devtools/gcc/gcc/0001-gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch
  25. 45 0
      recipes-devtools/gcc/gcc/0001-libsanitizer-cherry-pick-9cf13067cb5088626ba7-from-u.patch
  26. 22 12
      recipes-devtools/gcc/gcc/0001-merge-Kito-Cheng-s-patch-Handle-different-sigcontext.patch
  27. 0 73
      recipes-devtools/gcc/gcc/0001-testuite-Check-pthread-for-omp-module-testing.patch
  28. 0 31
      recipes-devtools/gcc/gcc/0002-Fix-a-test-failure-in-g-.dg-modules-omp-1_c.C.patch
  29. 27 27
      recipes-devtools/gcc/gcc/0002-gcc-poison-system-directories.patch
  30. 60 0
      recipes-devtools/gcc/gcc/0002-set-c-default-standard-to-c-14.patch
  31. 27 9
      recipes-devtools/gcc/gcc/0003-64-bit-multilib-hack.patch
  32. 6 6
      recipes-devtools/gcc/gcc/0003-fix-the-c-sources-building-failure-issue.patch
  33. 0 70
      recipes-devtools/gcc/gcc/0003-gcc-4.3.3-SYSROOT_CFLAGS_FOR_TARGET.patch
  34. 0 39
      recipes-devtools/gcc/gcc/0003-testuite-Check-pthread-for-omp-module-testing.patch
  35. 64 0
      recipes-devtools/gcc/gcc/0004-Pass-CXXFLAGS_FOR_BUILD-in-a-couple-of-places-to-avo.patch
  36. 26 0
      recipes-devtools/gcc/gcc/0004-define-__riscv_vector-macro.patch
  37. 0 180
      recipes-devtools/gcc/gcc/0004-varasm-Two-SECTION_RETAIN-fixes-PR100130.patch
  38. 8 8
      recipes-devtools/gcc/gcc/0005-Use-the-defaults.h-in-B-instead-of-S-and-t-oe-in-B.patch
  39. 6 6
      recipes-devtools/gcc/gcc/0005-enable-ifunc-for-riscv.patch
  40. 0 122
      recipes-devtools/gcc/gcc/0005-optional-libstdc.patch
  41. 0 142
      recipes-devtools/gcc/gcc/0005-testsuite-Add-fchecking-to-dg-ice-tests.patch
  42. 0 35
      recipes-devtools/gcc/gcc/0006-COLLECT_GCC_OPTIONS.patch
  43. 8 8
      recipes-devtools/gcc/gcc/0006-cpp-honor-sysroot.patch
  44. 277 0
      recipes-devtools/gcc/gcc/0006-merge-b-extension-changes.patch
  45. 0 25
      recipes-devtools/gcc/gcc/0006-testsuite-Add-ilp32-to-g-.dg-warn-Warray-bounds-20.C.patch
  46. 194 34
      recipes-devtools/gcc/gcc/0007-Define-GLIBC_DYNAMIC_LINKER-and-UCLIBC_DYNAMIC_LINKE.patch
  47. 488 0
      recipes-devtools/gcc/gcc/0007-add-initial-dubhe-scheduling-model.patch
  48. 0 131
      recipes-devtools/gcc/gcc/0007-merge-from-riscv-gcc-10.2.0-to-support-bitmanip.patch
  49. 177 0
      recipes-devtools/gcc/gcc/0008-add-dubhe-.md-file.patch
  50. 0 43
      recipes-devtools/gcc/gcc/0008-fortran-cross-compile-hack.patch
  51. 1 1
      recipes-devtools/gcc/gcc/0008-libtool.patch
  52. 0 1542
      recipes-devtools/gcc/gcc/0008-merge-from-riscv-gcc-10.2.0-to-support-bitmanip.patch
  53. 58 0
      recipes-devtools/gcc/gcc/0009-add-multilib-config-for-baremetal.patch
  54. 3 3
      recipes-devtools/gcc/gcc/0009-gcc-armv4-pass-fix-v4bx-to-linker-to-support-EABI.patch
  55. 0 45
      recipes-devtools/gcc/gcc/0009-update-B-version-from-0.93-to-0.94.patch
  56. 0 54
      recipes-devtools/gcc/gcc/0010-MIPS64-Default-to-N64-ABI.patch
  57. 0 253
      recipes-devtools/gcc/gcc/0010-Merge-B-instruction-from-0p94-to-1.0.patch
  58. 7 7
      recipes-devtools/gcc/gcc/0010-Use-the-multilib-config-files-from-B-instead-of-usin.patch
  59. 41 0
      recipes-devtools/gcc/gcc/0010-only-generate-strictly-aligned-code.patch
  60. 1 1
      recipes-devtools/gcc/gcc/0011-Avoid-using-libdir-from-.la-which-usually-points-to-.patch
  61. 94 0
      recipes-devtools/gcc/gcc/0011-Make-ranger-vrp1-default.patch
  62. 0 77
      recipes-devtools/gcc/gcc/0011-remove-b-flag-and-use-zba_zbb_zbc_zbs-instead.patch
  63. 4 4
      recipes-devtools/gcc/gcc/0012-export-CPP.patch
  64. 0 42
      recipes-devtools/gcc/gcc/0012-gcc-Fix-argument-list-too-long-error.patch
  65. 0 32
      recipes-devtools/gcc/gcc/0012-replace-x_riscv_bitmanip_subext-with-x_riscv_bitmani.patch
  66. 0 110
      recipes-devtools/gcc/gcc/0013-Disable-sdt.patch
  67. 113 0
      recipes-devtools/gcc/gcc/0013-Ensure-target-gcc-headers-can-be-included.patch
  68. 0 24
      recipes-devtools/gcc/gcc/0013-remove-b-gcc-options.patch
  69. 1 1
      recipes-devtools/gcc/gcc/0014-Don-t-search-host-directory-during-relink-if-inst_pr.patch
  70. 0 31
      recipes-devtools/gcc/gcc/0014-fix-incorrect-subext-name.patch
  71. 0 127
      recipes-devtools/gcc/gcc/0015-add-builtin-orc.b-clmul-clmulr-clmulh.patch
  72. 4 4
      recipes-devtools/gcc/gcc/0015-libcc1-fix-libcc1-s-install-path-and-rpath.patch
  73. 200 39
      recipes-devtools/gcc/gcc/0016-handle-sysroot-support-for-nativesdk-gcc.patch
  74. 0 545
      recipes-devtools/gcc/gcc/0016-merge-sifve-change-for-bitmanip.patch
  75. 0 208
      recipes-devtools/gcc/gcc/0017-Implement-instruction-patterns-for-ZBA-extension.patch
  76. 8 8
      recipes-devtools/gcc/gcc/0017-Search-target-sysroot-gcc-version-specific-dirs-with.patch
  77. 8 8
      recipes-devtools/gcc/gcc/0018-Add-ssp_nonshared-to-link-commandline-for-musl-targe.patch
  78. 0 119
      recipes-devtools/gcc/gcc/0018-Cost-model-for-zba-extension.patch
  79. 0 57
      recipes-devtools/gcc/gcc/0019-Ensure-target-gcc-headers-can-be-included.patch
  80. 0 274
      recipes-devtools/gcc/gcc/0019-Implement-instruction-patterns-for-ZBB-extension.patch
  81. 3 3
      recipes-devtools/gcc/gcc/0019-Re-introduce-spe-commandline-options.patch
  82. 0 48
      recipes-devtools/gcc/gcc/0020-Cost-model-for-zbb-extension.patch
  83. 14 14
      recipes-devtools/gcc/gcc/0020-libgcc_s-Use-alias-for-__cpu_indicator_init-instead-.patch
  84. 0 26
      recipes-devtools/gcc/gcc/0021-Use-SYSTEMLIBS_DIR-replacement-instead-of-hardcoding.patch
  85. 0 108
      recipes-devtools/gcc/gcc/0021-Use-li-and-rori-to-load-constants.patch
  86. 36 36
      recipes-devtools/gcc/gcc/0021-gentypes-genmodes-Do-not-use-__LINE__-for-maintainin.patch
  87. 0 297
      recipes-devtools/gcc/gcc/0022-Implement-instruction-patterns-for-ZBS-extension.patch
  88. 0 25
      recipes-devtools/gcc/gcc/0022-aarch64-Add-support-for-musl-ldso.patch
  89. 2 2
      recipes-devtools/gcc/gcc/0022-mingw32-Enable-operation_not_supported.patch
  90. 0 88
      recipes-devtools/gcc/gcc/0023-Cost-model-for-ZBS-extension.patch
  91. 5 5
      recipes-devtools/gcc/gcc/0023-libatomic-Do-not-enforce-march-on-aarch64.patch
  92. 31 0
      recipes-devtools/gcc/gcc/0024-Fix-install-path-of-linux64.h.patch
  93. 0 31
      recipes-devtools/gcc/gcc/0024-RISC-V-costs-handle-BSWAP.patch
  94. 56 0
      recipes-devtools/gcc/gcc/0025-Move-sched.h-include-ahead-of-user-headers.patch
  95. 0 54
      recipes-devtools/gcc/gcc/0025-RISC-V-costs-support-shift-and-add-in-strength-reduc.patch
  96. 0 134
      recipes-devtools/gcc/gcc/0026-Fix-various-_FOR_BUILD-and-related-variables.patch
  97. 0 35
      recipes-devtools/gcc/gcc/0026-RISC-V-bitmanip-fix-constant-loading-for-1ULL-31-in-.patch
  98. 92 0
      recipes-devtools/gcc/gcc/0026-rust-recursion-limit.patch
  99. 0 25
      recipes-devtools/gcc/gcc/0027-nios2-Define-MUSL_DYNAMIC_LINKER.patch
  100. 0 53
      recipes-devtools/gcc/gcc/0028-define-__riscv_vector-macro.patch

+ 0 - 148
recipes-devtools/gcc/gcc-11.1.inc

@@ -1,148 +0,0 @@
-require gcc-common.inc
-
-# Third digit in PV should be incremented after a minor release
-
-PV = "11.1.0"
-
-# BINV should be incremented to a revision after a minor gcc release
-
-BINV = "11.1.0"
-
-FILESEXTRAPATHS =. "${FILE_DIRNAME}/gcc:${FILE_DIRNAME}/gcc/backport:"
-
-DEPENDS =+ "mpfr gmp libmpc zlib flex-native"
-NATIVEDEPS = "mpfr-native gmp-native libmpc-native zlib-native flex-native"
-
-LICENSE = "GPL-3.0-with-GCC-exception & GPLv3"
-
-LIC_FILES_CHKSUM = "\
-    file://COPYING;md5=59530bdf33659b29e73d4adb9f9f6552 \
-    file://COPYING3;md5=d32239bcb673463ab874e80d47fae504 \
-    file://COPYING3.LIB;md5=6a6a8e020838b23406c81b19c1d46df6 \
-    file://COPYING.LIB;md5=2d5025d4aa3495befef8f17206a5b0a1 \
-    file://COPYING.RUNTIME;md5=fe60d87048567d4fe8c8a0ed2448bcc8 \
-"
-
-#RELEASE ?= "5b2ac9b40c325e9209c0bd55955db84aad4a0cc5"
-#BASEURI ?= "https://github.com/gcc-mirror/gcc/archive/${RELEASE}.zip;downloadfilename=gcc-${PV}-${RELEASE}.zip"
-BASEURI ?= "${GNU_MIRROR}/gcc/gcc-${PV}/gcc-${PV}.tar.xz \
-           "
-SRC_URI = "\
-           ${BASEURI} \
-           file://0001-gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch \
-           file://0002-gcc-poison-system-directories.patch \
-           file://0003-gcc-4.3.3-SYSROOT_CFLAGS_FOR_TARGET.patch \
-           file://0004-64-bit-multilib-hack.patch \
-           file://0005-optional-libstdc.patch \
-           file://0006-COLLECT_GCC_OPTIONS.patch \
-           file://0007-Use-the-defaults.h-in-B-instead-of-S-and-t-oe-in-B.patch \
-           file://0008-fortran-cross-compile-hack.patch \
-           file://0009-cpp-honor-sysroot.patch \
-           file://0010-MIPS64-Default-to-N64-ABI.patch \
-           file://0011-Define-GLIBC_DYNAMIC_LINKER-and-UCLIBC_DYNAMIC_LINKE.patch \
-           file://0012-gcc-Fix-argument-list-too-long-error.patch \
-           file://0013-Disable-sdt.patch \
-           file://0014-libtool.patch \
-           file://0015-gcc-armv4-pass-fix-v4bx-to-linker-to-support-EABI.patch \
-           file://0016-Use-the-multilib-config-files-from-B-instead-of-usin.patch \
-           file://0017-Avoid-using-libdir-from-.la-which-usually-points-to-.patch \
-           file://0018-export-CPP.patch \
-           file://0019-Ensure-target-gcc-headers-can-be-included.patch \
-           file://0020-Don-t-search-host-directory-during-relink-if-inst_pr.patch \
-           file://0021-Use-SYSTEMLIBS_DIR-replacement-instead-of-hardcoding.patch \
-           file://0022-aarch64-Add-support-for-musl-ldso.patch \
-           file://0023-libcc1-fix-libcc1-s-install-path-and-rpath.patch \
-           file://0024-handle-sysroot-support-for-nativesdk-gcc.patch \
-           file://0025-Search-target-sysroot-gcc-version-specific-dirs-with.patch \
-           file://0026-Fix-various-_FOR_BUILD-and-related-variables.patch \
-           file://0027-nios2-Define-MUSL_DYNAMIC_LINKER.patch \
-           file://0028-Add-ssp_nonshared-to-link-commandline-for-musl-targe.patch \
-           file://0029-Link-libgcc-using-LDFLAGS-not-just-SHLIB_LDFLAGS.patch \
-           file://0030-sync-gcc-stddef.h-with-musl.patch \
-           file://0031-fix-segmentation-fault-in-precompiled-header-generat.patch \
-           file://0032-Fix-for-testsuite-failure.patch \
-           file://0033-Re-introduce-spe-commandline-options.patch \
-           file://0034-libgcc_s-Use-alias-for-__cpu_indicator_init-instead-.patch \
-           file://0035-gentypes-genmodes-Do-not-use-__LINE__-for-maintainin.patch \
-           file://0036-mingw32-Enable-operation_not_supported.patch \
-           file://0037-libatomic-Do-not-enforce-march-on-aarch64.patch \
-           file://0001-testuite-Check-pthread-for-omp-module-testing.patch \
-           file://0002-Fix-a-test-failure-in-g-.dg-modules-omp-1_c.C.patch \
-           file://0003-testuite-Check-pthread-for-omp-module-testing.patch \
-           file://0004-varasm-Two-SECTION_RETAIN-fixes-PR100130.patch \
-           file://0006-testsuite-Add-ilp32-to-g-.dg-warn-Warray-bounds-20.C.patch \
-           file://0007-merge-from-riscv-gcc-10.2.0-to-support-bitmanip.patch \
-           file://0008-merge-from-riscv-gcc-10.2.0-to-support-bitmanip.patch \
-           file://0009-update-B-version-from-0.93-to-0.94.patch \
-           file://0010-Merge-B-instruction-from-0p94-to-1.0.patch \
-           file://0011-remove-b-flag-and-use-zba_zbb_zbc_zbs-instead.patch \
-           file://0012-replace-x_riscv_bitmanip_subext-with-x_riscv_bitmani.patch \
-           file://0013-remove-b-gcc-options.patch \
-           file://0014-fix-incorrect-subext-name.patch \
-           file://0015-add-builtin-orc.b-clmul-clmulr-clmulh.patch \
-           file://0016-merge-sifve-change-for-bitmanip.patch \
-           file://0017-Implement-instruction-patterns-for-ZBA-extension.patch \
-           file://0018-Cost-model-for-zba-extension.patch \
-           file://0019-Implement-instruction-patterns-for-ZBB-extension.patch \
-           file://0020-Cost-model-for-zbb-extension.patch \
-           file://0021-Use-li-and-rori-to-load-constants.patch \
-           file://0022-Implement-instruction-patterns-for-ZBS-extension.patch \
-           file://0023-Cost-model-for-ZBS-extension.patch \
-           file://0024-RISC-V-costs-handle-BSWAP.patch \
-           file://0025-RISC-V-costs-support-shift-and-add-in-strength-reduc.patch \
-           file://0026-RISC-V-bitmanip-fix-constant-loading-for-1ULL-31-in-.patch \
-	   file://0027-enable-ifunc-for-riscv.patch \
-	   file://0028-define-__riscv_vector-macro.patch \
-	   file://0029-fix-libcc-compiling-error.patch \
-	   file://0030-add-multilib-support-for-v-b.patch \
-	   file://0031-Revert-c-Change-the-default-dialect-to-C-17.patch \
-	   file://0032-fix-the-c-sources-building-failure-issue.patch \
-	   file://0033-merge-Kito-Cheng-s-patch-Handle-different-sigcontext.patch \
-           file://0001-Yocto-patch-for-arch-canonicalize-to-use-python3.patch \
-"
-SRC_URI[sha256sum] = "4c4a6fb8a8396059241c2e674b85b351c26a5d678274007f076957afa1cc9ddf"
-
-S = "${TMPDIR}/work-shared/gcc-${PV}-${PR}/gcc-${PV}"
-
-# For dev release snapshotting
-#S = "${TMPDIR}/work-shared/gcc-${PV}-${PR}/gcc-${RELEASE}"
-#B = "${WORKDIR}/gcc-${PV}/build.${HOST_SYS}.${TARGET_SYS}"
-
-# Language Overrides
-FORTRAN = ""
-JAVA = ""
-
-SSP ?= "--disable-libssp"
-SSP:mingw32 = "--enable-libssp"
-
-EXTRA_OECONF_BASE = "\
-    --enable-lto \
-    --disable-bootstrap \
-    --with-system-zlib \
-    ${@'--with-linker-hash-style=${LINKER_HASH_STYLE}' if '${LINKER_HASH_STYLE}' else ''} \
-    --enable-linker-build-id \
-    --with-ppl=no \
-    --with-cloog=no \
-    --enable-checking=release \
-    --enable-cheaders=c_global \
-    --without-isl \
-"
-
-EXTRA_OECONF_INITIAL = "\
-    --disable-libgomp \
-    --disable-libitm \
-    --disable-libquadmath \
-    --with-system-zlib \
-    --disable-lto \
-    --disable-plugin \
-    --enable-linker-build-id \
-    --enable-decimal-float=no \
-    --without-isl \
-    --disable-libssp \
-"
-
-EXTRA_OECONF_PATHS = "\
-    --with-gxx-include-dir=/not/exist{target_includedir}/c++/${BINV} \
-    --with-sysroot=/not/exist \
-    --with-build-sysroot=${STAGING_DIR_TARGET} \
-"

+ 129 - 0
recipes-devtools/gcc/gcc-12.1.inc

@@ -0,0 +1,129 @@
+require gcc-common.inc
+
+# Third digit in PV should be incremented after a minor release
+
+PV = "12.1.0"
+
+# BINV should be incremented to a revision after a minor gcc release
+
+BINV = "12.1.0"
+
+FILESEXTRAPATHS =. "${FILE_DIRNAME}/gcc:${FILE_DIRNAME}/gcc/backport:"
+
+DEPENDS =+ "mpfr gmp libmpc zlib flex-native"
+NATIVEDEPS = "mpfr-native gmp-native libmpc-native zlib-native flex-native zstd-native"
+
+LICENSE = "GPL-3.0-with-GCC-exception & GPL-3.0-only"
+
+LIC_FILES_CHKSUM = "\
+    file://COPYING;md5=59530bdf33659b29e73d4adb9f9f6552 \
+    file://COPYING3;md5=d32239bcb673463ab874e80d47fae504 \
+    file://COPYING3.LIB;md5=6a6a8e020838b23406c81b19c1d46df6 \
+    file://COPYING.LIB;md5=2d5025d4aa3495befef8f17206a5b0a1 \
+    file://COPYING.RUNTIME;md5=fe60d87048567d4fe8c8a0ed2448bcc8 \
+"
+# from git
+#RELEASE ?= "7092b7aea122a91824d048aeb23834cf1d19b1a1"
+#BASEURI ?= "https://repo.or.cz/official-gcc.git/snapshot/${RELEASE}.tar.gz;downloadfilename=gcc-${PV}-${RELEASE}.tar.gz"
+#SOURCEDIR ?= "official-gcc-${@'${RELEASE}'[0:7]}"
+
+# from snapshot
+#RELEASE ?= "12.1.0-RC-20220429"
+#SOURCEDIR ?= "gcc-${RELEASE}"
+#BASEURI ?= "https://gcc.gnu.org/pub/gcc/snapshots/${RELEASE}/gcc-${RELEASE}.tar.xz"
+
+# official release
+RELEASE ?= "${PV}"
+BASEURI ?= "${GNU_MIRROR}/gcc/gcc-${PV}/gcc-${PV}.tar.xz"
+SOURCEDIR ?= "gcc-${PV}"
+
+SRC_URI = "${BASEURI} \
+           file://0001-gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch \
+           file://0002-gcc-poison-system-directories.patch \
+           file://0003-64-bit-multilib-hack.patch \
+           file://0004-Pass-CXXFLAGS_FOR_BUILD-in-a-couple-of-places-to-avo.patch \
+           file://0005-Use-the-defaults.h-in-B-instead-of-S-and-t-oe-in-B.patch \
+           file://0006-cpp-honor-sysroot.patch \
+           file://0007-Define-GLIBC_DYNAMIC_LINKER-and-UCLIBC_DYNAMIC_LINKE.patch \
+           file://0008-libtool.patch \
+           file://0009-gcc-armv4-pass-fix-v4bx-to-linker-to-support-EABI.patch \
+           file://0010-Use-the-multilib-config-files-from-B-instead-of-usin.patch \
+           file://0011-Avoid-using-libdir-from-.la-which-usually-points-to-.patch \
+           file://0012-export-CPP.patch \
+           file://0013-Ensure-target-gcc-headers-can-be-included.patch \
+           file://0014-Don-t-search-host-directory-during-relink-if-inst_pr.patch \
+           file://0015-libcc1-fix-libcc1-s-install-path-and-rpath.patch \
+           file://0016-handle-sysroot-support-for-nativesdk-gcc.patch \
+           file://0017-Search-target-sysroot-gcc-version-specific-dirs-with.patch \
+           file://0018-Add-ssp_nonshared-to-link-commandline-for-musl-targe.patch \
+           file://0019-Re-introduce-spe-commandline-options.patch \
+           file://0020-libgcc_s-Use-alias-for-__cpu_indicator_init-instead-.patch \
+           file://0021-gentypes-genmodes-Do-not-use-__LINE__-for-maintainin.patch \
+           file://0022-mingw32-Enable-operation_not_supported.patch \
+           file://0023-libatomic-Do-not-enforce-march-on-aarch64.patch \
+           file://0024-Fix-install-path-of-linux64.h.patch \
+           file://0025-Move-sched.h-include-ahead-of-user-headers.patch \
+           file://0026-rust-recursion-limit.patch \
+           file://0001-libsanitizer-cherry-pick-9cf13067cb5088626ba7-from-u.patch \
+           file://prefix-map-realpath.patch \
+           file://hardcoded-paths.patch \
+	   file://0001-merge-Kito-Cheng-s-patch-Handle-different-sigcontext.patch \
+           file://0002-set-c-default-standard-to-c-14.patch \
+           file://0003-fix-the-c-sources-building-failure-issue.patch \
+           file://0004-define-__riscv_vector-macro.patch \
+           file://0005-enable-ifunc-for-riscv.patch \
+           file://0006-merge-b-extension-changes.patch \
+           file://0007-add-initial-dubhe-scheduling-model.patch \
+           file://0008-add-dubhe-.md-file.patch \
+           file://0009-add-multilib-config-for-baremetal.patch \
+           file://0010-only-generate-strictly-aligned-code.patch \
+           file://0011-Make-ranger-vrp1-default.patch \
+           "
+SRC_URI[sha256sum] = "62fd634889f31c02b64af2c468f064b47ad1ca78411c45abe6ac4b5f8dd19c7b"
+
+S = "${TMPDIR}/work-shared/gcc-${PV}-${PR}/${SOURCEDIR}"
+B = "${WORKDIR}/gcc-${PV}/build.${HOST_SYS}.${TARGET_SYS}"
+
+# Language Overrides
+FORTRAN = ""
+JAVA = ""
+
+SSP ?= "--disable-libssp"
+SSP:mingw32 = "--enable-libssp"
+
+# Removed "--enable-libitm"
+EXTRA_OECONF_BASE = "\
+    ${SSP} \
+    --enable-lto \
+    --disable-bootstrap \
+    --with-system-zlib \
+    ${@'--with-linker-hash-style=${LINKER_HASH_STYLE}' if '${LINKER_HASH_STYLE}' else ''} \
+    --enable-linker-build-id \
+    --with-ppl=no \
+    --with-cloog=no \
+    --enable-checking=release \
+    --enable-cheaders=c_global \
+    --without-isl \
+"
+
+EXTRA_OECONF_INITIAL = "\
+    --disable-libgomp \
+    --disable-libitm \
+    --disable-libquadmath \
+    --with-system-zlib \
+    --disable-lto \
+    --disable-plugin \
+    --enable-linker-build-id \
+    --enable-decimal-float=no \
+    --without-isl \
+    --disable-libssp \
+"
+
+EXTRA_OECONF_PATHS = "\
+    --with-gxx-include-dir=/not/exist{target_includedir}/c++/${BINV} \
+    --with-sysroot=/not/exist \
+    --with-build-sysroot=${STAGING_DIR_TARGET} \
+"
+
+# Is a binutils 2.26 issue, not gcc
+CVE_CHECK_IGNORE += "CVE-2021-37322"

+ 2 - 6
recipes-devtools/gcc/gcc-common.inc

@@ -86,11 +86,7 @@ get_tune_parameters[vardepsexclude] = "AVAILTUNES TUNE_CCARGS OVERRIDES TUNE_FEA
 DEBIANNAME:${MLPREFIX}libgcc = "libgcc1"
 
 MIRRORS =+ "\
-${GNU_MIRROR}/gcc    ftp://gcc.gnu.org/pub/gcc/releases/ \n \
-${GNU_MIRROR}/gcc	ftp://gd.tuwien.ac.at/gnu/gcc/ \n \
-${GNU_MIRROR}/gcc	http://mirrors.rcn.net/pub/sourceware/gcc/releases/ \n \
-${GNU_MIRROR}/gcc   http://gcc.get-software.com/releases/ \n \
-${GNU_MIRROR}/gcc	http://gcc.get-software.com/releases/ \n \
+    ${GNU_MIRROR}/gcc https://gcc.gnu.org/pub/gcc/releases/ \
 "
 #
 # Set some default values
@@ -100,7 +96,7 @@ BINV = "${PV}"
 #S = "${WORKDIR}/gcc-${PV}"
 S = "${TMPDIR}/work-shared/gcc-${PV}-${PR}/gcc-${PV}"
 
-B = "${WORKDIR}/gcc-${PV}/build.${HOST_SYS}.${TARGET_SYS}"
+B ?= "${WORKDIR}/gcc-${PV}/build.${HOST_SYS}.${TARGET_SYS}"
 
 target_includedir ?= "${includedir}"
 target_libdir ?= "${libdir}"

+ 10 - 1
recipes-devtools/gcc/gcc-configure-common.inc

@@ -21,18 +21,22 @@ SYMVERS_CONF ?= "--enable-symvers=gnu"
 
 EXTRA_OECONF = "\
     ${@['--enable-clocale=generic', ''][d.getVar('USE_NLS') != 'no']} \
+    --enable-shared \
     --enable-languages=${LANGUAGES} \
     --enable-threads=${GCCTHREADS} \
     ${GCCMULTILIB} \
+    ${GCCPIE} \
     ${SYMVERS_CONF} \
     --program-prefix=${TARGET_PREFIX} \
     --without-local-prefix \
     --enable-lto \
+    ${EXTRA_OECONF_BASE} \
     ${EXTRA_OECONF_GCC_FLOAT} \
     ${EXTRA_OECONF_PATHS} \
     ${@get_gcc_mips_plt_setting(bb, d)} \
     ${@get_gcc_ppc_plt_settings(bb, d)} \
     ${@get_gcc_multiarch_setting(bb, d)} \
+    --enable-standard-branch-protection \
     --disable-libmudflap \
     --disable-libgomp \
     --disable-libssp \
@@ -40,6 +44,11 @@ EXTRA_OECONF = "\
     --disable-libquadmath-support \
     --disable-libmpx \
     --enable-target-optspace \
+    --with-gmp \
+    --with-mpfr \
+    --with-mpc \
+    --enable-tls \
+    --without-isl \
 "
 
 # glibc version is a minimum controlling whether features are enabled. 
@@ -48,7 +57,7 @@ EXTRA_OECONF:append:libc-glibc = " --with-glibc-version=2.28 "
 
 # Set this here since GCC configure won't auto-detect and enable
 # initfini-arry when cross compiling.
-###EXTRA_OECONF:append = " --enable-initfini-array"
+#EXTRA_OECONF:append = " --enable-initfini-array"
 
 export gcc_cv_collect2_libs = 'none required'
 # We need to set gcc_cv_collect2_libs else there is cross-compilation badness

+ 6 - 6
recipes-devtools/gcc/gcc-cross-canadian.inc

@@ -53,6 +53,9 @@ export WINDRES_FOR_TARGET = "${TARGET_PREFIX}windres"
 export ARCH_FLAGS_FOR_TARGET = "--sysroot=${STAGING_DIR_TARGET}"
 
 do_configure () {
+        if [ ! -d ${RECIPE_SYSROOT}/${target_includedir} ]; then
+            mkdir -p ${RECIPE_SYSROOT}/${target_includedir}
+        fi
 	export CC_FOR_BUILD="${BUILD_CC}"
 	export CXX_FOR_BUILD="${BUILD_CXX}"
 	export CFLAGS_FOR_BUILD="${BUILD_CFLAGS}"
@@ -132,7 +135,7 @@ do_install () {
 	dest=${D}${libexecdir}/gcc/${TARGET_SYS}/${BINV}/
 	install -d $dest
 	suffix=${EXEEXT}
-	for t in ar as ld nm objcopy objdump ranlib strip g77 gcc cpp gfortran; do
+	for t in ar as ld ld.bfd ld.gold nm objcopy objdump ranlib strip g77 gcc cpp gfortran; do
 		if [ "$t" = "g77" -o "$t" = "gfortran" ] && [ ! -e ${D}${bindir}/${TARGET_PREFIX}$t$suffix ]; then
 			continue
 		fi
@@ -180,7 +183,7 @@ do_install () {
 }
 
 ELFUTILS = "nativesdk-elfutils"
-DEPENDS += "nativesdk-gmp nativesdk-mpfr nativesdk-libmpc ${ELFUTILS} nativesdk-zlib"
+DEPENDS += "nativesdk-gmp nativesdk-mpfr nativesdk-libmpc ${ELFUTILS} nativesdk-zlib nativesdk-zstd"
 RDEPENDS:${PN} += "nativesdk-mpfr nativesdk-libmpc ${ELFUTILS}"
 
 SYSTEMHEADERS = "${target_includedir}/"
@@ -188,9 +191,6 @@ SYSTEMLIBS = "${target_base_libdir}/"
 SYSTEMLIBS1 = "${target_libdir}/"
 
 EXTRA_OECONF += "--enable-poison-system-directories"
-EXTRA_OECONF:remove:elf = "--with-sysroot=/not/exist"
-EXTRA_OECONF:remove:eabi = "--with-sysroot=/not/exist"
-EXTRA_OECONF:append:elf = " --without-headers --with-newlib"
-EXTRA_OECONF:append:eabi = " --without-headers --with-newlib"
+
 # gcc 4.7 needs -isystem
 export ARCH_FLAGS_FOR_TARGET = "--sysroot=${STAGING_DIR_TARGET} -isystem=${target_includedir}"

+ 0 - 4
recipes-devtools/gcc/gcc-cross-canadian_11.1.bb

@@ -1,4 +0,0 @@
-require recipes-devtools/gcc/gcc-${PV}.inc
-require gcc-cross-canadian.inc
-
-EXTRA_OECONF:append:riscv64 = " --with-arch=rv64gcbv --with-abi=lp64d CFLAGS_FOR_TARGET="-O2 -mcmodel=medany" CXXFLAGS_FOR_TARGET="-O2 -mcmodel=medany""

+ 5 - 0
recipes-devtools/gcc/gcc-cross-canadian_12.1.bb

@@ -0,0 +1,5 @@
+require recipes-devtools/gcc/gcc-${PV}.inc
+require gcc-cross-canadian.inc
+
+EXTRA_OECONF:append:riscv64 = " --with-arch=rv64gcb --with-abi=lp64d CFLAGS_FOR_TARGET="-O2 -mcmodel=medany -march=rv64gcb" CXXFLAGS_FOR_TARGET="-O2 -mcmodel=medany -march=rv64gcb" "
+#EXTRA_OECONF:append:riscv64 = " --with-arch=rv64gcb --with-abi=lp64d CFLAGS_FOR_TARGET="-O2 -mcmodel=medany" CXXFLAGS_FOR_TARGET="-O2 -mcmodel=medany""

+ 10 - 8
recipes-devtools/gcc/gcc-cross.inc

@@ -22,19 +22,20 @@ require gcc-configure-common.inc
 LINKER_HASH_STYLE ?= "sysv"
 
 EXTRA_OECONF += "--enable-poison-system-directories=error \
-    --with-host-libstdcxx='-static-libgcc -Wl,-Bstatic,-lstdc++,-Bdynamic -lm' \
-    --disable-libsanitizer \
-    --disable-plugin \
-    --enable-long-long \
-"
+		 --with-host-libstdcxx='-static-libgcc -Wl,-Bstatic,-lstdc++,-Bdynamic -lm' \
+		 --disable-libsanitizer \
+		 --disable-plugin \
+		 --enable-long-long \
+		 "
+
 EXTRA_OECONF:append:sh4 = " \
     --with-multilib-list= \
     --enable-incomplete-targets \
 "
 
-###EXTRA_OECONF += "
-###    --with-system-zlib
-###"
+EXTRA_OECONF += "\
+    --with-system-zlib \
+"
 
 EXTRA_OECONF:append:libc-baremetal = " --without-headers"
 EXTRA_OECONF:remove:libc-baremetal = "--enable-threads=posix"
@@ -154,6 +155,7 @@ do_gcc_stash_builddir () {
 	# Makefile does move-if-change which can end up with 'timestamp' as file contents so break links to those files
 	rm $dest/gcc/include/*.h
 	cp gcc/include/*.h $dest/gcc/include/
+	sysroot-relativelinks.py $dest
 }
 addtask do_gcc_stash_builddir after do_compile before do_install
 SSTATETASKS += "do_gcc_stash_builddir"

+ 0 - 4
recipes-devtools/gcc/gcc-cross_11.1.bb

@@ -1,4 +0,0 @@
-require recipes-devtools/gcc/gcc-${PV}.inc
-require gcc-cross.inc
-
-EXTRA_OECONF:append:riscv64 = " --with-arch=rv64gcbv --with-abi=lp64d CFLAGS_FOR_TARGET="-O2 -mcmodel=medany" CXXFLAGS_FOR_TARGET="-O2 -mcmodel=medany""

+ 5 - 0
recipes-devtools/gcc/gcc-cross_12.1.bb

@@ -0,0 +1,5 @@
+require recipes-devtools/gcc/gcc-${PV}.inc
+require gcc-cross.inc
+
+EXTRA_OECONF:append:riscv64 = " --with-arch=rv64gcb --with-abi=lp64d CFLAGS_FOR_TARGET="-O2 -mcmodel=medany -march=rv64gcb" CXXFLAGS_FOR_TARGET="-O2 -mcmodel=medany -march=rv64gcb" "
+#EXTRA_OECONF:append:riscv64 = " --with-arch=rv64gcb --with-abi=lp64d CFLAGS_FOR_TARGET="-O2 -mcmodel=medany" CXXFLAGS_FOR_TARGET="-O2 -mcmodel=medany""

+ 0 - 4
recipes-devtools/gcc/gcc-crosssdk_11.1.bb

@@ -1,4 +0,0 @@
-require recipes-devtools/gcc/gcc-cross_${PV}.bb
-require gcc-crosssdk.inc
-
-EXTRA_OECONF:append:riscv64 = " --with-arch=rv64gcbv --with-abi=lp64d CFLAGS_FOR_TARGET="-O2 -mcmodel=medany" CXXFLAGS_FOR_TARGET="-O2 -mcmodel=medany""

+ 5 - 0
recipes-devtools/gcc/gcc-crosssdk_12.1.bb

@@ -0,0 +1,5 @@
+require recipes-devtools/gcc/gcc-cross_${PV}.bb
+require gcc-crosssdk.inc
+
+EXTRA_OECONF:append:riscv64 = " --with-arch=rv64gcb --with-abi=lp64d CFLAGS_FOR_TARGET="-O2 -mcmodel=medany -march=rv64gcb" CXXFLAGS_FOR_TARGET="-O2 -mcmodel=medany -march=rv64gcb" "
+#EXTRA_OECONF:append:riscv64 = " --with-arch=rv64gcb --with-abi=lp64d CFLAGS_FOR_TARGET="-O2 -mcmodel=medany" CXXFLAGS_FOR_TARGET="-O2 -mcmodel=medany""

+ 23 - 9
recipes-devtools/gcc/gcc-multilib-config.inc

@@ -31,7 +31,9 @@ python gcc_multilib_setup() {
                 '%s/*/linux64.h' % src_conf_dir,
                 '%s/aarch64/t-aarch64' % src_conf_dir,
                 '%s/aarch64/aarch64.h' % src_conf_dir,
+                '%s/aarch64/aarch64-linux.h' % src_conf_dir,
                 '%s/aarch64/aarch64-cores.def' % src_conf_dir,
+                '%s/arm/linux-eabi.h' % src_conf_dir,
                 '%s/*/linux.h' % src_conf_dir,
                 '%s/linux.h' % src_conf_dir)
 
@@ -102,6 +104,8 @@ python gcc_multilib_setup() {
                         r'\1' + wrap_libdir(libdir64) + r'\3'),
                     (r'^(#define\s*GLIBC_DYNAMIC_LINKER64\s*\"\S+\"\s*)(\S+)(\s*\"\S+\"\s*)(\S+)(\s*\".*\")$',
                         r'\1' + wrap_libdir(libdir64) + r'\3' + wrap_libdir(libdir64) + r'\5'),
+                    (r'^(#define\s*GLIBC_DYNAMIC_LINKER\b\s*)(\S+)(\s*\".*\")$',
+                        r'\1' + wrap_libdir(libdir32) + r'\3'),
                     (r'^(#define\s*GLIBC_DYNAMIC_LINKERX32\s*)(\S+)(\s*\".*\")$',
                         r'\1' + wrap_libdir(libdirx32) + r'\3'),
                     (r'^(#define\s*GLIBC_DYNAMIC_LINKERN32\s*)(\S+)(\s*\".*\")$',
@@ -112,8 +116,18 @@ python gcc_multilib_setup() {
                         r'\1' + wrap_libdir(libdir64) + r'\3'),
                     (r'^(#define\s*UCLIBC_DYNAMIC_LINKERN32\s*)(\S+)(\s*\".*\")$',
                         r'\1' + wrap_libdir(libdirn32) + r'\3'),
+                    (r'^(#define\s*UCLIBC_DYNAMIC_LINKERX32\s*)(\S+)(\s*\".*\")$',
+                        r'\1' + wrap_libdir(libdirx32) + r'\3'),
                     (r'^(#define\s*UCLIBC_DYNAMIC_LINKER\b\s*)(\S+)(\s*\".*\")$',
                         r'\1' + wrap_libdir(libdir32) + r'\3'),
+                    (r'^(#define\s*MUSL_DYNAMIC_LINKER32\s*)(\S+)(\s*\".*\")$',
+                        r'\1' + wrap_libdir(libdir32) + r'\3'),
+                    (r'^(#define\s*MUSL_DYNAMIC_LINKER64\s*)(\S+)(\s*\".*\")$',
+                        r'\1' + wrap_libdir(libdir64) + r'\3'),
+                    (r'^(#define\s*MUSL_DYNAMIC_LINKERX32\s*)(\S+)(\s*\".*\")$',
+                        r'\1' + wrap_libdir(libdirx32) + r'\3'),
+                    (r'^(#define\s*MUSL_DYNAMIC_LINKER\b\s*)(\S+)(\s*\".*\")$',
+                        r'\1' + wrap_libdir(libdir32) + r'\3'),
                 ]
 
                 for (i, line) in enumerate(filelines):
@@ -138,15 +152,15 @@ python gcc_multilib_setup() {
     }
 
     gcc_header_config_files = {
-        'x86_64'    : ['gcc/config/i386/linux64.h'],
-        'i586'      : ['gcc/config/i386/linux64.h'],
-        'i686'      : ['gcc/config/i386/linux64.h'],
-        'mips'      : ['gcc/config/mips/linux.h', 'gcc/config/mips/linux64.h'],
-        'mips64'    : ['gcc/config/mips/linux.h', 'gcc/config/mips/linux64.h'],
-        'powerpc'   : ['gcc/config/rs6000/linux64.h'],
-        'powerpc64' : ['gcc/config/rs6000/linux64.h'],
-        'aarch64'   : ['gcc/config/aarch64/aarch64.h'],
-        'arm'       : ['gcc/config/aarch64/aarch64.h'],
+        'x86_64'    : ['gcc/config/linux.h', 'gcc/config/i386/linux.h', 'gcc/config/i386/linux64.h'],
+        'i586'      : ['gcc/config/linux.h', 'gcc/config/i386/linux.h', 'gcc/config/i386/linux64.h'],
+        'i686'      : ['gcc/config/linux.h', 'gcc/config/i386/linux64.h'],
+        'mips'      : ['gcc/config/linux.h', 'gcc/config/mips/linux.h', 'gcc/config/mips/linux64.h'],
+        'mips64'    : ['gcc/config/linux.h', 'gcc/config/mips/linux.h', 'gcc/config/mips/linux64.h'],
+        'powerpc'   : ['gcc/config/linux.h', 'gcc/config/rs6000/linux64.h'],
+        'powerpc64' : ['gcc/config/linux.h', 'gcc/config/rs6000/linux64.h'],
+        'aarch64'   : ['gcc/config/linux.h', 'gcc/config/aarch64/aarch64-linux.h', 'gcc/config/arm/linux-eabi.h'],
+        'arm'       : ['gcc/config/linux.h', 'gcc/config/aarch64/aarch64-linux.h', 'gcc/config/arm/linux-eabi.h'],
     }
 
     libdir32 = 'SYSTEMLIBS_DIR'

+ 10 - 19
recipes-devtools/gcc/gcc-runtime.inc

@@ -16,7 +16,8 @@ EXTRA_OECONF_PATHS = "\
 
 EXTRA_OECONF:append:linuxstdbase = " --enable-clocale=gnu"
 EXTRA_OECONF:append = " --cache-file=${B}/config.cache"
-EXTRA_OECONF:append:libc-newlib = " --with-newlib"
+EXTRA_OECONF:append:libc-newlib = " --with-newlib --with-target-subdir"
+EXTRA_OECONF:append:libc-baremetal = " --with-target-subdir"
 
 # Disable ifuncs for libatomic on arm conflicts -march/-mcpu
 EXTRA_OECONF:append:arm = " libat_cv_have_ifunc=no "
@@ -49,30 +50,20 @@ RUNTIMETARGET:libc-newlib = "libstdc++-v3"
 # libiberty
 # libgfortran needs separate recipe due to libquadmath dependency
 
-# Relative path to be repaced into debug info
-REL_S = "/usr/src/debug/${PN}/${EXTENDPE}${PV}-${PR}"
-
-DEBUG_PREFIX_MAP:class-target = " \
-   -fdebug-prefix-map=${WORKDIR}/recipe-sysroot= \
-   -fdebug-prefix-map=${WORKDIR}/recipe-sysroot-native= \
-   -fdebug-prefix-map=${S}=${REL_S} \
-   -fdebug-prefix-map=${S}/include=${REL_S}/libstdc++-v3/../include \
-   -fdebug-prefix-map=${S}/libiberty=${REL_S}/libstdc++-v3/../libiberty \
-   -fdebug-prefix-map=${S}/libgcc=${REL_S}/libstdc++-v3/../libgcc \
-   -fdebug-prefix-map=${B}=${REL_S} \
-   -ffile-prefix-map=${B}/${HOST_SYS}/libstdc++-v3/include=${includedir}/c++/${BINV} \
-   "
-
 do_configure () {
-	export CXX="${CXX} -nostdinc++ -nostdlib++"
+	export CXX="${CXX} -nostdinc++ -L${WORKDIR}/dummylib"
+	# libstdc++ isn't built yet so CXX would error not able to find it which breaks stdc++'s configure
+	# tests. Create a dummy empty lib for the purposes of configure.
+	mkdir -p ${WORKDIR}/dummylib
+	${CC} -x c /dev/null -c -o ${WORKDIR}/dummylib/dummylib.o
+	${AR} rcs ${WORKDIR}/dummylib/libstdc++.a ${WORKDIR}/dummylib/dummylib.o
 	for d in libgcc ${RUNTIMETARGET}; do
 		echo "Configuring $d"
 		rm -rf ${B}/${TARGET_SYS}/$d/
 		mkdir -p ${B}/${TARGET_SYS}/$d/
 		cd ${B}/${TARGET_SYS}/$d/
 		chmod a+x ${S}/$d/configure
-		relpath=${@os.path.relpath("${S}/$d", "${B}/${TARGET_SYS}/$d")}
-		$relpath/configure ${CONFIGUREOPTS} ${EXTRA_OECONF}
+		${S}/$d/configure ${CONFIGUREOPTS} ${EXTRA_OECONF}
 		if [ "$d" = "libgcc" ]; then
 			(cd ${B}/${TARGET_SYS}/libgcc; oe_runmake enable-execute-stack.c unwind.h md-unwind-support.h sfp-machine.h gthr-default.h)
 		fi
@@ -302,7 +293,7 @@ do_check() {
     export DEJAGNU="${WORKDIR}/dejagnu/site.exp"
 
     # HACK: this works around the configure setting CXX with -nostd* args
-    sed -i 's/-nostdinc++ -nostdlib++//g' $(find ${B} -name testsuite_flags | head -1)
+    sed -i 's#-nostdinc++ -L${WORKDIR}/dummylib##g' $(find ${B} -name testsuite_flags | head -1)
 
     if [ "${TOOLCHAIN_TEST_TARGET}" = "user" ]; then
         # qemu user has issues allocating large amounts of memory

+ 0 - 0
recipes-devtools/gcc/gcc-runtime_11.1.bb → recipes-devtools/gcc/gcc-runtime_12.1.bb


+ 3 - 1
recipes-devtools/gcc/gcc-sanitizers.inc

@@ -90,7 +90,9 @@ FILES:libasan-dev += "\
     ${libdir}/libhwasan.so \
     ${libdir}/libasan.la \
 "
-FILES:libasan-staticdev += "${libdir}/libasan.a"
+FILES:libasan-staticdev += "${libdir}/libasan.a \
+    ${libdir}/libhwasan.a \
+"
 
 FILES:libubsan += "${libdir}/libubsan.so.*"
 FILES:libubsan-dev += "\

+ 0 - 0
recipes-devtools/gcc/gcc-sanitizers_11.1.bb → recipes-devtools/gcc/gcc-sanitizers_12.1.bb


+ 1 - 0
recipes-devtools/gcc/gcc-source.inc

@@ -18,6 +18,7 @@ INHIBIT_DEFAULT_DEPS = "1"
 DEPENDS = ""
 PACKAGES = ""
 
+B = "${WORKDIR}/build"
 
 # This needs to be Python to avoid lots of shell variables becoming dependencies.
 python do_preconfigure () {

+ 0 - 6
recipes-devtools/gcc/gcc-source_11.1.bb

@@ -1,6 +0,0 @@
-require recipes-devtools/gcc/gcc-${PV}.inc
-require recipes-devtools/gcc/gcc-source.inc
-
-EXCLUDE_FROM_WORLD = "1"
-
-EXTRA_OECONF:append:riscv64 = " --with-arch=rv64gcbv --with-abi=lp64d CFLAGS_FOR_TARGET="-O2 -mcmodel=medany" CXXFLAGS_FOR_TARGET="-O2 -mcmodel=medany""

+ 7 - 0
recipes-devtools/gcc/gcc-source_12.1.bb

@@ -0,0 +1,7 @@
+require recipes-devtools/gcc/gcc-${PV}.inc
+require recipes-devtools/gcc/gcc-source.inc
+
+EXCLUDE_FROM_WORLD = "1"
+
+EXTRA_OECONF:append:riscv64 = " --with-arch=rv64gcb --with-abi=lp64d CFLAGS_FOR_TARGET="-O2 -mcmodel=medany -march=rv64gcb" CXXFLAGS_FOR_TARGET="-O2 -mcmodel=medany -march=rv64gcb" "
+#EXTRA_OECONF:append:riscv64 = " --with-arch=rv64gcb --with-abi=lp64d CFLAGS_FOR_TARGET="-O2 -mcmodel=medany" CXXFLAGS_FOR_TARGET="-O2 -mcmodel=medany""

+ 1 - 2
recipes-devtools/gcc/gcc-target.inc

@@ -44,7 +44,6 @@ FILES:${PN} = "\
     ${bindir}/${TARGET_PREFIX}gcc* \
     ${bindir}/${TARGET_PREFIX}lto* \
     ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/collect2* \
-    ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/cc1plus \
     ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/g++-mapper-server \
     ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/lto* \
     ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/lib*${SOLIBS} \
@@ -193,7 +192,7 @@ do_install () {
 	rm -f *c++*
 
 	# We don't care about the gcc-<version> ones for this
-	rm -f *gcc-?.?*
+	rm -f *gcc-?*.?*
 
 	# Not sure why we end up with these but we don't want them...
 	rm -f ${TARGET_PREFIX}${TARGET_PREFIX}*

+ 0 - 96
recipes-devtools/gcc/gcc/0001-Upstream-Status-Backport.patch

@@ -1,96 +0,0 @@
-From b93236bd8cd749196e787a9d36bcd09e673b3604 Mon Sep 17 00:00:00 2001
-From: Jun Yuan Tan <junyuan.tan@starfivetech.com>
-Date: Mon, 22 Nov 2021 00:13:28 +0800
-Subject: [PATCH 1/1] Upstream-Status: Backport Signed-off-by: Ross Burton
- <ross.burton@arm.com>
-
-From ad4c21f0f59b52357019148ec94d767aa2acd8f2 Mon Sep 17 00:00:00 2001
-From: Jonathan Wakely <jwakely@redhat.com>
-Date: Tue, 1 Jun 2021 11:00:16 +0100
-Subject: [PATCH] libstdc++: Fix installation of python hooks [PR 99453]
-
-When no shared library is installed, the new code to determine the name
-of the -gdb.py file yields an empty string. Use the name of the static
-library in that case.
-
-libstdc++-v3/ChangeLog:
-
-	PR libstdc++/99453
-	* python/Makefile.am: Use archive name for printer hook if no
-	dynamic library name is available.
-	* python/Makefile.in: Regenerate.
-
-(cherry picked from commit 9f7bc160b4a0f27dce248d1226e3ae7104b0e67b)
-
-Signed-off-by: Jun Yuan Tan <junyuan.tan@starfivetech.com>
----
- libstdc++-v3/python/Makefile.am | 24 ++++++++----------------
- libstdc++-v3/python/Makefile.in | 18 ++++++------------
- 2 files changed, 14 insertions(+), 28 deletions(-)
-
-diff --git a/libstdc++-v3/python/Makefile.am b/libstdc++-v3/python/Makefile.am
-index 01517a2a522..8efefa5725c 100644
---- a/libstdc++-v3/python/Makefile.am
-+++ b/libstdc++-v3/python/Makefile.am
-@@ -44,21 +44,13 @@ gdb.py: hook.in Makefile
- install-data-local: gdb.py
- 	@$(mkdir_p) $(DESTDIR)$(toolexeclibdir)
- ## We want to install gdb.py as SOMETHING-gdb.py.  SOMETHING is the
--## full name of the final library.  We want to ignore symlinks, the
--## .la file, and any previous -gdb.py file.  This is inherently
--## fragile, but there does not seem to be a better option, because
--## libtool hides the real names from us.
--	@here=`pwd`; cd $(DESTDIR)$(toolexeclibdir); \
--	  for file in libstdc++.*; do \
--	    case $$file in \
--	      *-gdb.py) ;; \
--	      *.la) ;; \
--	      *) if test -h $$file; then \
--	           continue; \
--	         fi; \
--	         libname=$$file;; \
--	    esac; \
--	  done; \
--	cd $$here; \
-+## full name of the final library.  We use the libtool .la file to get
-+## the correct name.
-+	@libname=`sed -ne "/^library_names=/{s/.*='//;s/'$$//;s/ .*//;p;}" \
-+	          $(DESTDIR)$(toolexeclibdir)/libstdc++.la`; \
-+	if [ -z "$$libname" ]; then \
-+	  libname=`sed -ne "/^old_library=/{s/.*='//;s/'$$//;s/ .*//;p;}" \
-+		  $(DESTDIR)$(toolexeclibdir)/libstdc++.la`; \
-+	fi; \
- 	echo " $(INSTALL_DATA) gdb.py $(DESTDIR)$(toolexeclibdir)/$$libname-gdb.py"; \
- 	$(INSTALL_DATA) gdb.py $(DESTDIR)$(toolexeclibdir)/$$libname-gdb.py
-diff --git a/libstdc++-v3/python/Makefile.in b/libstdc++-v3/python/Makefile.in
-index c35dbe55961..9904a9197de 100644
---- a/libstdc++-v3/python/Makefile.in
-+++ b/libstdc++-v3/python/Makefile.in
-@@ -607,18 +607,12 @@ gdb.py: hook.in Makefile
- 
- install-data-local: gdb.py
- 	@$(mkdir_p) $(DESTDIR)$(toolexeclibdir)
--	@here=`pwd`; cd $(DESTDIR)$(toolexeclibdir); \
--	  for file in libstdc++.*; do \
--	    case $$file in \
--	      *-gdb.py) ;; \
--	      *.la) ;; \
--	      *) if test -h $$file; then \
--	           continue; \
--	         fi; \
--	         libname=$$file;; \
--	    esac; \
--	  done; \
--	cd $$here; \
-+	@libname=`sed -ne "/^library_names=/{s/.*='//;s/'$$//;s/ .*//;p;}" \
-+	          $(DESTDIR)$(toolexeclibdir)/libstdc++.la`; \
-+	if [ -z "$$libname" ]; then \
-+	  libname=`sed -ne "/^old_library=/{s/.*='//;s/'$$//;s/ .*//;p;}" \
-+		  $(DESTDIR)$(toolexeclibdir)/libstdc++.la`; \
-+	fi; \
- 	echo " $(INSTALL_DATA) gdb.py $(DESTDIR)$(toolexeclibdir)/$$libname-gdb.py"; \
- 	$(INSTALL_DATA) gdb.py $(DESTDIR)$(toolexeclibdir)/$$libname-gdb.py
- 
--- 
-2.33.1
-

+ 0 - 25
recipes-devtools/gcc/gcc/0001-Yocto-patch-for-arch-canonicalize-to-use-python3.patch

@@ -1,25 +0,0 @@
-From 32ad3862042b90805f402ee4a1615d5e68502c5b Mon Sep 17 00:00:00 2001
-From: Jun Yuan Tan <junyuan.tan@starfivetech.com>
-Date: Fri, 12 Nov 2021 12:38:34 +0800
-Subject: [PATCH 1/2] Yocto patch for arch-canonicalize to use python3
-
-This patch is required for Yocto to build properly
-
-Signed-off-by: Jun Yuan Tan <junyuan.tan@starfivetech.com>
----
- gcc/config/riscv/arch-canonicalize | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize
-index ea95a0693f3..fab933f8af1 100755
---- a/gcc/config/riscv/arch-canonicalize
-+++ b/gcc/config/riscv/arch-canonicalize
-@@ -1,4 +1,4 @@
--#!/usr/bin/env python
-+#!/usr/bin/env python3
- 
- # Tool for canonical RISC-V architecture string.
- # Copyright (C) 2011-2021 Free Software Foundation, Inc.
--- 
-2.33.1
-

+ 5 - 5
recipes-devtools/gcc/gcc/0001-gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch

@@ -1,4 +1,4 @@
-From 368eaf1846733a9920c7cf5bc547a377e7167785 Mon Sep 17 00:00:00 2001
+From 31f94ef5b43a984a98f0eebd2dcf1b53aa1d7bce Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Fri, 29 Mar 2013 08:37:11 +0400
 Subject: [PATCH] gcc-4.3.1: ARCH_FLAGS_FOR_TARGET
@@ -12,10 +12,10 @@ Upstream-Status: Inappropriate [embedded specific]
  2 files changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/configure b/configure
-index 504f6410274..bcebad264ec 100755
+index 5dcaab14ae9..f76310a36bb 100755
 --- a/configure
 +++ b/configure
-@@ -9728,7 +9728,7 @@ fi
+@@ -10165,7 +10165,7 @@ fi
  # for target_alias and gcc doesn't manage it consistently.
  target_configargs="--cache-file=./config.cache ${target_configargs}"
  
@@ -25,10 +25,10 @@ index 504f6410274..bcebad264ec 100755
   *" newlib "*)
    case " $target_configargs " in
 diff --git a/configure.ac b/configure.ac
-index 088e735c5db..1289fe08760 100644
+index 85977482aee..8b9097c7a45 100644
 --- a/configure.ac
 +++ b/configure.ac
-@@ -3240,7 +3240,7 @@ fi
+@@ -3346,7 +3346,7 @@ fi
  # for target_alias and gcc doesn't manage it consistently.
  target_configargs="--cache-file=./config.cache ${target_configargs}"
  

+ 45 - 0
recipes-devtools/gcc/gcc/0001-libsanitizer-cherry-pick-9cf13067cb5088626ba7-from-u.patch

@@ -0,0 +1,45 @@
+From 2701442d0cf6292f6624443c15813d6d1a3562fe Mon Sep 17 00:00:00 2001
+From: Martin Liska <mliska@suse.cz>
+Date: Mon, 11 Jul 2022 22:03:14 +0200
+Subject: [PATCH] libsanitizer: cherry-pick 9cf13067cb5088626ba7 from upstream
+
+9cf13067cb5088626ba7ee1ec4c42ec59c7995a0 [sanitizer] Remove #include <linux/fs.h> to resolve fsconfig_command/mount_attr conflict with glibc 2.36
+
+Upstream-Status: Backport [https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=2701442d0cf6292f6624443c15813d6d1a3562fe]
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ .../sanitizer_platform_limits_posix.cpp                | 10 ++++++----
+ 1 file changed, 6 insertions(+), 4 deletions(-)
+
+diff --git a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
+index 8ed3e92d270..97fd07acf9d 100644
+--- a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
++++ b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp
+@@ -73,7 +73,9 @@
+ #include <sys/vt.h>
+ #include <linux/cdrom.h>
+ #include <linux/fd.h>
++#if SANITIZER_ANDROID
+ #include <linux/fs.h>
++#endif
+ #include <linux/hdreg.h>
+ #include <linux/input.h>
+ #include <linux/ioctl.h>
+@@ -869,10 +871,10 @@ unsigned struct_ElfW_Phdr_sz = sizeof(Elf_Phdr);
+   unsigned IOCTL_EVIOCGPROP = IOCTL_NOT_PRESENT;
+   unsigned IOCTL_EVIOCSKEYCODE_V2 = IOCTL_NOT_PRESENT;
+ #endif
+-  unsigned IOCTL_FS_IOC_GETFLAGS = FS_IOC_GETFLAGS;
+-  unsigned IOCTL_FS_IOC_GETVERSION = FS_IOC_GETVERSION;
+-  unsigned IOCTL_FS_IOC_SETFLAGS = FS_IOC_SETFLAGS;
+-  unsigned IOCTL_FS_IOC_SETVERSION = FS_IOC_SETVERSION;
++  unsigned IOCTL_FS_IOC_GETFLAGS = _IOR('f', 1, long);
++  unsigned IOCTL_FS_IOC_GETVERSION = _IOR('v', 1, long);
++  unsigned IOCTL_FS_IOC_SETFLAGS = _IOW('f', 2, long);
++  unsigned IOCTL_FS_IOC_SETVERSION = _IOW('v', 2, long);
+   unsigned IOCTL_GIO_CMAP = GIO_CMAP;
+   unsigned IOCTL_GIO_FONT = GIO_FONT;
+   unsigned IOCTL_GIO_UNIMAP = GIO_UNIMAP;
+-- 
+2.37.1
+

+ 22 - 12
recipes-devtools/gcc/gcc/0033-merge-Kito-Cheng-s-patch-Handle-different-sigcontext.patch → recipes-devtools/gcc/gcc/0001-merge-Kito-Cheng-s-patch-Handle-different-sigcontext.patch

@@ -1,17 +1,23 @@
-From 5771cefd7b63e8d80fc010eb691f5676bce68f72 Mon Sep 17 00:00:00 2001
+From 1d04f60838519cdb685c293dbd2fb6c63e64c091 Mon Sep 17 00:00:00 2001
 From: "max.ma" <max.ma@starfivetech.com>
 Date: Wed, 16 Feb 2022 20:09:03 -0800
-Subject: [PATCH 33/33] merge Kito Cheng's patch "Handle different sigcontext
+Subject: [PATCH 01/11] merge Kito Cheng's patch "Handle different sigcontext
  struct layout"
 
 ---
- libgcc/config/riscv/linux-unwind.h | 27 +++++++++++++++++++++++++--
- 1 file changed, 25 insertions(+), 2 deletions(-)
+ libgcc/config/riscv/linux-unwind.h | 31 +++++++++++++++++++++++++++---
+ 1 file changed, 28 insertions(+), 3 deletions(-)
 
 diff --git a/libgcc/config/riscv/linux-unwind.h b/libgcc/config/riscv/linux-unwind.h
-index 0710bdad1a7..3dc488acf9b 100644
+index c86df2f85bc..0c3f8cf888c 100644
 --- a/libgcc/config/riscv/linux-unwind.h
 +++ b/libgcc/config/riscv/linux-unwind.h
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2016-2022 Free Software Foundation, Inc.
++/* Copyright (C) 2016-2021 Free Software Foundation, Inc.
+ 
+    This file is free software; you can redistribute it and/or modify it
+    under the terms of the GNU General Public License as published by the
 @@ -29,6 +29,25 @@
  #define ECALL    0x00000073
  
@@ -38,20 +44,25 @@ index 0710bdad1a7..3dc488acf9b 100644
  
  static _Unwind_Reason_Code
  riscv_fallback_frame_state (struct _Unwind_Context *context,
-@@ -51,6 +70,8 @@ riscv_fallback_frame_state (struct _Unwind_Context *context,
+@@ -50,6 +69,9 @@ riscv_fallback_frame_state (struct _Unwind_Context *context,
+   uint16_t *pc = context->ra;
    struct sigcontext *sc;
    int i;
-   _Unwind_Ptr reg_ptr;
++  _Unwind_Ptr reg_ptr;
 +  /* Get regsister offest from register size.  */
 +  _Unwind_Ptr reg_offset = __riscv_xlen / 8;
  
    /* A signal frame will have a return address pointing to
       __default_sa_restorer. This code is hardwired as:
-@@ -76,16 +97,18 @@ riscv_fallback_frame_state (struct _Unwind_Context *context,
+@@ -71,19 +93,22 @@ riscv_fallback_frame_state (struct _Unwind_Context *context,
+   fs->regs.cfa_reg = __LIBGCC_STACK_POINTER_REGNUM__;
+   fs->regs.cfa_offset = new_cfa - (_Unwind_Ptr) context->cfa;
+ 
++  reg_ptr = (_Unwind_Ptr) &sc->sc_regs.pc;
    for (i = 0; i < 32; i++)
      {
        fs->regs.reg[i].how = REG_SAVED_OFFSET;
--      fs->regs.reg[i].loc.offset = (_Unwind_Ptr) (reg_ptr + i) - new_cfa;
+-      fs->regs.reg[i].loc.offset = (_Unwind_Ptr) &sc->gregs[i] - new_cfa;
 +      fs->regs.reg[i].loc.offset = 
 +        (_Unwind_Ptr) &SIGCONTEXT_PC (sc) + (i * reg_offset) - new_cfa;     
      }
@@ -60,7 +71,7 @@ index 0710bdad1a7..3dc488acf9b 100644
    fs->retaddr_column = __LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__;
    fs->regs.reg[fs->retaddr_column].how = REG_SAVED_VAL_OFFSET;
    fs->regs.reg[fs->retaddr_column].loc.offset =
--    (_Unwind_Ptr) sc->sc_regs.pc - new_cfa;
+-    (_Unwind_Ptr) sc->gregs[0] - new_cfa;
 +    (_Unwind_Ptr) SIGCONTEXT_PC (sc) - new_cfa;
  
    return _URC_NO_REASON;
@@ -68,7 +79,6 @@ index 0710bdad1a7..3dc488acf9b 100644
  
 +#undef SIGCONTEXT_PC
  #endif
-\ No newline at end of file
 -- 
-2.33.1
+2.25.1
 

+ 0 - 73
recipes-devtools/gcc/gcc/0001-testuite-Check-pthread-for-omp-module-testing.patch

@@ -1,73 +0,0 @@
-From c108c54011f6256806d4fe1a653e631fa66dba51 Mon Sep 17 00:00:00 2001
-From: Kito Cheng <kito.cheng@sifive.com>
-Date: Wed, 19 May 2021 18:06:27 +0800
-Subject: [PATCH 01/15] testuite: Check pthread for omp module testing
-
-gcc/testsuite/ChangeLog:
-
-	* g++.dg/modules/omp-1_a.C: Check pthread is available.
-	* g++.dg/modules/omp-1_b.C: Ditto.
-	* g++.dg/modules/omp-1_c.C: Ditto.
-	* g++.dg/modules/omp-2_a.C: Ditto.
-	* g++.dg/modules/omp-2_b.C: Ditto.
----
- gcc/testsuite/g++.dg/modules/omp-1_a.C | 1 +
- gcc/testsuite/g++.dg/modules/omp-1_b.C | 1 +
- gcc/testsuite/g++.dg/modules/omp-1_c.C | 1 +
- gcc/testsuite/g++.dg/modules/omp-2_a.C | 1 +
- gcc/testsuite/g++.dg/modules/omp-2_b.C | 1 +
- 5 files changed, 5 insertions(+)
-
-diff --git a/gcc/testsuite/g++.dg/modules/omp-1_a.C b/gcc/testsuite/g++.dg/modules/omp-1_a.C
-index 722720a0e93..94e1171f03c 100644
---- a/gcc/testsuite/g++.dg/modules/omp-1_a.C
-+++ b/gcc/testsuite/g++.dg/modules/omp-1_a.C
-@@ -1,4 +1,5 @@
- // { dg-additional-options "-fmodules-ts -fopenmp" }
-+// { dg-require-effective-target pthread }
- 
- export module foo;
- // { dg-module-cmi foo }
-diff --git a/gcc/testsuite/g++.dg/modules/omp-1_b.C b/gcc/testsuite/g++.dg/modules/omp-1_b.C
-index f3f5d92e517..09d97e4ac4e 100644
---- a/gcc/testsuite/g++.dg/modules/omp-1_b.C
-+++ b/gcc/testsuite/g++.dg/modules/omp-1_b.C
-@@ -1,4 +1,5 @@
- // { dg-additional-options "-fmodules-ts -fopenmp" }
-+// { dg-require-effective-target pthread }
- 
- import foo;
- 
-diff --git a/gcc/testsuite/g++.dg/modules/omp-1_c.C b/gcc/testsuite/g++.dg/modules/omp-1_c.C
-index f30f6115277..599a5a5d34f 100644
---- a/gcc/testsuite/g++.dg/modules/omp-1_c.C
-+++ b/gcc/testsuite/g++.dg/modules/omp-1_c.C
-@@ -1,4 +1,5 @@
- // { dg-additional-options "-fmodules-ts" }
-+// { dg-require-effective-target pthread }
- 
- import foo;
- 
-diff --git a/gcc/testsuite/g++.dg/modules/omp-2_a.C b/gcc/testsuite/g++.dg/modules/omp-2_a.C
-index d2291b6bbe0..b0d4bbc6e8a 100644
---- a/gcc/testsuite/g++.dg/modules/omp-2_a.C
-+++ b/gcc/testsuite/g++.dg/modules/omp-2_a.C
-@@ -1,4 +1,5 @@
- // { dg-additional-options "-fmodules-ts -fopenmp" }
-+// { dg-require-effective-target pthread }
- 
- export module foo;
- // { dg-module-cmi foo }
-diff --git a/gcc/testsuite/g++.dg/modules/omp-2_b.C b/gcc/testsuite/g++.dg/modules/omp-2_b.C
-index 39f34c70275..aeee4d1561a 100644
---- a/gcc/testsuite/g++.dg/modules/omp-2_b.C
-+++ b/gcc/testsuite/g++.dg/modules/omp-2_b.C
-@@ -1,4 +1,5 @@
- // { dg-additional-options "-fmodules-ts" }
-+// { dg-require-effective-target pthread }
- 
- import foo;
- 
--- 
-2.33.1
-

+ 0 - 31
recipes-devtools/gcc/gcc/0002-Fix-a-test-failure-in-g-.dg-modules-omp-1_c.C.patch

@@ -1,31 +0,0 @@
-From 9d923e3f7aff2107743bdd70d0cf04b969e1b1a1 Mon Sep 17 00:00:00 2001
-From: Bernd Edlinger <bernd.edlinger@hotmail.de>
-Date: Thu, 20 May 2021 20:19:43 +0200
-Subject: [PATCH 02/15] Fix a test failure in g++.dg/modules/omp-1_c.C
-
-Adjust the line number due to previous commit,
-which added a line for dg-require-effective-target.
-
-2021-05-20  Bernd Edlinger  <bernd.edlinger@hotmail.de>
-
-	* g++.dg/modules/omp-1_c.C: Fix testcase.
----
- gcc/testsuite/g++.dg/modules/omp-1_c.C | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/gcc/testsuite/g++.dg/modules/omp-1_c.C b/gcc/testsuite/g++.dg/modules/omp-1_c.C
-index 599a5a5d34f..71a24f6c8ef 100644
---- a/gcc/testsuite/g++.dg/modules/omp-1_c.C
-+++ b/gcc/testsuite/g++.dg/modules/omp-1_c.C
-@@ -3,7 +3,7 @@
- 
- import foo;
- 
--// { dg-regexp "In module imported at \[^\n]*omp-1_c.C:3:1:\nfoo: error: module contains OpenMP, use '-fopenmp' to enable\n" }
-+// { dg-regexp "In module imported at \[^\n]*omp-1_c.C:4:1:\nfoo: error: module contains OpenMP, use '-fopenmp' to enable\n" }
- // { dg-prune-output "failed to read" }
- // { dg-prune-output "fatal error:" }
- // { dg-prune-output "compilation terminated" }
--- 
-2.33.1
-

+ 27 - 27
recipes-devtools/gcc/gcc/0002-gcc-poison-system-directories.patch

@@ -1,4 +1,4 @@
-From 118c6f054711d437167ff125a88c9236bfc8099c Mon Sep 17 00:00:00 2001
+From e1dbdcd0ea667bab4b551294354e04c6fe288ab6 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Mon, 8 Mar 2021 16:04:20 -0800
 Subject: [PATCH] gcc: poison-system-directories
@@ -20,15 +20,15 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  gcc/configure       | 19 +++++++++++++++++++
  gcc/configure.ac    | 16 ++++++++++++++++
  gcc/doc/invoke.texi |  9 +++++++++
- gcc/gcc.c           |  9 +++++++--
- gcc/incpath.c       | 21 +++++++++++++++++++++
+ gcc/gcc.cc          |  9 +++++++--
+ gcc/incpath.cc      | 21 +++++++++++++++++++++
  7 files changed, 86 insertions(+), 2 deletions(-)
 
 diff --git a/gcc/common.opt b/gcc/common.opt
-index c75dd36843e..49acbd6ed44 100644
+index 8a0dafc522d..0357868e22c 100644
 --- a/gcc/common.opt
 +++ b/gcc/common.opt
-@@ -683,6 +683,10 @@ Wreturn-local-addr
+@@ -710,6 +710,10 @@ Wreturn-local-addr
  Common Var(warn_return_local_addr) Init(1) Warning
  Warn about returning a pointer/reference to a local or temporary variable.
  
@@ -40,10 +40,10 @@ index c75dd36843e..49acbd6ed44 100644
  Common Var(warn_shadow) Warning
  Warn when one variable shadows another.  Same as -Wshadow=global.
 diff --git a/gcc/config.in b/gcc/config.in
-index 10a13cde586..8848284da41 100644
+index 64c27c9cfac..a693cb8a886 100644
 --- a/gcc/config.in
 +++ b/gcc/config.in
-@@ -218,6 +218,16 @@
+@@ -230,6 +230,16 @@
  #endif
  
  
@@ -61,10 +61,10 @@ index 10a13cde586..8848284da41 100644
     optimizer and back end) to be checked for dynamic type safety at runtime.
     This is quite expensive. */
 diff --git a/gcc/configure b/gcc/configure
-index 9bb436ce7bd..3f0734bff11 100755
+index 5ce0557719a..dc2d59701ad 100755
 --- a/gcc/configure
 +++ b/gcc/configure
-@@ -1020,6 +1020,7 @@ enable_maintainer_mode
+@@ -1023,6 +1023,7 @@ enable_maintainer_mode
  enable_link_mutex
  enable_link_serialization
  enable_version_specific_runtime_libs
@@ -72,7 +72,7 @@ index 9bb436ce7bd..3f0734bff11 100755
  enable_plugin
  enable_host_shared
  enable_libquadmath_support
-@@ -1782,6 +1783,8 @@ Optional Features:
+@@ -1785,6 +1786,8 @@ Optional Features:
    --enable-version-specific-runtime-libs
                            specify that runtime libraries should be installed
                            in a compiler-specific directory
@@ -81,7 +81,7 @@ index 9bb436ce7bd..3f0734bff11 100755
    --enable-plugin         enable plugin support
    --enable-host-shared    build host code as shared libraries
    --disable-libquadmath-support
-@@ -31325,6 +31328,22 @@ if test "${enable_version_specific_runtime_libs+set}" = set; then :
+@@ -31982,6 +31985,22 @@ if test "${enable_version_specific_runtime_libs+set}" = set; then :
  fi
  
  
@@ -105,10 +105,10 @@ index 9bb436ce7bd..3f0734bff11 100755
  
  
 diff --git a/gcc/configure.ac b/gcc/configure.ac
-index caa611933df..54e21764b3e 100644
+index 23bee7010a3..36ce78924de 100644
 --- a/gcc/configure.ac
 +++ b/gcc/configure.ac
-@@ -7123,6 +7123,22 @@ AC_ARG_ENABLE(version-specific-runtime-libs,
+@@ -7421,6 +7421,22 @@ AC_ARG_ENABLE(version-specific-runtime-libs,
                  [specify that runtime libraries should be
                   installed in a compiler-specific directory])])
  
@@ -132,10 +132,10 @@ index caa611933df..54e21764b3e 100644
  AC_SUBST(subdirs)
  AC_SUBST(srcdir)
 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
-index 7a368959e5e..6659a903bf0 100644
+index 07b440190c3..b2de464798a 100644
 --- a/gcc/doc/invoke.texi
 +++ b/gcc/doc/invoke.texi
-@@ -369,6 +369,7 @@ Objective-C and Objective-C++ Dialects}.
+@@ -379,6 +379,7 @@ Objective-C and Objective-C++ Dialects}.
  -Wpacked  -Wno-packed-bitfield-compat  -Wpacked-not-aligned  -Wpadded @gol
  -Wparentheses  -Wno-pedantic-ms-format @gol
  -Wpointer-arith  -Wno-pointer-compare  -Wno-pointer-to-int-cast @gol
@@ -143,7 +143,7 @@ index 7a368959e5e..6659a903bf0 100644
  -Wno-pragmas  -Wno-prio-ctor-dtor  -Wredundant-decls @gol
  -Wrestrict  -Wno-return-local-addr  -Wreturn-type @gol
  -Wno-scalar-storage-order  -Wsequence-point @gol
-@@ -7735,6 +7736,14 @@ made up of data only and thus requires no special treatment.  But, for
+@@ -8029,6 +8030,14 @@ made up of data only and thus requires no special treatment.  But, for
  most targets, it is made up of code and thus requires the stack to be
  made executable in order for the program to work properly.
  
@@ -158,11 +158,11 @@ index 7a368959e5e..6659a903bf0 100644
  @item -Wfloat-equal
  @opindex Wfloat-equal
  @opindex Wno-float-equal
-diff --git a/gcc/gcc.c b/gcc/gcc.c
-index 7837553958b..19c75b6e20d 100644
---- a/gcc/gcc.c
-+++ b/gcc/gcc.c
-@@ -1152,6 +1152,8 @@ proper position among the other output files.  */
+diff --git a/gcc/gcc.cc b/gcc/gcc.cc
+index bb07cc244e3..ce161d3c853 100644
+--- a/gcc/gcc.cc
++++ b/gcc/gcc.cc
+@@ -1159,6 +1159,8 @@ proper position among the other output files.  */
     "%{fuse-ld=*:-fuse-ld=%*} " LINK_COMPRESS_DEBUG_SPEC \
     "%X %{o*} %{e*} %{N} %{n} %{r}\
      %{s} %{t} %{u*} %{z} %{Z} %{!nostdlib:%{!r:%{!nostartfiles:%S}}} \
@@ -171,7 +171,7 @@ index 7837553958b..19c75b6e20d 100644
      %{static|no-pie|static-pie:} %@{L*} %(mfwrap) %(link_libgcc) " \
      VTABLE_VERIFICATION_SPEC " " SANITIZER_EARLY_SPEC " %o "" \
      %{fopenacc|fopenmp|%:gt(%{ftree-parallelize-loops=*:%*} 1):\
-@@ -1247,8 +1249,11 @@ static const char *cpp_unique_options =
+@@ -1254,8 +1256,11 @@ static const char *cpp_unique_options =
  static const char *cpp_options =
  "%(cpp_unique_options) %1 %{m*} %{std*&ansi&trigraphs} %{W*&pedantic*} %{w}\
   %{f*} %{g*:%{%:debug-level-gt(0):%{g*}\
@@ -185,10 +185,10 @@ index 7837553958b..19c75b6e20d 100644
  
  /* Pass -d* flags, possibly modifying -dumpdir, -dumpbase et al.
  
-diff --git a/gcc/incpath.c b/gcc/incpath.c
-index 446d280321d..fbfc0ce03b8 100644
---- a/gcc/incpath.c
-+++ b/gcc/incpath.c
+diff --git a/gcc/incpath.cc b/gcc/incpath.cc
+index bd2a97938eb..c80f100f476 100644
+--- a/gcc/incpath.cc
++++ b/gcc/incpath.cc
 @@ -26,6 +26,7 @@
  #include "intl.h"
  #include "incpath.h"
@@ -197,7 +197,7 @@ index 446d280321d..fbfc0ce03b8 100644
  
  /* Microsoft Windows does not natively support inodes.
     VMS has non-numeric inodes.  */
-@@ -395,6 +396,26 @@ merge_include_chains (const char *sysroot, cpp_reader *pfile, int verbose)
+@@ -399,6 +400,26 @@ merge_include_chains (const char *sysroot, cpp_reader *pfile, int verbose)
  	}
        fprintf (stderr, _("End of search list.\n"));
      }

+ 60 - 0
recipes-devtools/gcc/gcc/0002-set-c-default-standard-to-c-14.patch

@@ -0,0 +1,60 @@
+From 5fb88421181bac4a3cf160f9b52258f23c06dd05 Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Wed, 6 Jul 2022 19:26:53 -0700
+Subject: [PATCH 02/11] set c++ default standard to c++14
+
+---
+ gcc/doc/invoke.texi                   | 2 +-
+ gcc/doc/standards.texi                | 2 +-
+ gcc/testsuite/lib/target-supports.exp | 2 +-
+ 3 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
+index 07b440190c3..490287b85d1 100644
+--- a/gcc/doc/invoke.texi
++++ b/gcc/doc/invoke.texi
+@@ -2446,6 +2446,7 @@ The name @samp{c++1y} is deprecated.
+ @item gnu++14
+ @itemx gnu++1y
+ GNU dialect of @option{-std=c++14}.
++This is the default for C++ code.
+ The name @samp{gnu++1y} is deprecated.
+ 
+ @item c++17
+@@ -2456,7 +2457,6 @@ The name @samp{c++1z} is deprecated.
+ @item gnu++17
+ @itemx gnu++1z
+ GNU dialect of @option{-std=c++17}.
+-This is the default for C++ code.
+ The name @samp{gnu++1z} is deprecated.
+ 
+ @item c++20
+diff --git a/gcc/doc/standards.texi b/gcc/doc/standards.texi
+index f878615ca30..fd6d270a567 100644
+--- a/gcc/doc/standards.texi
++++ b/gcc/doc/standards.texi
+@@ -254,7 +254,7 @@ select an extended version of the C++ language explicitly with
+ @option{-std=gnu++20} (for C++20 with GNU extensions).
+ 
+ The default, if
+-no C++ language dialect options are given, is @option{-std=gnu++17}.
++no C++ language dialect options are given, is @option{-std=gnu++14}.
+ 
+ @section Objective-C and Objective-C++ Languages
+ @cindex Objective-C
+diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
+index 2d5d0539bb4..f59ef570aa5 100644
+--- a/gcc/testsuite/lib/target-supports.exp
++++ b/gcc/testsuite/lib/target-supports.exp
+@@ -10153,7 +10153,7 @@ proc check_effective_target_c++ { } {
+  return 0
+ }
+ 
+-set cxx_default "c++17"
++set cxx_default "c++14"
+ # Check whether the current active language standard supports the features
+ # of C++11/C++14 by checking for the presence of one of the -std flags.
+ # This assumes that the default for the compiler is $cxx_default, and that
+-- 
+2.25.1
+

+ 27 - 9
recipes-devtools/gcc/gcc/0004-64-bit-multilib-hack.patch → recipes-devtools/gcc/gcc/0003-64-bit-multilib-hack.patch

@@ -1,4 +1,4 @@
-From 28e7c312b1292ca216d4b54ec9f6b7ac055907a8 Mon Sep 17 00:00:00 2001
+From 34b861e7a4cfd7b1f0d2c0f8cf9bb0b0b81eb61a Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Fri, 29 Mar 2013 09:10:06 +0400
 Subject: [PATCH] 64-bit multilib hack.
@@ -19,25 +19,27 @@ and be able to patch these entries with a complete set of correct paths but this
 don't have such code at this point. This is something the target gcc recipe should do
 and override these platform defaults in its build config.
 
-Do same for riscv64 and aarch64
+Do same for riscv64, aarch64 & arc
 
 RP 15/8/11
 
-Upstream-Status: Inappropriate[OE-Specific]
+Upstream-Status: Inappropriate [OE-Specific]
 
 Signed-off-by: Khem Raj <raj.khem@gmail.com>
 Signed-off-by: Elvis Dowson <elvis.dowson@gmail.com>
 Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
 ---
  gcc/config/aarch64/t-aarch64-linux |  8 ++++----
+ gcc/config/arc/t-multilib-linux    |  4 ++--
  gcc/config/i386/t-linux64          |  6 ++----
  gcc/config/mips/t-linux64          | 10 +++-------
  gcc/config/riscv/t-linux           |  6 ++++--
  gcc/config/rs6000/t-linux64        |  5 ++---
- 5 files changed, 15 insertions(+), 20 deletions(-)
+ 6 files changed, 17 insertions(+), 22 deletions(-)
 
 diff --git a/gcc/config/aarch64/t-aarch64-linux b/gcc/config/aarch64/t-aarch64-linux
-index 241b0ef20b6..a7dadb2d64f 100644
+index d0cd546002a..f4056d68372 100644
 --- a/gcc/config/aarch64/t-aarch64-linux
 +++ b/gcc/config/aarch64/t-aarch64-linux
 @@ -21,8 +21,8 @@
@@ -53,8 +55,24 @@ index 241b0ef20b6..a7dadb2d64f 100644
  
 -MULTILIB_OSDIRNAMES += mabi.ilp32=../libilp32$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu_ilp32)
 +#MULTILIB_OSDIRNAMES += mabi.ilp32=../libilp32$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu_ilp32)
+diff --git a/gcc/config/arc/t-multilib-linux b/gcc/config/arc/t-multilib-linux
+index ecb9ae6859f..12a164028d4 100644
+--- a/gcc/config/arc/t-multilib-linux
++++ b/gcc/config/arc/t-multilib-linux
+@@ -16,9 +16,9 @@
+ # along with GCC; see the file COPYING3.  If not see
+ # <http://www.gnu.org/licenses/>.
+ 
+-MULTILIB_OPTIONS = mcpu=hs/mcpu=archs/mcpu=hs38/mcpu=hs38_linux/mcpu=arc700/mcpu=nps400
++#MULTILIB_OPTIONS = mcpu=hs/mcpu=archs/mcpu=hs38/mcpu=hs38_linux/mcpu=arc700/mcpu=nps400
+ 
+-MULTILIB_DIRNAMES = hs archs hs38 hs38_linux arc700 nps400
++#MULTILIB_DIRNAMES = hs archs hs38 hs38_linux arc700 nps400
+ 
+ # Aliases:
+ MULTILIB_MATCHES += mcpu?arc700=mA7
 diff --git a/gcc/config/i386/t-linux64 b/gcc/config/i386/t-linux64
-index d288b093522..7b5980a9d21 100644
+index 5526ad0e6cc..fa51c88912b 100644
 --- a/gcc/config/i386/t-linux64
 +++ b/gcc/config/i386/t-linux64
 @@ -32,7 +32,5 @@
@@ -68,7 +86,7 @@ index d288b093522..7b5980a9d21 100644
 +MULTILIB_DIRNAMES = . .
 +MULTILIB_OSDIRNAMES = ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir))
 diff --git a/gcc/config/mips/t-linux64 b/gcc/config/mips/t-linux64
-index 130e1f04707..3b7eb6b2a2f 100644
+index 2fdd8e00407..04f2099250f 100644
 --- a/gcc/config/mips/t-linux64
 +++ b/gcc/config/mips/t-linux64
 @@ -17,10 +17,6 @@
@@ -98,7 +116,7 @@ index 216d2776a18..e4d817621fc 100644
 +#MULTILIB_OSDIRNAMES := $(patsubst lib%,../lib%,$(MULTILIB_DIRNAMES))
 +MULTILIB_OSDIRNAMES := ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir))
 diff --git a/gcc/config/rs6000/t-linux64 b/gcc/config/rs6000/t-linux64
-index e11a118cb5f..4eaffb416fe 100644
+index 47e0efd5764..05f5a3f188e 100644
 --- a/gcc/config/rs6000/t-linux64
 +++ b/gcc/config/rs6000/t-linux64
 @@ -26,10 +26,9 @@
@@ -112,5 +130,5 @@ index e11a118cb5f..4eaffb416fe 100644
 -MULTILIB_OSDIRNAMES += m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:powerpc-linux-gnu)
 +MULTILIB_OSDIRNAMES := ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir))
  
- rs6000-linux.o: $(srcdir)/config/rs6000/rs6000-linux.c
+ rs6000-linux.o: $(srcdir)/config/rs6000/rs6000-linux.cc
  	$(COMPILE) $<

+ 6 - 6
recipes-devtools/gcc/gcc/0032-fix-the-c-sources-building-failure-issue.patch → recipes-devtools/gcc/gcc/0003-fix-the-c-sources-building-failure-issue.patch

@@ -1,7 +1,7 @@
-From 77b3694016a9b418b3d1cb6e0ff5d13954f7e798 Mon Sep 17 00:00:00 2001
+From 3df151fb8079302aa549dad7618b7798648f98c2 Mon Sep 17 00:00:00 2001
 From: "max.ma" <max.ma@starfivetech.com>
 Date: Wed, 19 Jan 2022 19:46:15 -0800
-Subject: [PATCH 32/32] fix the c++ sources building failure issue
+Subject: [PATCH 03/11] fix the c++ sources building failure issue
 
 ---
  libstdc++-v3/libsupc++/Makefile.am | 22 ++++++++++++++++++++++
@@ -9,7 +9,7 @@ Subject: [PATCH 32/32] fix the c++ sources building failure issue
  2 files changed, 44 insertions(+)
 
 diff --git a/libstdc++-v3/libsupc++/Makefile.am b/libstdc++-v3/libsupc++/Makefile.am
-index 10ac4bb0124..cf41fb45101 100644
+index 65b5c1a87fd..a50f93c4489 100644
 --- a/libstdc++-v3/libsupc++/Makefile.am
 +++ b/libstdc++-v3/libsupc++/Makefile.am
 @@ -128,6 +128,28 @@ cp-demangle.lo: cp-demangle.c
@@ -42,10 +42,10 @@ index 10ac4bb0124..cf41fb45101 100644
  atomicity.cc: ${atomicity_file}
  	$(LN_S) ${atomicity_file} ./atomicity.cc || true
 diff --git a/libstdc++-v3/libsupc++/Makefile.in b/libstdc++-v3/libsupc++/Makefile.in
-index 5776a56282b..c8524e808bb 100644
+index a4402009b85..d83c289c021 100644
 --- a/libstdc++-v3/libsupc++/Makefile.in
 +++ b/libstdc++-v3/libsupc++/Makefile.in
-@@ -965,6 +965,28 @@ cp-demangle.o: cp-demangle.c
+@@ -973,6 +973,28 @@ cp-demangle.o: cp-demangle.c
  atomicity.cc: ${atomicity_file}
  	$(LN_S) ${atomicity_file} ./atomicity.cc || true
  
@@ -75,5 +75,5 @@ index 5776a56282b..c8524e808bb 100644
  	@$(NORMAL_INSTALL)
  	$(mkinstalldirs) $(DESTDIR)$(stddir)
 -- 
-2.33.1
+2.25.1
 

+ 0 - 70
recipes-devtools/gcc/gcc/0003-gcc-4.3.3-SYSROOT_CFLAGS_FOR_TARGET.patch

@@ -1,70 +0,0 @@
-From 274a27da6fe355c4c49953b3b69c8949d2412c62 Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Fri, 29 Mar 2013 09:08:31 +0400
-Subject: [PATCH] gcc-4.3.3: SYSROOT_CFLAGS_FOR_TARGET
-
-Before committing, I noticed that PR/32161 was marked as a dup of PR/32009, but my previous patch did not fix it.
-
-This alternative patch is better because it lets you just use CFLAGS_FOR_TARGET to set the compilation flags for libgcc. Since bootstrapped target libraries are never compiled with the native compiler, it makes little sense to use different flags for stage1 and later stages. And it also makes little sense to use a different variable than CFLAGS_FOR_TARGET.
-
-Other changes I had to do include:
-
-- moving the creation of default CFLAGS_FOR_TARGET from Makefile.am to configure.ac, because otherwise the BOOT_CFLAGS are substituted into CFLAGS_FOR_TARGET (which is "-O2 -g $(CFLAGS)") via $(CFLAGS). It is also cleaner this way though.
-
-- passing the right CFLAGS to configure scripts as exported environment variables
-
-I also stopped passing LIBCFLAGS to configure scripts since they are unused in the whole src tree. And I updated the documentation as H-P reminded me to do.
-
-Bootstrapped/regtested i686-pc-linux-gnu, will commit to 4.4 shortly. Ok for 4.3?
-
-Signed-off-by: Paolo Bonzini  <bonzini@gnu.org>
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
-
-Upstream-Status: Pending
----
- configure | 32 ++++++++++++++++++++++++++++++++
- 1 file changed, 32 insertions(+)
-
-diff --git a/configure b/configure
-index bcebad264ec..86e4ee7c383 100755
---- a/configure
-+++ b/configure
-@@ -8977,6 +8977,38 @@ fi
- 
- 
- 
-+# During gcc bootstrap, if we use some random cc for stage1 then CFLAGS
-+# might be empty or "-g".  We don't require a C++ compiler, so CXXFLAGS
-+# might also be empty (or "-g", if a non-GCC C++ compiler is in the path).
-+# We want to ensure that TARGET libraries (which we know are built with
-+# gcc) are built with "-O2 -g", so include those options when setting
-+# CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET.
-+if test "x$CFLAGS_FOR_TARGET" = x; then
-+  CFLAGS_FOR_TARGET=$CFLAGS
-+  case " $CFLAGS " in
-+    *" -O2 "*) ;;
-+    *) CFLAGS_FOR_TARGET="-O2 $CFLAGS" ;;
-+  esac
-+  case " $CFLAGS " in
-+    *" -g "* | *" -g3 "*) ;;
-+    *) CFLAGS_FOR_TARGET="-g $CFLAGS" ;;
-+  esac
-+fi
-+
-+
-+if test "x$CXXFLAGS_FOR_TARGET" = x; then
-+  CXXFLAGS_FOR_TARGET=$CXXFLAGS
-+  case " $CXXFLAGS " in
-+    *" -O2 "*) ;;
-+    *) CXXFLAGS_FOR_TARGET="-O2 $CXXFLAGS" ;;
-+  esac
-+  case " $CXXFLAGS " in
-+    *" -g "* | *" -g3 "*) ;;
-+    *) CXXFLAGS_FOR_TARGET="-g $CXXFLAGS" ;;
-+  esac
-+fi
-+
-+
- # Handle --with-headers=XXX.  If the value is not "yes", the contents of
- # the named directory are copied to $(tooldir)/sys-include.
- if test x"${with_headers}" != x && test x"${with_headers}" != xno ; then

+ 0 - 39
recipes-devtools/gcc/gcc/0003-testuite-Check-pthread-for-omp-module-testing.patch

@@ -1,39 +0,0 @@
-From d0a7ad164b60ddc34e9705c1e9225510345e5208 Mon Sep 17 00:00:00 2001
-From: Kito Cheng <kito.cheng@sifive.com>
-Date: Mon, 21 Jun 2021 21:19:38 +0800
-Subject: [PATCH 03/15] testuite: Check pthread for omp module testing
-
----
- gcc/testsuite/g++.dg/modules/omp-1_a.C | 2 +-
- gcc/testsuite/g++.dg/modules/omp-2_a.C | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/testsuite/g++.dg/modules/omp-1_a.C b/gcc/testsuite/g++.dg/modules/omp-1_a.C
-index 94e1171f03c..7ddb776d6a1 100644
---- a/gcc/testsuite/g++.dg/modules/omp-1_a.C
-+++ b/gcc/testsuite/g++.dg/modules/omp-1_a.C
-@@ -2,7 +2,7 @@
- // { dg-require-effective-target pthread }
- 
- export module foo;
--// { dg-module-cmi foo }
-+// { dg-module-cmi foo { target pthread } }
- 
- export inline void frob (unsigned (&ary)[64])
- {
-diff --git a/gcc/testsuite/g++.dg/modules/omp-2_a.C b/gcc/testsuite/g++.dg/modules/omp-2_a.C
-index b0d4bbc6e8a..e030ac7acf7 100644
---- a/gcc/testsuite/g++.dg/modules/omp-2_a.C
-+++ b/gcc/testsuite/g++.dg/modules/omp-2_a.C
-@@ -2,7 +2,7 @@
- // { dg-require-effective-target pthread }
- 
- export module foo;
--// { dg-module-cmi foo }
-+// { dg-module-cmi foo { target pthread } }
- 
- // The OpenMPness doesn't escape to the interface.
- export void frob (unsigned (&ary)[64])
--- 
-2.33.1
-

+ 64 - 0
recipes-devtools/gcc/gcc/0004-Pass-CXXFLAGS_FOR_BUILD-in-a-couple-of-places-to-avo.patch

@@ -0,0 +1,64 @@
+From 7f40f8321fb999e9b34d948724517d3fb0d26820 Mon Sep 17 00:00:00 2001
+From: Richard Purdie <richard.purdie@linuxfoundation.org>
+Date: Thu, 28 Oct 2021 11:33:40 +0100
+Subject: [PATCH] Pass CXXFLAGS_FOR_BUILD in a couple of places to avoid these
+ errors.
+
+If CXXFLAGS contains something unsupported by the build CXX, we see build failures (e.g. using -fmacro-prefix-map for the target).
+
+2021-10-28 Richard Purdie <richard.purdie@linuxfoundation.org>
+
+ChangeLog:
+
+    * Makefile.in: Regenerate.
+    * Makefile.tpl: Add missing CXXFLAGS_FOR_BUILD overrides
+
+Upstream-Status: Pending [should be submittable]
+
+Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ Makefile.in  | 2 ++
+ Makefile.tpl | 2 ++
+ 2 files changed, 4 insertions(+)
+
+diff --git a/Makefile.in b/Makefile.in
+index 593495e1650..1d9c83cc566 100644
+--- a/Makefile.in
++++ b/Makefile.in
+@@ -176,6 +176,7 @@ BUILD_EXPORTS = \
+ # built for the build system to override those in BASE_FLAGS_TO_PASS.
+ EXTRA_BUILD_FLAGS = \
+ 	CFLAGS="$(CFLAGS_FOR_BUILD)" \
++	CXXFLAGS="$(CXXFLAGS_FOR_BUILD)" \
+ 	LDFLAGS="$(LDFLAGS_FOR_BUILD)"
+ 
+ # This is the list of directories to built for the host system.
+@@ -207,6 +208,7 @@ HOST_EXPORTS = \
+ 	CPP_FOR_BUILD="$(CPP_FOR_BUILD)"; export CPP_FOR_BUILD; \
+ 	CPPFLAGS_FOR_BUILD="$(CPPFLAGS_FOR_BUILD)"; export CPPFLAGS_FOR_BUILD; \
+ 	CXX_FOR_BUILD="$(CXX_FOR_BUILD)"; export CXX_FOR_BUILD; \
++	CXXFLAGS_FOR_BUILD="$(CXXFLAGS_FOR_BUILD)"; export CXXFLAGS_FOR_BUILD; \
+ 	DLLTOOL="$(DLLTOOL)"; export DLLTOOL; \
+ 	DSYMUTIL="$(DSYMUTIL)"; export DSYMUTIL; \
+ 	LD="$(LD)"; export LD; \
+diff --git a/Makefile.tpl b/Makefile.tpl
+index ef58fac2b9a..bab04f335c2 100644
+--- a/Makefile.tpl
++++ b/Makefile.tpl
+@@ -179,6 +179,7 @@ BUILD_EXPORTS = \
+ # built for the build system to override those in BASE_FLAGS_TO_PASS.
+ EXTRA_BUILD_FLAGS = \
+ 	CFLAGS="$(CFLAGS_FOR_BUILD)" \
++	CXXFLAGS="$(CXXFLAGS_FOR_BUILD)" \
+ 	LDFLAGS="$(LDFLAGS_FOR_BUILD)"
+ 
+ # This is the list of directories to built for the host system.
+@@ -210,6 +211,7 @@ HOST_EXPORTS = \
+ 	CPP_FOR_BUILD="$(CPP_FOR_BUILD)"; export CPP_FOR_BUILD; \
+ 	CPPFLAGS_FOR_BUILD="$(CPPFLAGS_FOR_BUILD)"; export CPPFLAGS_FOR_BUILD; \
+ 	CXX_FOR_BUILD="$(CXX_FOR_BUILD)"; export CXX_FOR_BUILD; \
++	CXXFLAGS_FOR_BUILD="$(CXXFLAGS_FOR_BUILD)"; export CXXFLAGS_FOR_BUILD; \
+ 	DLLTOOL="$(DLLTOOL)"; export DLLTOOL; \
+ 	DSYMUTIL="$(DSYMUTIL)"; export DSYMUTIL; \
+ 	LD="$(LD)"; export LD; \

+ 26 - 0
recipes-devtools/gcc/gcc/0004-define-__riscv_vector-macro.patch

@@ -0,0 +1,26 @@
+From ab6d30861b9f6571d10ac978066c45b96e060cce Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Sun, 26 Dec 2021 21:28:53 -0800
+Subject: [PATCH 04/11] define __riscv_vector macro
+
+---
+ gcc/config/riscv/riscv-c.cc | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
+index eb7ef09297e..e38746b7ff8 100644
+--- a/gcc/config/riscv/riscv-c.cc
++++ b/gcc/config/riscv/riscv-c.cc
+@@ -54,6 +54,9 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
+   if (TARGET_DIV && TARGET_MUL)
+     builtin_define ("__riscv_muldiv");
+ 
++  if (TARGET_VECTOR)
++    builtin_define ("__riscv_vector");
++
+   builtin_define_with_int_value ("__riscv_xlen", UNITS_PER_WORD * 8);
+   if (TARGET_HARD_FLOAT)
+     builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
+-- 
+2.25.1
+

+ 0 - 180
recipes-devtools/gcc/gcc/0004-varasm-Two-SECTION_RETAIN-fixes-PR100130.patch

@@ -1,180 +0,0 @@
-From 3ef4e867281820ac2298c1783fbeda40224687d8 Mon Sep 17 00:00:00 2001
-From: Richard Sandiford <richard.sandiford@arm.com>
-Date: Wed, 21 Apr 2021 09:08:44 +0100
-Subject: [PATCH 04/15] varasm: Two SECTION_RETAIN fixes [PR100130]
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-switch_to_section warns if we try to output a retain decl in a
-section without a retain flag, or if we try to output a non-retain
-decl in a section with a retain flag.  However, the warning only
-applied if we were trying to “switch” to the current section.
-This works if all decls that use a section are generated consecutively,
-but not if there is an unrelated decl in between.
-
-This patch makes the check unconditional, but suppresses the warning
-if we're writing the section's named.decl (i.e. the decl from which
-the section name and original flags were derived).
-
-Also, the warning didn't fire for -fsection-anchors, for two reasons:
-we allowed retain and non-retain decls to be put into the same block,
-and we didn't pass a decl to switch_to_section.
-
-Although these are arguably separate bugs, it isn't easy to fix them
-independently without temporarily regressing -fsection-anchor targets.
-
-gcc/
-	PR middle-end/100130
-	* varasm.c (get_block_for_decl): Make sure that any use of the
-	retain attribute matches the section's retain flag.
-	(switch_to_section): Check for retain mismatches even when
-	changing sections, but do not warn if the given decl is the
-	section's named.decl.
-	(output_object_block): Pass the first decl in the block (if any)
-	to switch_to_section.
-
-gcc/testsuite/
-	PR middle-end/100130
-	* c-c++-common/attr-retain-10.c: New test.
-	* c-c++-common/attr-retain-11.c: Likewise.
----
- gcc/testsuite/c-c++-common/attr-retain-10.c | 11 ++++
- gcc/testsuite/c-c++-common/attr-retain-11.c | 11 ++++
- gcc/varasm.c                                | 60 +++++++++++----------
- 3 files changed, 54 insertions(+), 28 deletions(-)
- create mode 100644 gcc/testsuite/c-c++-common/attr-retain-10.c
- create mode 100644 gcc/testsuite/c-c++-common/attr-retain-11.c
-
-diff --git a/gcc/testsuite/c-c++-common/attr-retain-10.c b/gcc/testsuite/c-c++-common/attr-retain-10.c
-new file mode 100644
-index 00000000000..0bac947023a
---- /dev/null
-+++ b/gcc/testsuite/c-c++-common/attr-retain-10.c
-@@ -0,0 +1,11 @@
-+/* { dg-do compile { target R_flag_in_section } } */
-+/* { dg-skip-if "non-ELF target" { *-*-darwin* powerpc*-*-aix* } } */
-+/* { dg-options "-Wall -O2 -fno-toplevel-reorder" } */
-+
-+int __attribute__((used,retain,section(".data.foo"))) foo2 = 2;
-+int between = 1;
-+int __attribute__((section(".data.foo"))) foo1 = 1;
-+/* { dg-warning "'.*' without 'retain' attribute and '.*' with 'retain' attribute are placed in a section with the same name" "" { target R_flag_in_section } .-1 } */
-+
-+/* { dg-final { scan-assembler ".data.foo,\"aw\"" { target R_flag_in_section } } } */
-+/* { dg-final { scan-assembler ".data.foo,\"awR\"" { target R_flag_in_section } } } */
-diff --git a/gcc/testsuite/c-c++-common/attr-retain-11.c b/gcc/testsuite/c-c++-common/attr-retain-11.c
-new file mode 100644
-index 00000000000..d1d3d9e8c9f
---- /dev/null
-+++ b/gcc/testsuite/c-c++-common/attr-retain-11.c
-@@ -0,0 +1,11 @@
-+/* { dg-do compile { target R_flag_in_section } } */
-+/* { dg-skip-if "non-ELF target" { *-*-darwin* powerpc*-*-aix* } } */
-+/* { dg-options "-Wall -O2 -fno-toplevel-reorder" } */
-+
-+int __attribute__((section(".data.foo"))) foo1 = 1;
-+/* { dg-warning "'.*' without 'retain' attribute and '.*' with 'retain' attribute are placed in a section with the same name" "" { target R_flag_in_section } .-1 } */
-+int between = 1;
-+int __attribute__((used,retain,section(".data.foo"))) foo2 = 2;
-+
-+/* { dg-final { scan-assembler ".data.foo,\"aw\"" { target R_flag_in_section } } } */
-+/* { dg-final { scan-assembler ".data.foo,\"awR\"" { target R_flag_in_section } } } */
-diff --git a/gcc/varasm.c b/gcc/varasm.c
-index 8bb921faa26..3ecf9e039bb 100644
---- a/gcc/varasm.c
-+++ b/gcc/varasm.c
-@@ -1314,6 +1314,10 @@ get_block_for_decl (tree decl)
-   if (SECTION_STYLE (sect) == SECTION_NOSWITCH)
-     return NULL;
- 
-+  if (bool (lookup_attribute ("retain", DECL_ATTRIBUTES (decl)))
-+      != bool (sect->common.flags & SECTION_RETAIN))
-+    return NULL;
-+
-   return get_block_for_section (sect);
- }
- 
-@@ -7758,33 +7762,33 @@ output_section_asm_op (const void *directive)
- void
- switch_to_section (section *new_section, tree decl)
- {
--  if (in_section == new_section)
-+  bool retain_p;
-+  if ((new_section->common.flags & SECTION_NAMED)
-+      && decl != nullptr
-+      && DECL_P (decl)
-+      && ((retain_p = !!lookup_attribute ("retain",
-+					  DECL_ATTRIBUTES (decl)))
-+	  != !!(new_section->common.flags & SECTION_RETAIN)))
-     {
--      bool retain_p;
--      if ((new_section->common.flags & SECTION_NAMED)
--	  && decl != nullptr
--	  && DECL_P (decl)
--	  && ((retain_p = !!lookup_attribute ("retain",
--					      DECL_ATTRIBUTES (decl)))
--	      != !!(new_section->common.flags & SECTION_RETAIN)))
--	{
--	  /* If the SECTION_RETAIN bit doesn't match, switch to a new
--	     section.  */
--	  tree used_decl, no_used_decl;
-+      /* If the SECTION_RETAIN bit doesn't match, switch to a new
-+	 section.  */
-+      tree used_decl, no_used_decl;
- 
--	  if (retain_p)
--	    {
--	      new_section->common.flags |= SECTION_RETAIN;
--	      used_decl = decl;
--	      no_used_decl = new_section->named.decl;
--	    }
--	  else
--	    {
--	      new_section->common.flags &= ~(SECTION_RETAIN
--					     | SECTION_DECLARED);
--	      used_decl = new_section->named.decl;
--	      no_used_decl = decl;
--	    }
-+      if (retain_p)
-+	{
-+	  new_section->common.flags |= SECTION_RETAIN;
-+	  used_decl = decl;
-+	  no_used_decl = new_section->named.decl;
-+	}
-+      else
-+	{
-+	  new_section->common.flags &= ~(SECTION_RETAIN
-+					 | SECTION_DECLARED);
-+	  used_decl = new_section->named.decl;
-+	  no_used_decl = decl;
-+	}
-+      if (no_used_decl != used_decl)
-+	{
- 	  warning (OPT_Wattributes,
- 		   "%+qD without %<retain%> attribute and %qD with "
- 		   "%<retain%> attribute are placed in a section with "
-@@ -7792,9 +7796,9 @@ switch_to_section (section *new_section, tree decl)
- 	  inform (DECL_SOURCE_LOCATION (used_decl),
- 		  "%qD was declared here", used_decl);
- 	}
--      else
--	return;
-     }
-+  else if (in_section == new_section)
-+    return;
- 
-   if (new_section->common.flags & SECTION_FORGET)
-     in_section = NULL;
-@@ -8007,7 +8011,7 @@ output_object_block (struct object_block *block)
-       && (strcmp (block->sect->named.name, ".vtable_map_vars") == 0))
-     handle_vtv_comdat_section (block->sect, block->sect->named.decl);
-   else
--    switch_to_section (block->sect);
-+    switch_to_section (block->sect, SYMBOL_REF_DECL ((*block->objects)[0]));
- 
-   gcc_checking_assert (!(block->sect->common.flags & SECTION_MERGE));
-   assemble_align (block->alignment);
--- 
-2.33.1
-

+ 8 - 8
recipes-devtools/gcc/gcc/0007-Use-the-defaults.h-in-B-instead-of-S-and-t-oe-in-B.patch → recipes-devtools/gcc/gcc/0005-Use-the-defaults.h-in-B-instead-of-S-and-t-oe-in-B.patch

@@ -1,4 +1,4 @@
-From e64342df647829d3e1c52fd480a5be7c1281ced0 Mon Sep 17 00:00:00 2001
+From 5455fc1de74897a27c1199dc5611ec02243e24af Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Fri, 29 Mar 2013 09:17:25 +0400
 Subject: [PATCH] Use the defaults.h in ${B} instead of ${S}, and t-oe in ${B}
@@ -26,10 +26,10 @@ Signed-off-by: Hongxu Jia <hongxu.jia@windriver.com>
  4 files changed, 7 insertions(+), 7 deletions(-)
 
 diff --git a/gcc/Makefile.in b/gcc/Makefile.in
-index 8a5fb3fd99c..7da6f439fff 100644
+index 31ff95500c9..a8277254696 100644
 --- a/gcc/Makefile.in
 +++ b/gcc/Makefile.in
-@@ -552,7 +552,7 @@ TARGET_SYSTEM_ROOT = @TARGET_SYSTEM_ROOT@
+@@ -553,7 +553,7 @@ TARGET_SYSTEM_ROOT = @TARGET_SYSTEM_ROOT@
  TARGET_SYSTEM_ROOT_DEFINE = @TARGET_SYSTEM_ROOT_DEFINE@
  
  xmake_file=@xmake_file@
@@ -39,10 +39,10 @@ index 8a5fb3fd99c..7da6f439fff 100644
  TM_MULTILIB_CONFIG=@TM_MULTILIB_CONFIG@
  TM_MULTILIB_EXCEPTIONS_CONFIG=@TM_MULTILIB_EXCEPTIONS_CONFIG@
 diff --git a/gcc/configure b/gcc/configure
-index 3f0734bff11..c5d3bc4ee2d 100755
+index dc2d59701ad..3fc0e2f5813 100755
 --- a/gcc/configure
 +++ b/gcc/configure
-@@ -13090,8 +13090,8 @@ for f in $tm_file; do
+@@ -13381,8 +13381,8 @@ for f in $tm_file; do
         tm_include_list="${tm_include_list} $f"
         ;;
      defaults.h )
@@ -54,10 +54,10 @@ index 3f0734bff11..c5d3bc4ee2d 100755
      * )
         tm_file_list="${tm_file_list} \$(srcdir)/config/$f"
 diff --git a/gcc/configure.ac b/gcc/configure.ac
-index 54e21764b3e..f83420326d6 100644
+index 36ce78924de..46de496b256 100644
 --- a/gcc/configure.ac
 +++ b/gcc/configure.ac
-@@ -2263,8 +2263,8 @@ for f in $tm_file; do
+@@ -2332,8 +2332,8 @@ for f in $tm_file; do
         tm_include_list="${tm_include_list} $f"
         ;;
      defaults.h )
@@ -69,7 +69,7 @@ index 54e21764b3e..f83420326d6 100644
      * )
         tm_file_list="${tm_file_list} \$(srcdir)/config/$f"
 diff --git a/gcc/mkconfig.sh b/gcc/mkconfig.sh
-index c49acd8f7e4..a0a657bdbb9 100644
+index 91cc43f69ff..8de33713cd8 100644
 --- a/gcc/mkconfig.sh
 +++ b/gcc/mkconfig.sh
 @@ -77,7 +77,7 @@ if [ -n "$HEADERS" ]; then

+ 6 - 6
recipes-devtools/gcc/gcc/0027-enable-ifunc-for-riscv.patch → recipes-devtools/gcc/gcc/0005-enable-ifunc-for-riscv.patch

@@ -1,25 +1,25 @@
-From cf24c1d52d8de2597605d9c2e9b5a8db8d43e1c5 Mon Sep 17 00:00:00 2001
+From 7dd16b0fbc894b47e4611a514bc7685bb562e167 Mon Sep 17 00:00:00 2001
 From: "max.ma" <max.ma@starfivetech.com>
 Date: Wed, 8 Dec 2021 17:56:57 -0800
-Subject: [PATCH 27/32] enable ifunc for riscv
+Subject: [PATCH 05/11] enable ifunc for riscv
 
 ---
  gcc/config.gcc | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/gcc/config.gcc b/gcc/config.gcc
-index 357b0bed067..20367a70382 100644
+index c5064dd3766..8e1cbb85c2e 100644
 --- a/gcc/config.gcc
 +++ b/gcc/config.gcc
-@@ -3628,7 +3628,7 @@ case ${target} in
+@@ -3622,7 +3622,7 @@ case ${target} in
          ;;
  *-*-linux* | *-*-gnu*)
  	case ${target} in
--	aarch64*-* | arm*-* | i[34567]86-* | powerpc*-* | s390*-* | sparc*-* | x86_64-*)
+-	aarch64*-* | arm*-* | i[34567]86-* | powerpc*-* | s390*-* | sparc*-* | x86_64-* | loongarch*-*)
 +	aarch64*-* | arm*-* | i[34567]86-* | powerpc*-* | s390*-* | sparc*-* | riscv*-*-* | x86_64-*)
  		default_gnu_indirect_function=yes
  		;;
  	esac
 -- 
-2.33.1
+2.25.1
 

+ 0 - 122
recipes-devtools/gcc/gcc/0005-optional-libstdc.patch

@@ -1,122 +0,0 @@
-From 57e2c5e35732988c0b287289eb0997b4e9769371 Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Fri, 29 Mar 2013 09:12:56 +0400
-Subject: [PATCH] optional libstdc
-
-gcc-runtime builds libstdc++ separately from gcc-cross-*. Its configure tests using g++
-will not run correctly since by default the linker will try to link against libstdc++
-which shouldn't exist yet. We need an option to disable -lstdc++
-option whilst leaving -lc, -lgcc and other automatic library dependencies added by gcc
-driver. This patch adds such an option which only disables the -lstdc++.
-
-A "standard" gcc build uses xgcc and hence avoids this. We should ask upstream how to
-do this officially, the likely answer is don't build libstdc++ separately.
-
-RP 29/6/10
-
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
-
-Upstream-Status: Inappropriate [embedded specific]
----
- gcc/c-family/c.opt  |  4 ++++
- gcc/cp/g++spec.c    |  1 +
- gcc/doc/invoke.texi | 32 +++++++++++++++++++++++++++++++-
- gcc/gcc.c           |  1 +
- 4 files changed, 37 insertions(+), 1 deletion(-)
-
-diff --git a/gcc/c-family/c.opt b/gcc/c-family/c.opt
-index 64e46e7573e..1824380f27a 100644
---- a/gcc/c-family/c.opt
-+++ b/gcc/c-family/c.opt
-@@ -2166,6 +2166,10 @@ nostdinc++
- C++ ObjC++
- Do not search standard system include directories for C++.
- 
-+nostdlib++
-+Driver
-+Do not link standard C++ runtime library
-+
- o
- C ObjC C++ ObjC++ Joined Separate
- ; Documented in common.opt
-diff --git a/gcc/cp/g++spec.c b/gcc/cp/g++spec.c
-index 3c9bd1490b4..818beb61cee 100644
---- a/gcc/cp/g++spec.c
-+++ b/gcc/cp/g++spec.c
-@@ -159,6 +159,7 @@ lang_specific_driver (struct cl_decoded_option **in_decoded_options,
-       switch (decoded_options[i].opt_index)
- 	{
- 	case OPT_nostdlib:
-+	case OPT_nostdlib__:
- 	case OPT_nodefaultlibs:
- 	  library = -1;
- 	  break;
-diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
-index 6659a903bf0..9ee63dbe52f 100644
---- a/gcc/doc/invoke.texi
-+++ b/gcc/doc/invoke.texi
-@@ -239,6 +239,9 @@ in the following sections.
- -fno-weak  -nostdinc++ @gol
- -fvisibility-inlines-hidden @gol
- -fvisibility-ms-compat @gol
-+-fvtable-verify=@r{[}std@r{|}preinit@r{|}none@r{]} @gol
-+-fvtv-counts -fvtv-debug @gol
-+-nostdlib++ @gol
- -fext-numeric-literals @gol
- -flang-info-include-translate@r{[}=@var{header}@r{]} @gol
- -flang-info-include-translate-not @gol
-@@ -632,7 +635,7 @@ Objective-C and Objective-C++ Dialects}.
- -pie  -pthread  -r  -rdynamic @gol
- -s  -static  -static-pie  -static-libgcc  -static-libstdc++ @gol
- -static-libasan  -static-libtsan  -static-liblsan  -static-libubsan @gol
---shared  -shared-libgcc  -symbolic @gol
-+-shared  -shared-libgcc  -symbolic -nostdlib++ @gol
- -T @var{script}  -Wl,@var{option}  -Xlinker @var{option} @gol
- -u @var{symbol}  -z @var{keyword}}
- 
-@@ -15708,6 +15711,33 @@ Specify that the program entry point is @var{entry}.  The argument is
- interpreted by the linker; the GNU linker accepts either a symbol name
- or an address.
- 
-+@item -nostdlib++
-+@opindex nostdlib++
-+Do not use the standard system C++ runtime libraries when linking.
-+Only the libraries you specify will be passed to the linker.
-+
-+@cindex @option{-lgcc}, use with @option{-nostdlib}
-+@cindex @option{-nostdlib} and unresolved references
-+@cindex unresolved references and @option{-nostdlib}
-+@cindex @option{-lgcc}, use with @option{-nodefaultlibs}
-+@cindex @option{-nodefaultlibs} and unresolved references
-+@cindex unresolved references and @option{-nodefaultlibs}
-+One of the standard libraries bypassed by @option{-nostdlib} and
-+@option{-nodefaultlibs} is @file{libgcc.a}, a library of internal subroutines
-+which GCC uses to overcome shortcomings of particular machines, or special
-+needs for some languages.
-+(@xref{Interface,,Interfacing to GCC Output,gccint,GNU Compiler
-+Collection (GCC) Internals},
-+for more discussion of @file{libgcc.a}.)
-+In most cases, you need @file{libgcc.a} even when you want to avoid
-+other standard libraries.  In other words, when you specify @option{-nostdlib}
-+or @option{-nodefaultlibs} you should usually specify @option{-lgcc} as well.
-+This ensures that you have no unresolved references to internal GCC
-+library subroutines.
-+(An example of such an internal subroutine is @code{__main}, used to ensure C++
-+constructors are called; @pxref{Collect2,,@code{collect2}, gccint,
-+GNU Compiler Collection (GCC) Internals}.)
-+
- @item -pie
- @opindex pie
- Produce a dynamically linked position independent executable on targets
-diff --git a/gcc/gcc.c b/gcc/gcc.c
-index 19c75b6e20d..be7630ffd8c 100644
---- a/gcc/gcc.c
-+++ b/gcc/gcc.c
-@@ -1162,6 +1162,7 @@ proper position among the other output files.  */
-     %(mflib) " STACK_SPLIT_SPEC "\
-     %{fprofile-arcs|fprofile-generate*|coverage:-lgcov} " SANITIZER_SPEC " \
-     %{!nostdlib:%{!r:%{!nodefaultlibs:%(link_ssp) %(link_gcc_c_sequence)}}}\
-+    %{!nostdlib++:}\
-     %{!nostdlib:%{!r:%{!nostartfiles:%E}}} %{T*}  \n%(post_link) }}}}}}"
- #endif
- 

+ 0 - 142
recipes-devtools/gcc/gcc/0005-testsuite-Add-fchecking-to-dg-ice-tests.patch

@@ -1,142 +0,0 @@
-From 484239a45044ffefebb54286ce89e71ce3304d8f Mon Sep 17 00:00:00 2001
-From: Jakub Jelinek <jakub@redhat.com>
-Date: Wed, 21 Apr 2021 15:17:10 +0200
-Subject: [PATCH 05/15] testsuite: Add -fchecking to dg-ice tests
-
-In --enable-checking=release builds (which is the default on release
-branches), I'm getting various extra FAILs that don't appear in
---enable-checking=yes builds.
-
-XPASS: g++.dg/cpp0x/constexpr-52830.C  -std=c++14 (internal compiler error)
-FAIL: g++.dg/cpp0x/constexpr-52830.C  -std=c++14 (test for excess errors)
-XPASS: g++.dg/cpp0x/constexpr-52830.C  -std=c++17 (internal compiler error)
-FAIL: g++.dg/cpp0x/constexpr-52830.C  -std=c++17 (test for excess errors)
-XPASS: g++.dg/cpp0x/constexpr-52830.C  -std=c++2a (internal compiler error)
-FAIL: g++.dg/cpp0x/constexpr-52830.C  -std=c++2a (test for excess errors)
-FAIL: g++.dg/cpp0x/vt-88982.C  -std=c++14 (test for excess errors)
-FAIL: g++.dg/cpp0x/vt-88982.C  -std=c++17 (test for excess errors)
-FAIL: g++.dg/cpp0x/vt-88982.C  -std=c++2a (test for excess errors)
-FAIL: g++.dg/cpp1y/auto-fn61.C  -std=c++14 (test for excess errors)
-FAIL: g++.dg/cpp1y/auto-fn61.C  -std=c++17 (test for excess errors)
-FAIL: g++.dg/cpp1y/auto-fn61.C  -std=c++2a (test for excess errors)
-FAIL: g++.dg/cpp1z/constexpr-lambda26.C  -std=c++17 (test for excess errors)
-FAIL: g++.dg/cpp1z/constexpr-lambda26.C  -std=c++2a (test for excess errors)
-FAIL: g++.dg/cpp2a/nontype-class39.C  -std=c++2a (test for excess errors)
-FAIL: c-c++-common/goacc/kernels-decompose-ice-1.c  -std=c++14 (test for excess errors)
-FAIL: c-c++-common/goacc/kernels-decompose-ice-1.c  -std=c++17 (test for excess errors)
-FAIL: c-c++-common/goacc/kernels-decompose-ice-1.c  -std=c++2a (test for excess errors)
-FAIL: c-c++-common/goacc/kernels-decompose-ice-1.c  -std=c++98 (test for excess errors)
-FAIL: c-c++-common/goacc/kernels-decompose-ice-2.c  -std=c++14 (test for excess errors)
-FAIL: c-c++-common/goacc/kernels-decompose-ice-2.c  -std=c++17 (test for excess errors)
-FAIL: c-c++-common/goacc/kernels-decompose-ice-2.c  -std=c++2a (test for excess errors)
-FAIL: c-c++-common/goacc/kernels-decompose-ice-2.c  -std=c++98 (test for excess errors)
-
-These are tests that have dg-ice and most of those ICEs are checking ICEs
-which go away in release checking when -fno-checking is the default.
-
-The following patch adds -fchecking option to those.
-
-2021-04-21  Jakub Jelinek  <jakub@redhat.com>
-
-	* g++.dg/cpp1z/constexpr-lambda26.C: Add dg-additional-options
-	-fchecking.
-	* g++.dg/cpp1y/auto-fn61.C: Likewise.
-	* g++.dg/cpp2a/nontype-class39.C: Likewise.
-	* g++.dg/cpp0x/constexpr-52830.C: Likewise.
-	* g++.dg/cpp0x/vt-88982.C: Likewise.
-	* c-c++-common/goacc/kernels-decompose-ice-1.c: Add -fchecking to
-	dg-additional-options.
-	* c-c++-common/goacc/kernels-decompose-ice-2.c: Likewise.
----
- gcc/testsuite/c-c++-common/goacc/kernels-decompose-ice-1.c | 2 +-
- gcc/testsuite/c-c++-common/goacc/kernels-decompose-ice-2.c | 2 +-
- gcc/testsuite/g++.dg/cpp0x/constexpr-52830.C               | 1 +
- gcc/testsuite/g++.dg/cpp0x/vt-88982.C                      | 1 +
- gcc/testsuite/g++.dg/cpp1y/auto-fn61.C                     | 1 +
- gcc/testsuite/g++.dg/cpp1z/constexpr-lambda26.C            | 1 +
- gcc/testsuite/g++.dg/cpp2a/nontype-class39.C               | 1 +
- 7 files changed, 7 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/testsuite/c-c++-common/goacc/kernels-decompose-ice-1.c b/gcc/testsuite/c-c++-common/goacc/kernels-decompose-ice-1.c
-index d770b91dd09..8c3884bdc00 100644
---- a/gcc/testsuite/c-c++-common/goacc/kernels-decompose-ice-1.c
-+++ b/gcc/testsuite/c-c++-common/goacc/kernels-decompose-ice-1.c
-@@ -1,7 +1,7 @@
- /* Test OpenACC 'kernels' construct decomposition.  */
- 
- /* { dg-additional-options "-fopt-info-omp-all" } */
--/* { dg-additional-options "--param=openacc-kernels=decompose" } */
-+/* { dg-additional-options "-fchecking --param=openacc-kernels=decompose" } */
- /* { dg-ice "TODO" }
-    { dg-prune-output "during GIMPLE pass: omplower" } */
- 
-diff --git a/gcc/testsuite/c-c++-common/goacc/kernels-decompose-ice-2.c b/gcc/testsuite/c-c++-common/goacc/kernels-decompose-ice-2.c
-index ae059eb354b..8bf60a9a509 100644
---- a/gcc/testsuite/c-c++-common/goacc/kernels-decompose-ice-2.c
-+++ b/gcc/testsuite/c-c++-common/goacc/kernels-decompose-ice-2.c
-@@ -1,6 +1,6 @@
- /* Test OpenACC 'kernels' construct decomposition.  */
- 
--/* { dg-additional-options "--param=openacc-kernels=decompose" } */
-+/* { dg-additional-options "-fchecking --param=openacc-kernels=decompose" } */
- /* { dg-ice "TODO" }
-    { dg-prune-output "during GIMPLE pass: omplower" } */
- 
-diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-52830.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-52830.C
-index 2c9d2f9b329..eae0d8c377b 100644
---- a/gcc/testsuite/g++.dg/cpp0x/constexpr-52830.C
-+++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-52830.C
-@@ -1,5 +1,6 @@
- // PR c++/52830
- // { dg-do compile { target c++11 } }
-+// { dg-additional-options "-fchecking" }
- // { dg-ice "comptypes" }
- 
- template<bool b> struct eif { typedef void type; };
-diff --git a/gcc/testsuite/g++.dg/cpp0x/vt-88982.C b/gcc/testsuite/g++.dg/cpp0x/vt-88982.C
-index cb9530dcee1..7a868233d73 100644
---- a/gcc/testsuite/g++.dg/cpp0x/vt-88982.C
-+++ b/gcc/testsuite/g++.dg/cpp0x/vt-88982.C
-@@ -1,5 +1,6 @@
- // PR c++/88982
- // { dg-do compile { target c++11 } }
-+// { dg-additional-options "-fchecking" }
- // { dg-ice "tsubst_pack_expansion" }
- 
- template<typename...Ts> struct A {
-diff --git a/gcc/testsuite/g++.dg/cpp1y/auto-fn61.C b/gcc/testsuite/g++.dg/cpp1y/auto-fn61.C
-index c24c3b85d78..bed5ea0cfc0 100644
---- a/gcc/testsuite/g++.dg/cpp1y/auto-fn61.C
-+++ b/gcc/testsuite/g++.dg/cpp1y/auto-fn61.C
-@@ -1,5 +1,6 @@
- // PR c++/88003
- // { dg-do compile { target c++14 } }
-+// { dg-additional-options "-fchecking" }
- // { dg-ice "poplevel_class" }
- 
- auto test() {
-diff --git a/gcc/testsuite/g++.dg/cpp1z/constexpr-lambda26.C b/gcc/testsuite/g++.dg/cpp1z/constexpr-lambda26.C
-index d6c8bae525f..0cdb400d21c 100644
---- a/gcc/testsuite/g++.dg/cpp1z/constexpr-lambda26.C
-+++ b/gcc/testsuite/g++.dg/cpp1z/constexpr-lambda26.C
-@@ -1,5 +1,6 @@
- // PR c++/87765
- // { dg-do compile { target c++17 } }
-+// { dg-additional-options "-fchecking" }
- // { dg-ice "cxx_eval_constant_expression" }
- 
- template <int N>
-diff --git a/gcc/testsuite/g++.dg/cpp2a/nontype-class39.C b/gcc/testsuite/g++.dg/cpp2a/nontype-class39.C
-index f5f79a71ec2..512afad8e4f 100644
---- a/gcc/testsuite/g++.dg/cpp2a/nontype-class39.C
-+++ b/gcc/testsuite/g++.dg/cpp2a/nontype-class39.C
-@@ -1,5 +1,6 @@
- // PR c++/89565
- // { dg-do compile { target c++20 } }
-+// { dg-additional-options "-fchecking" }
- // { dg-ice "resolve_args" }
- 
- template <auto>
--- 
-2.33.1
-

+ 0 - 35
recipes-devtools/gcc/gcc/0006-COLLECT_GCC_OPTIONS.patch

@@ -1,35 +0,0 @@
-From 127716a32a11ca2a6b3aac068054bfc69c4dcfd8 Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Fri, 29 Mar 2013 09:16:28 +0400
-Subject: [PATCH] COLLECT_GCC_OPTIONS
-
-This patch adds --sysroot into COLLECT_GCC_OPTIONS which is used to
-invoke collect2.
-
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
-
-Upstream-Status: Pending
----
- gcc/gcc.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/gcc/gcc.c b/gcc/gcc.c
-index be7630ffd8c..1bc45285384 100644
---- a/gcc/gcc.c
-+++ b/gcc/gcc.c
-@@ -5383,6 +5383,15 @@ set_collect_gcc_options (void)
- 		sizeof ("COLLECT_GCC_OPTIONS=") - 1);
- 
-   first_time = TRUE;
-+#ifdef HAVE_LD_SYSROOT
-+  if (target_system_root_changed && target_system_root)
-+    {
-+      obstack_grow (&collect_obstack, "'--sysroot=", sizeof("'--sysroot=")-1);
-+      obstack_grow (&collect_obstack, target_system_root,strlen(target_system_root));
-+      obstack_grow (&collect_obstack, "'", 1);
-+      first_time = FALSE;
-+    }
-+#endif
-   for (i = 0; (int) i < n_switches; i++)
-     {
-       const char *const *args;

+ 8 - 8
recipes-devtools/gcc/gcc/0009-cpp-honor-sysroot.patch → recipes-devtools/gcc/gcc/0006-cpp-honor-sysroot.patch

@@ -1,4 +1,4 @@
-From 33a7a55d39c040ba09af2d69f7fa9cf8e6f84c91 Mon Sep 17 00:00:00 2001
+From abc3b82ab24169277f2090e9df1ceac3573142be Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Fri, 29 Mar 2013 09:22:00 +0400
 Subject: [PATCH] cpp: honor sysroot.
@@ -22,11 +22,11 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
 Upstream-Status: Pending
 ---
  gcc/cp/lang-specs.h | 2 +-
- gcc/gcc.c           | 2 +-
+ gcc/gcc.cc          | 2 +-
  2 files changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/gcc/cp/lang-specs.h b/gcc/cp/lang-specs.h
-index 8902ae1d2ed..e99e2fcd6ad 100644
+index f35c9fab76b..19ddc98ce7f 100644
 --- a/gcc/cp/lang-specs.h
 +++ b/gcc/cp/lang-specs.h
 @@ -116,7 +116,7 @@ along with GCC; see the file COPYING3.  If not see
@@ -38,11 +38,11 @@ index 8902ae1d2ed..e99e2fcd6ad 100644
        "  %{!fsyntax-only:"
        "    %{fmodule-only:%{!S:-o %g.s%V}}"
        "    %{!fmodule-only:%{!fmodule-header*:%(invoke_as)}}}"
-diff --git a/gcc/gcc.c b/gcc/gcc.c
-index 1bc45285384..8737bae5353 100644
---- a/gcc/gcc.c
-+++ b/gcc/gcc.c
-@@ -1470,7 +1470,7 @@ static const struct compiler default_compilers[] =
+diff --git a/gcc/gcc.cc b/gcc/gcc.cc
+index ce161d3c853..aa4cf92fb78 100644
+--- a/gcc/gcc.cc
++++ b/gcc/gcc.cc
+@@ -1476,7 +1476,7 @@ static const struct compiler default_compilers[] =
  					   %W{o*:--output-pch=%*}}%V}}}}}}}", 0, 0, 0},
    {".i", "@cpp-output", 0, 0, 0},
    {"@cpp-output",

+ 277 - 0
recipes-devtools/gcc/gcc/0006-merge-b-extension-changes.patch

@@ -0,0 +1,277 @@
+From fb72ef1b706a2dd0079a2bebd301f9503f5d2893 Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Thu, 7 Jul 2022 00:30:21 -0700
+Subject: [PATCH 06/11] merge b extension changes
+
+---
+ gcc/common/config/riscv/riscv-common.cc | 17 +++++++++--
+ gcc/config/riscv/riscv-builtins.cc      | 10 +++++++
+ gcc/config/riscv/riscv-ftypes.def       |  2 ++
+ gcc/config/riscv/riscv.cc               | 34 +++++++++++++++++++++-
+ gcc/config/riscv/riscv.h                |  9 ++----
+ gcc/config/riscv/riscv.md               | 38 +++++++++++++++++++++++++
+ gcc/config/riscv/riscv.opt              |  2 ++
+ 7 files changed, 103 insertions(+), 9 deletions(-)
+
+diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
+index 1501242e296..967c28d0498 100644
+--- a/gcc/common/config/riscv/riscv-common.cc
++++ b/gcc/common/config/riscv/riscv-common.cc
+@@ -47,6 +47,10 @@ struct riscv_implied_info_t
+ /* Implied ISA info, must end with NULL sentinel.  */
+ static const riscv_implied_info_t riscv_implied_info[] =
+ {
++  {"b", "zbb"},
++  {"b", "zbs"},
++  {"b", "zba"},
++  {"b", "zbc"},
+   {"d", "f"},
+   {"f", "zicsr"},
+   {"d", "zicsr"},
+@@ -149,6 +153,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
+   {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
+   {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
+ 
++  {"b", ISA_SPEC_CLASS_NONE, 1, 0},
+   {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
+   {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
+   {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
+@@ -787,7 +792,14 @@ riscv_subset_list::parse_std_ext (const char *p)
+ 
+       p = parsing_subset_version (subset, p, &major_version, &minor_version,
+ 				  /* std_ext_p= */ true, &explicit_version_p);
+-
++      if (std_ext == 'b')
++        { 
++          add ("zba", major_version, minor_version, explicit_version_p, false);
++          add ("zbb", major_version, minor_version, explicit_version_p, false);
++          add ("zbc", major_version, minor_version, explicit_version_p, false);
++          add ("zbs", major_version, minor_version, explicit_version_p, false);
++        }
++      else 
+       add (subset, major_version, minor_version, explicit_version_p, false);
+     }
+   return p;
+@@ -1094,6 +1106,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
+   {"zicsr",    &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
+   {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
+ 
++  {"b", &gcc_options::x_target_flags, MASK_BITMANIP},
+   {"zba",    &gcc_options::x_riscv_zb_subext, MASK_ZBA},
+   {"zbb",    &gcc_options::x_riscv_zb_subext, MASK_ZBB},
+   {"zbc",    &gcc_options::x_riscv_zb_subext, MASK_ZBC},
+@@ -1304,4 +1317,4 @@ static const struct default_options riscv_option_optimization_table[] =
+ #undef TARGET_HANDLE_OPTION
+ #define TARGET_HANDLE_OPTION riscv_handle_option
+ 
+-struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
++struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
+\ No newline at end of file
+diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
+index 0658f8d3047..d50876a26f7 100644
+--- a/gcc/config/riscv/riscv-builtins.cc
++++ b/gcc/config/riscv/riscv-builtins.cc
+@@ -40,6 +40,7 @@ along with GCC; see the file COPYING3.  If not see
+ /* Macros to create an enumeration identifier for a function prototype.  */
+ #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE
+ #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
++#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
+ 
+ /* Classifies the prototype of a built-in function.  */
+ enum riscv_function_type {
+@@ -86,6 +87,8 @@ struct riscv_builtin_description {
+ };
+ 
+ AVAIL (hard_float, TARGET_HARD_FLOAT)
++AVAIL (zbb, TARGET_ZBB)
++AVAIL (zbc, TARGET_ZBC)
+ 
+ /* Construct a riscv_builtin_description from the given arguments.
+ 
+@@ -119,6 +122,7 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
+ /* Argument types.  */
+ #define RISCV_ATYPE_VOID void_type_node
+ #define RISCV_ATYPE_USI unsigned_intSI_type_node
++#define RISCV_ATYPE_SI intSI_type_node
+ 
+ /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
+    their associated RISCV_ATYPEs.  */
+@@ -126,8 +130,14 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
+   RISCV_ATYPE_##A
+ #define RISCV_FTYPE_ATYPES1(A, B) \
+   RISCV_ATYPE_##A, RISCV_ATYPE_##B
++#define RISCV_FTYPE_ATYPES2(A, B, C) \
++  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
+ 
+ static const struct riscv_builtin_description riscv_builtins[] = {
++  DIRECT_BUILTIN (orc_b, RISCV_SI_FTYPE_SI, zbb),
++  DIRECT_BUILTIN (clmul, RISCV_SI_FTYPE_SI_SI, zbc),
++  DIRECT_BUILTIN (clmulh, RISCV_SI_FTYPE_SI_SI, zbc),
++  DIRECT_BUILTIN (clmulr, RISCV_SI_FTYPE_SI_SI, zbc),
+   DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
+   DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float)
+ };
+diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
+index 2214c496f9b..edcfd44dacc 100644
+--- a/gcc/config/riscv/riscv-ftypes.def
++++ b/gcc/config/riscv/riscv-ftypes.def
+@@ -28,3 +28,5 @@ along with GCC; see the file COPYING3.  If not see
+ 
+ DEF_RISCV_FTYPE (0, (USI))
+ DEF_RISCV_FTYPE (1, (VOID, USI))
++DEF_RISCV_FTYPE (1, (SI, SI))
++DEF_RISCV_FTYPE (2, (SI, SI, SI))
+\ No newline at end of file
+diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
+index ee756aab694..ec7030f6c2e 100644
+--- a/gcc/config/riscv/riscv.cc
++++ b/gcc/config/riscv/riscv.cc
+@@ -415,6 +415,15 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
+       /* Simply BSETI.  */
+       codes[0].code = UNKNOWN;
+       codes[0].value = value;
++
++      /* RISC-V sign-extends all 32bit values that life in a 32bit
++	 register.  To avoid paradoxes, we thus need to use the
++	 sign-extended (negative) representation for the value, if we
++	 want to build 0x80000000 in SImode.  This will then expand
++	 to an ADDI/LI instruction.  */
++      if (mode == SImode && value == 0x80000000)
++	    codes[0].value = -2147483648;
++
+       return 1;
+     }
+ 
+@@ -2014,8 +2023,22 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
+ 	      (TARGET_64BIT && (mode == DImode)))
+ 	  && (GET_CODE (XEXP (x, 0)) == ASHIFT)
+ 	  && REG_P (XEXP (XEXP (x, 0), 0))
++	  && CONST_INT_P (XEXP (XEXP (x, 0), 0))
++	  && IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 0)), 1, 3))
++	{
++	  *total = COSTS_N_INSNS (1);
++	  return true;
++	}
++    /* Before strength-reduction, the shNadd can be expressed as the addition
++	 of a multiplication with a power-of-two.  If this case is not handled,
++	 the strength-reduction in expmed.c will calculate an inflated cost. */
++      if (TARGET_ZBA
++	  && ((!TARGET_64BIT && (mode == SImode)) ||
++	      (TARGET_64BIT && (mode == DImode)))
++	  && (GET_CODE (XEXP (x, 0)) == MULT)
++	  && REG_P (XEXP (XEXP (x, 0), 0))
+ 	  && CONST_INT_P (XEXP (XEXP (x, 0), 1))
+-	  && IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1)), 1, 3))
++	  && IN_RANGE (pow2p_hwi (INTVAL (XEXP (XEXP (x, 0), 1))), 1, 3))
+ 	{
+ 	  *total = COSTS_N_INSNS (1);
+ 	  return true;
+@@ -2044,6 +2067,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
+ 	    if (!CONST_INT_P (and_rhs))
+ 	      break;
+ 
++	    rtx ashift_lhs = XEXP (and_lhs, 0);
+ 	    rtx ashift_rhs = XEXP (and_lhs, 1);
+ 
+ 	    if (!CONST_INT_P (ashift_rhs)
+@@ -2131,6 +2155,14 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
+       *total = riscv_extend_cost (XEXP (x, 0), GET_CODE (x) == ZERO_EXTEND);
+       return false;
+ 
++    case BSWAP:
++      if (TARGET_ZBB)
++	{
++	  *total = COSTS_N_INSNS (1);
++	  return true;
++	}
++      return false;
++
+     case FLOAT:
+     case UNSIGNED_FLOAT:
+     case FIX:
+diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
+index 8a4d2cf7f85..045920b49cf 100644
+--- a/gcc/config/riscv/riscv.h
++++ b/gcc/config/riscv/riscv.h
+@@ -528,13 +528,10 @@ enum reg_class
+   (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH)	\
+    || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
+ 
+-/* If this is a single bit mask, then we can load it with bseti.  But this
+-   is not useful for any of the low 31 bits because we can use addi or lui
+-   to load them.  It is wrong for loading SImode 0x80000000 on rv64 because it
+-   needs to be sign-extended.  So we restrict this to the upper 32-bits
+-   only.  */
++/* If this is a single bit mask, then we can load it with bseti.  Special
++   handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */
+ #define SINGLE_BIT_MASK_OPERAND(VALUE) \
+-  (pow2p_hwi (VALUE) && (ctz_hwi (VALUE) >= 32))
++  (pow2p_hwi (VALUE))
+ 
+ /* Stack layout; function entry, exit and calling.  */
+ 
+diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
+index b3c5bce842a..e56979ca800 100644
+--- a/gcc/config/riscv/riscv.md
++++ b/gcc/config/riscv/riscv.md
+@@ -2767,6 +2767,44 @@
+   [(set_attr "length" "0")]
+ )
+ 
++(define_insn "riscv_orc_b"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
++  "TARGET_ZBB"
++  "orc.b\t%0,%1,%2"
++  [(set_attr "type" "bitmanip")])
++
++(define_insn "riscv_rev8"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
++  "TARGET_ZBB"
++  "rev8\t%0,%1,%2"
++  [(set_attr "type" "bitmanip")])
++
++(define_insn "riscv_clmul"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
++				   (match_operand:SI 2 "register_operand" "r"))))]
++  "TARGET_ZBC"
++  "clmul\t%0,%1,%2"
++  [(set_attr "type" "bitmanip")])
++
++(define_insn "riscv_clmulh"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
++				   (match_operand:SI 2 "register_operand" "r"))))]
++  "TARGET_ZBC"
++  "clmulh\t%0,%1,%2"
++  [(set_attr "type" "bitmanip")])
++
++(define_insn "riscv_clmulr"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
++				   (match_operand:SI 2 "register_operand" "r"))))]
++  "TARGET_ZBC"
++  "clmulr\t%0,%1,%2"
++  [(set_attr "type" "bitmanip")])
++
+ ;; This fixes a failure with gcc.c-torture/execute/pr64242.c at -O2 for a
+ ;; 32-bit target when using -mtune=sifive-7-series.  The first sched pass
+ ;; runs before register elimination, and we have a non-obvious dependency
+diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
+index 492aad12324..fa6d61fc66a 100644
+--- a/gcc/config/riscv/riscv.opt
++++ b/gcc/config/riscv/riscv.opt
+@@ -136,6 +136,8 @@ Mask(64BIT)
+ 
+ Mask(MUL)
+ 
++Mask(BITMANIP)
++
+ Mask(ATOMIC)
+ 
+ Mask(HARD_FLOAT)
+-- 
+2.25.1
+

+ 0 - 25
recipes-devtools/gcc/gcc/0006-testsuite-Add-ilp32-to-g-.dg-warn-Warray-bounds-20.C.patch

@@ -1,25 +0,0 @@
-From 5964b5cd72721186ea2195a7be8d40cfe6554023 Mon Sep 17 00:00:00 2001
-From: Kito Cheng <kito.cheng@sifive.com>
-Date: Wed, 23 Jun 2021 11:14:27 +0800
-Subject: [PATCH 06/15] testsuite: Add !ilp32 to g++.dg/warn/Warray-bounds-20.C
-
----
- gcc/testsuite/g++.dg/warn/Warray-bounds-20.C | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/gcc/testsuite/g++.dg/warn/Warray-bounds-20.C b/gcc/testsuite/g++.dg/warn/Warray-bounds-20.C
-index e142ea16787..ab42ede0340 100644
---- a/gcc/testsuite/g++.dg/warn/Warray-bounds-20.C
-+++ b/gcc/testsuite/g++.dg/warn/Warray-bounds-20.C
-@@ -27,7 +27,7 @@ struct D1: virtual B, virtual C
-      to the opening brace.  */
-   D1 ()
-   {                           // { dg-warning "\\\[-Warray-bounds" "brace" }
--    ci = 0;                   // { dg-warning "\\\[-Warray-bounds" "assign" { xfail *-*-* } }
-+    ci = 0;                   // { dg-warning "\\\[-Warray-bounds" "assign" { xfail { ! ilp32 } } }
-   }
- };
- 
--- 
-2.33.1
-

+ 194 - 34
recipes-devtools/gcc/gcc/0011-Define-GLIBC_DYNAMIC_LINKER-and-UCLIBC_DYNAMIC_LINKE.patch → recipes-devtools/gcc/gcc/0007-Define-GLIBC_DYNAMIC_LINKER-and-UCLIBC_DYNAMIC_LINKE.patch

@@ -1,4 +1,4 @@
-From 8e9d6efecdc8c42f47e3a012dee764b13c3dad59 Mon Sep 17 00:00:00 2001
+From 4de00af67b57b5440bdf61ab364ad959ad0aeee7 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Fri, 29 Mar 2013 09:24:50 +0400
 Subject: [PATCH] Define GLIBC_DYNAMIC_LINKER and UCLIBC_DYNAMIC_LINKER
@@ -15,23 +15,47 @@ Removes the do_headerfix task in metadata
 Signed-off-by: Khem Raj <raj.khem@gmail.com>
 
 Upstream-Status: Inappropriate [OE configuration]
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
 ---
- gcc/config/alpha/linux-elf.h |  4 ++--
- gcc/config/arm/linux-eabi.h  |  4 ++--
- gcc/config/arm/linux-elf.h   |  2 +-
- gcc/config/i386/linux.h      |  2 +-
- gcc/config/i386/linux64.h    |  6 +++---
- gcc/config/linux.h           |  8 ++++----
- gcc/config/mips/linux.h      | 12 ++++++------
- gcc/config/riscv/linux.h     |  2 +-
- gcc/config/rs6000/linux64.h  | 15 +++++----------
- gcc/config/sh/linux.h        |  2 +-
- gcc/config/sparc/linux.h     |  2 +-
- gcc/config/sparc/linux64.h   |  4 ++--
- 12 files changed, 29 insertions(+), 34 deletions(-)
+ gcc/config/aarch64/aarch64-linux.h |  4 ++--
+ gcc/config/alpha/linux-elf.h       |  4 ++--
+ gcc/config/arm/linux-eabi.h        |  6 +++---
+ gcc/config/arm/linux-elf.h         |  2 +-
+ gcc/config/i386/linux.h            |  4 ++--
+ gcc/config/i386/linux64.h          | 12 ++++++------
+ gcc/config/linux.h                 |  8 ++++----
+ gcc/config/loongarch/gnu-user.h    |  4 ++--
+ gcc/config/microblaze/linux.h      |  4 ++--
+ gcc/config/mips/linux.h            | 18 +++++++++---------
+ gcc/config/nios2/linux.h           |  4 ++--
+ gcc/config/riscv/linux.h           |  4 ++--
+ gcc/config/rs6000/linux64.h        | 15 +++++----------
+ gcc/config/rs6000/sysv4.h          |  4 ++--
+ gcc/config/s390/linux.h            |  8 ++++----
+ gcc/config/sh/linux.h              |  4 ++--
+ gcc/config/sparc/linux.h           |  2 +-
+ gcc/config/sparc/linux64.h         |  4 ++--
+ 18 files changed, 53 insertions(+), 58 deletions(-)
 
+diff --git a/gcc/config/aarch64/aarch64-linux.h b/gcc/config/aarch64/aarch64-linux.h
+index 5e4553d79f5..877e8841eb2 100644
+--- a/gcc/config/aarch64/aarch64-linux.h
++++ b/gcc/config/aarch64/aarch64-linux.h
+@@ -21,10 +21,10 @@
+ #ifndef GCC_AARCH64_LINUX_H
+ #define GCC_AARCH64_LINUX_H
+ 
+-#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
++#define GLIBC_DYNAMIC_LINKER  SYSTEMLIBS_DIR "ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
+ 
+ #undef MUSL_DYNAMIC_LINKER
+-#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
++#define MUSL_DYNAMIC_LINKER  SYSTEMLIBS_DIR "ld-musl-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
+ 
+ #undef  ASAN_CC1_SPEC
+ #define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
 diff --git a/gcc/config/alpha/linux-elf.h b/gcc/config/alpha/linux-elf.h
-index c1dae8ca2cf..3ce2b76c1a4 100644
+index 17f16a55910..0a7be38fa63 100644
 --- a/gcc/config/alpha/linux-elf.h
 +++ b/gcc/config/alpha/linux-elf.h
 @@ -23,8 +23,8 @@ along with GCC; see the file COPYING3.  If not see
@@ -46,7 +70,7 @@ index c1dae8ca2cf..3ce2b76c1a4 100644
  #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
  #elif DEFAULT_LIBC == LIBC_GLIBC
 diff --git a/gcc/config/arm/linux-eabi.h b/gcc/config/arm/linux-eabi.h
-index 85d0136e76e..6bd95855827 100644
+index 50cc0bc6d08..17c18b27145 100644
 --- a/gcc/config/arm/linux-eabi.h
 +++ b/gcc/config/arm/linux-eabi.h
 @@ -65,8 +65,8 @@
@@ -60,8 +84,17 @@ index 85d0136e76e..6bd95855827 100644
  #define GLIBC_DYNAMIC_LINKER_DEFAULT GLIBC_DYNAMIC_LINKER_SOFT_FLOAT
  
  #define GLIBC_DYNAMIC_LINKER \
+@@ -89,7 +89,7 @@
+ #define MUSL_DYNAMIC_LINKER_E "%{mbig-endian:eb}"
+ #endif
+ #define MUSL_DYNAMIC_LINKER \
+-  "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}%{mfdpic:-fdpic}.so.1"
++  SYSTEMLIBS_DIR "ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}%{mfdpic:-fdpic}.so.1"
+ 
+ /* At this point, bpabi.h will have clobbered LINK_SPEC.  We want to
+    use the GNU/Linux version, not the generic BPABI version.  */
 diff --git a/gcc/config/arm/linux-elf.h b/gcc/config/arm/linux-elf.h
-index 0c1c4e70b6b..6bd643ade11 100644
+index df3da67c4f0..37456e9d5a4 100644
 --- a/gcc/config/arm/linux-elf.h
 +++ b/gcc/config/arm/linux-elf.h
 @@ -60,7 +60,7 @@
@@ -74,7 +107,7 @@ index 0c1c4e70b6b..6bd643ade11 100644
  #define LINUX_TARGET_LINK_SPEC  "%{h*} \
     %{static:-Bstatic} \
 diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h
-index 04b274f1654..7aafcf3ac2d 100644
+index 5d99ee56d5b..a76022c9ccc 100644
 --- a/gcc/config/i386/linux.h
 +++ b/gcc/config/i386/linux.h
 @@ -20,7 +20,7 @@ along with GCC; see the file COPYING3.  If not see
@@ -85,12 +118,13 @@ index 04b274f1654..7aafcf3ac2d 100644
 +#define GLIBC_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-linux.so.2"
  
  #undef MUSL_DYNAMIC_LINKER
- #define MUSL_DYNAMIC_LINKER "/lib/ld-musl-i386.so.1"
+-#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-i386.so.1"
++#define MUSL_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-musl-i386.so.1"
 diff --git a/gcc/config/i386/linux64.h b/gcc/config/i386/linux64.h
-index b3822ced528..92d303e80d6 100644
+index 8681e36f10d..ddce49b6b60 100644
 --- a/gcc/config/i386/linux64.h
 +++ b/gcc/config/i386/linux64.h
-@@ -27,9 +27,9 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+@@ -27,13 +27,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  #define GNU_USER_LINK_EMULATION64 "elf_x86_64"
  #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64"
  
@@ -102,12 +136,19 @@ index b3822ced528..92d303e80d6 100644
 +#define GLIBC_DYNAMIC_LINKERX32 SYSTEMLIBS_DIR "ld-linux-x32.so.2"
  
  #undef MUSL_DYNAMIC_LINKER32
- #define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-i386.so.1"
+-#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-i386.so.1"
++#define MUSL_DYNAMIC_LINKER32 SYSTEMLIBS_DIR "ld-musl-i386.so.1"
+ #undef MUSL_DYNAMIC_LINKER64
+-#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-x86_64.so.1"
++#define MUSL_DYNAMIC_LINKER64 SYSTEMLIBS_DIR "ld-musl-x86_64.so.1"
+ #undef MUSL_DYNAMIC_LINKERX32
+-#define MUSL_DYNAMIC_LINKERX32 "/lib/ld-musl-x32.so.1"
++#define MUSL_DYNAMIC_LINKERX32 SYSTEMLIBS_DIR "ld-musl-x32.so.1"
 diff --git a/gcc/config/linux.h b/gcc/config/linux.h
-index 4e1db60fced..87efc5f69fe 100644
+index 74f70793d90..4ce173384ef 100644
 --- a/gcc/config/linux.h
 +++ b/gcc/config/linux.h
-@@ -94,10 +94,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+@@ -99,10 +99,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
     GLIBC_DYNAMIC_LINKER must be defined for each target using them, or
     GLIBC_DYNAMIC_LINKER32 and GLIBC_DYNAMIC_LINKER64 for targets
     supporting both 32-bit and 64-bit compilation.  */
@@ -122,11 +163,51 @@ index 4e1db60fced..87efc5f69fe 100644
  #define BIONIC_DYNAMIC_LINKER "/system/bin/linker"
  #define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
  #define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
+diff --git a/gcc/config/loongarch/gnu-user.h b/gcc/config/loongarch/gnu-user.h
+index 664dc9206ad..082bd7cfc6f 100644
+--- a/gcc/config/loongarch/gnu-user.h
++++ b/gcc/config/loongarch/gnu-user.h
+@@ -31,11 +31,11 @@ along with GCC; see the file COPYING3.  If not see
+ 
+ #undef GLIBC_DYNAMIC_LINKER
+ #define GLIBC_DYNAMIC_LINKER \
+-  "/lib" ABI_GRLEN_SPEC "/ld-linux-loongarch-" ABI_SPEC ".so.1"
++  SYSTEMLIBS_DIR "ld-linux-loongarch-" ABI_SPEC ".so.1"
+ 
+ #undef MUSL_DYNAMIC_LINKER
+ #define MUSL_DYNAMIC_LINKER \
+-  "/lib" ABI_GRLEN_SPEC "/ld-musl-loongarch-" ABI_SPEC ".so.1"
++  SYSTEMLIBS_DIR "ld-musl-loongarch-" ABI_SPEC ".so.1"
+ 
+ #undef GNU_USER_TARGET_LINK_SPEC
+ #define GNU_USER_TARGET_LINK_SPEC \
+diff --git a/gcc/config/microblaze/linux.h b/gcc/config/microblaze/linux.h
+index 5b1a365eda4..2e63df1ae9c 100644
+--- a/gcc/config/microblaze/linux.h
++++ b/gcc/config/microblaze/linux.h
+@@ -28,7 +28,7 @@
+ #undef TLS_NEEDS_GOT
+ #define TLS_NEEDS_GOT 1
+ 
+-#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
++#define GLIBC_DYNAMIC_LINKER SYSTEMLIBS_DIR "/ld.so.1"
+ #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
+ 
+ #if TARGET_BIG_ENDIAN_DEFAULT == 0 /* LE */
+@@ -38,7 +38,7 @@
+ #endif
+ 
+ #undef MUSL_DYNAMIC_LINKER
+-#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-microblaze" MUSL_DYNAMIC_LINKER_E ".so.1"
++#define MUSL_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-musl-microblaze" MUSL_DYNAMIC_LINKER_E ".so.1"
+ 
+ #undef  SUBTARGET_EXTRA_SPECS
+ #define SUBTARGET_EXTRA_SPECS \
 diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h
-index 44a85e410d9..8d41b5574f6 100644
+index 230b7789bb8..d96d134bfcf 100644
 --- a/gcc/config/mips/linux.h
 +++ b/gcc/config/mips/linux.h
-@@ -22,20 +22,20 @@ along with GCC; see the file COPYING3.  If not see
+@@ -22,29 +22,29 @@ along with GCC; see the file COPYING3.  If not see
  #define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32"
  
  #define GLIBC_DYNAMIC_LINKER32 \
@@ -153,8 +234,35 @@ index 44a85e410d9..8d41b5574f6 100644
  
  #undef MUSL_DYNAMIC_LINKER32
  #define MUSL_DYNAMIC_LINKER32 \
+-  "/lib/ld-musl-mips%{mips32r6|mips64r6:r6}%{EL:el}%{msoft-float:-sf}.so.1"
++  SYSTEMLIBS_DIR "ld-musl-mips%{mips32r6|mips64r6:r6}%{EL:el}%{msoft-float:-sf}.so.1"
+ #undef MUSL_DYNAMIC_LINKER64
+ #define MUSL_DYNAMIC_LINKER64 \
+-  "/lib/ld-musl-mips64%{mips64r6:r6}%{EL:el}%{msoft-float:-sf}.so.1"
++  SYSTEMLIBS_DIR "ld-musl-mips64%{mips64r6:r6}%{EL:el}%{msoft-float:-sf}.so.1"
+ #define MUSL_DYNAMIC_LINKERN32 \
+-  "/lib/ld-musl-mipsn32%{mips64r6:r6}%{EL:el}%{msoft-float:-sf}.so.1"
++  SYSTEMLIBS_DIR "ld-musl-mipsn32%{mips64r6:r6}%{EL:el}%{msoft-float:-sf}.so.1"
+ 
+ #define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
+ #define GNU_USER_DYNAMIC_LINKERN32 \
+diff --git a/gcc/config/nios2/linux.h b/gcc/config/nios2/linux.h
+index f5dd813acad..7a13e1c9799 100644
+--- a/gcc/config/nios2/linux.h
++++ b/gcc/config/nios2/linux.h
+@@ -29,8 +29,8 @@
+ #undef CPP_SPEC
+ #define CPP_SPEC "%{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}"
+ 
+-#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-nios2.so.1"
+-#define MUSL_DYNAMIC_LINKER  "/lib/ld-musl-nios2.so.1"
++#define GLIBC_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-linux-nios2.so.1"
++#define MUSL_DYNAMIC_LINKER  SYSTEMLIBS_DIR "ld-musl-nios2.so.1"
+ 
+ #undef LINK_SPEC
+ #define LINK_SPEC LINK_SPEC_ENDIAN \
 diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h
-index 9238de5bc92..7136a83260a 100644
+index 38803723ba9..d5ef8a96a19 100644
 --- a/gcc/config/riscv/linux.h
 +++ b/gcc/config/riscv/linux.h
 @@ -22,7 +22,7 @@ along with GCC; see the file COPYING3.  If not see
@@ -166,11 +274,20 @@ index 9238de5bc92..7136a83260a 100644
  
  #define MUSL_ABI_SUFFIX \
    "%{mabi=ilp32:-sf}" \
+@@ -33,7 +33,7 @@ along with GCC; see the file COPYING3.  If not see
+   "%{mabi=lp64d:}"
+ 
+ #undef MUSL_DYNAMIC_LINKER
+-#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-riscv" XLEN_SPEC MUSL_ABI_SUFFIX ".so.1"
++#define MUSL_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-musl-riscv" XLEN_SPEC MUSL_ABI_SUFFIX ".so.1"
+ 
+ /* Because RISC-V only has word-sized atomics, it requries libatomic where
+    others do not.  So link libatomic by default, as needed.  */
 diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h
-index e3f2cd254f6..a11e01faa3d 100644
+index b2a7afabc73..364c1a5b155 100644
 --- a/gcc/config/rs6000/linux64.h
 +++ b/gcc/config/rs6000/linux64.h
-@@ -336,24 +336,19 @@ extern int dot_symbols;
+@@ -339,24 +339,19 @@ extern int dot_symbols;
  #undef	LINK_OS_DEFAULT_SPEC
  #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
  
@@ -200,12 +317,55 @@ index e3f2cd254f6..a11e01faa3d 100644
  
  #undef  DEFAULT_ASM_ENDIAN
  #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
+diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
+index 7e2519de5d4..a73954d9de5 100644
+--- a/gcc/config/rs6000/sysv4.h
++++ b/gcc/config/rs6000/sysv4.h
+@@ -779,10 +779,10 @@ GNU_USER_TARGET_CC1_SPEC
+ 
+ #define MUSL_DYNAMIC_LINKER_E ENDIAN_SELECT("","le","")
+ 
+-#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
++#define GLIBC_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld.so.1"
+ #undef MUSL_DYNAMIC_LINKER
+ #define MUSL_DYNAMIC_LINKER \
+-  "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"
++  SYSTEMLIBS_DIR "ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"
+ 
+ #ifndef GNU_USER_DYNAMIC_LINKER
+ #define GNU_USER_DYNAMIC_LINKER GLIBC_DYNAMIC_LINKER
+diff --git a/gcc/config/s390/linux.h b/gcc/config/s390/linux.h
+index d7b7e7a7b02..0139b4d06ca 100644
+--- a/gcc/config/s390/linux.h
++++ b/gcc/config/s390/linux.h
+@@ -72,13 +72,13 @@ along with GCC; see the file COPYING3.  If not see
+ #define MULTILIB_DEFAULTS { "m31" }
+ #endif
+ 
+-#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
+-#define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1"
++#define GLIBC_DYNAMIC_LINKER32 SYSTEMLIBS_DIR "ld.so.1"
++#define GLIBC_DYNAMIC_LINKER64 SYSTEMLIBS_DIR "ld64.so.1"
+ 
+ #undef MUSL_DYNAMIC_LINKER32
+-#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-s390.so.1"
++#define MUSL_DYNAMIC_LINKER32 SYSTEMLIBS_DIR "ld-musl-s390.so.1"
+ #undef MUSL_DYNAMIC_LINKER64
+-#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-s390x.so.1"
++#define MUSL_DYNAMIC_LINKER64 SYSTEMLIBS_DIR "ld-musl-s390x.so.1"
+ 
+ #undef  LINK_SPEC
+ #define LINK_SPEC \
 diff --git a/gcc/config/sh/linux.h b/gcc/config/sh/linux.h
-index 7558d2f7195..3aaa6c3a078 100644
+index d96d077c99e..7d27f9893ee 100644
 --- a/gcc/config/sh/linux.h
 +++ b/gcc/config/sh/linux.h
-@@ -64,7 +64,7 @@ along with GCC; see the file COPYING3.  If not see
-   "/lib/ld-musl-sh" MUSL_DYNAMIC_LINKER_E MUSL_DYNAMIC_LINKER_FP \
+@@ -61,10 +61,10 @@ along with GCC; see the file COPYING3.  If not see
+ 
+ #undef MUSL_DYNAMIC_LINKER
+ #define MUSL_DYNAMIC_LINKER \
+-  "/lib/ld-musl-sh" MUSL_DYNAMIC_LINKER_E MUSL_DYNAMIC_LINKER_FP \
++  SYSTEMLIBS_DIR "ld-musl-sh" MUSL_DYNAMIC_LINKER_E MUSL_DYNAMIC_LINKER_FP \
    "%{mfdpic:-fdpic}.so.1"
  
 -#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
@@ -214,7 +374,7 @@ index 7558d2f7195..3aaa6c3a078 100644
  #undef SUBTARGET_LINK_EMUL_SUFFIX
  #define SUBTARGET_LINK_EMUL_SUFFIX "%{mfdpic:_fd;:_linux}"
 diff --git a/gcc/config/sparc/linux.h b/gcc/config/sparc/linux.h
-index 2550d7ee8f0..a94f4cd8ba2 100644
+index 6a809e9092d..60603765ad6 100644
 --- a/gcc/config/sparc/linux.h
 +++ b/gcc/config/sparc/linux.h
 @@ -78,7 +78,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
@@ -227,7 +387,7 @@ index 2550d7ee8f0..a94f4cd8ba2 100644
  #undef  LINK_SPEC
  #define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
 diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h
-index 95af8afa9b5..63127afb074 100644
+index d08a2ef96fe..e6955da0a5b 100644
 --- a/gcc/config/sparc/linux64.h
 +++ b/gcc/config/sparc/linux64.h
 @@ -78,8 +78,8 @@ along with GCC; see the file COPYING3.  If not see

+ 488 - 0
recipes-devtools/gcc/gcc/0007-add-initial-dubhe-scheduling-model.patch

@@ -0,0 +1,488 @@
+From bda438df2f20aa476cfdfedca5ce017718a1eefd Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Thu, 1 Sep 2022 01:41:52 -0700
+Subject: [PATCH 07/11] add initial dubhe scheduling model
+
+---
+ gcc/config/riscv/bitmanip.md     | 96 ++++++++++++++++++++++----------
+ gcc/config/riscv/riscv-cores.def |  2 +
+ gcc/config/riscv/riscv-opts.h    |  3 +-
+ gcc/config/riscv/riscv.cc        | 23 +++++++-
+ gcc/config/riscv/riscv.md        | 47 ++--------------
+ 5 files changed, 98 insertions(+), 73 deletions(-)
+
+diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
+index 0ab9ffe3c0b..86ac00d9a76 100644
+--- a/gcc/config/riscv/bitmanip.md
++++ b/gcc/config/riscv/bitmanip.md
+@@ -62,7 +62,7 @@
+   "TARGET_ZBA
+    && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)"
+   "sh%2add\t%0,%1,%3"
+-  [(set_attr "type" "bitmanip")
++  [(set_attr "type" "bshiftadd")
+    (set_attr "mode" "<X:MODE>")])
+ 
+ (define_insn "*shNadduw"
+@@ -76,7 +76,7 @@
+    && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
+    && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
+   "sh%2add.uw\t%0,%1,%4"
+-  [(set_attr "type" "bitmanip")
++  [(set_attr "type" "bshiftadd")
+    (set_attr "mode" "DI")])
+ 
+ (define_insn "*add.uw"
+@@ -86,7 +86,7 @@
+ 		 (match_operand:DI 2 "register_operand" "r")))]
+   "TARGET_64BIT && TARGET_ZBA"
+   "add.uw\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")
++  [(set_attr "type" "bopext")
+    (set_attr "mode" "DI")])
+ 
+ (define_insn "*slliuw"
+@@ -97,7 +97,7 @@
+   "TARGET_64BIT && TARGET_ZBA
+    && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
+   "slli.uw\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")
++  [(set_attr "type" "bopext")
+    (set_attr "mode" "DI")])
+ 
+ ;; ZBB extension.
+@@ -108,7 +108,7 @@
+                             (match_operand:X 2 "register_operand" "r")))]
+   "TARGET_ZBB"
+   "<insn>n\t%0,%2,%1"
+-  [(set_attr "type" "bitmanip")
++  [(set_attr "type" "blogic_neg")
+    (set_attr "mode" "<X:MODE>")])
+ 
+ (define_insn "*xor_not<mode>"
+@@ -117,7 +117,7 @@
+                       (match_operand:X 2 "register_operand" "r"))))]
+   "TARGET_ZBB"
+   "xnor\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")
++  [(set_attr "type" "blogic_neg")
+    (set_attr "mode" "<X:MODE>")])
+ 
+ (define_insn "<bitmanip_optab>si2"
+@@ -125,16 +125,17 @@
+         (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))]
+   "TARGET_ZBB"
+   { return TARGET_64BIT ? "<bitmanip_insn>w\t%0,%1" : "<bitmanip_insn>\t%0,%1"; }
+-  [(set_attr "type" "bitmanip")
++  [(set_attr "type" "bcount_bit")
+    (set_attr "mode" "SI")])
+ 
++
+ (define_insn "*<bitmanip_optab>disi2"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+         (sign_extend:DI
+           (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))]
+   "TARGET_64BIT && TARGET_ZBB"
+   "<bitmanip_insn>w\t%0,%1"
+-  [(set_attr "type" "bitmanip")
++  [(set_attr "type" "bcount_bit")
+    (set_attr "mode" "SI")])
+ 
+ (define_insn "<bitmanip_optab>di2"
+@@ -142,7 +143,7 @@
+         (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))]
+   "TARGET_64BIT && TARGET_ZBB"
+   "<bitmanip_insn>\t%0,%1"
+-  [(set_attr "type" "bitmanip")
++  [(set_attr "type" "bcount_bit")
+    (set_attr "mode" "DI")])
+ 
+ (define_insn "*zero_extendhi<GPR:mode>2_bitmanip"
+@@ -155,6 +156,7 @@
+   [(set_attr "type" "bitmanip,load")
+    (set_attr "mode" "<GPR:MODE>")])
+ 
++
+ (define_insn "*extend<SHORT:mode><SUPERQI:mode>2_zbb"
+   [(set (match_operand:SUPERQI   0 "register_operand"     "=r,r")
+ 	(sign_extend:SUPERQI
+@@ -183,7 +185,7 @@
+ 		     (match_operand:QI 2 "arith_operand" "rI")))]
+   "TARGET_ZBB"
+   { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; }
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "brorate")])
+ 
+ (define_insn "rotrdi3"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+@@ -191,7 +193,7 @@
+ 		     (match_operand:QI 2 "arith_operand" "rI")))]
+   "TARGET_64BIT && TARGET_ZBB"
+   "ror%i2\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "brorate")])
+ 
+ (define_insn "rotrsi3_sext"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+@@ -199,7 +201,7 @@
+ 				     (match_operand:QI 2 "register_operand" "r"))))]
+   "TARGET_64BIT && TARGET_ZBB"
+   "rorw\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "brorate")])
+ 
+ (define_insn "rotlsi3"
+   [(set (match_operand:SI 0 "register_operand" "=r")
+@@ -207,7 +209,7 @@
+ 		   (match_operand:QI 2 "register_operand" "r")))]
+   "TARGET_ZBB"
+   { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; }
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "brorate")])
+ 
+ (define_insn "rotldi3"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+@@ -215,7 +217,7 @@
+ 		   (match_operand:QI 2 "register_operand" "r")))]
+   "TARGET_64BIT && TARGET_ZBB"
+   "rol\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "brorate")])
+ 
+ (define_insn "rotlsi3_sext"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+@@ -223,14 +225,14 @@
+ 				   (match_operand:QI 2 "register_operand" "r"))))]
+   "TARGET_64BIT && TARGET_ZBB"
+   "rolw\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "brorate")])
+ 
+ (define_insn "bswap<mode>2"
+   [(set (match_operand:X 0 "register_operand" "=r")
+         (bswap:X (match_operand:X 1 "register_operand" "r")))]
+   "TARGET_64BIT && TARGET_ZBB"
+   "rev8\t%0,%1"
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "bperm")])
+ 
+ (define_insn "<bitmanip_optab><mode>3"
+   [(set (match_operand:X 0 "register_operand" "=r")
+@@ -238,7 +240,7 @@
+ 			   (match_operand:X 2 "register_operand" "r")))]
+   "TARGET_ZBB"
+   "<bitmanip_insn>\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "bcount_bit")])
+ 
+ ;; ZBS extension.
+ 
+@@ -249,7 +251,7 @@
+ 	       (match_operand:X 1 "register_operand" "r")))]
+   "TARGET_ZBS"
+   "bset\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "bsbit")])
+ 
+ (define_insn "*bset<mode>_mask"
+   [(set (match_operand:X 0 "register_operand" "=r")
+@@ -260,7 +262,7 @@
+ 	       (match_operand:X 1 "register_operand" "r")))]
+   "TARGET_ZBS"
+   "bset\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "bsbit")])
+ 
+ (define_insn "*bset<mode>_1"
+   [(set (match_operand:X 0 "register_operand" "=r")
+@@ -268,7 +270,7 @@
+ 		  (match_operand:QI 1 "register_operand" "r")))]
+   "TARGET_ZBS"
+   "bset\t%0,x0,%1"
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "bsbit")])
+ 
+ (define_insn "*bset<mode>_1_mask"
+   [(set (match_operand:X 0 "register_operand" "=r")
+@@ -278,7 +280,7 @@
+ 			  (match_operand 2 "<X:shiftm1>" "i")) 0)))]
+   "TARGET_ZBS"
+   "bset\t%0,x0,%1"
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "bsbit")])
+ 
+ (define_insn "*bseti<mode>"
+   [(set (match_operand:X 0 "register_operand" "=r")
+@@ -286,7 +288,7 @@
+ 	       (match_operand 2 "single_bit_mask_operand" "i")))]
+   "TARGET_ZBS"
+   "bseti\t%0,%1,%S2"
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "bsbit")])
+ 
+ (define_insn "*bclr<mode>"
+   [(set (match_operand:X 0 "register_operand" "=r")
+@@ -295,7 +297,7 @@
+ 	       (match_operand:X 1 "register_operand" "r")))]
+   "TARGET_ZBS"
+   "bclr\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "bsbit")])
+ 
+ (define_insn "*bclri<mode>"
+   [(set (match_operand:X 0 "register_operand" "=r")
+@@ -303,7 +305,7 @@
+ 	       (match_operand 2 "not_single_bit_mask_operand" "i")))]
+   "TARGET_ZBS"
+   "bclri\t%0,%1,%T2"
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "bsbit")])
+ 
+ (define_insn "*binv<mode>"
+   [(set (match_operand:X 0 "register_operand" "=r")
+@@ -312,7 +314,7 @@
+ 	       (match_operand:X 1 "register_operand" "r")))]
+   "TARGET_ZBS"
+   "binv\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "bsbit")])
+ 
+ (define_insn "*binvi<mode>"
+   [(set (match_operand:X 0 "register_operand" "=r")
+@@ -320,7 +322,7 @@
+ 	       (match_operand 2 "single_bit_mask_operand" "i")))]
+   "TARGET_ZBS"
+   "binvi\t%0,%1,%S2"
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "bsbit")])
+ 
+ (define_insn "*bext<mode>"
+   [(set (match_operand:X 0 "register_operand" "=r")
+@@ -330,7 +332,7 @@
+ 			 (match_operand:QI 2 "register_operand" "r"))))]
+   "TARGET_ZBS"
+   "bext\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "bsbit")])
+ 
+ (define_insn "*bexti"
+   [(set (match_operand:X 0 "register_operand" "=r")
+@@ -339,4 +341,42 @@
+ 			(match_operand 2 "immediate_operand" "i")))]
+   "TARGET_ZBS"
+   "bexti\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
++  [(set_attr "type" "bopext")])
++
++(define_insn "riscv_orc_b"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
++  "TARGET_ZBB"
++  "orc.b\t%0,%1,%2"
++  [(set_attr "type" "bperm")])
++
++(define_insn "riscv_rev8"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
++  "TARGET_ZBB"
++  "rev8\t%0,%1,%2"
++  [(set_attr "type" "bperm")])
++
++(define_insn "riscv_clmul"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
++				   (match_operand:SI 2 "register_operand" "r"))))]
++  "TARGET_ZBC"
++  "clmul\t%0,%1,%2"
++  [(set_attr "type" "bclmul")])
++
++(define_insn "riscv_clmulh"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
++				   (match_operand:SI 2 "register_operand" "r"))))]
++  "TARGET_ZBC"
++  "clmulh\t%0,%1,%2"
++  [(set_attr "type" "bclmul")])
++
++(define_insn "riscv_clmulr"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
++				   (match_operand:SI 2 "register_operand" "r"))))]
++  "TARGET_ZBC"
++  "clmulr\t%0,%1,%2"
++  [(set_attr "type" "bclmul")])
+\ No newline at end of file
+diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
+index ecb5e213d98..051c9c5d05f 100644
+--- a/gcc/config/riscv/riscv-cores.def
++++ b/gcc/config/riscv/riscv-cores.def
+@@ -45,5 +45,7 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
+ 
+ RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
+ RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
++RISCV_CORE("starfive-dubhe",      "rv64imafdc", "starfive-dubhe-series")
++
+ 
+ #undef RISCV_CORE
+diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
+index 15bb5e76854..fcb1aaa4ba1 100644
+--- a/gcc/config/riscv/riscv-opts.h
++++ b/gcc/config/riscv/riscv-opts.h
+@@ -52,7 +52,8 @@ extern enum riscv_isa_spec_class riscv_isa_spec;
+ /* Keep this list in sync with define_attr "tune" in riscv.md.  */
+ enum riscv_microarchitecture_type {
+   generic,
+-  sifive_7
++  sifive_7,
++  starfive_dubhe
+ };
+ extern enum riscv_microarchitecture_type riscv_microarchitecture;
+ 
+diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
+index ec7030f6c2e..3baa05bd364 100644
+--- a/gcc/config/riscv/riscv.cc
++++ b/gcc/config/riscv/riscv.cc
+@@ -301,6 +301,19 @@ static const struct riscv_tune_param sifive_7_tune_info = {
+   true,						/* slow_unaligned_access */
+ };
+ 
++/* Costs to use when optimizing for dubhe.  */
++static const struct riscv_tune_param starfive_dubhe_tune_info = {
++  {COSTS_N_INSNS (6), COSTS_N_INSNS (6)},	/* fp_add */
++  {COSTS_N_INSNS (6), COSTS_N_INSNS (6)},	/* fp_mul */
++  {COSTS_N_INSNS (20), COSTS_N_INSNS (20)},	/* fp_div */
++  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},	/* int_mul */
++  {COSTS_N_INSNS (6), COSTS_N_INSNS (6)},	/* int_div */
++  8,						/* issue_rate */
++  1,						/* branch_cost */
++  3,						/* memory_cost */
++  true,						/* slow_unaligned_access */
++};
++
+ /* Costs to use when optimizing for T-HEAD c906.  */
+ static const struct riscv_tune_param thead_c906_tune_info = {
+   {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
+@@ -327,6 +340,7 @@ static const struct riscv_tune_param optimize_size_tune_info = {
+   false,					/* slow_unaligned_access */
+ };
+ 
++
+ static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
+ static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);
+ 
+@@ -361,7 +375,7 @@ static const struct riscv_tune_info riscv_tune_info_table[] = {
+   { "rocket", generic, &rocket_tune_info },
+   { "sifive-3-series", generic, &rocket_tune_info },
+   { "sifive-5-series", generic, &rocket_tune_info },
+-  { "sifive-7-series", sifive_7, &sifive_7_tune_info },
++  { "starfive-dubhe-series", starfive_dubhe, &starfive_dubhe_tune_info },  
+   { "thead-c906", generic, &thead_c906_tune_info },
+   { "size", generic, &optimize_size_tune_info },
+ };
+@@ -4763,12 +4777,15 @@ riscv_secondary_memory_needed (machine_mode mode, reg_class_t class1,
+ 	  && (class1 == FP_REGS) != (class2 == FP_REGS));
+ }
+ 
+-/* Implement TARGET_REGISTER_MOVE_COST.  */
+-
+ static int
+ riscv_register_move_cost (machine_mode mode,
+ 			  reg_class_t from, reg_class_t to)
+ {
++  /* do not move between fp and int registers.  */
++  if (from == FP_REGS && to == GR_REGS || from == GR_REGS && to == FP_REGS)
++    return 20;
++    
++
+   return riscv_secondary_memory_needed (mode, from, to) ? 8 : 2;
+ }
+ 
+diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
+index e56979ca800..1bcc6d49391 100644
+--- a/gcc/config/riscv/riscv.md
++++ b/gcc/config/riscv/riscv.md
+@@ -169,10 +169,12 @@
+ ;; nop		no operation
+ ;; ghost	an instruction that produces no real code
+ ;; bitmanip	bit manipulation instructions
++;; 
+ (define_attr "type"
+   "unknown,branch,jump,call,load,fpload,store,fpstore,
+    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
+-   fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate"
++   fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,
++   bopext,bshiftadd,brorate,blogic_neg,bminmax,bcount_bit,bclmul,bsbit,bperm"
+   (cond [(eq_attr "got" "load") (const_string "load")
+ 
+ 	 ;; If a doubleword move uses these expensive instructions,
+@@ -254,7 +256,7 @@
+ ;; Microarchitectures we know how to tune for.
+ ;; Keep this in sync with enum riscv_microarchitecture.
+ (define_attr "tune"
+-  "generic,sifive_7"
++  "generic,sifive_7, starfive_dubhe"
+   (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)")))
+ 
+ ;; Describe a user's asm statement.
+@@ -308,7 +310,7 @@
+ ;; instruction.
+ (define_mode_attr size [(QI "b") (HI "h")])
+ 
+-;; Mode attributes for loads.
++;; Mode attriutes for loads.
+ (define_mode_attr load [(QI "lb") (HI "lh") (SI "lw") (DI "ld") (SF "flw") (DF "fld")])
+ 
+ ;; Instruction names for integer loads that aren't explicitly sign or zero
+@@ -2767,44 +2769,6 @@
+   [(set_attr "length" "0")]
+ )
+ 
+-(define_insn "riscv_orc_b"
+-  [(set (match_operand:SI 0 "register_operand" "=r")
+-	(sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
+-  "TARGET_ZBB"
+-  "orc.b\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
+-
+-(define_insn "riscv_rev8"
+-  [(set (match_operand:SI 0 "register_operand" "=r")
+-	(sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
+-  "TARGET_ZBB"
+-  "rev8\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
+-
+-(define_insn "riscv_clmul"
+-  [(set (match_operand:SI 0 "register_operand" "=r")
+-	(sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
+-				   (match_operand:SI 2 "register_operand" "r"))))]
+-  "TARGET_ZBC"
+-  "clmul\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
+-
+-(define_insn "riscv_clmulh"
+-  [(set (match_operand:SI 0 "register_operand" "=r")
+-	(sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
+-				   (match_operand:SI 2 "register_operand" "r"))))]
+-  "TARGET_ZBC"
+-  "clmulh\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
+-
+-(define_insn "riscv_clmulr"
+-  [(set (match_operand:SI 0 "register_operand" "=r")
+-	(sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
+-				   (match_operand:SI 2 "register_operand" "r"))))]
+-  "TARGET_ZBC"
+-  "clmulr\t%0,%1,%2"
+-  [(set_attr "type" "bitmanip")])
+-
+ ;; This fixes a failure with gcc.c-torture/execute/pr64242.c at -O2 for a
+ ;; 32-bit target when using -mtune=sifive-7-series.  The first sched pass
+ ;; runs before register elimination, and we have a non-obvious dependency
+@@ -2907,3 +2871,4 @@
+ (include "pic.md")
+ (include "generic.md")
+ (include "sifive-7.md")
++(include "starfive-dubhe.md")
+-- 
+2.25.1
+

+ 0 - 131
recipes-devtools/gcc/gcc/0007-merge-from-riscv-gcc-10.2.0-to-support-bitmanip.patch

@@ -1,131 +0,0 @@
-From 2441e7b302dc5f3805b61b3a675adb80de35fb4b Mon Sep 17 00:00:00 2001
-From: "yilun.xie" <yilun.xie@starfivetech.com>
-Date: Sat, 9 Oct 2021 10:41:17 +0800
-Subject: [PATCH 07/15] merge from riscv-gcc-10.2.0 to support bitmanip
-
----
- gcc/common/config/riscv/riscv-common.c | 32 ++++++++++++++++++++++++++
- gcc/config/riscv/riscv-opts.h          | 22 ++++++++++++++++++
- gcc/config/riscv/riscv.opt             |  5 ++++
- 3 files changed, 59 insertions(+)
-
-diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
-index 34b74e52a2d..c7b6158af4b 100644
---- a/gcc/common/config/riscv/riscv-common.c
-+++ b/gcc/common/config/riscv/riscv-common.c
-@@ -50,6 +50,16 @@ static const riscv_implied_info_t riscv_implied_info[] =
-   {"d", "f"},
-   {"f", "zicsr"},
-   {"d", "zicsr"},
-+  {"b", "zbb"},
-+  {"b", "zbs"},
-+  {"b", "zba"},
-+  {"b", "zbp"},
-+  {"b", "zbe"},
-+  {"b", "zbf"},
-+  {"b", "zbc"},
-+  {"b", "zbm"},
-+  {"b", "zbr"},
-+  {"b", "zbt"},
-   {NULL, NULL}
- };
- 
-@@ -101,6 +111,17 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
-   {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
-   {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
- 
-+  {"b",   ISA_SPEC_CLASS_NONE, 0, 93},
-+  {"zba", ISA_SPEC_CLASS_NONE, 0, 93},
-+  {"zbb", ISA_SPEC_CLASS_NONE, 0, 93},
-+  {"zbc", ISA_SPEC_CLASS_NONE, 0, 93},
-+  {"zbe", ISA_SPEC_CLASS_NONE, 0, 93},
-+  {"zbf", ISA_SPEC_CLASS_NONE, 0, 93},
-+  {"zbr", ISA_SPEC_CLASS_NONE, 0, 93},
-+  {"zbm", ISA_SPEC_CLASS_NONE, 0, 93},
-+  {"zbs", ISA_SPEC_CLASS_NONE, 0, 93},
-+  {"zbt", ISA_SPEC_CLASS_NONE, 0, 93},
-+  {"zbp", ISA_SPEC_CLASS_NONE, 0, 93},
-   /* Terminate the list.  */
-   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
- };
-@@ -900,10 +921,21 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
-   {"f", &gcc_options::x_target_flags, MASK_HARD_FLOAT},
-   {"d", &gcc_options::x_target_flags, MASK_DOUBLE_FLOAT},
-   {"c", &gcc_options::x_target_flags, MASK_RVC},
-+  {"b", &gcc_options::x_target_flags, MASK_BITMANIP},
- 
-   {"zicsr",    &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
-   {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
- 
-+  {"zba", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBA},
-+  {"zbb", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBB},
-+  {"zbs", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBS},
-+  {"zbp", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBP},
-+  {"zbr", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBR},
-+  {"zbe", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBE},
-+  {"zbf", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBF},
-+  {"zbc", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBC},
-+  {"zbm", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBM},
-+  {"zbt", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBT},
-   {NULL, NULL, 0}
- };
- 
-diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
-index f4cf6ca4b82..ca3190b6414 100644
---- a/gcc/config/riscv/riscv-opts.h
-+++ b/gcc/config/riscv/riscv-opts.h
-@@ -67,6 +67,28 @@ enum stack_protector_guard {
-   SSP_GLOBAL			/* global canary */
- };
- 
-+#define MASK_ZBA (1 << 0)
-+#define MASK_ZBB (1 << 1)
-+#define MASK_ZBS (1 << 2)
-+#define MASK_ZBP (1 << 3)
-+#define MASK_ZBE (1 << 4)
-+#define MASK_ZBF (1 << 5)
-+#define MASK_ZBC (1 << 6)
-+#define MASK_ZBR (1 << 7)
-+#define MASK_ZBM (1 << 8)
-+#define MASK_ZBT (1 << 9)
-+
-+#define TARGET_ZBA ((riscv_bitmanip_subext & MASK_ZBA) != 0)
-+#define TARGET_ZBB ((riscv_bitmanip_subext & MASK_ZBB) != 0)
-+#define TARGET_ZBS ((riscv_bitmanip_subext & MASK_ZBS) != 0)
-+#define TARGET_ZBP ((riscv_bitmanip_subext & MASK_ZBP) != 0)
-+#define TARGET_ZBE ((riscv_bitmanip_subext & MASK_ZBE) != 0)
-+#define TARGET_ZBF ((riscv_bitmanip_subext & MASK_ZBF) != 0)
-+#define TARGET_ZBC ((riscv_bitmanip_subext & MASK_ZBC) != 0)
-+#define TARGET_ZBR ((riscv_bitmanip_subext & MASK_ZBR) != 0)
-+#define TARGET_ZBM ((riscv_bitmanip_subext & MASK_ZBM) != 0)
-+#define TARGET_ZBT ((riscv_bitmanip_subext & MASK_ZBT) != 0)
-+
- #define MASK_ZICSR    (1 << 0)
- #define MASK_ZIFENCEI (1 << 1)
- 
-diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
-index e294e223151..0e73e2ab758 100644
---- a/gcc/config/riscv/riscv.opt
-+++ b/gcc/config/riscv/riscv.opt
-@@ -136,6 +136,8 @@ Mask(64BIT)
- 
- Mask(MUL)
- 
-+Mask(BITMANIP)
-+
- Mask(ATOMIC)
- 
- Mask(HARD_FLOAT)
-@@ -195,6 +197,9 @@ long riscv_stack_protector_guard_offset = 0
- TargetVariable
- int riscv_zi_subext
- 
-+TargetVariable
-+int riscv_bitmanip_subext
-+
- Enum
- Name(isa_spec_class) Type(enum riscv_isa_spec_class)
- Supported ISA specs (for use with the -misa-spec= option):
--- 
-2.33.1
-

+ 177 - 0
recipes-devtools/gcc/gcc/0008-add-dubhe-.md-file.patch

@@ -0,0 +1,177 @@
+From 66b69324b10c9aeeab4ed19a4d247bec2f732afb Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Tue, 13 Sep 2022 01:22:47 -0700
+Subject: [PATCH 08/11] add dubhe .md file
+
+---
+ gcc/config/riscv/starfive-dubhe.md | 158 +++++++++++++++++++++++++++++
+ 1 file changed, 158 insertions(+)
+ create mode 100644 gcc/config/riscv/starfive-dubhe.md
+
+diff --git a/gcc/config/riscv/starfive-dubhe.md b/gcc/config/riscv/starfive-dubhe.md
+new file mode 100644
+index 00000000000..6cb288d2fd6
+--- /dev/null
++++ b/gcc/config/riscv/starfive-dubhe.md
+@@ -0,0 +1,158 @@
++(define_automaton "starfive_dubhe")
++
++(define_cpu_unit "dubhe_alu0" "starfive_dubhe")
++(define_cpu_unit "dubhe_alu1" "starfive_dubhe")
++
++(define_cpu_unit "dubhe_bru" "starfive_dubhe")
++
++(define_cpu_unit "dubhe_div" "starfive_dubhe")
++
++(define_cpu_unit "dubhe_lsu0" "starfive_dubhe")
++(define_cpu_unit "dubhe_lsu1" "starfive_dubhe")
++
++(define_cpu_unit "dubhe_fpu0" "starfive_dubhe")
++(define_cpu_unit "dubhe_fpu1" "starfive_dubhe")
++(define_cpu_unit "dubhe_fpu0_resource" "starfive_dubhe")
++
++(define_insn_reservation "dubhe_load" 3
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "load"))
++  "dubhe_lsu0 | dubhe_lsu1")
++
++(define_insn_reservation "dubhe_fpload" 3
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "fpload"))
++  "dubhe_lsu0 | dubhe_lsu1")
++
++(define_insn_reservation "dubhe_store"  1
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "store"))
++  "dubhe_lsu0 | dubhe_lsu1")
++
++(define_insn_reservation "dubhe_fpstore" 1
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "fpstore"))
++  "dubhe_lsu0 | dubhe_lsu1")
++
++(define_insn_reservation "dubhe_branch" 1
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "branch"))
++  "dubhe_bru")
++
++(define_insn_reservation "dubhe_jump"  4
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "jump,call"))
++  "dubhe_bru")
++
++(define_insn_reservation "dubhe_alu"  1  
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "unknown,arith,shift,slt,multi,logical,move"))
++  "dubhe_alu0|dubhe_alu1|dubhe_div")
++
++(define_insn_reservation "dubhe_sfb_alu"  4
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "sfb_alu"))
++  "(dubhe_alu0|dubhe_alu1)+dubhe_bru")
++
++(define_insn_reservation "dubhe_mul"    3
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "imul"))
++  "dubhe_div")
++
++(define_insn_reservation "dubhe_div" 45
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "idiv"))
++  "dubhe_div,sifive_7_idiv*45")
++
++(define_insn_reservation "dubhe_load_immediate"  1
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "nop,const,auipc"))
++  "dubhe_alu0|dubhe_alu1")
++
++(define_insn_reservation "dubhe_sfma"   6
++  (and (eq_attr "tune" "starfive_dubhe")
++       (and (eq_attr "type" "fadd,fmul,fmadd")
++	    (eq_attr "mode" "SF")))
++  "dubhe_fpu0 | dubhe_fpu1")
++
++(define_insn_reservation "dubhe_dfma" 6
++  (and (eq_attr "tune" "starfive_dubhe")
++       (and (eq_attr "type" "fadd,fmul,fmadd")
++	    (eq_attr "mode" "DF")))
++  "dubhe_fpu0 | dubhe_fpu1")
++
++(define_insn_reservation "dubhe_fp_other" 3
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "fcvt,fcmp,fmove"))
++  "dubhe_fpu1")
++
++(define_insn_reservation "dubhe_7_fdiv_s" 31
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "fdiv,fsqrt")
++       (eq_attr "mode" "SF"))
++  "dubhe_fpu0,dubhe_fpu0_resource*31")
++
++(define_insn_reservation "dubhe_fdiv_d" 60
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "fdiv,fsqrt")
++       (eq_attr "mode" "DF"))
++  "dubhe_fpu0,dubhe_fpu0_resource*60")
++
++(define_insn_reservation "dubhe_i2f" 3
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "mtc"))
++  "dubhe_alu0|dubhe_alu1") 
++
++(define_insn_reservation "dubhe_f2i" 3
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "mfc"))
++  "dubhe_alu0|dubhe_alu1")
++
++
++(define_insn_reservation "dubhe_opext" 1
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "bopext"))
++  "dubhe_alu0|dubhe_alu1")
++
++(define_insn_reservation "dubhe_shiftadd" 1
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "bshiftadd"))
++  "dubhe_alu0|dubhe_alu1|dubhe_div")
++
++(define_insn_reservation "dubhe_rorate" 2
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "brorate"))
++  "dubhe_alu0|dubhe_alu1|dubhe_div")
++
++(define_insn_reservation "dubhe_lneg" 1
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "blogic_neg"))
++  "dubhe_alu0|dubhe_alu1|dubhe_div")
++
++(define_insn_reservation "dubhe_count_bit" 3
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "bcount_bit"))
++  "dubhe_div")
++
++(define_insn_reservation "dubhe_minmax" 2
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "blogic_neg"))
++  "dubhe_alu0|dubhe_alu1|dubhe_div")
++
++(define_insn_reservation "dubhe_cmul" 10
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "bclmul"))
++  "dubhe_div")
++
++(define_insn_reservation "dubhe_bitset" 2
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "bsbit"))
++  "dubhe_alu0|dubhe_alu1|dubhe_div")
++
++(define_insn_reservation "dubhe_perm" 4
++  (and (eq_attr "tune" "starfive_dubhe")
++       (eq_attr "type" "bperm"))
++  "dubhe_div")
++
++
++
+-- 
+2.25.1
+

+ 0 - 43
recipes-devtools/gcc/gcc/0008-fortran-cross-compile-hack.patch

@@ -1,43 +0,0 @@
-From 904d102e3ccb93296b16ceb2e283a6ccf3c1d718 Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Fri, 29 Mar 2013 09:20:01 +0400
-Subject: [PATCH] fortran cross-compile hack.
-
-* Fortran would have searched for arm-angstrom-gnueabi-gfortran but would have used
-used gfortan. For gcc_4.2.2.bb we want to use the gfortran compiler from our cross
-directory.
-
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
-
-Upstream-Status: Inappropriate [embedded specific]
----
- libgfortran/configure    | 2 +-
- libgfortran/configure.ac | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/libgfortran/configure b/libgfortran/configure
-index f3634389cf8..f974e874b8e 100755
---- a/libgfortran/configure
-+++ b/libgfortran/configure
-@@ -13102,7 +13102,7 @@ esac
- 
- # We need gfortran to compile parts of the library
- #AC_PROG_FC(gfortran)
--FC="$GFORTRAN"
-+#FC="$GFORTRAN"
- ac_ext=${ac_fc_srcext-f}
- ac_compile='$FC -c $FCFLAGS $ac_fcflags_srcext conftest.$ac_ext >&5'
- ac_link='$FC -o conftest$ac_exeext $FCFLAGS $LDFLAGS $ac_fcflags_srcext conftest.$ac_ext $LIBS >&5'
-diff --git a/libgfortran/configure.ac b/libgfortran/configure.ac
-index 8961e314d82..49c8221cb6b 100644
---- a/libgfortran/configure.ac
-+++ b/libgfortran/configure.ac
-@@ -271,7 +271,7 @@ AC_SUBST(enable_static)
- 
- # We need gfortran to compile parts of the library
- #AC_PROG_FC(gfortran)
--FC="$GFORTRAN"
-+#FC="$GFORTRAN"
- AC_PROG_FC(gfortran)
- 
- # extra LD Flags which are required for targets

+ 1 - 1
recipes-devtools/gcc/gcc/0014-libtool.patch → recipes-devtools/gcc/gcc/0008-libtool.patch

@@ -1,4 +1,4 @@
-From a5b984db9669cf38a7bd76c3fcdb41c086f740db Mon Sep 17 00:00:00 2001
+From 5117519c1897a49b09fe7fff213b9c2ea15d37f5 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Fri, 29 Mar 2013 09:29:11 +0400
 Subject: [PATCH] libtool

+ 0 - 1542
recipes-devtools/gcc/gcc/0008-merge-from-riscv-gcc-10.2.0-to-support-bitmanip.patch

@@ -1,1542 +0,0 @@
-From 461f89263df4d8c27a2a99a9e0561e016e2752c6 Mon Sep 17 00:00:00 2001
-From: "yilun.xie" <yilun.xie@starfivetech.com>
-Date: Sat, 9 Oct 2021 10:43:19 +0800
-Subject: [PATCH 08/15] merge from riscv-gcc-10.2.0 to support bitmanip
-
----
- gcc/config/riscv/bitmanip.md |  482 ++++++++++++++++
- gcc/config/riscv/rvintrin.h  | 1033 ++++++++++++++++++++++++++++++++++
- 2 files changed, 1515 insertions(+)
- create mode 100644 gcc/config/riscv/bitmanip.md
- create mode 100644 gcc/config/riscv/rvintrin.h
-
-diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
-new file mode 100644
-index 00000000000..6653219c3f0
---- /dev/null
-+++ b/gcc/config/riscv/bitmanip.md
-@@ -0,0 +1,482 @@
-+;; Machine description for RISC-V Bit Manipulation operations.
-+;; Copyright (C) 2019 Free Software Foundation, Inc.
-+
-+;; This file is part of GCC.
-+
-+;; GCC is free software; you can redistribute it and/or modify
-+;; it under the terms of the GNU General Public License as published by
-+;; the Free Software Foundation; either version 3, or (at your option)
-+;; any later version.
-+
-+;; GCC is distributed in the hope that it will be useful,
-+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+;; GNU General Public License for more details.
-+
-+;; You should have received a copy of the GNU General Public License
-+;; along with GCC; see the file COPYING3.  If not see
-+;; <http://www.gnu.org/licenses/>.
-+
-+(define_code_iterator bitmanip_bitwise [and ior])
-+
-+(define_code_iterator any_minmax [smin smax umin umax])
-+
-+(define_code_iterator clz_ctz_pcnt [clz ctz popcount])
-+
-+(define_code_attr bitmanip_optab [(smin "smin")
-+				  (smax "smax")
-+				  (umin "umin")
-+				  (umax "umax")
-+				  (clz "clz")
-+				  (ctz "ctz")
-+				  (popcount "popcount")])
-+
-+(define_code_attr bitmanip_insn [(smin "min")
-+				 (smax "max")
-+				 (umin "minu")
-+				 (umax "maxu")
-+				 (clz "clz")
-+				 (ctz "ctz")
-+				 (popcount "cpop")])
-+
-+(define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")])
-+
-+(define_insn "<bitmanip_optab>si2"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+	(clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))]
-+  "TARGET_ZBB"
-+  { return TARGET_64BIT ? "<bitmanip_insn>w\t%0,%1" : "<bitmanip_insn>\t%0,%1"; }
-+  [(set_attr "type" "bitmanip")])
-+
-+;; TODO: In theory zero_extend should be OK to combine too, since the output
-+;;       range is 0 ~ 32, zero_extend or sign_extend will get same result.
-+(define_insn "*<bitmanip_optab>disi2"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(sign_extend:DI
-+	  (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))]
-+  "TARGET_64BIT && TARGET_ZBB"
-+  "<bitmanip_insn>w\t%0,%1"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "<bitmanip_optab>di2"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))]
-+  "TARGET_64BIT && TARGET_ZBB"
-+  "<bitmanip_insn>\t%0,%1"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*<optab>_not<mode>"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
-+			    (match_operand:X 2 "register_operand" "r")))]
-+  "TARGET_ZBB || TARGET_ZBP"
-+  "<insn>n\t%0,%2,%1"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*xor_not<mode>"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(not:X (xor:X (match_operand:X 1 "register_operand" "r")
-+		      (match_operand:X 2 "register_operand" "r"))))]
-+  "TARGET_ZBB || TARGET_ZBP"
-+  "xnor\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+ 
-+;;; ??? pack
-+
-+(define_insn "*zero_extendhi<GPR:mode>2_bitmanip"
-+  [(set (match_operand:GPR 0 "register_operand" "=r,r")
-+	(zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
-+  "TARGET_ZBB || TARGET_ZBP"
-+  "@
-+   zext.h\t%0,%1
-+   lhu\t%0,%1"
-+  [(set_attr "type" "bitmanip,load")])
-+
-+(define_insn "*zero_extendsidi2_bitmanip"
-+  [(set (match_operand:DI 0 "register_operand" "=r,r")
-+	(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
-+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBA)"
-+  "@
-+   zext.w\t%0,%1
-+   lwu\t%0,%1"
-+  [(set_attr "type" "bitmanip,load")])
-+
-+(define_insn "<bitmanip_optab><mode>3"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(any_minmax:X (match_operand:X 1 "register_operand" "r")
-+		      (match_operand:X 2 "register_operand" "r")))]
-+  "TARGET_ZBB"
-+  "<bitmanip_insn>\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*bset<mode>"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(ior:X (ashift:X (const_int 1)
-+			 (match_operand:QI 2 "register_operand" "r"))
-+	       (match_operand:X 1 "register_operand" "r")))]
-+  "TARGET_ZBS"
-+  "bset\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*bset<mode>_mask"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(ior:X (ashift:X (const_int 1)
-+			 (subreg:QI
-+			  (and:X (match_operand:X 2 "register_operand" "r")
-+				 (match_operand 3 "<X:shiftm1>" "i")) 0))
-+	       (match_operand:X 1 "register_operand" "r")))]
-+  "TARGET_ZBS"
-+  "bset\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*bset<mode>_1"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(ashift:X (const_int 1)
-+		  (match_operand:QI 1 "register_operand" "r")))]
-+  "TARGET_ZBS"
-+  "bset\t%0,x0,%1"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*bset<mode>_1_mask"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(ashift:X (const_int 1)
-+		  (subreg:QI
-+		   (and:X (match_operand:X 1 "register_operand" "r")
-+			  (match_operand 2 "<X:shiftm1>" "i")) 0)))]
-+  "TARGET_ZBS"
-+  "bset\t%0,x0,%1"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*bseti<mode>"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(ior:X (match_operand:X 1 "register_operand" "r")
-+	       (match_operand 2 "single_bit_mask_operand" "i")))]
-+  "TARGET_ZBS"
-+  "bseti\t%0,%1,%S2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*bsetw"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(sign_extend:DI
-+	 (subreg:SI
-+	  (ior:DI (subreg:DI
-+		   (ashift:SI (const_int 1)
-+			      (match_operand:QI 2 "register_operand" "r")) 0)
-+		  (match_operand:DI 1 "register_operand" "r")) 0)))]
-+  "TARGET_64BIT && TARGET_ZBS"
-+  "bsetw\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*bsetw_mask"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(sign_extend:DI
-+	 (subreg:SI
-+	  (ior:DI (subreg:DI
-+		   (ashift:SI
-+		    (const_int 1)
-+		    (subreg:QI
-+		     (and:DI (match_operand:DI 2 "register_operand" "r")
-+			     (match_operand 3 "const31_operand" "i")) 0)) 0)
-+		  (match_operand:DI 1 "register_operand" "r")) 0)))]
-+  "TARGET_64BIT && TARGET_ZBS"
-+  "bsetw\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*bsetiw"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(ior:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
-+		(match_operand 2 "single_bit_mask_operand" "i")))]
-+  "TARGET_64BIT && TARGET_ZBS"
-+  "bsetiw\t%0,%1,%S2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*bclr<mode>"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(and:X (rotate:X (const_int -2)
-+			 (match_operand:QI 2 "register_operand" "r"))
-+	       (match_operand:X 1 "register_operand" "r")))]
-+  "TARGET_ZBS"
-+  "bclr\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*bclri<mode>"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(and:X (match_operand:X 1 "register_operand" "r")
-+	       (match_operand 2 "not_single_bit_mask_operand" "i")))]
-+  "TARGET_ZBS"
-+  "bclri\t%0,%1,%T2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*bclrw"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(sign_extend:DI
-+	 (subreg:SI
-+	  (and:DI
-+	   (not:DI (subreg:DI
-+		    (ashift:SI (const_int 1)
-+			       (match_operand:QI 2 "register_operand" "r")) 0))
-+	   (match_operand:DI 1 "register_operand" "r")) 0)))]
-+  "TARGET_64BIT && TARGET_ZBS"
-+  "bclrw\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*bclriw"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(and:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
-+		(match_operand 2 "not_single_bit_mask_operand" "i")))]
-+  "TARGET_64BIT && TARGET_ZBS"
-+  "bclriw\t%0,%1,%T2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*binv<mode>"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(xor:X (ashift:X (const_int 1)
-+			 (match_operand:QI 2 "register_operand" "r"))
-+	       (match_operand:X 1 "register_operand" "r")))]
-+  "TARGET_ZBS"
-+  "binv\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*binvi<mode>"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(xor:X (match_operand:X 1 "register_operand" "r")
-+	       (match_operand 2 "single_bit_mask_operand" "i")))]
-+  "TARGET_ZBS"
-+  "binvi\t%0,%1,%S2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*binvw"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(sign_extend:DI
-+	 (subreg:SI
-+	  (xor:DI (subreg:DI
-+		   (ashift:SI (const_int 1)
-+			      (match_operand:QI 2 "register_operand" "r")) 0)
-+		  (match_operand:DI 1 "register_operand" "r")) 0)))]
-+  "TARGET_64BIT && TARGET_ZBS"
-+  "binvw\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*binviw"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(xor:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
-+		(match_operand 2 "single_bit_mask_operand" "i")))]
-+  "TARGET_64BIT && TARGET_ZBS"
-+  "binviw\t%0,%1,%S2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*bext<mode>"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(zero_extract:X (match_operand:X 1 "register_operand" "r")
-+			(const_int 1)
-+			(zero_extend:X
-+			 (match_operand:QI 2 "register_operand" "r"))))]
-+  "TARGET_ZBS"
-+  "bext\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*bexti"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(zero_extract:X (match_operand:X 1 "register_operand" "r")
-+			(const_int 1)
-+			(match_operand 2 "immediate_operand" "i")))]
-+  "TARGET_ZBS"
-+  "bexti\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*bextw"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(and:DI
-+	 (subreg:DI
-+	  (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
-+		       (match_operand:QI 2 "register_operand" "r")) 0)
-+	 (const_int 1)))]
-+  "TARGET_64BIT && TARGET_ZBS"
-+  "bextw\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+;;; ??? s[lr]o*
-+
-+(define_insn "rotrsi3"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+	(rotatert:SI (match_operand:SI 1 "register_operand" "r")
-+		     (match_operand:QI 2 "arith_operand" "rI")))]
-+  "TARGET_ZBB || TARGET_ZBP"
-+  { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; }
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "rotrdi3"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(rotatert:DI (match_operand:DI 1 "register_operand" "r")
-+		     (match_operand:QI 2 "arith_operand" "rI")))]
-+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
-+  "ror%i2\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_expand "riscv_rolw"
-+  [(match_operand:SI 0 "register_operand" "=r")
-+   (match_operand:SI 1 "register_operand" "r")
-+   (match_operand:SI 2 "register_operand" "r")]
-+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
-+{
-+  emit_insn (gen_rotlsi3 (operands[0], operands[1], operands[2]));
-+  DONE;
-+})
-+
-+(define_insn "rotlsi3"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+	(rotate:SI (match_operand:SI 1 "register_operand" "r")
-+		   (match_operand:QI 2 "register_operand" "r")))]
-+  "TARGET_ZBB || TARGET_ZBP"
-+  { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; }
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "rotldi3"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(rotate:DI (match_operand:DI 1 "register_operand" "r")
-+		   (match_operand:QI 2 "register_operand" "r")))]
-+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
-+  "rol\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "rotlsi3_sext"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
-+				   (match_operand:QI 2 "register_operand" "r"))))]
-+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
-+  "rolw\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+;;; ??? grev
-+
-+(define_insn "bswapsi2"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+        (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
-+  "TARGET_ZBB || TARGET_ZBP"
-+{
-+  if (TARGET_64BIT)
-+    return TARGET_ZBB ? "rev8\t%0,%1\n\tsrai\t%0,%0,32" : "rev8.w\t%0,%1";
-+  else
-+    return "rev8\t%0,%1";
-+}
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "bswapdi2"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(bswap:DI (match_operand:DI 1 "register_operand" "r")))]
-+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
-+  "rev8\t%0,%1"
-+  [(set_attr "type" "bitmanip")])
-+
-+;;; ??? shfl/unshfl
-+
-+;;; ??? bext/bdep
-+
-+;;; ??? clmul
-+
-+;;; ??? crc
-+
-+;;; ??? bmat
-+
-+(define_insn "*cmix"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(xor:X (and:X (xor:X (match_operand:X 1 "register_operand" "r")
-+			     (match_operand:X 3 "register_operand" "r"))
-+		      (match_operand:X 2 "register_operand" "r"))
-+	       (match_dup 3)))]
-+  "TARGET_ZBT"
-+  "cmix\t%0,%2,%1,%3"
-+  [(set_attr "type" "bitmanip")])
-+
-+;; ??? Can we do this by using the % communtative constraint?
-+
-+(define_insn "*cmix2"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(xor:X (and:X (xor:X (match_operand:X 1 "register_operand" "r")
-+			     (match_operand:X 3 "register_operand" "r"))
-+		      (match_operand:X 2 "register_operand" "r"))
-+	       (match_dup 1)))]
-+  "TARGET_ZBT"
-+  "cmix\t%0,%2,%3,%1"
-+  [(set_attr "type" "bitmanip")])
-+
-+;;; ??? cmov
-+
-+(define_insn "*mov<X:mode>cc_ne_bitmanip"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(if_then_else:X
-+	 (ne (match_operand:X 1 "register_operand" "r") (const_int 0))
-+	 (match_operand:X 2 "register_operand" "r")
-+	 (match_operand:X 3 "register_operand" "r")))]
-+  "TARGET_ZBT"
-+  "cmov\t%0,%1,%2,%3"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*mov<X:mode>cc_eq_bitmanip"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(if_then_else:X
-+	 (eq (match_operand:X 1 "register_operand" "r") (const_int 0))
-+	 (match_operand:X 2 "register_operand" "r")
-+	 (match_operand:X 3 "register_operand" "r")))]
-+  "TARGET_ZBT"
-+  "cmov\t%0,%1,%3,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+;;; ??? fs[lr]
-+
-+(define_insn "*shNadd"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
-+			  (match_operand:QI 2 "immediate_operand" "I"))
-+		(match_operand:X 3 "register_operand" "r")))]
-+  "TARGET_ZBA
-+   && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)"
-+  "sh%2add\t%0,%1,%3"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*shNadduw"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(plus:DI
-+	 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
-+			    (match_operand:QI 2 "immediate_operand" "I"))
-+		 (match_operand 3 "immediate_operand" ""))
-+	 (match_operand:DI 4 "register_operand" "r")))]
-+  "TARGET_64BIT && TARGET_ZBA
-+   && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
-+   && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
-+  "sh%2add.uw\t%0,%1,%4"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*add.uw"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(plus:DI (zero_extend:DI
-+		  (match_operand:SI 1 "register_operand" "r"))
-+		 (match_operand:DI 2 "register_operand" "r")))]
-+  "TARGET_64BIT && TARGET_ZBA"
-+  "add.uw\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "*slliuw"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
-+			   (match_operand:QI 2 "immediate_operand" "I"))
-+		(match_operand 3 "immediate_operand" "")))]
-+  "TARGET_64BIT && TARGET_ZBA
-+   && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
-+  "slli.uw\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+;; ??? bfxp
-+
-+;; sext
-+
-+(define_insn "*extend<SHORT:mode><SUPERQI:mode>2_bitmanip"
-+  [(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
-+	(sign_extend:SUPERQI
-+	    (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
-+  "TARGET_ZBB"
-+  "@
-+   sext.<SHORT:size>\t%0,%1
-+   l<SHORT:size>\t%0,%1"
-+  [(set_attr "type" "bitmanip")
-+   (set_attr "length" "4")])
-diff --git a/gcc/config/riscv/rvintrin.h b/gcc/config/riscv/rvintrin.h
-new file mode 100644
-index 00000000000..0f6bfef3ff4
---- /dev/null
-+++ b/gcc/config/riscv/rvintrin.h
-@@ -0,0 +1,1033 @@
-+/*
-+ *  RISC-V "B" extension proposal intrinsics and emulation
-+ *
-+ *  Copyright (C) 2019  Clifford Wolf <clifford@clifford.at>
-+ *
-+ *  Permission to use, copy, modify, and/or distribute this software for any
-+ *  purpose with or without fee is hereby granted, provided that the above
-+ *  copyright notice and this permission notice appear in all copies.
-+ *
-+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ *
-+ *  ----------------------------------------------------------------------
-+ *
-+ *  Define RVINTRIN_EMULATE to enable emulation mode.
-+ *
-+ *  This header defines C inline functions with "mockup intrinsics" for
-+ *  RISC-V "B" extension proposal instructions.
-+ *
-+ *  _rv_*(...)
-+ *    RV32/64 intrinsics that operate on the "long" data type
-+ *
-+ *  _rv32_*(...)
-+ *    RV32/64 intrinsics that operate on the "int32_t" data type
-+ *
-+ *  _rv64_*(...)
-+ *    RV64-only intrinsics that operate on the "int64_t" data type
-+ *
-+ */
-+
-+#ifndef RVINTRIN_H
-+#define RVINTRIN_H
-+
-+#include <limits.h>
-+#include <stdint.h>
-+
-+#if !defined(__riscv_xlen) && !defined(RVINTRIN_EMULATE)
-+#  warning "Target is not RISC-V. Enabling <rvintrin.h> emulation mode."
-+#  define RVINTRIN_EMULATE 1
-+#endif
-+
-+#ifndef RVINTRIN_EMULATE
-+
-+#if __riscv_xlen == 32
-+#  define RVINTRIN_RV32
-+#endif
-+
-+#if __riscv_xlen == 64
-+#  define RVINTRIN_RV64
-+#endif
-+
-+#ifdef RVINTRIN_RV32
-+static inline int32_t _rv32_clz   (int32_t rs1) { int32_t rd; __asm__ ("clz     %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline int32_t _rv32_ctz   (int32_t rs1) { int32_t rd; __asm__ ("ctz     %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline int32_t _rv32_pcnt  (int32_t rs1) { int32_t rd; __asm__ ("pcnt    %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline int32_t _rv32_sext_b(int32_t rs1) { int32_t rd; __asm__ ("sext.b  %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline int32_t _rv32_sext_h(int32_t rs1) { int32_t rd; __asm__ ("sext.h  %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+#endif
-+
-+#ifdef RVINTRIN_RV64
-+static inline int32_t _rv32_clz   (int32_t rs1) { int32_t rd; __asm__ ("clzw    %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline int32_t _rv32_ctz   (int32_t rs1) { int32_t rd; __asm__ ("ctzw    %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline int32_t _rv32_pcnt  (int32_t rs1) { int32_t rd; __asm__ ("pcntw   %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline int32_t _rv32_sext_b(int32_t rs1) { int32_t rd; __asm__ ("sext.b  %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline int32_t _rv32_sext_h(int32_t rs1) { int32_t rd; __asm__ ("sext.h  %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+
-+static inline int64_t _rv64_clz   (int64_t rs1) { int64_t rd; __asm__ ("clz     %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline int64_t _rv64_ctz   (int64_t rs1) { int64_t rd; __asm__ ("ctz     %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline int64_t _rv64_pcnt  (int64_t rs1) { int64_t rd; __asm__ ("pcnt    %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline int32_t _rv64_sext_b(int32_t rs1) { int32_t rd; __asm__ ("sext.b  %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline int32_t _rv64_sext_h(int32_t rs1) { int32_t rd; __asm__ ("sext.h  %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+#endif
-+
-+#ifdef RVINTRIN_RV32
-+static inline int32_t _rv32_pack (int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("pack  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_packu(int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("packu %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_packh(int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("packh %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_bfp  (int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("bfp   %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+#endif
-+
-+#ifdef RVINTRIN_RV64
-+static inline int32_t _rv32_pack (int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("packw  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_packu(int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("packuw %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_packh(int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("packh  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_bfp  (int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("bfpw   %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+
-+static inline int64_t _rv64_pack (int64_t rs1, int64_t rs2) { int64_t rd; __asm__ ("pack  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_packu(int64_t rs1, int64_t rs2) { int64_t rd; __asm__ ("packu %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_packh(int64_t rs1, int64_t rs2) { int64_t rd; __asm__ ("packh %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_bfp  (int64_t rs1, int64_t rs2) { int64_t rd; __asm__ ("bfp   %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+#endif
-+
-+static inline int32_t _rv32_min (int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("min  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_minu(int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("minu %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_max (int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("max  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_maxu(int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("maxu %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+
-+#ifdef RVINTRIN_RV64
-+static inline int64_t _rv64_min (int64_t rs1, int64_t rs2) { int64_t rd; __asm__ ("min  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_minu(int64_t rs1, int64_t rs2) { int64_t rd; __asm__ ("minu %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_max (int64_t rs1, int64_t rs2) { int64_t rd; __asm__ ("max  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_maxu(int64_t rs1, int64_t rs2) { int64_t rd; __asm__ ("maxu %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+#endif
-+
-+#ifdef RVINTRIN_RV32
-+static inline int32_t _rv32_bset (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("bseti %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 & rs2)); else __asm__ ("bset %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_bclr (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("bclri %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 & rs2)); else __asm__ ("bclr %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_binv (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("binvi %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 & rs2)); else __asm__ ("binv %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_bext (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("bexti %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 & rs2)); else __asm__ ("bext %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+#endif
-+
-+#ifdef RVINTRIN_RV64
-+static inline int32_t _rv32_bset (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("bsetiw %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 & rs2)); else __asm__ ("bsetw %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_bclr (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("bclriw %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 & rs2)); else __asm__ ("bclrw %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_binv (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("binviw %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 & rs2)); else __asm__ ("binvw %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_bext (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("bexti  %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 & rs2)); else __asm__ ("bextw %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+
-+static inline int64_t _rv64_bset (int64_t rs1, int64_t rs2) { int64_t rd; if (__builtin_constant_p(rs2)) __asm__ ("bseti %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(63 & rs2)); else __asm__ ("bset %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_bclr (int64_t rs1, int64_t rs2) { int64_t rd; if (__builtin_constant_p(rs2)) __asm__ ("bclri %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(63 & rs2)); else __asm__ ("bclr %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_binv (int64_t rs1, int64_t rs2) { int64_t rd; if (__builtin_constant_p(rs2)) __asm__ ("binvi %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(63 & rs2)); else __asm__ ("binv %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_bext (int64_t rs1, int64_t rs2) { int64_t rd; if (__builtin_constant_p(rs2)) __asm__ ("bexti %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(63 & rs2)); else __asm__ ("bext %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+#endif
-+
-+#ifdef RVINTRIN_RV32
-+static inline int32_t _rv32_sll    (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("slli    %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("sll     %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_srl    (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("srli    %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("srl     %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_sra    (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("srai    %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("sra     %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_slo    (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("sloi    %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("slo     %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_sro    (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("sroi    %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("sro     %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_rol    (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("rori    %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 & -rs2)); else __asm__ ("rol     %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_ror    (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("rori    %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("ror     %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_grev   (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("grevi   %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("grev    %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_gorc   (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("gorci   %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("gorc    %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_shfl   (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("shfli   %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(15 &  rs2)); else __asm__ ("shfl    %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_unshfl (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("unshfli %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(15 &  rs2)); else __asm__ ("unshfl  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+#endif
-+
-+#ifdef RVINTRIN_RV64
-+static inline int32_t _rv32_sll    (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("slliw   %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("sllw    %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_srl    (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("srliw   %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("srlw    %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_sra    (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("sraiw   %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("sraw    %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_slo    (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("sloiw   %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("slow    %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_sro    (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("sroiw   %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("srow    %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_rol    (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("roriw   %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 & -rs2)); else __asm__ ("rolw    %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_ror    (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("roriw   %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("rorw    %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_grev   (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("greviw  %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("grevw   %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_gorc   (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("gorciw  %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("gorcw   %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_shfl   (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("shfli   %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(15 &  rs2)); else __asm__ ("shflw   %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_unshfl (int32_t rs1, int32_t rs2) { int32_t rd; if (__builtin_constant_p(rs2)) __asm__ ("unshfli %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(15 &  rs2)); else __asm__ ("unshflw %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+
-+static inline int64_t _rv64_sll    (int64_t rs1, int64_t rs2) { int64_t rd; if (__builtin_constant_p(rs2)) __asm__ ("slli    %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(63 &  rs2)); else __asm__ ("sll     %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_srl    (int64_t rs1, int64_t rs2) { int64_t rd; if (__builtin_constant_p(rs2)) __asm__ ("srli    %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(63 &  rs2)); else __asm__ ("srl     %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_sra    (int64_t rs1, int64_t rs2) { int64_t rd; if (__builtin_constant_p(rs2)) __asm__ ("srai    %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(63 &  rs2)); else __asm__ ("sra     %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_slo    (int64_t rs1, int64_t rs2) { int64_t rd; if (__builtin_constant_p(rs2)) __asm__ ("sloi    %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(63 &  rs2)); else __asm__ ("slo     %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_sro    (int64_t rs1, int64_t rs2) { int64_t rd; if (__builtin_constant_p(rs2)) __asm__ ("sroi    %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(63 &  rs2)); else __asm__ ("sro     %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_rol    (int64_t rs1, int64_t rs2) { int64_t rd; if (__builtin_constant_p(rs2)) __asm__ ("rori    %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(63 & -rs2)); else __asm__ ("rol     %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_ror    (int64_t rs1, int64_t rs2) { int64_t rd; if (__builtin_constant_p(rs2)) __asm__ ("rori    %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(63 &  rs2)); else __asm__ ("ror     %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_grev   (int64_t rs1, int64_t rs2) { int64_t rd; if (__builtin_constant_p(rs2)) __asm__ ("grevi   %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(63 &  rs2)); else __asm__ ("grev    %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_gorc   (int64_t rs1, int64_t rs2) { int64_t rd; if (__builtin_constant_p(rs2)) __asm__ ("gorci   %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(63 &  rs2)); else __asm__ ("gorc    %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_shfl   (int64_t rs1, int64_t rs2) { int64_t rd; if (__builtin_constant_p(rs2)) __asm__ ("shfli   %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("shfl    %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_unshfl (int64_t rs1, int64_t rs2) { int64_t rd; if (__builtin_constant_p(rs2)) __asm__ ("unshfli %0, %1, %2" : "=r"(rd) : "r"(rs1), "i"(31 &  rs2)); else __asm__ ("unshfl  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+#endif
-+
-+#ifdef RVINTRIN_RV32
-+static inline int32_t _rv32_bext(int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("bext  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_bdep(int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("bdep  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+#endif
-+
-+#ifdef RVINTRIN_RV64
-+static inline int32_t _rv32_bext(int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("bextw %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_bdep(int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("bdepw %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+
-+static inline int64_t _rv64_bext(int64_t rs1, int64_t rs2) { int64_t rd; __asm__ ("bext  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_bdep(int64_t rs1, int64_t rs2) { int64_t rd; __asm__ ("bdep  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+#endif
-+
-+#ifdef RVINTRIN_RV32
-+static inline int32_t _rv32_clmul (int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("clmul   %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_clmulh(int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("clmulh  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_clmulr(int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("clmulr  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+#endif
-+
-+#ifdef RVINTRIN_RV64
-+static inline int32_t _rv32_clmul (int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("clmulw  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_clmulh(int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("clmulhw %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int32_t _rv32_clmulr(int32_t rs1, int32_t rs2) { int32_t rd; __asm__ ("clmulrw %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+
-+static inline int64_t _rv64_clmul (int64_t rs1, int64_t rs2) { int64_t rd; __asm__ ("clmul   %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_clmulh(int64_t rs1, int64_t rs2) { int64_t rd; __asm__ ("clmulh  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_clmulr(int64_t rs1, int64_t rs2) { int64_t rd; __asm__ ("clmulr  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+#endif
-+
-+static inline long _rv_crc32_b (long rs1) { long rd; __asm__ ("crc32.b  %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline long _rv_crc32_h (long rs1) { long rd; __asm__ ("crc32.h  %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline long _rv_crc32_w (long rs1) { long rd; __asm__ ("crc32.w  %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+
-+static inline long _rv_crc32c_b(long rs1) { long rd; __asm__ ("crc32c.b %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline long _rv_crc32c_h(long rs1) { long rd; __asm__ ("crc32c.h %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline long _rv_crc32c_w(long rs1) { long rd; __asm__ ("crc32c.w %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+
-+#ifdef RVINTRIN_RV64
-+static inline long _rv_crc32_d (long rs1) { long rd; __asm__ ("crc32.d  %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline long _rv_crc32c_d(long rs1) { long rd; __asm__ ("crc32c.d %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+#endif
-+
-+#ifdef RVINTRIN_RV64
-+static inline int64_t _rv64_bmatflip(int64_t rs1) { long rd; __asm__ ("bmatflip %0, %1" : "=r"(rd) : "r"(rs1)); return rd; }
-+static inline int64_t _rv64_bmator  (int64_t rs1, int64_t rs2) { long rd; __asm__ ("bmator  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline int64_t _rv64_bmatxor (int64_t rs1, int64_t rs2) { long rd; __asm__ ("bmatxor %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+#endif
-+
-+static inline long _rv_cmix(long rs2, long rs1, long rs3) { long rd; __asm__ ("cmix %0, %1, %2, %3" : "=r"(rd) : "r"(rs2), "r"(rs1), "r"(rs3)); return rd; }
-+static inline long _rv_cmov(long rs2, long rs1, long rs3) { long rd; __asm__ ("cmov %0, %1, %2, %3" : "=r"(rd) : "r"(rs2), "r"(rs1), "r"(rs3)); return rd; }
-+
-+#ifdef RVINTRIN_RV32
-+static inline int32_t _rv32_fsl(int32_t rs1, int32_t rs3, int32_t rs2)
-+{
-+	int32_t rd;
-+	if (__builtin_constant_p(rs2)) {
-+		rs2 &= 63;
-+		if (rs2 < 32)
-+			__asm__ ("fsli  %0, %1, %2, %3" : "=r"(rd) : "r"(rs1), "r"(rs3), "i"(rs2));
-+		else
-+			__asm__ ("fsli  %0, %1, %2, %3" : "=r"(rd) : "r"(rs3), "r"(rs1), "i"(rs2 & 31));
-+	} else {
-+		__asm__ ("fsl  %0, %1, %2, %3" : "=r"(rd) : "r"(rs1), "r"(rs3), "r"(rs2));
-+	}
-+	return rd;
-+}
-+
-+static inline int32_t _rv32_fsr(int32_t rs1, int32_t rs3, int32_t rs2)
-+{
-+	int32_t rd;
-+	if (__builtin_constant_p(rs2)) {
-+		rs2 &= 63;
-+		if (rs2 < 32)
-+			__asm__ ("fsri  %0, %1, %2, %3" : "=r"(rd) : "r"(rs1), "r"(rs3), "i"(rs2));
-+		else
-+			__asm__ ("fsri  %0, %1, %2, %3" : "=r"(rd) : "r"(rs3), "r"(rs1), "i"(rs2 & 31));
-+	} else {
-+		__asm__ ("fsr  %0, %1, %2, %3" : "=r"(rd) : "r"(rs1), "r"(rs3), "r"(rs2));
-+	}
-+	return rd;
-+}
-+#endif
-+
-+#ifdef RVINTRIN_RV64
-+static inline int32_t _rv32_fsl(int32_t rs1, int32_t rs3, int32_t rs2)
-+{
-+	int32_t rd;
-+	if (__builtin_constant_p(rs2)) {
-+		rs2 &= 63;
-+		if (rs2 < 32)
-+			__asm__ ("fsliw %0, %1, %2, %3" : "=r"(rd) : "r"(rs1), "r"(rs3), "i"(rs2));
-+		else
-+			__asm__ ("fsliw %0, %1, %2, %3" : "=r"(rd) : "r"(rs3), "r"(rs1), "i"(rs2 & 31));
-+	} else {
-+		__asm__ ("fslw %0, %1, %2, %3" : "=r"(rd) : "r"(rs1), "r"(rs3), "r"(rs2));
-+	}
-+	return rd;
-+}
-+
-+static inline int32_t _rv32_fsr(int32_t rs1, int32_t rs3, int32_t rs2)
-+{
-+	int32_t rd;
-+	if (__builtin_constant_p(rs2)) {
-+		rs2 &= 63;
-+		if (rs2 < 32)
-+			__asm__ ("fsriw %0, %1, %2, %3" : "=r"(rd) : "r"(rs1), "r"(rs3), "i"(rs2));
-+		else
-+			__asm__ ("fsriw %0, %1, %2, %3" : "=r"(rd) : "r"(rs3), "r"(rs1), "i"(rs2 & 31));
-+	} else {
-+		__asm__ ("fsrw %0, %1, %2, %3" : "=r"(rd) : "r"(rs1), "r"(rs3), "r"(rs2));
-+	}
-+	return rd;
-+}
-+
-+static inline int64_t _rv64_fsl(int64_t rs1, int64_t rs3, int64_t rs2)
-+{
-+	int64_t rd;
-+	if (__builtin_constant_p(rs2)) {
-+		rs2 &= 127;
-+		if (rs2 < 64)
-+			__asm__ ("fsli  %0, %1, %2, %3" : "=r"(rd) : "r"(rs1), "r"(rs3), "i"(rs2));
-+		else
-+			__asm__ ("fsli  %0, %1, %2, %3" : "=r"(rd) : "r"(rs3), "r"(rs1), "i"(rs2 & 63));
-+	} else {
-+		__asm__ ("fsl  %0, %1, %2, %3" : "=r"(rd) : "r"(rs1), "r"(rs3), "r"(rs2));
-+	}
-+	return rd;
-+}
-+
-+static inline int64_t _rv64_fsr(int64_t rs1, int64_t rs3, int64_t rs2)
-+{
-+	int64_t rd;
-+	if (__builtin_constant_p(rs2)) {
-+		rs2 &= 127;
-+		if (rs2 < 64)
-+			__asm__ ("fsri  %0, %1, %2, %3" : "=r"(rd) : "r"(rs1), "r"(rs3), "i"(rs2));
-+		else
-+			__asm__ ("fsri  %0, %1, %2, %3" : "=r"(rd) : "r"(rs3), "r"(rs1), "i"(rs2 & 63));
-+	} else {
-+		__asm__ ("fsr  %0, %1, %2, %3" : "=r"(rd) : "r"(rs1), "r"(rs3), "r"(rs2));
-+	}
-+	return rd;
-+}
-+#endif
-+
-+static inline long _rv_andn(long rs1, long rs2) { long rd; __asm__ ("andn %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline long _rv_orn (long rs1, long rs2) { long rd; __asm__ ("orn  %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+static inline long _rv_xnor(long rs1, long rs2) { long rd; __asm__ ("xnor %0, %1, %2" : "=r"(rd) : "r"(rs1), "r"(rs2)); return rd; }
-+
-+#else // RVINTRIN_EMULATE
-+
-+#if UINT_MAX != 0xffffffffU
-+#  error "<rvintrin.h> emulation mode only supports systems with sizeof(int) = 4."
-+#endif
-+
-+#if (ULLONG_MAX == 0xffffffffLLU) || (ULLONG_MAX != 0xffffffffffffffffLLU)
-+#  error "<rvintrin.h> emulation mode only supports systems with sizeof(long long) = 8."
-+#endif
-+
-+#if UINT_MAX == ULONG_MAX
-+#  define RVINTRIN_RV32
-+#else
-+#  define RVINTRIN_RV64
-+#endif
-+
-+#ifdef RVINTRIN_NOBUILTINS
-+static inline int32_t _rv32_clz(int32_t rs1) { for (int i=0; i < 32; i++) { if (1 & (rs1 >> (31-i))) return i; } return 32; }
-+static inline int64_t _rv64_clz(int64_t rs1) { for (int i=0; i < 64; i++) { if (1 & (rs1 >> (63-i))) return i; } return 64; }
-+
-+static inline int32_t _rv32_ctz(int32_t rs1) { for (int i=0; i < 32; i++) { if (1 & (rs1 >> i)) return i; } return 32; }
-+static inline int64_t _rv64_ctz(int64_t rs1) { for (int i=0; i < 64; i++) { if (1 & (rs1 >> i)) return i; } return 64; }
-+
-+static inline int32_t _rv32_pcnt(int32_t rs1) { int k=0; for (int i=0; i < 32; i++) { if (1 & (rs1 >> i)) k++; } return k; }
-+static inline int64_t _rv64_pcnt(int64_t rs1) { int k=0; for (int i=0; i < 64; i++) { if (1 & (rs1 >> i)) k++; } return k; }
-+#else
-+static inline int32_t _rv32_clz(int32_t rs1) { return rs1 ? __builtin_clz(rs1)   : 32; }
-+static inline int64_t _rv64_clz(int64_t rs1) { return rs1 ? __builtin_clzll(rs1) : 64; }
-+
-+static inline int32_t _rv32_ctz(int32_t rs1) { return rs1 ? __builtin_ctz(rs1)   : 32; }
-+static inline int64_t _rv64_ctz(int64_t rs1) { return rs1 ? __builtin_ctzll(rs1) : 64; }
-+
-+static inline int32_t _rv32_pcnt(int32_t rs1) { return __builtin_popcount(rs1);   }
-+static inline int64_t _rv64_pcnt(int64_t rs1) { return __builtin_popcountll(rs1); }
-+#endif
-+
-+static inline int32_t _rv32_sext_b(int32_t rs1) { return rs1 << (32-8) >> (32-8); }
-+static inline int64_t _rv64_sext_b(int64_t rs1) { return rs1 << (64-8) >> (64-8); }
-+
-+static inline int32_t _rv32_sext_h(int32_t rs1) { return rs1 << (32-16) >> (32-16); }
-+static inline int64_t _rv64_sext_h(int64_t rs1) { return rs1 << (64-16) >> (64-16); }
-+
-+static inline int32_t _rv32_pack(int32_t rs1, int32_t rs2) { return (rs1 & 0x0000ffff)   | (rs2 << 16); }
-+static inline int64_t _rv64_pack(int64_t rs1, int64_t rs2) { return (rs1 & 0xffffffffLL) | (rs2 << 32); }
-+
-+static inline int32_t _rv32_packu(int32_t rs1, int32_t rs2) { return ((rs1 >> 16) & 0x0000ffff)   | (rs2 >> 16 << 16); }
-+static inline int64_t _rv64_packu(int64_t rs1, int64_t rs2) { return ((rs1 >> 32) & 0xffffffffLL) | (rs2 >> 32 << 32); }
-+
-+static inline int32_t _rv32_packh(int32_t rs1, int32_t rs2) { return (rs1 & 0xff) | ((rs2 & 0xff) << 8); }
-+static inline int64_t _rv64_packh(int64_t rs1, int64_t rs2) { return (rs1 & 0xff) | ((rs2 & 0xff) << 8); }
-+
-+static inline int32_t _rv32_min (int32_t rs1, int32_t rs2) { return rs1 < rs2 ? rs1 : rs2; }
-+static inline int32_t _rv32_minu(int32_t rs1, int32_t rs2) { return (uint32_t)rs1 < (uint32_t)rs2 ? rs1 : rs2; }
-+static inline int32_t _rv32_max (int32_t rs1, int32_t rs2) { return rs1 > rs2 ? rs1 : rs2; }
-+static inline int32_t _rv32_maxu(int32_t rs1, int32_t rs2) { return (uint32_t)rs1 > (uint32_t)rs2 ? rs1 : rs2; }
-+
-+static inline int64_t _rv64_min (int64_t rs1, int64_t rs2) { return rs1 < rs2 ? rs1 : rs2; }
-+static inline int64_t _rv64_minu(int64_t rs1, int64_t rs2) { return (uint64_t)rs1 < (uint64_t)rs2 ? rs1 : rs2; }
-+static inline int64_t _rv64_max (int64_t rs1, int64_t rs2) { return rs1 > rs2 ? rs1 : rs2; }
-+static inline int64_t _rv64_maxu(int64_t rs1, int64_t rs2) { return (uint64_t)rs1 > (uint64_t)rs2 ? rs1 : rs2; }
-+
-+static inline int32_t _rv32_bset (int32_t rs1, int32_t rs2) { return rs1 |  (1   << (rs2 & 31)); }
-+static inline int32_t _rv32_bclr (int32_t rs1, int32_t rs2) { return rs1 & ~(1   << (rs2 & 31)); }
-+static inline int32_t _rv32_binv (int32_t rs1, int32_t rs2) { return rs1 ^  (1   << (rs2 & 31)); }
-+static inline int32_t _rv32_bext (int32_t rs1, int32_t rs2) { return 1   &  (rs1 >> (rs2 & 31)); }
-+
-+static inline int64_t _rv64_bset (int64_t rs1, int64_t rs2) { return rs1 |  (1LL << (rs2 & 63)); }
-+static inline int64_t _rv64_bclr (int64_t rs1, int64_t rs2) { return rs1 & ~(1LL << (rs2 & 63)); }
-+static inline int64_t _rv64_binv (int64_t rs1, int64_t rs2) { return rs1 ^  (1LL << (rs2 & 63)); }
-+static inline int64_t _rv64_bext (int64_t rs1, int64_t rs2) { return 1LL &  (rs1 >> (rs2 & 63)); }
-+
-+static inline int32_t _rv32_sll    (int32_t rs1, int32_t rs2) { return rs1 << (rs2 & 31); }
-+static inline int32_t _rv32_srl    (int32_t rs1, int32_t rs2) { return (uint32_t)rs1 >> (rs2 & 31); }
-+static inline int32_t _rv32_sra    (int32_t rs1, int32_t rs2) { return rs1 >> (rs2 & 31); }
-+static inline int32_t _rv32_slo    (int32_t rs1, int32_t rs2) { return ~(~rs1 << (rs2 & 31)); }
-+static inline int32_t _rv32_sro    (int32_t rs1, int32_t rs2) { return ~(~(uint32_t)rs1 >> (rs2 & 31)); }
-+static inline int32_t _rv32_rol    (int32_t rs1, int32_t rs2) { return _rv32_sll(rs1, rs2) | _rv32_srl(rs1, -rs2); }
-+static inline int32_t _rv32_ror    (int32_t rs1, int32_t rs2) { return _rv32_srl(rs1, rs2) | _rv32_sll(rs1, -rs2); }
-+
-+static inline int32_t _rv32_bfp(int32_t rs1, int32_t rs2)
-+{
-+	uint32_t cfg = rs2 >> 16;
-+	int len = (cfg >> 8) & 15;
-+	int off = cfg & 31;
-+	len = len ? len : 16;
-+	uint32_t mask = _rv32_slo(0, len) << off;
-+	uint32_t data = rs2 << off;
-+	return (data & mask) | (rs1 & ~mask);
-+}
-+
-+static inline int32_t _rv32_grev(int32_t rs1, int32_t rs2)
-+{
-+	uint32_t x = rs1;
-+	int shamt = rs2 & 31;
-+	if (shamt &  1) x = ((x & 0x55555555) <<  1) | ((x & 0xAAAAAAAA) >>  1);
-+	if (shamt &  2) x = ((x & 0x33333333) <<  2) | ((x & 0xCCCCCCCC) >>  2);
-+	if (shamt &  4) x = ((x & 0x0F0F0F0F) <<  4) | ((x & 0xF0F0F0F0) >>  4);
-+	if (shamt &  8) x = ((x & 0x00FF00FF) <<  8) | ((x & 0xFF00FF00) >>  8);
-+	if (shamt & 16) x = ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
-+	return x;
-+}
-+
-+static inline int32_t _rv32_gorc(int32_t rs1, int32_t rs2)
-+{
-+	uint32_t x = rs1;
-+	int shamt = rs2 & 31;
-+	if (shamt &  1) x |= ((x & 0x55555555) <<  1) | ((x & 0xAAAAAAAA) >>  1);
-+	if (shamt &  2) x |= ((x & 0x33333333) <<  2) | ((x & 0xCCCCCCCC) >>  2);
-+	if (shamt &  4) x |= ((x & 0x0F0F0F0F) <<  4) | ((x & 0xF0F0F0F0) >>  4);
-+	if (shamt &  8) x |= ((x & 0x00FF00FF) <<  8) | ((x & 0xFF00FF00) >>  8);
-+	if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
-+	return x;
-+}
-+
-+static inline uint32_t _rvintrin_shuffle32_stage(uint32_t src, uint32_t maskL, uint32_t maskR, int N)
-+{
-+	uint32_t x = src & ~(maskL | maskR);
-+	x |= ((src <<  N) & maskL) | ((src >>  N) & maskR);
-+	return x;
-+}
-+
-+static inline int32_t _rv32_shfl(int32_t rs1, int32_t rs2)
-+{
-+	uint32_t x = rs1;
-+	int shamt = rs2 & 15;
-+
-+	if (shamt & 8) x = _rvintrin_shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
-+	if (shamt & 4) x = _rvintrin_shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
-+	if (shamt & 2) x = _rvintrin_shuffle32_stage(x, 0x30303030, 0x0c0c0c0c, 2);
-+	if (shamt & 1) x = _rvintrin_shuffle32_stage(x, 0x44444444, 0x22222222, 1);
-+
-+	return x;
-+}
-+
-+static inline int32_t _rv32_unshfl(int32_t rs1, int32_t rs2)
-+{
-+	uint32_t x = rs1;
-+	int shamt = rs2 & 15;
-+
-+	if (shamt & 1) x = _rvintrin_shuffle32_stage(x, 0x44444444, 0x22222222, 1);
-+	if (shamt & 2) x = _rvintrin_shuffle32_stage(x, 0x30303030, 0x0c0c0c0c, 2);
-+	if (shamt & 4) x = _rvintrin_shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
-+	if (shamt & 8) x = _rvintrin_shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
-+
-+	return x;
-+}
-+
-+static inline int64_t _rv64_sll    (int64_t rs1, int64_t rs2) { return rs1 << (rs2 & 63); }
-+static inline int64_t _rv64_srl    (int64_t rs1, int64_t rs2) { return (uint64_t)rs1 >> (rs2 & 63); }
-+static inline int64_t _rv64_sra    (int64_t rs1, int64_t rs2) { return rs1 >> (rs2 & 63); }
-+static inline int64_t _rv64_slo    (int64_t rs1, int64_t rs2) { return ~(~rs1 << (rs2 & 63)); }
-+static inline int64_t _rv64_sro    (int64_t rs1, int64_t rs2) { return ~(~(uint64_t)rs1 >> (rs2 & 63)); }
-+static inline int64_t _rv64_rol    (int64_t rs1, int64_t rs2) { return _rv64_sll(rs1, rs2) | _rv64_srl(rs1, -rs2); }
-+static inline int64_t _rv64_ror    (int64_t rs1, int64_t rs2) { return _rv64_srl(rs1, rs2) | _rv64_sll(rs1, -rs2); }
-+
-+static inline int64_t _rv64_bfp(int64_t rs1, int64_t rs2)
-+{
-+	uint64_t cfg = (uint64_t)rs2 >> 32;
-+	if ((cfg >> 30) == 2)
-+		cfg = cfg >> 16;
-+	int len = (cfg >> 8) & 31;
-+	int off = cfg & 63;
-+	len = len ? len : 32;
-+	uint64_t mask = _rv64_slo(0, len) << off;
-+	uint64_t data = rs2 << off;
-+	return (data & mask) | (rs1 & ~mask);
-+}
-+
-+static inline int64_t _rv64_grev(int64_t rs1, int64_t rs2)
-+{
-+	uint64_t x = rs1;
-+	int shamt = rs2 & 63;
-+	if (shamt &  1) x = ((x & 0x5555555555555555LL) <<  1) | ((x & 0xAAAAAAAAAAAAAAAALL) >>  1);
-+	if (shamt &  2) x = ((x & 0x3333333333333333LL) <<  2) | ((x & 0xCCCCCCCCCCCCCCCCLL) >>  2);
-+	if (shamt &  4) x = ((x & 0x0F0F0F0F0F0F0F0FLL) <<  4) | ((x & 0xF0F0F0F0F0F0F0F0LL) >>  4);
-+	if (shamt &  8) x = ((x & 0x00FF00FF00FF00FFLL) <<  8) | ((x & 0xFF00FF00FF00FF00LL) >>  8);
-+	if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) | ((x & 0xFFFF0000FFFF0000LL) >> 16);
-+	if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) | ((x & 0xFFFFFFFF00000000LL) >> 32);
-+	return x;
-+}
-+
-+static inline int64_t _rv64_gorc(int64_t rs1, int64_t rs2)
-+{
-+	uint64_t x = rs1;
-+	int shamt = rs2 & 63;
-+	if (shamt &  1) x |= ((x & 0x5555555555555555LL) <<  1) | ((x & 0xAAAAAAAAAAAAAAAALL) >>  1);
-+	if (shamt &  2) x |= ((x & 0x3333333333333333LL) <<  2) | ((x & 0xCCCCCCCCCCCCCCCCLL) >>  2);
-+	if (shamt &  4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) <<  4) | ((x & 0xF0F0F0F0F0F0F0F0LL) >>  4);
-+	if (shamt &  8) x |= ((x & 0x00FF00FF00FF00FFLL) <<  8) | ((x & 0xFF00FF00FF00FF00LL) >>  8);
-+	if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) | ((x & 0xFFFF0000FFFF0000LL) >> 16);
-+	if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) | ((x & 0xFFFFFFFF00000000LL) >> 32);
-+	return x;
-+}
-+
-+static inline uint64_t _rvintrin_shuffle64_stage(uint64_t src, uint64_t maskL, uint64_t maskR, int N)
-+{
-+	uint64_t x = src & ~(maskL | maskR);
-+	x |= ((src <<  N) & maskL) | ((src >>  N) & maskR);
-+	return x;
-+}
-+
-+static inline int64_t _rv64_shfl(int64_t rs1, int64_t rs2)
-+{
-+	uint64_t x = rs1;
-+	int shamt = rs2 & 31;
-+	if (shamt & 16) x = _rvintrin_shuffle64_stage(x, 0x0000ffff00000000LL, 0x00000000ffff0000LL, 16);
-+	if (shamt &  8) x = _rvintrin_shuffle64_stage(x, 0x00ff000000ff0000LL, 0x0000ff000000ff00LL,  8);
-+	if (shamt &  4) x = _rvintrin_shuffle64_stage(x, 0x0f000f000f000f00LL, 0x00f000f000f000f0LL,  4);
-+	if (shamt &  2) x = _rvintrin_shuffle64_stage(x, 0x3030303030303030LL, 0x0c0c0c0c0c0c0c0cLL,  2);
-+	if (shamt &  1) x = _rvintrin_shuffle64_stage(x, 0x4444444444444444LL, 0x2222222222222222LL,  1);
-+	return x;
-+}
-+
-+static inline int64_t _rv64_unshfl(int64_t rs1, int64_t rs2)
-+{
-+	uint64_t x = rs1;
-+	int shamt = rs2 & 31;
-+	if (shamt &  1) x = _rvintrin_shuffle64_stage(x, 0x4444444444444444LL, 0x2222222222222222LL,  1);
-+	if (shamt &  2) x = _rvintrin_shuffle64_stage(x, 0x3030303030303030LL, 0x0c0c0c0c0c0c0c0cLL,  2);
-+	if (shamt &  4) x = _rvintrin_shuffle64_stage(x, 0x0f000f000f000f00LL, 0x00f000f000f000f0LL,  4);
-+	if (shamt &  8) x = _rvintrin_shuffle64_stage(x, 0x00ff000000ff0000LL, 0x0000ff000000ff00LL,  8);
-+	if (shamt & 16) x = _rvintrin_shuffle64_stage(x, 0x0000ffff00000000LL, 0x00000000ffff0000LL, 16);
-+	return x;
-+}
-+
-+static inline int32_t _rv32_bext(int32_t rs1, int32_t rs2)
-+{
-+	uint32_t c = 0, i = 0, data = rs1, mask = rs2;
-+	while (mask) {
-+		uint32_t b = mask & ~((mask | (mask-1)) + 1);
-+		c |= (data & b) >> (_rv32_ctz(b) - i);
-+		i += _rv32_pcnt(b);
-+		mask -= b;
-+	}
-+	return c;
-+}
-+
-+static inline int32_t _rv32_bdep(int32_t rs1, int32_t rs2)
-+{
-+	uint32_t c = 0, i = 0, data = rs1, mask = rs2;
-+	while (mask) {
-+		uint32_t b = mask & ~((mask | (mask-1)) + 1);
-+		c |= (data << (_rv32_ctz(b) - i)) & b;
-+		i += _rv32_pcnt(b);
-+		mask -= b;
-+	}
-+	return c;
-+}
-+
-+static inline int64_t _rv64_bext(int64_t rs1, int64_t rs2)
-+{
-+	uint64_t c = 0, i = 0, data = rs1, mask = rs2;
-+	while (mask) {
-+		uint64_t b = mask & ~((mask | (mask-1)) + 1);
-+		c |= (data & b) >> (_rv64_ctz(b) - i);
-+		i += _rv64_pcnt(b);
-+		mask -= b;
-+	}
-+	return c;
-+}
-+
-+static inline int64_t _rv64_bdep(int64_t rs1, int64_t rs2)
-+{
-+	uint64_t c = 0, i = 0, data = rs1, mask = rs2;
-+	while (mask) {
-+		uint64_t b = mask & ~((mask | (mask-1)) + 1);
-+		c |= (data << (_rv64_ctz(b) - i)) & b;
-+		i += _rv64_pcnt(b);
-+		mask -= b;
-+	}
-+	return c;
-+}
-+
-+static inline int32_t _rv32_clmul(int32_t rs1, int32_t rs2)
-+{
-+	uint32_t a = rs1, b = rs2, x = 0;
-+	for (int i = 0; i < 32; i++)
-+		if ((b >> i) & 1)
-+			x ^= a << i;
-+	return x;
-+}
-+
-+static inline int32_t _rv32_clmulh(int32_t rs1, int32_t rs2)
-+{
-+	uint32_t a = rs1, b = rs2, x = 0;
-+	for (int i = 1; i < 32; i++)
-+		if ((b >> i) & 1)
-+			x ^= a >> (32-i);
-+	return x;
-+}
-+
-+static inline int32_t _rv32_clmulr(int32_t rs1, int32_t rs2)
-+{
-+	uint32_t a = rs1, b = rs2, x = 0;
-+	for (int i = 0; i < 32; i++)
-+		if ((b >> i) & 1)
-+			x ^= a >> (31-i);
-+	return x;
-+}
-+
-+static inline int64_t _rv64_clmul(int64_t rs1, int64_t rs2)
-+{
-+	uint64_t a = rs1, b = rs2, x = 0;
-+	for (int i = 0; i < 64; i++)
-+		if ((b >> i) & 1)
-+			x ^= a << i;
-+	return x;
-+}
-+
-+static inline int64_t _rv64_clmulh(int64_t rs1, int64_t rs2)
-+{
-+	uint64_t a = rs1, b = rs2, x = 0;
-+	for (int i = 1; i < 64; i++)
-+		if ((b >> i) & 1)
-+			x ^= a >> (64-i);
-+	return x;
-+}
-+
-+static inline int64_t _rv64_clmulr(int64_t rs1, int64_t rs2)
-+{
-+	uint64_t a = rs1, b = rs2, x = 0;
-+	for (int i = 0; i < 64; i++)
-+		if ((b >> i) & 1)
-+			x ^= a >> (63-i);
-+	return x;
-+}
-+
-+static inline long _rvintrin_crc32(unsigned long x, int nbits)
-+{
-+	for (int i = 0; i < nbits; i++)
-+		x = (x >> 1) ^ (0xEDB88320 & ~((x&1)-1));
-+	return x;
-+}
-+
-+static inline long _rvintrin_crc32c(unsigned long x, int nbits)
-+{
-+	for (int i = 0; i < nbits; i++)
-+		x = (x >> 1) ^ (0x82F63B78 & ~((x&1)-1));
-+	return x;
-+}
-+
-+static inline long _rv_crc32_b(long rs1) { return _rvintrin_crc32(rs1, 8); }
-+static inline long _rv_crc32_h(long rs1) { return _rvintrin_crc32(rs1, 16); }
-+static inline long _rv_crc32_w(long rs1) { return _rvintrin_crc32(rs1, 32); }
-+
-+static inline long _rv_crc32c_b(long rs1) { return _rvintrin_crc32c(rs1, 8); }
-+static inline long _rv_crc32c_h(long rs1) { return _rvintrin_crc32c(rs1, 16); }
-+static inline long _rv_crc32c_w(long rs1) { return _rvintrin_crc32c(rs1, 32); }
-+
-+#ifdef RVINTRIN_RV64
-+static inline long _rv_crc32_d (long rs1) { return _rvintrin_crc32 (rs1, 64); }
-+static inline long _rv_crc32c_d(long rs1) { return _rvintrin_crc32c(rs1, 64); }
-+#endif
-+
-+static inline int64_t _rv64_bmatflip(int64_t rs1)
-+{
-+	uint64_t x = rs1;
-+	x = _rv64_shfl(x, 31);
-+	x = _rv64_shfl(x, 31);
-+	x = _rv64_shfl(x, 31);
-+	return x;
-+}
-+
-+static inline int64_t _rv64_bmatxor(int64_t rs1, int64_t rs2)
-+{
-+	// transpose of rs2
-+	int64_t rs2t = _rv64_bmatflip(rs2);
-+
-+	uint8_t u[8]; // rows of rs1
-+	uint8_t v[8]; // cols of rs2
-+
-+	for (int i = 0; i < 8; i++) {
-+		u[i] = rs1 >> (i*8);
-+		v[i] = rs2t >> (i*8);
-+	}
-+
-+	uint64_t x = 0;
-+	for (int i = 0; i < 64; i++) {
-+		if (_rv64_pcnt(u[i / 8] & v[i % 8]) & 1)
-+			x |= 1LL << i;
-+	}
-+
-+	return x;
-+}
-+
-+static inline int64_t _rv64_bmator(int64_t rs1, int64_t rs2)
-+{
-+	// transpose of rs2
-+	int64_t rs2t = _rv64_bmatflip(rs2);
-+
-+	uint8_t u[8]; // rows of rs1
-+	uint8_t v[8]; // cols of rs2
-+
-+	for (int i = 0; i < 8; i++) {
-+		u[i] = rs1 >> (i*8);
-+		v[i] = rs2t >> (i*8);
-+	}
-+
-+	uint64_t x = 0;
-+	for (int i = 0; i < 64; i++) {
-+		if ((u[i / 8] & v[i % 8]) != 0)
-+			x |= 1LL << i;
-+	}
-+
-+	return x;
-+}
-+
-+static inline long _rv_cmix(long rs2, long rs1, long rs3)
-+{
-+	return (rs1 & rs2) | (rs3 & ~rs2);
-+}
-+
-+static inline long _rv_cmov(long rs2, long rs1, long rs3)
-+{
-+	return rs2 ? rs1 : rs3;
-+}
-+
-+static inline int32_t _rv32_fsl(int32_t rs1, int32_t rs3, int32_t rs2)
-+{
-+	int shamt = rs2 & 63;
-+	uint32_t A = rs1, B = rs3;
-+	if (shamt >= 32) {
-+		shamt -= 32;
-+		A = rs3;
-+		B = rs1;
-+	}
-+	return shamt ? (A << shamt) | (B >> (32-shamt)) : A;
-+}
-+
-+static inline int32_t _rv32_fsr(int32_t rs1, int32_t rs3, int32_t rs2)
-+{
-+	int shamt = rs2 & 63;
-+	uint32_t A = rs1, B = rs3;
-+	if (shamt >= 32) {
-+		shamt -= 32;
-+		A = rs3;
-+		B = rs1;
-+	}
-+	return shamt ? (A >> shamt) | (B << (32-shamt)) : A;
-+}
-+
-+static inline int64_t _rv64_fsl(int64_t rs1, int64_t rs3, int64_t rs2)
-+{
-+	int shamt = rs2 & 127;
-+	uint64_t A = rs1, B = rs3;
-+	if (shamt >= 64) {
-+		shamt -= 64;
-+		A = rs3;
-+		B = rs1;
-+	}
-+	return shamt ? (A << shamt) | (B >> (64-shamt)) : A;
-+}
-+
-+static inline int64_t _rv64_fsr(int64_t rs1, int64_t rs3, int64_t rs2)
-+{
-+	int shamt = rs2 & 127;
-+	uint64_t A = rs1, B = rs3;
-+	if (shamt >= 64) {
-+		shamt -= 64;
-+		A = rs3;
-+		B = rs1;
-+	}
-+	return shamt ? (A >> shamt) | (B << (64-shamt)) : A;
-+}
-+
-+static inline long _rv_andn(long rs1, long rs2) { return rs1 & ~rs2; }
-+static inline long _rv_orn (long rs1, long rs2) { return rs1 | ~rs2; }
-+static inline long _rv_xnor(long rs1, long rs2) { return rs1 ^ ~rs2; }
-+
-+#endif // RVINTRIN_EMULATE
-+
-+#ifdef RVINTRIN_RV32
-+static inline long _rv_clz    (long rs1) { return _rv32_clz   (rs1); }
-+static inline long _rv_ctz    (long rs1) { return _rv32_ctz   (rs1); }
-+static inline long _rv_pcnt   (long rs1) { return _rv32_pcnt  (rs1); }
-+static inline long _rv_sext_b (long rs1) { return _rv32_sext_b(rs1); }
-+static inline long _rv_sext_h (long rs1) { return _rv32_sext_h(rs1); }
-+
-+static inline long _rv_pack   (long rs1, long rs2) { return _rv32_pack   (rs1, rs2); }
-+static inline long _rv_packu  (long rs1, long rs2) { return _rv32_packu  (rs1, rs2); }
-+static inline long _rv_packh  (long rs1, long rs2) { return _rv32_packh  (rs1, rs2); }
-+static inline long _rv_bfp    (long rs1, long rs2) { return _rv32_bfp    (rs1, rs2); }
-+static inline long _rv_min    (long rs1, long rs2) { return _rv32_min    (rs1, rs2); }
-+static inline long _rv_minu   (long rs1, long rs2) { return _rv32_minu   (rs1, rs2); }
-+static inline long _rv_max    (long rs1, long rs2) { return _rv32_max    (rs1, rs2); }
-+static inline long _rv_maxu   (long rs1, long rs2) { return _rv32_maxu   (rs1, rs2); }
-+static inline long _rv_bset  (long rs1, long rs2) { return _rv32_bset  (rs1, rs2); }
-+static inline long _rv_bclr  (long rs1, long rs2) { return _rv32_bclr  (rs1, rs2); }
-+static inline long _rv_binv  (long rs1, long rs2) { return _rv32_binv  (rs1, rs2); }
-+static inline long _rv_bext  (long rs1, long rs2) { return _rv32_bext  (rs1, rs2); }
-+static inline long _rv_sll    (long rs1, long rs2) { return _rv32_sll    (rs1, rs2); }
-+static inline long _rv_srl    (long rs1, long rs2) { return _rv32_srl    (rs1, rs2); }
-+static inline long _rv_sra    (long rs1, long rs2) { return _rv32_sra    (rs1, rs2); }
-+static inline long _rv_slo    (long rs1, long rs2) { return _rv32_slo    (rs1, rs2); }
-+static inline long _rv_sro    (long rs1, long rs2) { return _rv32_sro    (rs1, rs2); }
-+static inline long _rv_rol    (long rs1, long rs2) { return _rv32_rol    (rs1, rs2); }
-+static inline long _rv_ror    (long rs1, long rs2) { return _rv32_ror    (rs1, rs2); }
-+static inline long _rv_grev   (long rs1, long rs2) { return _rv32_grev   (rs1, rs2); }
-+static inline long _rv_gorc   (long rs1, long rs2) { return _rv32_gorc   (rs1, rs2); }
-+static inline long _rv_shfl   (long rs1, long rs2) { return _rv32_shfl   (rs1, rs2); }
-+static inline long _rv_unshfl (long rs1, long rs2) { return _rv32_unshfl (rs1, rs2); }
-+static inline long _rv_bext   (long rs1, long rs2) { return _rv32_bext   (rs1, rs2); }
-+static inline long _rv_bdep   (long rs1, long rs2) { return _rv32_bdep   (rs1, rs2); }
-+static inline long _rv_clmul  (long rs1, long rs2) { return _rv32_clmul  (rs1, rs2); }
-+static inline long _rv_clmulh (long rs1, long rs2) { return _rv32_clmulh (rs1, rs2); }
-+static inline long _rv_clmulr (long rs1, long rs2) { return _rv32_clmulr (rs1, rs2); }
-+
-+static inline long _rv_fsl(long rs1, long rs3, long rs2) { return _rv32_fsl(rs1, rs3, rs2); }
-+static inline long _rv_fsr(long rs1, long rs3, long rs2) { return _rv32_fsr(rs1, rs3, rs2); }
-+#endif
-+
-+#ifdef RVINTRIN_RV64
-+static inline long _rv_clz     (long rs1) { return _rv64_clz     (rs1); }
-+static inline long _rv_ctz     (long rs1) { return _rv64_ctz     (rs1); }
-+static inline long _rv_pcnt    (long rs1) { return _rv64_pcnt    (rs1); }
-+static inline long _rv_sext_b  (long rs1) { return _rv64_sext_b  (rs1); }
-+static inline long _rv_sext_h  (long rs1) { return _rv64_sext_h  (rs1); }
-+static inline long _rv_bmatflip(long rs1) { return _rv64_bmatflip(rs1); }
-+
-+static inline long _rv_pack   (long rs1, long rs2) { return _rv64_pack   (rs1, rs2); }
-+static inline long _rv_packu  (long rs1, long rs2) { return _rv64_packu  (rs1, rs2); }
-+static inline long _rv_packh  (long rs1, long rs2) { return _rv64_packh  (rs1, rs2); }
-+static inline long _rv_bfp    (long rs1, long rs2) { return _rv64_bfp    (rs1, rs2); }
-+static inline long _rv_min    (long rs1, long rs2) { return _rv64_min    (rs1, rs2); }
-+static inline long _rv_minu   (long rs1, long rs2) { return _rv64_minu   (rs1, rs2); }
-+static inline long _rv_max    (long rs1, long rs2) { return _rv64_max    (rs1, rs2); }
-+static inline long _rv_maxu   (long rs1, long rs2) { return _rv64_maxu   (rs1, rs2); }
-+static inline long _rv_bset  (long rs1, long rs2) { return _rv64_bset  (rs1, rs2); }
-+static inline long _rv_bclr  (long rs1, long rs2) { return _rv64_bclr  (rs1, rs2); }
-+static inline long _rv_binv  (long rs1, long rs2) { return _rv64_binv  (rs1, rs2); }
-+static inline long _rv_bext  (long rs1, long rs2) { return _rv64_bext  (rs1, rs2); }
-+static inline long _rv_sll    (long rs1, long rs2) { return _rv64_sll    (rs1, rs2); }
-+static inline long _rv_srl    (long rs1, long rs2) { return _rv64_srl    (rs1, rs2); }
-+static inline long _rv_sra    (long rs1, long rs2) { return _rv64_sra    (rs1, rs2); }
-+static inline long _rv_slo    (long rs1, long rs2) { return _rv64_slo    (rs1, rs2); }
-+static inline long _rv_sro    (long rs1, long rs2) { return _rv64_sro    (rs1, rs2); }
-+static inline long _rv_rol    (long rs1, long rs2) { return _rv64_rol    (rs1, rs2); }
-+static inline long _rv_ror    (long rs1, long rs2) { return _rv64_ror    (rs1, rs2); }
-+static inline long _rv_grev   (long rs1, long rs2) { return _rv64_grev   (rs1, rs2); }
-+static inline long _rv_gorc   (long rs1, long rs2) { return _rv64_gorc   (rs1, rs2); }
-+static inline long _rv_shfl   (long rs1, long rs2) { return _rv64_shfl   (rs1, rs2); }
-+static inline long _rv_unshfl (long rs1, long rs2) { return _rv64_unshfl (rs1, rs2); }
-+static inline long _rv_bext   (long rs1, long rs2) { return _rv64_bext   (rs1, rs2); }
-+static inline long _rv_bdep   (long rs1, long rs2) { return _rv64_bdep   (rs1, rs2); }
-+static inline long _rv_clmul  (long rs1, long rs2) { return _rv64_clmul  (rs1, rs2); }
-+static inline long _rv_clmulh (long rs1, long rs2) { return _rv64_clmulh (rs1, rs2); }
-+static inline long _rv_clmulr (long rs1, long rs2) { return _rv64_clmulr (rs1, rs2); }
-+static inline long _rv_bmator (long rs1, long rs2) { return _rv64_bmator (rs1, rs2); }
-+static inline long _rv_bmatxor(long rs1, long rs2) { return _rv64_bmatxor(rs1, rs2); }
-+
-+static inline long _rv_fsl(long rs1, long rs3, long rs2) { return _rv64_fsl(rs1, rs3, rs2); }
-+static inline long _rv_fsr(long rs1, long rs3, long rs2) { return _rv64_fsr(rs1, rs3, rs2); }
-+#endif
-+
-+#ifdef RVINTRIN_RV32
-+
-+#define RVINTRIN_GREV_PSEUDO_OP32(_arg, _name) \
-+	static inline long    _rv_   ## _name(long    rs1) { return _rv_grev  (rs1, _arg); } \
-+	static inline int32_t _rv32_ ## _name(int32_t rs1) { return _rv32_grev(rs1, _arg); }
-+
-+#define RVINTRIN_GREV_PSEUDO_OP64(_arg, _name)
-+
-+#else
-+
-+#define RVINTRIN_GREV_PSEUDO_OP32(_arg, _name) \
-+	static inline int32_t _rv32_ ## _name(int32_t rs1) { return _rv32_grev(rs1, _arg); }
-+
-+#define RVINTRIN_GREV_PSEUDO_OP64(_arg, _name) \
-+	static inline long    _rv_   ## _name(long    rs1) { return _rv_grev  (rs1, _arg); } \
-+	static inline int64_t _rv64_ ## _name(int64_t rs1) { return _rv64_grev(rs1, _arg); }
-+#endif
-+
-+RVINTRIN_GREV_PSEUDO_OP32( 1, rev_p)
-+RVINTRIN_GREV_PSEUDO_OP32( 2, rev2_n)
-+RVINTRIN_GREV_PSEUDO_OP32( 3, rev_n)
-+RVINTRIN_GREV_PSEUDO_OP32( 4, rev4_b)
-+RVINTRIN_GREV_PSEUDO_OP32( 6, rev2_b)
-+RVINTRIN_GREV_PSEUDO_OP32( 7, rev_b)
-+RVINTRIN_GREV_PSEUDO_OP32( 8, rev8_h)
-+RVINTRIN_GREV_PSEUDO_OP32(12, rev4_h)
-+RVINTRIN_GREV_PSEUDO_OP32(14, rev2_h)
-+RVINTRIN_GREV_PSEUDO_OP32(15, rev_h)
-+RVINTRIN_GREV_PSEUDO_OP32(16, rev16)
-+RVINTRIN_GREV_PSEUDO_OP32(24, rev8)
-+RVINTRIN_GREV_PSEUDO_OP32(28, rev4)
-+RVINTRIN_GREV_PSEUDO_OP32(30, rev2)
-+RVINTRIN_GREV_PSEUDO_OP32(31, rev)
-+
-+RVINTRIN_GREV_PSEUDO_OP64( 1, rev_p)
-+RVINTRIN_GREV_PSEUDO_OP64( 2, rev2_n)
-+RVINTRIN_GREV_PSEUDO_OP64( 3, rev_n)
-+RVINTRIN_GREV_PSEUDO_OP64( 4, rev4_b)
-+RVINTRIN_GREV_PSEUDO_OP64( 6, rev2_b)
-+RVINTRIN_GREV_PSEUDO_OP64( 7, rev_b)
-+RVINTRIN_GREV_PSEUDO_OP64( 8, rev8_h)
-+RVINTRIN_GREV_PSEUDO_OP64(12, rev4_h)
-+RVINTRIN_GREV_PSEUDO_OP64(14, rev2_h)
-+RVINTRIN_GREV_PSEUDO_OP64(15, rev_h)
-+RVINTRIN_GREV_PSEUDO_OP64(16, rev16_w)
-+RVINTRIN_GREV_PSEUDO_OP64(24, rev8_w)
-+RVINTRIN_GREV_PSEUDO_OP64(28, rev4_w)
-+RVINTRIN_GREV_PSEUDO_OP64(30, rev2_w)
-+RVINTRIN_GREV_PSEUDO_OP64(31, rev_w)
-+RVINTRIN_GREV_PSEUDO_OP64(32, rev32)
-+RVINTRIN_GREV_PSEUDO_OP64(48, rev16)
-+RVINTRIN_GREV_PSEUDO_OP64(56, rev8)
-+RVINTRIN_GREV_PSEUDO_OP64(60, rev4)
-+RVINTRIN_GREV_PSEUDO_OP64(62, rev2)
-+RVINTRIN_GREV_PSEUDO_OP64(63, rev)
-+
-+#ifdef RVINTRIN_RV32
-+
-+#define RVINTRIN_GORC_PSEUDO_OP32(_arg, _name) \
-+	static inline long    _rv_   ## _name(long    rs1) { return _rv_gorc  (rs1, _arg); } \
-+	static inline int32_t _rv32_ ## _name(int32_t rs1) { return _rv32_gorc(rs1, _arg); }
-+
-+#define RVINTRIN_GORC_PSEUDO_OP64(_arg, _name)
-+
-+#else
-+
-+#define RVINTRIN_GORC_PSEUDO_OP32(_arg, _name) \
-+	static inline int32_t _rv32_ ## _name(int32_t rs1) { return _rv32_gorc(rs1, _arg); }
-+
-+#define RVINTRIN_GORC_PSEUDO_OP64(_arg, _name) \
-+	static inline long    _rv_   ## _name(long    rs1) { return _rv_gorc  (rs1, _arg); } \
-+	static inline int64_t _rv64_ ## _name(int64_t rs1) { return _rv64_gorc(rs1, _arg); }
-+#endif
-+
-+RVINTRIN_GORC_PSEUDO_OP32( 1, orc_p)
-+RVINTRIN_GORC_PSEUDO_OP32( 2, orc2_n)
-+RVINTRIN_GORC_PSEUDO_OP32( 3, orc_n)
-+RVINTRIN_GORC_PSEUDO_OP32( 4, orc4_b)
-+RVINTRIN_GORC_PSEUDO_OP32( 6, orc2_b)
-+RVINTRIN_GORC_PSEUDO_OP32( 7, orc_b)
-+RVINTRIN_GORC_PSEUDO_OP32( 8, orc8_h)
-+RVINTRIN_GORC_PSEUDO_OP32(12, orc4_h)
-+RVINTRIN_GORC_PSEUDO_OP32(14, orc2_h)
-+RVINTRIN_GORC_PSEUDO_OP32(15, orc_h)
-+RVINTRIN_GORC_PSEUDO_OP32(16, orc16)
-+RVINTRIN_GORC_PSEUDO_OP32(24, orc8)
-+RVINTRIN_GORC_PSEUDO_OP32(28, orc4)
-+RVINTRIN_GORC_PSEUDO_OP32(30, orc2)
-+RVINTRIN_GORC_PSEUDO_OP32(31, orc)
-+
-+RVINTRIN_GORC_PSEUDO_OP64( 1, orc_p)
-+RVINTRIN_GORC_PSEUDO_OP64( 2, orc2_n)
-+RVINTRIN_GORC_PSEUDO_OP64( 3, orc_n)
-+RVINTRIN_GORC_PSEUDO_OP64( 4, orc4_b)
-+RVINTRIN_GORC_PSEUDO_OP64( 6, orc2_b)
-+RVINTRIN_GORC_PSEUDO_OP64( 7, orc_b)
-+RVINTRIN_GORC_PSEUDO_OP64( 8, orc8_h)
-+RVINTRIN_GORC_PSEUDO_OP64(12, orc4_h)
-+RVINTRIN_GORC_PSEUDO_OP64(14, orc2_h)
-+RVINTRIN_GORC_PSEUDO_OP64(15, orc_h)
-+RVINTRIN_GORC_PSEUDO_OP64(16, orc16_w)
-+RVINTRIN_GORC_PSEUDO_OP64(24, orc8_w)
-+RVINTRIN_GORC_PSEUDO_OP64(28, orc4_w)
-+RVINTRIN_GORC_PSEUDO_OP64(30, orc2_w)
-+RVINTRIN_GORC_PSEUDO_OP64(31, orc_w)
-+RVINTRIN_GORC_PSEUDO_OP64(32, orc32)
-+RVINTRIN_GORC_PSEUDO_OP64(48, orc16)
-+RVINTRIN_GORC_PSEUDO_OP64(56, orc8)
-+RVINTRIN_GORC_PSEUDO_OP64(60, orc4)
-+RVINTRIN_GORC_PSEUDO_OP64(62, orc2)
-+RVINTRIN_GORC_PSEUDO_OP64(63, orc)
-+
-+#ifdef RVINTRIN_RV32
-+
-+#define RVINTRIN_SHFL_PSEUDO_OP32(_arg, _name) \
-+	static inline long    _rv_     ## _name(long    rs1) { return _rv_shfl    (rs1, _arg); } \
-+	static inline long    _rv_un   ## _name(long    rs1) { return _rv_unshfl  (rs1, _arg); } \
-+	static inline int32_t _rv32_un ## _name(int32_t rs1) { return _rv32_shfl  (rs1, _arg); } \
-+	static inline int32_t _rv32_   ## _name(int32_t rs1) { return _rv32_unshfl(rs1, _arg); }
-+
-+#define RVINTRIN_SHFL_PSEUDO_OP64(_arg, _name)
-+
-+#else
-+
-+#define RVINTRIN_SHFL_PSEUDO_OP32(_arg, _name)
-+
-+#define RVINTRIN_SHFL_PSEUDO_OP64(_arg, _name) \
-+	static inline long    _rv_     ## _name(long    rs1) { return _rv_shfl    (rs1, _arg); } \
-+	static inline long    _rv_un   ## _name(long    rs1) { return _rv_unshfl  (rs1, _arg); } \
-+	static inline int64_t _rv64_   ## _name(int64_t rs1) { return _rv64_shfl  (rs1, _arg); } \
-+	static inline int64_t _rv64_un ## _name(int64_t rs1) { return _rv64_unshfl(rs1, _arg); }
-+
-+#endif
-+
-+RVINTRIN_SHFL_PSEUDO_OP32( 1, zip_n)
-+RVINTRIN_SHFL_PSEUDO_OP32( 2, zip2_b)
-+RVINTRIN_SHFL_PSEUDO_OP32( 3, zip_b)
-+RVINTRIN_SHFL_PSEUDO_OP32( 4, zip4_h)
-+RVINTRIN_SHFL_PSEUDO_OP32( 6, zip2_h)
-+RVINTRIN_SHFL_PSEUDO_OP32( 7, zip_h)
-+RVINTRIN_SHFL_PSEUDO_OP32( 8, zip8)
-+RVINTRIN_SHFL_PSEUDO_OP32(12, zip4)
-+RVINTRIN_SHFL_PSEUDO_OP32(14, zip2)
-+RVINTRIN_SHFL_PSEUDO_OP32(15, zip)
-+
-+RVINTRIN_SHFL_PSEUDO_OP64( 1, zip_n)
-+RVINTRIN_SHFL_PSEUDO_OP64( 2, zip2_b)
-+RVINTRIN_SHFL_PSEUDO_OP64( 3, zip_b)
-+RVINTRIN_SHFL_PSEUDO_OP64( 4, zip4_h)
-+RVINTRIN_SHFL_PSEUDO_OP64( 6, zip2_h)
-+RVINTRIN_SHFL_PSEUDO_OP64( 7, zip_h)
-+RVINTRIN_SHFL_PSEUDO_OP64( 8, zip8_w)
-+RVINTRIN_SHFL_PSEUDO_OP64(12, zip4_w)
-+RVINTRIN_SHFL_PSEUDO_OP64(14, zip2_w)
-+RVINTRIN_SHFL_PSEUDO_OP64(15, zip_w)
-+RVINTRIN_SHFL_PSEUDO_OP64(16, zip16)
-+RVINTRIN_SHFL_PSEUDO_OP64(24, zip8)
-+RVINTRIN_SHFL_PSEUDO_OP64(28, zip4)
-+RVINTRIN_SHFL_PSEUDO_OP64(30, zip2)
-+RVINTRIN_SHFL_PSEUDO_OP64(31, zip)
-+
-+#endif // RVINTRIN_H
--- 
-2.33.1
-

+ 58 - 0
recipes-devtools/gcc/gcc/0009-add-multilib-config-for-baremetal.patch

@@ -0,0 +1,58 @@
+From 8d4080b38baab581c714d29527abb2172efe6883 Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Sun, 9 Oct 2022 02:11:31 -0700
+Subject: [PATCH 09/11] add multilib config for baremetal
+
+---
+ gcc/config/riscv/t-elf-multilib | 41 +++++++++------------------------
+ 1 file changed, 11 insertions(+), 30 deletions(-)
+
+diff --git a/gcc/config/riscv/t-elf-multilib b/gcc/config/riscv/t-elf-multilib
+index 19f9434616c..5307a8610eb 100644
+--- a/gcc/config/riscv/t-elf-multilib
++++ b/gcc/config/riscv/t-elf-multilib
+@@ -1,30 +1,11 @@
+-# This file was generated by multilib-generator with the command:
+-#  ./multilib-generator rv32i-ilp32--c rv32im-ilp32--c rv32iac-ilp32-- rv32imac-ilp32-- rv32imafc-ilp32f-rv32imafdc- rv64imac-lp64-- rv64imafdc-lp64d--
+-MULTILIB_OPTIONS = march=rv32i/march=rv32ic/march=rv32im/march=rv32imc/march=rv32iac/march=rv32imac/march=rv32imafc/march=rv32imafdc/march=rv32gc/march=rv64imac/march=rv64imafdc/march=rv64gc mabi=ilp32/mabi=ilp32f/mabi=lp64/mabi=lp64d
+-MULTILIB_DIRNAMES = rv32i \
+-rv32ic \
+-rv32im \
+-rv32imc \
+-rv32iac \
+-rv32imac \
+-rv32imafc \
+-rv32imafdc \
+-rv32gc \
+-rv64imac \
+-rv64imafdc \
+-rv64gc ilp32 \
+-ilp32f \
+-lp64 \
+-lp64d
+-MULTILIB_REQUIRED = march=rv32i/mabi=ilp32 \
+-march=rv32im/mabi=ilp32 \
+-march=rv32iac/mabi=ilp32 \
+-march=rv32imac/mabi=ilp32 \
+-march=rv32imafc/mabi=ilp32f \
+-march=rv64imac/mabi=lp64 \
+-march=rv64imafdc/mabi=lp64d
+-MULTILIB_REUSE = march.rv32i/mabi.ilp32=march.rv32ic/mabi.ilp32 \
+-march.rv32im/mabi.ilp32=march.rv32imc/mabi.ilp32 \
+-march.rv32imafc/mabi.ilp32f=march.rv32imafdc/mabi.ilp32f \
+-march.rv32imafc/mabi.ilp32f=march.rv32gc/mabi.ilp32f \
+-march.rv64imafdc/mabi.lp64d=march.rv64gc/mabi.lp64d
++#  ./riscv-gcc/gcc/config/riscv/multilib-generator rv64imafdc_zicsr_zifencei-lp64d-- rv64imafdc_zicsr_zifencei_zba_zbb_zbc_zbs-lp64d-- rv64imafdcv_zicsr_zifencei-lp64d-- rv64imafdcv_zicsr_zifencei_zba_zbb_zbc_zbs-lp64d--
++MULTILIB_OPTIONS = march=rv64imafdc_zicsr_zifencei/march=rv64imafdc_zicsr_zifencei_zba_zbb_zbc_zbs/march=rv64imafdcv_zicsr_zifencei_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b/march=rv64imafdcv_zicsr_zifencei_zba_zbb_zbc_zbs_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b mabi=lp64d 
++MULTILIB_DIRNAMES = rv64imafdc_zicsr_zifencei \
++rv64imafdc_zicsr_zifencei_zba_zbb_zbc_zbs \
++rv64imafdcv_zicsr_zifencei_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b \
++rv64imafdcv_zicsr_zifencei_zba_zbb_zbc_zbs_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b lp64d 
++MULTILIB_REQUIRED = march=rv64imafdc_zicsr_zifencei/mabi=lp64d \
++march=rv64imafdc_zicsr_zifencei_zba_zbb_zbc_zbs/mabi=lp64d \
++march=rv64imafdcv_zicsr_zifencei_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b/mabi=lp64d \
++march=rv64imafdcv_zicsr_zifencei_zba_zbb_zbc_zbs_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b/mabi=lp64d
++MULTILIB_REUSE = 
+-- 
+2.25.1
+

+ 3 - 3
recipes-devtools/gcc/gcc/0015-gcc-armv4-pass-fix-v4bx-to-linker-to-support-EABI.patch → recipes-devtools/gcc/gcc/0009-gcc-armv4-pass-fix-v4bx-to-linker-to-support-EABI.patch

@@ -1,4 +1,4 @@
-From 0ae7090dec149cb2ff0c87eef87c043d4000ece1 Mon Sep 17 00:00:00 2001
+From 32129f9682d0d27fc67af10f077ad2768935cbe6 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Fri, 29 Mar 2013 09:30:32 +0400
 Subject: [PATCH] gcc: armv4: pass fix-v4bx to linker to support EABI.
@@ -19,12 +19,12 @@ Upstream-Status: Pending
  1 file changed, 5 insertions(+), 1 deletion(-)
 
 diff --git a/gcc/config/arm/linux-eabi.h b/gcc/config/arm/linux-eabi.h
-index 6bd95855827..77befab5da8 100644
+index 17c18b27145..8eacb099317 100644
 --- a/gcc/config/arm/linux-eabi.h
 +++ b/gcc/config/arm/linux-eabi.h
 @@ -91,10 +91,14 @@
  #define MUSL_DYNAMIC_LINKER \
-   "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}%{mfdpic:-fdpic}.so.1"
+   SYSTEMLIBS_DIR "ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}%{mfdpic:-fdpic}.so.1"
  
 +/* For armv4 we pass --fix-v4bx to linker to support EABI */
 +#undef TARGET_FIX_V4BX_SPEC

+ 0 - 45
recipes-devtools/gcc/gcc/0009-update-B-version-from-0.93-to-0.94.patch

@@ -1,45 +0,0 @@
-From 7bcd04ce147c1cd442a1e6e8b9ba8b11e7d3f483 Mon Sep 17 00:00:00 2001
-From: "yilun.xie" <yilun.xie@starfivetech.com>
-Date: Mon, 11 Oct 2021 10:00:48 +0800
-Subject: [PATCH 09/15] update B version from 0.93 to 0.94
-
----
- gcc/common/config/riscv/riscv-common.c | 22 +++++++++++-----------
- 1 file changed, 11 insertions(+), 11 deletions(-)
-
-diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
-index c7b6158af4b..28475fc76b5 100644
---- a/gcc/common/config/riscv/riscv-common.c
-+++ b/gcc/common/config/riscv/riscv-common.c
-@@ -111,17 +111,17 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
-   {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
-   {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
- 
--  {"b",   ISA_SPEC_CLASS_NONE, 0, 93},
--  {"zba", ISA_SPEC_CLASS_NONE, 0, 93},
--  {"zbb", ISA_SPEC_CLASS_NONE, 0, 93},
--  {"zbc", ISA_SPEC_CLASS_NONE, 0, 93},
--  {"zbe", ISA_SPEC_CLASS_NONE, 0, 93},
--  {"zbf", ISA_SPEC_CLASS_NONE, 0, 93},
--  {"zbr", ISA_SPEC_CLASS_NONE, 0, 93},
--  {"zbm", ISA_SPEC_CLASS_NONE, 0, 93},
--  {"zbs", ISA_SPEC_CLASS_NONE, 0, 93},
--  {"zbt", ISA_SPEC_CLASS_NONE, 0, 93},
--  {"zbp", ISA_SPEC_CLASS_NONE, 0, 93},
-+  {"b",   ISA_SPEC_CLASS_NONE, 0, 94},
-+  {"zba", ISA_SPEC_CLASS_NONE, 0, 94},
-+  {"zbb", ISA_SPEC_CLASS_NONE, 0, 94},
-+  {"zbc", ISA_SPEC_CLASS_NONE, 0, 94},
-+  {"zbe", ISA_SPEC_CLASS_NONE, 0, 94},
-+  {"zbf", ISA_SPEC_CLASS_NONE, 0, 94},
-+  {"zbr", ISA_SPEC_CLASS_NONE, 0, 94},
-+  {"zbm", ISA_SPEC_CLASS_NONE, 0, 94},
-+  {"zbs", ISA_SPEC_CLASS_NONE, 0, 94},
-+  {"zbt", ISA_SPEC_CLASS_NONE, 0, 94},
-+  {"zbp", ISA_SPEC_CLASS_NONE, 0, 94},
-   /* Terminate the list.  */
-   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
- };
--- 
-2.33.1
-

+ 0 - 54
recipes-devtools/gcc/gcc/0010-MIPS64-Default-to-N64-ABI.patch

@@ -1,54 +0,0 @@
-From a2dc2fa4cc7e5d54544d4a7b6601eef79bc26cad Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Fri, 29 Mar 2013 09:23:08 +0400
-Subject: [PATCH] MIPS64: Default to N64 ABI
-
-MIPS64 defaults to n32 ABI, this patch makes it
-so that it defaults to N64 ABI
-
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
-
-Upstream-Status: Inappropriate [OE config specific]
----
- gcc/config.gcc | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/gcc/config.gcc b/gcc/config.gcc
-index 3ec7582f5dd..a046fa6945c 100644
---- a/gcc/config.gcc
-+++ b/gcc/config.gcc
-@@ -2543,29 +2543,29 @@ mips*-*-linux*)				# Linux MIPS, either endian.
- 			default_mips_arch=mips32
- 			;;
- 		mips64el-st-linux-gnu)
--			default_mips_abi=n32
-+			default_mips_abi=64
- 			tm_file="${tm_file} mips/st.h"
- 			tmake_file="${tmake_file} mips/t-st"
- 			enable_mips_multilibs="yes"
- 			;;
- 		mips64octeon*-*-linux*)
--			default_mips_abi=n32
-+			default_mips_abi=64
- 			tm_defines="${tm_defines} MIPS_CPU_STRING_DEFAULT=\\\"octeon\\\""
- 			target_cpu_default=MASK_SOFT_FLOAT_ABI
- 			enable_mips_multilibs="yes"
- 			;;
- 		mipsisa64r6*-*-linux*)
--			default_mips_abi=n32
-+			default_mips_abi=64
- 			default_mips_arch=mips64r6
- 			enable_mips_multilibs="yes"
- 			;;
- 		mipsisa64r2*-*-linux*)
--			default_mips_abi=n32
-+			default_mips_abi=64
- 			default_mips_arch=mips64r2
- 			enable_mips_multilibs="yes"
- 			;;
- 		mips64*-*-linux* | mipsisa64*-*-linux*)
--			default_mips_abi=n32
-+			default_mips_abi=64
- 			enable_mips_multilibs="yes"
- 			;;
- 	esac

+ 0 - 253
recipes-devtools/gcc/gcc/0010-Merge-B-instruction-from-0p94-to-1.0.patch

@@ -1,253 +0,0 @@
-From c1eb999a3aed84d42c792280ea2c313d1c6063ca Mon Sep 17 00:00:00 2001
-From: "yilun.xie" <yilun.xie@starfivetech.com>
-Date: Fri, 22 Oct 2021 16:10:16 +0800
-Subject: [PATCH 10/15] Merge B instruction from 0p94 to 1.0
-
----
- gcc/common/config/riscv/riscv-common.c | 28 +++---------
- gcc/config/riscv/bitmanip.md           | 62 +++++---------------------
- gcc/config/riscv/riscv-opts.h          | 14 +-----
- 3 files changed, 17 insertions(+), 87 deletions(-)
-
-diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
-index 28475fc76b5..48eb558bcf5 100644
---- a/gcc/common/config/riscv/riscv-common.c
-+++ b/gcc/common/config/riscv/riscv-common.c
-@@ -53,13 +53,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
-   {"b", "zbb"},
-   {"b", "zbs"},
-   {"b", "zba"},
--  {"b", "zbp"},
--  {"b", "zbe"},
--  {"b", "zbf"},
-   {"b", "zbc"},
--  {"b", "zbm"},
--  {"b", "zbr"},
--  {"b", "zbt"},
-   {NULL, NULL}
- };
- 
-@@ -111,17 +105,11 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
-   {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
-   {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
- 
--  {"b",   ISA_SPEC_CLASS_NONE, 0, 94},
--  {"zba", ISA_SPEC_CLASS_NONE, 0, 94},
--  {"zbb", ISA_SPEC_CLASS_NONE, 0, 94},
--  {"zbc", ISA_SPEC_CLASS_NONE, 0, 94},
--  {"zbe", ISA_SPEC_CLASS_NONE, 0, 94},
--  {"zbf", ISA_SPEC_CLASS_NONE, 0, 94},
--  {"zbr", ISA_SPEC_CLASS_NONE, 0, 94},
--  {"zbm", ISA_SPEC_CLASS_NONE, 0, 94},
--  {"zbs", ISA_SPEC_CLASS_NONE, 0, 94},
--  {"zbt", ISA_SPEC_CLASS_NONE, 0, 94},
--  {"zbp", ISA_SPEC_CLASS_NONE, 0, 94},
-+  {"b",   ISA_SPEC_CLASS_NONE, 1, 0},
-+  {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
-+  {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
-+  {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
-+  {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
-   /* Terminate the list.  */
-   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
- };
-@@ -929,13 +917,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
-   {"zba", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBA},
-   {"zbb", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBB},
-   {"zbs", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBS},
--  {"zbp", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBP},
--  {"zbr", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBR},
--  {"zbe", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBE},
--  {"zbf", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBF},
-   {"zbc", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBC},
--  {"zbm", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBM},
--  {"zbt", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBT},
-   {NULL, NULL, 0}
- };
- 
-diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
-index 6653219c3f0..ceb5c89dd47 100644
---- a/gcc/config/riscv/bitmanip.md
-+++ b/gcc/config/riscv/bitmanip.md
-@@ -69,7 +69,7 @@
-   [(set (match_operand:X 0 "register_operand" "=r")
- 	(bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
- 			    (match_operand:X 2 "register_operand" "r")))]
--  "TARGET_ZBB || TARGET_ZBP"
-+  "TARGET_ZBB"
-   "<insn>n\t%0,%2,%1"
-   [(set_attr "type" "bitmanip")])
- 
-@@ -77,7 +77,7 @@
-   [(set (match_operand:X 0 "register_operand" "=r")
- 	(not:X (xor:X (match_operand:X 1 "register_operand" "r")
- 		      (match_operand:X 2 "register_operand" "r"))))]
--  "TARGET_ZBB || TARGET_ZBP"
-+  "TARGET_ZBB"
-   "xnor\t%0,%1,%2"
-   [(set_attr "type" "bitmanip")])
-  
-@@ -86,7 +86,7 @@
- (define_insn "*zero_extendhi<GPR:mode>2_bitmanip"
-   [(set (match_operand:GPR 0 "register_operand" "=r,r")
- 	(zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
--  "TARGET_ZBB || TARGET_ZBP"
-+  "TARGET_ZBB"
-   "@
-    zext.h\t%0,%1
-    lhu\t%0,%1"
-@@ -301,7 +301,7 @@
-   [(set (match_operand:SI 0 "register_operand" "=r")
- 	(rotatert:SI (match_operand:SI 1 "register_operand" "r")
- 		     (match_operand:QI 2 "arith_operand" "rI")))]
--  "TARGET_ZBB || TARGET_ZBP"
-+  "TARGET_ZBB"
-   { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; }
-   [(set_attr "type" "bitmanip")])
- 
-@@ -309,7 +309,7 @@
-   [(set (match_operand:DI 0 "register_operand" "=r")
- 	(rotatert:DI (match_operand:DI 1 "register_operand" "r")
- 		     (match_operand:QI 2 "arith_operand" "rI")))]
--  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
-+  "TARGET_64BIT && TARGET_ZBB"
-   "ror%i2\t%0,%1,%2"
-   [(set_attr "type" "bitmanip")])
- 
-@@ -317,7 +317,7 @@
-   [(match_operand:SI 0 "register_operand" "=r")
-    (match_operand:SI 1 "register_operand" "r")
-    (match_operand:SI 2 "register_operand" "r")]
--  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
-+  "TARGET_64BIT && TARGET_ZBB"
- {
-   emit_insn (gen_rotlsi3 (operands[0], operands[1], operands[2]));
-   DONE;
-@@ -327,7 +327,7 @@
-   [(set (match_operand:SI 0 "register_operand" "=r")
- 	(rotate:SI (match_operand:SI 1 "register_operand" "r")
- 		   (match_operand:QI 2 "register_operand" "r")))]
--  "TARGET_ZBB || TARGET_ZBP"
-+  "TARGET_ZBB"
-   { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; }
-   [(set_attr "type" "bitmanip")])
- 
-@@ -335,7 +335,7 @@
-   [(set (match_operand:DI 0 "register_operand" "=r")
- 	(rotate:DI (match_operand:DI 1 "register_operand" "r")
- 		   (match_operand:QI 2 "register_operand" "r")))]
--  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
-+  "TARGET_64BIT && TARGET_ZBB"
-   "rol\t%0,%1,%2"
-   [(set_attr "type" "bitmanip")])
- 
-@@ -343,7 +343,7 @@
-   [(set (match_operand:DI 0 "register_operand" "=r")
- 	(sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
- 				   (match_operand:QI 2 "register_operand" "r"))))]
--  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
-+  "TARGET_64BIT && TARGET_ZBB"
-   "rolw\t%0,%1,%2"
-   [(set_attr "type" "bitmanip")])
- 
-@@ -352,7 +352,7 @@
- (define_insn "bswapsi2"
-   [(set (match_operand:SI 0 "register_operand" "=r")
-         (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
--  "TARGET_ZBB || TARGET_ZBP"
-+  "TARGET_ZBB"
- {
-   if (TARGET_64BIT)
-     return TARGET_ZBB ? "rev8\t%0,%1\n\tsrai\t%0,%0,32" : "rev8.w\t%0,%1";
-@@ -364,7 +364,7 @@
- (define_insn "bswapdi2"
-   [(set (match_operand:DI 0 "register_operand" "=r")
- 	(bswap:DI (match_operand:DI 1 "register_operand" "r")))]
--  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
-+  "TARGET_64BIT && TARGET_ZBB"
-   "rev8\t%0,%1"
-   [(set_attr "type" "bitmanip")])
- 
-@@ -378,50 +378,10 @@
- 
- ;;; ??? bmat
- 
--(define_insn "*cmix"
--  [(set (match_operand:X 0 "register_operand" "=r")
--	(xor:X (and:X (xor:X (match_operand:X 1 "register_operand" "r")
--			     (match_operand:X 3 "register_operand" "r"))
--		      (match_operand:X 2 "register_operand" "r"))
--	       (match_dup 3)))]
--  "TARGET_ZBT"
--  "cmix\t%0,%2,%1,%3"
--  [(set_attr "type" "bitmanip")])
--
- ;; ??? Can we do this by using the % communtative constraint?
- 
--(define_insn "*cmix2"
--  [(set (match_operand:X 0 "register_operand" "=r")
--	(xor:X (and:X (xor:X (match_operand:X 1 "register_operand" "r")
--			     (match_operand:X 3 "register_operand" "r"))
--		      (match_operand:X 2 "register_operand" "r"))
--	       (match_dup 1)))]
--  "TARGET_ZBT"
--  "cmix\t%0,%2,%3,%1"
--  [(set_attr "type" "bitmanip")])
--
- ;;; ??? cmov
- 
--(define_insn "*mov<X:mode>cc_ne_bitmanip"
--  [(set (match_operand:X 0 "register_operand" "=r")
--	(if_then_else:X
--	 (ne (match_operand:X 1 "register_operand" "r") (const_int 0))
--	 (match_operand:X 2 "register_operand" "r")
--	 (match_operand:X 3 "register_operand" "r")))]
--  "TARGET_ZBT"
--  "cmov\t%0,%1,%2,%3"
--  [(set_attr "type" "bitmanip")])
--
--(define_insn "*mov<X:mode>cc_eq_bitmanip"
--  [(set (match_operand:X 0 "register_operand" "=r")
--	(if_then_else:X
--	 (eq (match_operand:X 1 "register_operand" "r") (const_int 0))
--	 (match_operand:X 2 "register_operand" "r")
--	 (match_operand:X 3 "register_operand" "r")))]
--  "TARGET_ZBT"
--  "cmov\t%0,%1,%3,%2"
--  [(set_attr "type" "bitmanip")])
--
- ;;; ??? fs[lr]
- 
- (define_insn "*shNadd"
-diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
-index ca3190b6414..61d1e9d96d8 100644
---- a/gcc/config/riscv/riscv-opts.h
-+++ b/gcc/config/riscv/riscv-opts.h
-@@ -70,24 +70,12 @@ enum stack_protector_guard {
- #define MASK_ZBA (1 << 0)
- #define MASK_ZBB (1 << 1)
- #define MASK_ZBS (1 << 2)
--#define MASK_ZBP (1 << 3)
--#define MASK_ZBE (1 << 4)
--#define MASK_ZBF (1 << 5)
--#define MASK_ZBC (1 << 6)
--#define MASK_ZBR (1 << 7)
--#define MASK_ZBM (1 << 8)
--#define MASK_ZBT (1 << 9)
-+#define MASK_ZBC (1 << 3)
- 
- #define TARGET_ZBA ((riscv_bitmanip_subext & MASK_ZBA) != 0)
- #define TARGET_ZBB ((riscv_bitmanip_subext & MASK_ZBB) != 0)
- #define TARGET_ZBS ((riscv_bitmanip_subext & MASK_ZBS) != 0)
--#define TARGET_ZBP ((riscv_bitmanip_subext & MASK_ZBP) != 0)
--#define TARGET_ZBE ((riscv_bitmanip_subext & MASK_ZBE) != 0)
--#define TARGET_ZBF ((riscv_bitmanip_subext & MASK_ZBF) != 0)
- #define TARGET_ZBC ((riscv_bitmanip_subext & MASK_ZBC) != 0)
--#define TARGET_ZBR ((riscv_bitmanip_subext & MASK_ZBR) != 0)
--#define TARGET_ZBM ((riscv_bitmanip_subext & MASK_ZBM) != 0)
--#define TARGET_ZBT ((riscv_bitmanip_subext & MASK_ZBT) != 0)
- 
- #define MASK_ZICSR    (1 << 0)
- #define MASK_ZIFENCEI (1 << 1)
--- 
-2.33.1
-

+ 7 - 7
recipes-devtools/gcc/gcc/0016-Use-the-multilib-config-files-from-B-instead-of-usin.patch → recipes-devtools/gcc/gcc/0010-Use-the-multilib-config-files-from-B-instead-of-usin.patch

@@ -1,4 +1,4 @@
-From 5ce8aa4615a3816d12c43752323154744517ae9f Mon Sep 17 00:00:00 2001
+From bf85b8bbcb4b77725d4c22c1bb25a29f6ff21038 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Fri, 29 Mar 2013 09:33:04 +0400
 Subject: [PATCH] Use the multilib config files from ${B} instead of using the
@@ -18,10 +18,10 @@ Upstream-Status: Inappropriate [configuration]
  2 files changed, 36 insertions(+), 8 deletions(-)
 
 diff --git a/gcc/configure b/gcc/configure
-index 5160917d73e..e663052cad2 100755
+index 3fc0e2f5813..2f0f0e057a9 100755
 --- a/gcc/configure
 +++ b/gcc/configure
-@@ -13070,10 +13070,20 @@ done
+@@ -13361,10 +13361,20 @@ done
  tmake_file_=
  for f in ${tmake_file}
  do
@@ -46,7 +46,7 @@ index 5160917d73e..e663052cad2 100755
  done
  tmake_file="${tmake_file_}${omp_device_property_tmake_file}"
  
-@@ -13084,6 +13094,10 @@ tm_file_list="options.h"
+@@ -13375,6 +13385,10 @@ tm_file_list="options.h"
  tm_include_list="options.h insn-constants.h"
  for f in $tm_file; do
    case $f in
@@ -58,10 +58,10 @@ index 5160917d73e..e663052cad2 100755
         f=`echo $f | sed 's/^..//'`
         tm_file_list="${tm_file_list} $f"
 diff --git a/gcc/configure.ac b/gcc/configure.ac
-index 50f78308e8a..2b84875b028 100644
+index 46de496b256..6155b83a732 100644
 --- a/gcc/configure.ac
 +++ b/gcc/configure.ac
-@@ -2243,10 +2243,20 @@ done
+@@ -2312,10 +2312,20 @@ done
  tmake_file_=
  for f in ${tmake_file}
  do
@@ -86,7 +86,7 @@ index 50f78308e8a..2b84875b028 100644
  done
  tmake_file="${tmake_file_}${omp_device_property_tmake_file}"
  
-@@ -2257,6 +2267,10 @@ tm_file_list="options.h"
+@@ -2326,6 +2336,10 @@ tm_file_list="options.h"
  tm_include_list="options.h insn-constants.h"
  for f in $tm_file; do
    case $f in

+ 41 - 0
recipes-devtools/gcc/gcc/0010-only-generate-strictly-aligned-code.patch

@@ -0,0 +1,41 @@
+From 6deaf5a014958a132eae634487783c7424ae57c2 Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Wed, 7 Dec 2022 18:36:45 -0800
+Subject: [PATCH 10/11] only generate strictly aligned code
+
+---
+ gcc/config/riscv/riscv.cc | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
+index 3baa05bd364..981dbf60bd1 100644
+--- a/gcc/config/riscv/riscv.cc
++++ b/gcc/config/riscv/riscv.cc
+@@ -5046,9 +5046,12 @@ riscv_option_override (void)
+      -m[no-]strict-align is left unspecified, heed -mtune's advice.  */
+   riscv_slow_unaligned_access_p = (cpu->tune_param->slow_unaligned_access
+ 				   || TARGET_STRICT_ALIGN);
+-  if ((target_flags_explicit & MASK_STRICT_ALIGN) == 0
++  /* if ((target_flags_explicit & MASK_STRICT_ALIGN) == 0
+       && cpu->tune_param->slow_unaligned_access)
+     target_flags |= MASK_STRICT_ALIGN;
++  */
++  /* for dubhe, it will not support unaligned mempry access */
++  target_flags |= MASK_STRICT_ALIGN;
+ 
+   /* If the user hasn't specified a branch cost, use the processor's
+      default.  */
+@@ -5827,6 +5830,10 @@ riscv_asan_shadow_offset (void)
+ #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_ENDIAN)
+ #endif
+ 
++/* For dubhe, it will not support unaligned memory access */
++#undef TARGET_DEFAULT_TARGET_FLAGS
++#define TARGET_DEFAULT_TARGET_FLAGS (MASK_STRICT_ALIGN)
++
+ struct gcc_target targetm = TARGET_INITIALIZER;
+ 
+ #include "gt-riscv.h"
+-- 
+2.25.1
+

+ 1 - 1
recipes-devtools/gcc/gcc/0017-Avoid-using-libdir-from-.la-which-usually-points-to-.patch → recipes-devtools/gcc/gcc/0011-Avoid-using-libdir-from-.la-which-usually-points-to-.patch

@@ -1,4 +1,4 @@
-From 75a1ce0265ca123f74f17a40ad8bd8f26d9c2ab3 Mon Sep 17 00:00:00 2001
+From e5463727ff028cee5e452da38f5b4c44d52e412e Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Fri, 20 Feb 2015 09:39:38 +0000
 Subject: [PATCH] Avoid using libdir from .la which usually points to a host

+ 94 - 0
recipes-devtools/gcc/gcc/0011-Make-ranger-vrp1-default.patch

@@ -0,0 +1,94 @@
+From 7686fe30835daa7e5fea0067f3b923bdae68c988 Mon Sep 17 00:00:00 2001
+From: Andrew MacLeod <amacleod@redhat.com>
+Date: Tue, 25 Oct 2022 16:42:41 -0400
+Subject: [PATCH 11/11] Make ranger vrp1 default.
+
+Turn on ranger as the default vrp1 pass and adjust testcases.
+
+	gcc/
+	* params.opt (param_vrp1_mode): Make ranger default.
+
+	gcc/testsuite/
+	* gcc.dg/pr68217.c: Test [-INF, -INF][0, 0] instead of [-INF, 0].
+	* gcc.dg/tree-ssa/vrp-unreachable.c: New.  Test unreachable removal.
+---
+ gcc/params.opt                                |  2 +-
+ gcc/testsuite/gcc.dg/pr68217.c                |  2 +-
+ .../gcc.dg/tree-ssa/vrp-unreachable.c         | 42 +++++++++++++++++++
+ 3 files changed, 44 insertions(+), 2 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/vrp-unreachable.c
+
+diff --git a/gcc/params.opt b/gcc/params.opt
+index b88e1372005..f629246d9fa 100644
+--- a/gcc/params.opt
++++ b/gcc/params.opt
+@@ -1185,7 +1185,7 @@ Common Joined UInteger Var(param_vect_induction_float) Init(1) IntegerRage(0, 1)
+ Enable loop vectorization of floating point inductions.
+ 
+ -param=vrp1-mode=
+-Common Joined Var(param_vrp1_mode) Enum(vrp_mode) Init(VRP_MODE_VRP) Param Optimization
++Common Joined Var(param_vrp1_mode) Enum(vrp_mode) Init(VRP_MODE_RANGER) Param Optimization
+ --param=vrp1-mode=[vrp|ranger] Specifies the mode VRP1 should operate in.
+ 
+ -param=vrp2-mode=
+diff --git a/gcc/testsuite/gcc.dg/pr68217.c b/gcc/testsuite/gcc.dg/pr68217.c
+index eb4f15e048f..60c80106760 100644
+--- a/gcc/testsuite/gcc.dg/pr68217.c
++++ b/gcc/testsuite/gcc.dg/pr68217.c
+@@ -10,4 +10,4 @@ int foo (void)
+     return 0;
+ }
+ 
+-/* { dg-final { scan-tree-dump "\\\[-INF, 0\\\]" "vrp1" } } */
++/* { dg-final { scan-tree-dump "\\\[-INF, -INF\\\]\\\[0, 0\\\]" "vrp1" } } */
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/vrp-unreachable.c b/gcc/testsuite/gcc.dg/tree-ssa/vrp-unreachable.c
+new file mode 100644
+index 00000000000..cdc57403c6e
+--- /dev/null
++++ b/gcc/testsuite/gcc.dg/tree-ssa/vrp-unreachable.c
+@@ -0,0 +1,42 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-tree-vrp1-alias -fdump-tree-vrp2-alias" } */
++
++void dead (unsigned n);
++void alive (unsigned n);
++
++void func (unsigned n, unsigned m)
++{
++  if (n == 0)
++    __builtin_unreachable();
++  if (n == 1)
++    __builtin_unreachable();
++  if (n & 0x1)
++    __builtin_unreachable();
++  if (n == 2)
++    __builtin_unreachable();
++  if (n == 3)
++    __builtin_unreachable();
++  if (n & 0x2)
++    __builtin_unreachable();
++  if (n == 4)
++    __builtin_unreachable();
++  if (n == 5)
++    __builtin_unreachable();
++  if (n & 0x4)
++    __builtin_unreachable();
++  if (n == 6)
++    __builtin_unreachable();
++  if (n == 7)
++    __builtin_unreachable();
++ if (n <8)
++   dead (n);
++ if (n != m)
++    __builtin_unreachable();
++ alive (n);
++ alive (m);
++}
++
++/* { dg-final { scan-tree-dump-not "dead" "vrp1" } } */
++/* { dg-final { scan-tree-dump-times "builtin_unreachable" 1 "vrp1" } } */
++/* { dg-final { scan-tree-dump-not "builtin_unreachable" "vrp2" } } */
++/* { dg-final { scan-tree-dump-times "fff8" 4 "vrp2" } } */
+-- 
+2.25.1
+

+ 0 - 77
recipes-devtools/gcc/gcc/0011-remove-b-flag-and-use-zba_zbb_zbc_zbs-instead.patch

@@ -1,77 +0,0 @@
-From b4060fc036995229bd9c4c0d7d9b74b45a4ccf50 Mon Sep 17 00:00:00 2001
-From: "max.ma" <max.ma@starfivetech.com>
-Date: Wed, 27 Oct 2021 19:09:37 -0700
-Subject: [PATCH 11/15] remove 'b' flag and use zba_zbb_zbc_zbs instead
-
----
- gcc/common/config/riscv/riscv-common.c |  1 -
- gcc/config/riscv/riscv-opts.h          | 18 +++++++++---------
- gcc/config/riscv/riscv.opt             |  4 +---
- 3 files changed, 10 insertions(+), 13 deletions(-)
-
-diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
-index 48eb558bcf5..a00b20e065a 100644
---- a/gcc/common/config/riscv/riscv-common.c
-+++ b/gcc/common/config/riscv/riscv-common.c
-@@ -105,7 +105,6 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
-   {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
-   {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
- 
--  {"b",   ISA_SPEC_CLASS_NONE, 1, 0},
-   {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
-   {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
-   {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
-diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
-index 61d1e9d96d8..617feebc7bb 100644
---- a/gcc/config/riscv/riscv-opts.h
-+++ b/gcc/config/riscv/riscv-opts.h
-@@ -67,15 +67,15 @@ enum stack_protector_guard {
-   SSP_GLOBAL			/* global canary */
- };
- 
--#define MASK_ZBA (1 << 0)
--#define MASK_ZBB (1 << 1)
--#define MASK_ZBS (1 << 2)
--#define MASK_ZBC (1 << 3)
--
--#define TARGET_ZBA ((riscv_bitmanip_subext & MASK_ZBA) != 0)
--#define TARGET_ZBB ((riscv_bitmanip_subext & MASK_ZBB) != 0)
--#define TARGET_ZBS ((riscv_bitmanip_subext & MASK_ZBS) != 0)
--#define TARGET_ZBC ((riscv_bitmanip_subext & MASK_ZBC) != 0)
-+#define MASK_ZBA      (1 << 0)
-+#define MASK_ZBB      (1 << 1)
-+#define MASK_ZBC      (1 << 2)
-+#define MASK_ZBS      (1 << 3)
-+
-+#define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0)
-+#define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0)
-+#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
-+#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
- 
- #define MASK_ZICSR    (1 << 0)
- #define MASK_ZIFENCEI (1 << 1)
-diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
-index 0e73e2ab758..7f7e1c4f50b 100644
---- a/gcc/config/riscv/riscv.opt
-+++ b/gcc/config/riscv/riscv.opt
-@@ -136,8 +136,6 @@ Mask(64BIT)
- 
- Mask(MUL)
- 
--Mask(BITMANIP)
--
- Mask(ATOMIC)
- 
- Mask(HARD_FLOAT)
-@@ -198,7 +196,7 @@ TargetVariable
- int riscv_zi_subext
- 
- TargetVariable
--int riscv_bitmanip_subext
-+int riscv_zb_subext
- 
- Enum
- Name(isa_spec_class) Type(enum riscv_isa_spec_class)
--- 
-2.33.1
-

+ 4 - 4
recipes-devtools/gcc/gcc/0018-export-CPP.patch → recipes-devtools/gcc/gcc/0012-export-CPP.patch

@@ -1,4 +1,4 @@
-From b6e229a13aebfbb3fe38c216fd51b68bf71cfa9c Mon Sep 17 00:00:00 2001
+From 20afebc61199cd74481b0b831c1b56465cd37fa0 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Fri, 20 Feb 2015 09:40:59 +0000
 Subject: [PATCH] export CPP
@@ -37,14 +37,14 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 1 insertion(+)
 
 diff --git a/Makefile.in b/Makefile.in
-index 047be0255e2..af19589fa95 100644
+index 1d9c83cc566..11819667751 100644
 --- a/Makefile.in
 +++ b/Makefile.in
-@@ -149,6 +149,7 @@ BUILD_EXPORTS = \
+@@ -152,6 +152,7 @@ BUILD_EXPORTS = \
  	AR="$(AR_FOR_BUILD)"; export AR; \
  	AS="$(AS_FOR_BUILD)"; export AS; \
  	CC="$(CC_FOR_BUILD)"; export CC; \
 +	CPP="$(CC_FOR_BUILD) -E"; export CPP; \
  	CFLAGS="$(CFLAGS_FOR_BUILD)"; export CFLAGS; \
  	CONFIG_SHELL="$(SHELL)"; export CONFIG_SHELL; \
- 	CXX="$(CXX_FOR_BUILD)"; export CXX; \
+ 	CPP="$(CPP_FOR_BUILD)"; export CPP; \

+ 0 - 42
recipes-devtools/gcc/gcc/0012-gcc-Fix-argument-list-too-long-error.patch

@@ -1,42 +0,0 @@
-From 12646c0899dec1b127ce71ebacf2571c1c7360f4 Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Fri, 29 Mar 2013 09:26:37 +0400
-Subject: [PATCH] gcc: Fix argument list too long error.
-
-There would be an "Argument list too long" error when the
-build directory is longer than 200, this is caused by:
-
-headers=`echo $(PLUGIN_HEADERS) | tr ' ' '\012' | sort -u`
-
-The PLUGIN_HEADERS is too long before sort, so the "echo" can't handle
-it, use the $(sort list) of GNU make which can handle the too long list
-would fix the problem, the header would be short enough after sorted.
-The "tr ' ' '\012'" was used for translating the space to "\n", the
-$(sort list) doesn't need this.
-
-Signed-off-by: Robert Yang <liezhi.yang@windriver.com>
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
-
-RP: gcc then added *.h and *.def additions to this list, breaking the original
-fix. Add the sort to the original gcc code, leaving the tr+sort to fix the original
-issue but include the new files too as reported by Zhuang <qiuguang.zqg@alibaba-inc.com>
-
-Upstream-Status: Pending
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
----
- gcc/Makefile.in | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/gcc/Makefile.in b/gcc/Makefile.in
-index 7da6f439fff..59c45c81393 100644
---- a/gcc/Makefile.in
-+++ b/gcc/Makefile.in
-@@ -3678,7 +3678,7 @@ install-plugin: installdirs lang.install-plugin s-header-vars install-gengtype
- # We keep the directory structure for files in config, common/config or
- # c-family and .def files. All other files are flattened to a single directory.
- 	$(mkinstalldirs) $(DESTDIR)$(plugin_includedir)
--	headers=`echo $(PLUGIN_HEADERS) $$(cd $(srcdir); echo *.h *.def) | tr ' ' '\012' | sort -u`; \
-+	headers=`echo $(sort $(PLUGIN_HEADERS)) $$(cd $(srcdir); echo *.h *.def) | tr ' ' '\012' | sort -u`; \
- 	srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*|]/\\\\&/g'`; \
- 	for file in $$headers; do \
- 	  if [ -f $$file ] ; then \

+ 0 - 32
recipes-devtools/gcc/gcc/0012-replace-x_riscv_bitmanip_subext-with-x_riscv_bitmani.patch

@@ -1,32 +0,0 @@
-From 718c3eae9b25018221379210a0b14bb5e84d8cda Mon Sep 17 00:00:00 2001
-From: "max.ma" <max.ma@starfivetech.com>
-Date: Wed, 27 Oct 2021 23:06:15 -0700
-Subject: [PATCH 12/15] replace x_riscv_bitmanip_subext with
- x_riscv_bitmanip_subext
-
----
- gcc/common/config/riscv/riscv-common.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
-index a00b20e065a..569cea68461 100644
---- a/gcc/common/config/riscv/riscv-common.c
-+++ b/gcc/common/config/riscv/riscv-common.c
-@@ -913,10 +913,10 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
-   {"zicsr",    &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
-   {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
- 
--  {"zba", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBA},
--  {"zbb", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBB},
--  {"zbs", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBS},
--  {"zbc", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBC},
-+  {"zba", &gcc_options::riscv_zb_subext, MASK_ZBA},
-+  {"zbb", &gcc_options::riscv_zb_subext, MASK_ZBB},
-+  {"zbs", &gcc_options::riscv_zb_subext, MASK_ZBS},
-+  {"zbc", &gcc_options::riscv_zb_subext, MASK_ZBC},
-   {NULL, NULL, 0}
- };
- 
--- 
-2.33.1
-

+ 0 - 110
recipes-devtools/gcc/gcc/0013-Disable-sdt.patch

@@ -1,110 +0,0 @@
-From 7928a4eddc4a6d821a6aa6eaaea1fd60d54e3da9 Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Fri, 29 Mar 2013 09:28:10 +0400
-Subject: [PATCH] Disable sdt.
-
-We don't list dtrace in DEPENDS so we shouldn't be depending on this header.
-It may or may not exist from preivous builds though. To be determinstic, disable
-sdt.h usage always. This avoids build failures if the header is removed after configure
-but before libgcc is compiled for example.
-
-RP 2012/8/7
-
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
-
-Disable sdt for libstdc++-v3.
-
-Signed-off-by: Robert Yang <liezhi.yang@windriver.com>
-
-Upstream-Status: Inappropriate [hack]
----
- gcc/configure             | 12 ++++++------
- gcc/configure.ac          | 18 +++++++++---------
- libstdc++-v3/configure    |  6 +++---
- libstdc++-v3/configure.ac |  2 +-
- 4 files changed, 19 insertions(+), 19 deletions(-)
-
-diff --git a/gcc/configure b/gcc/configure
-index c5d3bc4ee2d..5160917d73e 100755
---- a/gcc/configure
-+++ b/gcc/configure
-@@ -30812,12 +30812,12 @@ fi
- { $as_echo "$as_me:${as_lineno-$LINENO}: checking sys/sdt.h in the target C library" >&5
- $as_echo_n "checking sys/sdt.h in the target C library... " >&6; }
- have_sys_sdt_h=no
--if test -f $target_header_dir/sys/sdt.h; then
--  have_sys_sdt_h=yes
--
--$as_echo "#define HAVE_SYS_SDT_H 1" >>confdefs.h
--
--fi
-+#if test -f $target_header_dir/sys/sdt.h; then
-+#  have_sys_sdt_h=yes
-+#
-+#$as_echo "#define HAVE_SYS_SDT_H 1" >>confdefs.h
-+#
-+#fi
- { $as_echo "$as_me:${as_lineno-$LINENO}: result: $have_sys_sdt_h" >&5
- $as_echo "$have_sys_sdt_h" >&6; }
- 
-diff --git a/gcc/configure.ac b/gcc/configure.ac
-index f83420326d6..50f78308e8a 100644
---- a/gcc/configure.ac
-+++ b/gcc/configure.ac
-@@ -6653,15 +6653,15 @@ fi
- AC_SUBST([enable_default_ssp])
- 
- # Test for <sys/sdt.h> on the target.
--GCC_TARGET_TEMPLATE([HAVE_SYS_SDT_H])
--AC_MSG_CHECKING(sys/sdt.h in the target C library)
--have_sys_sdt_h=no
--if test -f $target_header_dir/sys/sdt.h; then
--  have_sys_sdt_h=yes
--  AC_DEFINE(HAVE_SYS_SDT_H, 1,
--            [Define if your target C library provides sys/sdt.h])
--fi
--AC_MSG_RESULT($have_sys_sdt_h)
-+#GCC_TARGET_TEMPLATE([HAVE_SYS_SDT_H])
-+#AC_MSG_CHECKING(sys/sdt.h in the target C library)
-+#have_sys_sdt_h=no
-+#if test -f $target_header_dir/sys/sdt.h; then
-+#  have_sys_sdt_h=yes
-+#  AC_DEFINE(HAVE_SYS_SDT_H, 1,
-+#            [Define if your target C library provides sys/sdt.h])
-+#fi
-+#AC_MSG_RESULT($have_sys_sdt_h)
- 
- # Check if TFmode long double should be used by default or not.
- # Some glibc targets used DFmode long double, but with glibc 2.4
-diff --git a/libstdc++-v3/configure b/libstdc++-v3/configure
-index a310e9feb6c..c879445b8a6 100755
---- a/libstdc++-v3/configure
-+++ b/libstdc++-v3/configure
-@@ -22014,11 +22014,11 @@ ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
- ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
- ac_compiler_gnu=$ac_cv_c_compiler_gnu
- 
--  if test $glibcxx_cv_sys_sdt_h = yes; then
-+#  if test $glibcxx_cv_sys_sdt_h = yes; then
- 
--$as_echo "#define HAVE_SYS_SDT_H 1" >>confdefs.h
-+#$as_echo "#define HAVE_SYS_SDT_H 1" >>confdefs.h
- 
--  fi
-+#  fi
-   { $as_echo "$as_me:${as_lineno-$LINENO}: result: $glibcxx_cv_sys_sdt_h" >&5
- $as_echo "$glibcxx_cv_sys_sdt_h" >&6; }
- 
-diff --git a/libstdc++-v3/configure.ac b/libstdc++-v3/configure.ac
-index 3c799be82b1..3f63a8ec9ce 100644
---- a/libstdc++-v3/configure.ac
-+++ b/libstdc++-v3/configure.ac
-@@ -240,7 +240,7 @@ GLIBCXX_CHECK_SC_NPROCESSORS_ONLN
- GLIBCXX_CHECK_SC_NPROC_ONLN
- GLIBCXX_CHECK_PTHREADS_NUM_PROCESSORS_NP
- GLIBCXX_CHECK_SYSCTL_HW_NCPU
--GLIBCXX_CHECK_SDT_H
-+#GLIBCXX_CHECK_SDT_H
- 
- # Check for available headers.
- AC_CHECK_HEADERS([endian.h execinfo.h float.h fp.h ieeefp.h inttypes.h \

+ 113 - 0
recipes-devtools/gcc/gcc/0013-Ensure-target-gcc-headers-can-be-included.patch

@@ -0,0 +1,113 @@
+From 612801d426e75ff997cfabda380dbe52c2cbc532 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Fri, 20 Feb 2015 10:25:11 +0000
+Subject: [PATCH] Ensure target gcc headers can be included
+
+There are a few headers installed as part of the OpenEmbedded
+gcc-runtime target (omp.h, ssp/*.h). Being installed from a recipe
+built for the target architecture, these are within the target
+sysroot and not cross/nativesdk; thus they weren't able to be
+found by gcc with the existing search paths. Add support for
+picking up these headers under the sysroot supplied on the gcc
+command line in order to resolve this.
+
+Extend target gcc headers search to musl too
+
+Upstream-Status: Pending
+
+Signed-off-by: Paul Eggleton <paul.eggleton@linux.intel.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ gcc/Makefile.in           | 2 ++
+ gcc/config/linux.h        | 8 ++++++++
+ gcc/config/rs6000/sysv4.h | 8 ++++++++
+ gcc/cppdefault.cc         | 4 ++++
+ 4 files changed, 22 insertions(+)
+
+diff --git a/gcc/Makefile.in b/gcc/Makefile.in
+index a8277254696..07fa63b6640 100644
+--- a/gcc/Makefile.in
++++ b/gcc/Makefile.in
+@@ -632,6 +632,7 @@ libexecdir = @libexecdir@
+ 
+ # Directory in which the compiler finds libraries etc.
+ libsubdir = $(libdir)/gcc/$(real_target_noncanonical)/$(version)$(accel_dir_suffix)
++libsubdir_target = $(target_noncanonical)/$(version)
+ # Directory in which the compiler finds executables
+ libexecsubdir = $(libexecdir)/gcc/$(real_target_noncanonical)/$(version)$(accel_dir_suffix)
+ # Directory in which all plugin resources are installed
+@@ -3024,6 +3025,7 @@ CFLAGS-intl.o += -DLOCALEDIR=\"$(localedir)\"
+ 
+ PREPROCESSOR_DEFINES = \
+   -DGCC_INCLUDE_DIR=\"$(libsubdir)/include\" \
++  -DGCC_INCLUDE_SUBDIR_TARGET=\"$(libsubdir_target)/include\" \
+   -DFIXED_INCLUDE_DIR=\"$(libsubdir)/include-fixed\" \
+   -DGPLUSPLUS_INCLUDE_DIR=\"$(gcc_gxx_include_dir)\" \
+   -DGPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT=$(gcc_gxx_include_dir_add_sysroot) \
+diff --git a/gcc/config/linux.h b/gcc/config/linux.h
+index 4ce173384ef..8a3cd4f2d34 100644
+--- a/gcc/config/linux.h
++++ b/gcc/config/linux.h
+@@ -170,6 +170,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+ #define INCLUDE_DEFAULTS_MUSL_TOOL
+ #endif
+ 
++#ifdef GCC_INCLUDE_SUBDIR_TARGET
++#define INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET		\
++    { STANDARD_STARTFILE_PREFIX_2 GCC_INCLUDE_SUBDIR_TARGET, "GCC", 0, 0, 1, 0},
++#else
++#define INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET
++#endif
++
+ #ifdef NATIVE_SYSTEM_HEADER_DIR
+ #define INCLUDE_DEFAULTS_MUSL_NATIVE			\
+     { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 },	\
+@@ -196,6 +203,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+     INCLUDE_DEFAULTS_MUSL_PREFIX			\
+     INCLUDE_DEFAULTS_MUSL_CROSS				\
+     INCLUDE_DEFAULTS_MUSL_TOOL				\
++    INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET			\
+     INCLUDE_DEFAULTS_MUSL_NATIVE			\
+     { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 },		\
+     { 0, 0, 0, 0, 0, 0 }				\
+diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
+index a73954d9de5..e5dd6538358 100644
+--- a/gcc/config/rs6000/sysv4.h
++++ b/gcc/config/rs6000/sysv4.h
+@@ -994,6 +994,13 @@ ncrtn.o%s"
+ #define INCLUDE_DEFAULTS_MUSL_TOOL
+ #endif
+ 
++#ifdef GCC_INCLUDE_SUBDIR_TARGET
++#define INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET            \
++    { STANDARD_STARTFILE_PREFIX_2 GCC_INCLUDE_SUBDIR_TARGET, "GCC", 0, 0, 1, 0},
++#else
++#define INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET
++#endif
++
+ #ifdef NATIVE_SYSTEM_HEADER_DIR
+ #define INCLUDE_DEFAULTS_MUSL_NATIVE			\
+     { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 },	\
+@@ -1020,6 +1027,7 @@ ncrtn.o%s"
+     INCLUDE_DEFAULTS_MUSL_PREFIX			\
+     INCLUDE_DEFAULTS_MUSL_CROSS				\
+     INCLUDE_DEFAULTS_MUSL_TOOL				\
++    INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET			\
+     INCLUDE_DEFAULTS_MUSL_NATIVE			\
+     { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 },		\
+     { 0, 0, 0, 0, 0, 0 }				\
+diff --git a/gcc/cppdefault.cc b/gcc/cppdefault.cc
+index 7888300f277..52cf14e92f8 100644
+--- a/gcc/cppdefault.cc
++++ b/gcc/cppdefault.cc
+@@ -64,6 +64,10 @@ const struct default_include cpp_include_defaults[]
+     /* This is the dir for gcc's private headers.  */
+     { GCC_INCLUDE_DIR, "GCC", 0, 0, 0, 0 },
+ #endif
++#ifdef GCC_INCLUDE_SUBDIR_TARGET
++    /* This is the dir for gcc's private headers under the specified sysroot.  */
++    { STANDARD_STARTFILE_PREFIX_2 GCC_INCLUDE_SUBDIR_TARGET, "GCC", 0, 0, 1, 0 },
++#endif
+ #ifdef LOCAL_INCLUDE_DIR
+     /* /usr/local/include comes before the fixincluded header files.  */
+     { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 },

+ 0 - 24
recipes-devtools/gcc/gcc/0013-remove-b-gcc-options.patch

@@ -1,24 +0,0 @@
-From e4a5e8cfb91dab067e8f224046e085f8faaa4b93 Mon Sep 17 00:00:00 2001
-From: "max.ma" <max.ma@starfivetech.com>
-Date: Thu, 28 Oct 2021 02:10:21 -0700
-Subject: [PATCH 13/15] remove b gcc options
-
----
- gcc/common/config/riscv/riscv-common.c | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
-index 569cea68461..6a3bda64e68 100644
---- a/gcc/common/config/riscv/riscv-common.c
-+++ b/gcc/common/config/riscv/riscv-common.c
-@@ -908,7 +908,6 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
-   {"f", &gcc_options::x_target_flags, MASK_HARD_FLOAT},
-   {"d", &gcc_options::x_target_flags, MASK_DOUBLE_FLOAT},
-   {"c", &gcc_options::x_target_flags, MASK_RVC},
--  {"b", &gcc_options::x_target_flags, MASK_BITMANIP},
- 
-   {"zicsr",    &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
-   {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
--- 
-2.33.1
-

+ 1 - 1
recipes-devtools/gcc/gcc/0020-Don-t-search-host-directory-during-relink-if-inst_pr.patch → recipes-devtools/gcc/gcc/0014-Don-t-search-host-directory-during-relink-if-inst_pr.patch

@@ -1,4 +1,4 @@
-From cd09adb1e7f2a7e81a9f595a17c36f24911b90ac Mon Sep 17 00:00:00 2001
+From 9ae49e7b88c208ab79ec9c2fc4a2fa8a3f1e85bb Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Tue, 3 Mar 2015 08:21:19 +0000
 Subject: [PATCH] Don't search host directory during "relink" if $inst_prefix

+ 0 - 31
recipes-devtools/gcc/gcc/0014-fix-incorrect-subext-name.patch

@@ -1,31 +0,0 @@
-From 2b5f08aa28efa2ee545eb1f49d147b0d39b4b695 Mon Sep 17 00:00:00 2001
-From: "max.ma" <max.ma@starfivetech.com>
-Date: Thu, 28 Oct 2021 16:54:05 -0700
-Subject: [PATCH 14/15] fix incorrect subext name
-
----
- gcc/common/config/riscv/riscv-common.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
-index 6a3bda64e68..0927554d506 100644
---- a/gcc/common/config/riscv/riscv-common.c
-+++ b/gcc/common/config/riscv/riscv-common.c
-@@ -912,10 +912,10 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
-   {"zicsr",    &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
-   {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
- 
--  {"zba", &gcc_options::riscv_zb_subext, MASK_ZBA},
--  {"zbb", &gcc_options::riscv_zb_subext, MASK_ZBB},
--  {"zbs", &gcc_options::riscv_zb_subext, MASK_ZBS},
--  {"zbc", &gcc_options::riscv_zb_subext, MASK_ZBC},
-+  {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA},
-+  {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB},
-+  {"zbs", &gcc_options::x_riscv_zb_subext, MASK_ZBS},
-+  {"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC},
-   {NULL, NULL, 0}
- };
- 
--- 
-2.33.1
-

+ 0 - 127
recipes-devtools/gcc/gcc/0015-add-builtin-orc.b-clmul-clmulr-clmulh.patch

@@ -1,127 +0,0 @@
-From 7b4956f76d1f495d8c7b785c97682a36d852d184 Mon Sep 17 00:00:00 2001
-From: "yilun.xie" <yilun.xie@starfivetech.com>
-Date: Thu, 4 Nov 2021 17:26:53 +0800
-Subject: [PATCH 15/15] add builtin orc.b/clmul/clmulr/clmulh
-
----
- gcc/config/riscv/riscv-builtins.c | 10 ++++++++
- gcc/config/riscv/riscv-ftypes.def |  2 ++
- gcc/config/riscv/riscv.md         | 40 ++++++++++++++++++++++++++++++-
- 3 files changed, 51 insertions(+), 1 deletion(-)
-
-diff --git a/gcc/config/riscv/riscv-builtins.c b/gcc/config/riscv/riscv-builtins.c
-index 97b1480a15e..674e3f6dc04 100644
---- a/gcc/config/riscv/riscv-builtins.c
-+++ b/gcc/config/riscv/riscv-builtins.c
-@@ -40,6 +40,7 @@ along with GCC; see the file COPYING3.  If not see
- /* Macros to create an enumeration identifier for a function prototype.  */
- #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE
- #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
-+#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
- 
- /* Classifies the prototype of a built-in function.  */
- enum riscv_function_type {
-@@ -86,6 +87,8 @@ struct riscv_builtin_description {
- };
- 
- AVAIL (hard_float, TARGET_HARD_FLOAT)
-+AVAIL (zbb, TARGET_ZBB)
-+AVAIL (zbc, TARGET_ZBC)
- 
- /* Construct a riscv_builtin_description from the given arguments.
- 
-@@ -119,6 +122,7 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
- /* Argument types.  */
- #define RISCV_ATYPE_VOID void_type_node
- #define RISCV_ATYPE_USI unsigned_intSI_type_node
-+#define RISCV_ATYPE_SI intSI_type_node
- 
- /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
-    their associated RISCV_ATYPEs.  */
-@@ -126,8 +130,14 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
-   RISCV_ATYPE_##A
- #define RISCV_FTYPE_ATYPES1(A, B) \
-   RISCV_ATYPE_##A, RISCV_ATYPE_##B
-+#define RISCV_FTYPE_ATYPES2(A, B, C) \
-+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
- 
- static const struct riscv_builtin_description riscv_builtins[] = {
-+  DIRECT_BUILTIN (orc_b, RISCV_SI_FTYPE_SI, zbb),
-+  DIRECT_BUILTIN (clmul, RISCV_SI_FTYPE_SI_SI, zbc),
-+  DIRECT_BUILTIN (clmulh, RISCV_SI_FTYPE_SI_SI, zbc),
-+  DIRECT_BUILTIN (clmulr, RISCV_SI_FTYPE_SI_SI, zbc),
-   DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
-   DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float)
- };
-diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
-index b19b731bdf2..ab7348d1d7d 100644
---- a/gcc/config/riscv/riscv-ftypes.def
-+++ b/gcc/config/riscv/riscv-ftypes.def
-@@ -28,3 +28,5 @@ along with GCC; see the file COPYING3.  If not see
- 
- DEF_RISCV_FTYPE (0, (USI))
- DEF_RISCV_FTYPE (1, (VOID, USI))
-+DEF_RISCV_FTYPE (1, (SI, SI))
-+DEF_RISCV_FTYPE (2, (SI, SI, SI))
-\ No newline at end of file
-diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
-index c3687d57047..26003ac5df7 100644
---- a/gcc/config/riscv/riscv.md
-+++ b/gcc/config/riscv/riscv.md
-@@ -170,7 +170,7 @@
- (define_attr "type"
-   "unknown,branch,jump,call,load,fpload,store,fpstore,
-    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
--   fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost"
-+   fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip"
-   (cond [(eq_attr "got" "load") (const_string "load")
- 
- 	 ;; If a doubleword move uses these expensive instructions,
-@@ -2504,6 +2504,44 @@
-   [(set_attr "length" "0")]
- )
- 
-+(define_insn "riscv_orc_b"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+	(sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
-+  "TARGET_ZBB"
-+  "orc.b\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "riscv_rev8"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+	(sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
-+  "TARGET_ZBB"
-+  "rev8\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "riscv_clmul"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+	(sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
-+				   (match_operand:SI 2 "register_operand" "r"))))]
-+  "TARGET_ZBC"
-+  "clmul\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "riscv_clmulh"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+	(sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
-+				   (match_operand:SI 2 "register_operand" "r"))))]
-+  "TARGET_ZBC"
-+  "clmulh\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "riscv_clmulr"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+	(sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
-+				   (match_operand:SI 2 "register_operand" "r"))))]
-+  "TARGET_ZBC"
-+  "clmulr\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
- ;; This fixes a failure with gcc.c-torture/execute/pr64242.c at -O2 for a
- ;; 32-bit target when using -mtune=sifive-7-series.  The first sched pass
- ;; runs before register elimination, and we have a non-obvious dependency
--- 
-2.33.1
-

+ 4 - 4
recipes-devtools/gcc/gcc/0023-libcc1-fix-libcc1-s-install-path-and-rpath.patch → recipes-devtools/gcc/gcc/0015-libcc1-fix-libcc1-s-install-path-and-rpath.patch

@@ -1,4 +1,4 @@
-From 2cfc5ee38b3f5ec1d7965aae0991bcd48b5dc2e6 Mon Sep 17 00:00:00 2001
+From bf918db7117f41d3c04162095641165ca241707d Mon Sep 17 00:00:00 2001
 From: Robert Yang <liezhi.yang@windriver.com>
 Date: Sun, 5 Jul 2015 20:25:18 -0700
 Subject: [PATCH] libcc1: fix libcc1's install path and rpath
@@ -20,7 +20,7 @@ Signed-off-by: Robert Yang <liezhi.yang@windriver.com>
  2 files changed, 4 insertions(+), 4 deletions(-)
 
 diff --git a/libcc1/Makefile.am b/libcc1/Makefile.am
-index f148fdd7aa2..0b6eb8f2855 100644
+index 6e3a34ff7e2..3f3f6391aba 100644
 --- a/libcc1/Makefile.am
 +++ b/libcc1/Makefile.am
 @@ -40,8 +40,8 @@ libiberty = $(if $(wildcard $(libiberty_noasan)),$(Wc)$(libiberty_noasan), \
@@ -35,10 +35,10 @@ index f148fdd7aa2..0b6eb8f2855 100644
  if ENABLE_PLUGIN
  plugin_LTLIBRARIES = libcc1plugin.la libcp1plugin.la
 diff --git a/libcc1/Makefile.in b/libcc1/Makefile.in
-index 753d435c9cb..455627b0a3b 100644
+index f8f590d71e9..56462492045 100644
 --- a/libcc1/Makefile.in
 +++ b/libcc1/Makefile.in
-@@ -398,8 +398,8 @@ libiberty = $(if $(wildcard $(libiberty_noasan)),$(Wc)$(libiberty_noasan), \
+@@ -396,8 +396,8 @@ libiberty = $(if $(wildcard $(libiberty_noasan)),$(Wc)$(libiberty_noasan), \
  	    $(Wc)$(libiberty_normal)))
  
  libiberty_dep = $(patsubst $(Wc)%,%,$(libiberty))

+ 200 - 39
recipes-devtools/gcc/gcc/0024-handle-sysroot-support-for-nativesdk-gcc.patch → recipes-devtools/gcc/gcc/0016-handle-sysroot-support-for-nativesdk-gcc.patch

@@ -1,4 +1,4 @@
-From 35c084a051bcd6587ebc73e4acb045cb2bdf7e99 Mon Sep 17 00:00:00 2001
+From 4fbbd40d7db89cdbeaf93df1e1da692b1f80a5bc Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Mon, 7 Dec 2015 23:39:54 +0000
 Subject: [PATCH] handle sysroot support for nativesdk-gcc
@@ -23,6 +23,9 @@ b) Add other paths which need relocation into a .gccrelocprefix section
 Upstream-Status: Inappropriate
 RP 2015/7/28
 
+Extend the gccrelocprefix support to musl config too, this ensures
+that gcc will get right bits in SDK installations
+
 Signed-off-by: Khem Raj <raj.khem@gmail.com>
 
 Added PREFIXVAR and EXEC_PREFIXVAR to support runtime relocation.  Without
@@ -32,19 +35,21 @@ implementation.)
 
 Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
 ---
- gcc/c-family/c-opts.c |  4 +--
- gcc/cppdefault.c      | 63 ++++++++++++++++++++++++++-----------------
- gcc/cppdefault.h      | 13 ++++-----
- gcc/gcc.c             | 20 +++++++++-----
- gcc/incpath.c         | 12 ++++-----
- gcc/prefix.c          |  6 +++--
- 6 files changed, 70 insertions(+), 48 deletions(-)
+ gcc/c-family/c-opts.cc    |  4 +--
+ gcc/config/linux.h        | 24 +++++++--------
+ gcc/config/rs6000/sysv4.h | 24 +++++++--------
+ gcc/cppdefault.cc         | 63 ++++++++++++++++++++++++---------------
+ gcc/cppdefault.h          | 13 ++++----
+ gcc/gcc.cc                | 20 +++++++++----
+ gcc/incpath.cc            | 12 ++++----
+ gcc/prefix.cc             |  6 ++--
+ 8 files changed, 94 insertions(+), 72 deletions(-)
 
-diff --git a/gcc/c-family/c-opts.c b/gcc/c-family/c-opts.c
-index bd15b9cd902..2bd667e3f58 100644
---- a/gcc/c-family/c-opts.c
-+++ b/gcc/c-family/c-opts.c
-@@ -1436,8 +1436,8 @@ add_prefixed_path (const char *suffix, incpath_kind chain)
+diff --git a/gcc/c-family/c-opts.cc b/gcc/c-family/c-opts.cc
+index a341a061758..83b0bef4dbb 100644
+--- a/gcc/c-family/c-opts.cc
++++ b/gcc/c-family/c-opts.cc
+@@ -1458,8 +1458,8 @@ add_prefixed_path (const char *suffix, incpath_kind chain)
    size_t prefix_len, suffix_len;
  
    suffix_len = strlen (suffix);
@@ -55,10 +60,166 @@ index bd15b9cd902..2bd667e3f58 100644
  
    path = (char *) xmalloc (prefix_len + suffix_len + 1);
    memcpy (path, prefix, prefix_len);
-diff --git a/gcc/cppdefault.c b/gcc/cppdefault.c
-index d54d6ce0076..784a92a0c24 100644
---- a/gcc/cppdefault.c
-+++ b/gcc/cppdefault.c
+diff --git a/gcc/config/linux.h b/gcc/config/linux.h
+index 8a3cd4f2d34..58143dff731 100644
+--- a/gcc/config/linux.h
++++ b/gcc/config/linux.h
+@@ -134,53 +134,53 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+  * Unfortunately, this is mostly duplicated from cppdefault.cc */
+ #if DEFAULT_LIBC == LIBC_MUSL
+ #define INCLUDE_DEFAULTS_MUSL_GPP			\
+-    { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1,		\
++    { GPLUSPLUS_INCLUDE_DIRVAR, "G++", 1, 1,		\
+       GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 },		\
+-    { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1,		\
++    { GPLUSPLUS_TOOL_INCLUDE_DIRVAR, "G++", 1, 1,	\
+       GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 },		\
+-    { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1,	\
++    { GPLUSPLUS_BACKWARD_INCLUDE_DIRVAR, "G++", 1, 1,	\
+       GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 },
+ 
+ #ifdef LOCAL_INCLUDE_DIR
+ #define INCLUDE_DEFAULTS_MUSL_LOCAL			\
+-    { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 },		\
+-    { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 },
++    { LOCAL_INCLUDE_DIRVAR, 0, 0, 1, 1, 2 },		\
++    { LOCAL_INCLUDE_DIRVAR, 0, 0, 1, 1, 0 },
+ #else
+ #define INCLUDE_DEFAULTS_MUSL_LOCAL
+ #endif
+ 
+ #ifdef PREFIX_INCLUDE_DIR
+ #define INCLUDE_DEFAULTS_MUSL_PREFIX			\
+-    { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0},
++    { PREFIX_INCLUDE_DIRVAR, 0, 0, 1, 0, 0},
+ #else
+ #define INCLUDE_DEFAULTS_MUSL_PREFIX
+ #endif
+ 
+ #ifdef CROSS_INCLUDE_DIR
+ #define INCLUDE_DEFAULTS_MUSL_CROSS			\
+-    { CROSS_INCLUDE_DIR, "GCC", 0, 0, 0, 0},
++    { CROSS_INCLUDE_DIRVAR, "GCC", 0, 0, 0, 0},
+ #else
+ #define INCLUDE_DEFAULTS_MUSL_CROSS
+ #endif
+ 
+ #ifdef TOOL_INCLUDE_DIR
+ #define INCLUDE_DEFAULTS_MUSL_TOOL			\
+-    { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1, 0, 0},
++    { TOOL_INCLUDE_DIRVAR, "BINUTILS", 0, 1, 0, 0},
+ #else
+ #define INCLUDE_DEFAULTS_MUSL_TOOL
+ #endif
+ 
+ #ifdef GCC_INCLUDE_SUBDIR_TARGET
+ #define INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET		\
+-    { STANDARD_STARTFILE_PREFIX_2 GCC_INCLUDE_SUBDIR_TARGET, "GCC", 0, 0, 1, 0},
++    { STANDARD_STARTFILE_PREFIX_2VAR, "GCC", 0, 0, 1, 0},
+ #else
+ #define INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET
+ #endif
+ 
+ #ifdef NATIVE_SYSTEM_HEADER_DIR
+ #define INCLUDE_DEFAULTS_MUSL_NATIVE			\
+-    { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 },	\
+-    { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 0 },
++    { NATIVE_SYSTEM_HEADER_DIRVAR, 0, 0, 0, 1, 2 },	\
++    { NATIVE_SYSTEM_HEADER_DIRVAR, 0, 0, 0, 1, 0 },
+ #else
+ #define INCLUDE_DEFAULTS_MUSL_NATIVE
+ #endif
+@@ -205,7 +205,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+     INCLUDE_DEFAULTS_MUSL_TOOL				\
+     INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET			\
+     INCLUDE_DEFAULTS_MUSL_NATIVE			\
+-    { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 },		\
++    { GCC_INCLUDE_DIRVAR, "GCC", 0, 1, 0, 0 },		\
+     { 0, 0, 0, 0, 0, 0 }				\
+   }
+ #endif
+diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
+index e5dd6538358..b496849b792 100644
+--- a/gcc/config/rs6000/sysv4.h
++++ b/gcc/config/rs6000/sysv4.h
+@@ -958,53 +958,53 @@ ncrtn.o%s"
+ /* Include order changes for musl, same as in generic linux.h.  */
+ #if DEFAULT_LIBC == LIBC_MUSL
+ #define INCLUDE_DEFAULTS_MUSL_GPP			\
+-    { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1,		\
++    { GPLUSPLUS_INCLUDE_DIRVAR, "G++", 1, 1,		\
+       GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 },		\
+-    { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1,		\
++    { GPLUSPLUS_TOOL_INCLUDE_DIRVAR, "G++", 1, 1,	\
+       GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 },		\
+-    { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1,	\
++    { GPLUSPLUS_BACKWARD_INCLUDE_DIRVAR, "G++", 1, 1,	\
+       GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 },
+ 
+ #ifdef LOCAL_INCLUDE_DIR
+ #define INCLUDE_DEFAULTS_MUSL_LOCAL			\
+-    { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 },		\
+-    { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 },
++    { LOCAL_INCLUDE_DIRVAR, 0, 0, 1, 1, 2 },		\
++    { LOCAL_INCLUDE_DIRVAR, 0, 0, 1, 1, 0 },
+ #else
+ #define INCLUDE_DEFAULTS_MUSL_LOCAL
+ #endif
+ 
+ #ifdef PREFIX_INCLUDE_DIR
+ #define INCLUDE_DEFAULTS_MUSL_PREFIX			\
+-    { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0},
++    { PREFIX_INCLUDE_DIRVAR, 0, 0, 1, 0, 0},
+ #else
+ #define INCLUDE_DEFAULTS_MUSL_PREFIX
+ #endif
+ 
+ #ifdef CROSS_INCLUDE_DIR
+ #define INCLUDE_DEFAULTS_MUSL_CROSS			\
+-    { CROSS_INCLUDE_DIR, "GCC", 0, 0, 0, 0},
++    { CROSS_INCLUDE_DIRVAR, "GCC", 0, 0, 0, 0},
+ #else
+ #define INCLUDE_DEFAULTS_MUSL_CROSS
+ #endif
+ 
+ #ifdef TOOL_INCLUDE_DIR
+ #define INCLUDE_DEFAULTS_MUSL_TOOL			\
+-    { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1, 0, 0},
++    { TOOL_INCLUDE_DIRVAR, "BINUTILS", 0, 1, 0, 0},
+ #else
+ #define INCLUDE_DEFAULTS_MUSL_TOOL
+ #endif
+ 
+ #ifdef GCC_INCLUDE_SUBDIR_TARGET
+ #define INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET            \
+-    { STANDARD_STARTFILE_PREFIX_2 GCC_INCLUDE_SUBDIR_TARGET, "GCC", 0, 0, 1, 0},
++    { STANDARD_STARTFILE_PREFIX_2VAR, "GCC", 0, 0, 1, 0},
+ #else
+ #define INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET
+ #endif
+ 
+ #ifdef NATIVE_SYSTEM_HEADER_DIR
+ #define INCLUDE_DEFAULTS_MUSL_NATIVE			\
+-    { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 },	\
+-    { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 0 },
++    { NATIVE_SYSTEM_HEADER_DIRVAR, 0, 0, 0, 1, 2 },	\
++    { NATIVE_SYSTEM_HEADER_DIRVAR, 0, 0, 0, 1, 0 },
+ #else
+ #define INCLUDE_DEFAULTS_MUSL_NATIVE
+ #endif
+@@ -1029,7 +1029,7 @@ ncrtn.o%s"
+     INCLUDE_DEFAULTS_MUSL_TOOL				\
+     INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET			\
+     INCLUDE_DEFAULTS_MUSL_NATIVE			\
+-    { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 },		\
++    { GCC_INCLUDE_DIRVAR, "GCC", 0, 1, 0, 0 },		\
+     { 0, 0, 0, 0, 0, 0 }				\
+   }
+ #endif
+diff --git a/gcc/cppdefault.cc b/gcc/cppdefault.cc
+index 52cf14e92f8..d8977afc05e 100644
+--- a/gcc/cppdefault.cc
++++ b/gcc/cppdefault.cc
 @@ -35,6 +35,30 @@
  # undef CROSS_INCLUDE_DIR
  #endif
@@ -182,7 +343,7 @@ index d54d6ce0076..784a92a0c24 100644
  /* This value is set by cpp_relocated at runtime */
  const char *gcc_exec_prefix;
 diff --git a/gcc/cppdefault.h b/gcc/cppdefault.h
-index fd3c655db1c..20669ac427d 100644
+index fb97c0b5814..6267150facc 100644
 --- a/gcc/cppdefault.h
 +++ b/gcc/cppdefault.h
 @@ -33,7 +33,8 @@
@@ -193,7 +354,7 @@ index fd3c655db1c..20669ac427d 100644
 +  const char *fname;     /* The name of the directory.  */
 +
    const char *const component;	/* The component containing the directory
- 				   (see update_path in prefix.c) */
+ 				   (see update_path in prefix.cc) */
    const char cplusplus;		/* When this is non-zero, we should only
 @@ -55,17 +56,13 @@ struct default_include
  };
@@ -216,10 +377,10 @@ index fd3c655db1c..20669ac427d 100644
  /* The run-time execution prefix.  This is typically the lib/gcc
     subdirectory of the actual installation.  */
  extern const char *gcc_exec_prefix;
-diff --git a/gcc/gcc.c b/gcc/gcc.c
-index 8737bae5353..aa6fbe43965 100644
---- a/gcc/gcc.c
-+++ b/gcc/gcc.c
+diff --git a/gcc/gcc.cc b/gcc/gcc.cc
+index aa4cf92fb78..5569a39a14a 100644
+--- a/gcc/gcc.cc
++++ b/gcc/gcc.cc
 @@ -252,6 +252,8 @@ FILE *report_times_to_file = NULL;
  #endif
  static const char *target_system_root = DEFAULT_TARGET_SYSTEM_ROOT;
@@ -229,7 +390,7 @@ index 8737bae5353..aa6fbe43965 100644
  /* Nonzero means pass the updated target_system_root to the compiler.  */
  
  static int target_system_root_changed;
-@@ -568,6 +570,7 @@ or with constant text in a single argument.
+@@ -575,6 +577,7 @@ or with constant text in a single argument.
   %G     process LIBGCC_SPEC as a spec.
   %R     Output the concatenation of target_system_root and
          target_sysroot_suffix.
@@ -237,7 +398,7 @@ index 8737bae5353..aa6fbe43965 100644
   %S     process STARTFILE_SPEC as a spec.  A capital S is actually used here.
   %E     process ENDFILE_SPEC as a spec.  A capital E is actually used here.
   %C     process CPP_SPEC as a spec.
-@@ -1621,10 +1624,10 @@ static const char *gcc_libexec_prefix;
+@@ -1627,10 +1630,10 @@ static const char *gcc_libexec_prefix;
     gcc_exec_prefix is set because, in that case, we know where the
     compiler has been installed, and use paths relative to that
     location instead.  */
@@ -252,7 +413,7 @@ index 8737bae5353..aa6fbe43965 100644
  
  /* For native compilers, these are well-known paths containing
     components that may be provided by the system.  For cross
-@@ -1632,9 +1635,9 @@ static const char *const standard_startfile_prefix = STANDARD_STARTFILE_PREFIX;
+@@ -1638,9 +1641,9 @@ static const char *const standard_startfile_prefix = STANDARD_STARTFILE_PREFIX;
  static const char *md_exec_prefix = MD_EXEC_PREFIX;
  static const char *md_startfile_prefix = MD_STARTFILE_PREFIX;
  static const char *md_startfile_prefix_1 = MD_STARTFILE_PREFIX_1;
@@ -264,7 +425,7 @@ index 8737bae5353..aa6fbe43965 100644
    = STANDARD_STARTFILE_PREFIX_2;
  
  /* A relative path to be used in finding the location of tools
-@@ -6564,6 +6567,11 @@ do_spec_1 (const char *spec, int inswitch, const char *soft_matched_part)
+@@ -6676,6 +6679,11 @@ do_spec_1 (const char *spec, int inswitch, const char *soft_matched_part)
  	      }
  	    break;
  
@@ -276,11 +437,11 @@ index 8737bae5353..aa6fbe43965 100644
  	  case 'S':
  	    value = do_spec_1 (startfile_spec, 0, NULL);
  	    if (value != 0)
-diff --git a/gcc/incpath.c b/gcc/incpath.c
-index fbfc0ce03b8..a82e543428b 100644
---- a/gcc/incpath.c
-+++ b/gcc/incpath.c
-@@ -131,7 +131,7 @@ add_standard_paths (const char *sysroot, const char *iprefix,
+diff --git a/gcc/incpath.cc b/gcc/incpath.cc
+index c80f100f476..5ac03c08693 100644
+--- a/gcc/incpath.cc
++++ b/gcc/incpath.cc
+@@ -135,7 +135,7 @@ add_standard_paths (const char *sysroot, const char *iprefix,
    int relocated = cpp_relocated ();
    size_t len;
  
@@ -289,7 +450,7 @@ index fbfc0ce03b8..a82e543428b 100644
      {
        /* Look for directories that start with the standard prefix.
  	 "Translate" them, i.e. replace /usr/local/lib/gcc... with
-@@ -146,7 +146,7 @@ add_standard_paths (const char *sysroot, const char *iprefix,
+@@ -150,7 +150,7 @@ add_standard_paths (const char *sysroot, const char *iprefix,
  		 now.  */
  	      if (sysroot && p->add_sysroot)
  		continue;
@@ -298,7 +459,7 @@ index fbfc0ce03b8..a82e543428b 100644
  		{
  		  char *str = concat (iprefix, p->fname + len, NULL);
  		  if (p->multilib == 1 && imultilib)
-@@ -187,7 +187,7 @@ add_standard_paths (const char *sysroot, const char *iprefix,
+@@ -191,7 +191,7 @@ add_standard_paths (const char *sysroot, const char *iprefix,
  	      free (sysroot_no_trailing_dir_separator);
  	    }
  	  else if (!p->add_sysroot && relocated
@@ -307,7 +468,7 @@ index fbfc0ce03b8..a82e543428b 100644
  	    {
   	      static const char *relocated_prefix;
  	      char *ostr;
-@@ -204,12 +204,12 @@ add_standard_paths (const char *sysroot, const char *iprefix,
+@@ -208,12 +208,12 @@ add_standard_paths (const char *sysroot, const char *iprefix,
  		  dummy = concat (gcc_exec_prefix, "dummy", NULL);
  		  relocated_prefix
  		    = make_relative_prefix (dummy,
@@ -323,10 +484,10 @@ index fbfc0ce03b8..a82e543428b 100644
  			     NULL);
  	      str = update_path (ostr, p->component);
  	      free (ostr);
-diff --git a/gcc/prefix.c b/gcc/prefix.c
-index 747c09de638..f728638dc65 100644
---- a/gcc/prefix.c
-+++ b/gcc/prefix.c
+diff --git a/gcc/prefix.cc b/gcc/prefix.cc
+index 096ed5afa3d..2526f0ecc39 100644
+--- a/gcc/prefix.cc
++++ b/gcc/prefix.cc
 @@ -72,7 +72,9 @@ License along with GCC; see the file COPYING3.  If not see
  #include "prefix.h"
  #include "common/common-target.h"

+ 0 - 545
recipes-devtools/gcc/gcc/0016-merge-sifve-change-for-bitmanip.patch

@@ -1,545 +0,0 @@
-From e243539f72938317c85bb9859576c39b1baf011d Mon Sep 17 00:00:00 2001
-From: "yilun.xie" <yilun.xie@starfivetech.com>
-Date: Thu, 18 Nov 2021 14:25:18 +0800
-Subject: [PATCH 16/26] merge sifve change for bitmanip
-
----
- gcc/config/riscv/bitmanip.md | 446 ++++++++++++++---------------------
- 1 file changed, 173 insertions(+), 273 deletions(-)
-
-diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
-index ceb5c89dd47..d2e1d6c936b 100644
---- a/gcc/config/riscv/bitmanip.md
-+++ b/gcc/config/riscv/bitmanip.md
-@@ -1,5 +1,5 @@
- ;; Machine description for RISC-V Bit Manipulation operations.
--;; Copyright (C) 2019 Free Software Foundation, Inc.
-+;; Copyright (C) 2021 Free Software Foundation, Inc.
- 
- ;; This file is part of GCC.
- 
-@@ -19,7 +19,7 @@
- 
- (define_code_iterator bitmanip_bitwise [and ior])
- 
--(define_code_iterator any_minmax [smin smax umin umax])
-+(define_code_iterator bitmanip_minmax [smin umin smax umax])
- 
- (define_code_iterator clz_ctz_pcnt [clz ctz popcount])
- 
-@@ -31,6 +31,7 @@
- 				  (ctz "ctz")
- 				  (popcount "popcount")])
- 
-+
- (define_code_attr bitmanip_insn [(smin "min")
- 				 (smax "max")
- 				 (umin "minu")
-@@ -41,74 +42,206 @@
- 
- (define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")])
- 
-+;; ZBA extension.
-+
-+(define_insn "*zero_extendsidi2_bitmanip"
-+  [(set (match_operand:DI 0 "register_operand" "=r,r")
-+	(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
-+  "TARGET_64BIT && TARGET_ZBA"
-+  "@
-+   zext.w\t%0,%1
-+   lwu\t%0,%1"
-+  [(set_attr "type" "bitmanip,load")
-+   (set_attr "mode" "DI")])
-+
-+(define_insn "*shNadd"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+	(plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
-+			  (match_operand:QI 2 "immediate_operand" "I"))
-+		(match_operand:X 3 "register_operand" "r")))]
-+  "TARGET_ZBA
-+   && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)"
-+  "sh%2add\t%0,%1,%3"
-+  [(set_attr "type" "bitmanip")
-+   (set_attr "mode" "<X:MODE>")])
-+
-+(define_insn "*shNadduw"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(plus:DI
-+	  (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
-+			     (match_operand:QI 2 "immediate_operand" "I"))
-+		 (match_operand 3 "immediate_operand" ""))
-+	  (match_operand:DI 4 "register_operand" "r")))]
-+  "TARGET_64BIT && TARGET_ZBA
-+   && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
-+   && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
-+  "sh%2add.uw\t%0,%1,%4"
-+  [(set_attr "type" "bitmanip")
-+   (set_attr "mode" "DI")])
-+
-+(define_insn "*add.uw"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(plus:DI (zero_extend:DI
-+		   (match_operand:SI 1 "register_operand" "r"))
-+		 (match_operand:DI 2 "register_operand" "r")))]
-+  "TARGET_64BIT && TARGET_ZBA"
-+  "add.uw\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")
-+   (set_attr "mode" "DI")])
-+
-+(define_insn "*slliuw"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
-+			   (match_operand:QI 2 "immediate_operand" "I"))
-+		(match_operand 3 "immediate_operand" "")))]
-+  "TARGET_64BIT && TARGET_ZBA
-+   && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
-+  "slli.uw\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")
-+   (set_attr "mode" "DI")])
-+
-+;; ZBB extension.
-+
-+(define_insn "*<optab>_not<mode>"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+        (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
-+                            (match_operand:X 2 "register_operand" "r")))]
-+  "TARGET_ZBB"
-+  "<insn>n\t%0,%2,%1"
-+  [(set_attr "type" "bitmanip")
-+   (set_attr "mode" "<X:MODE>")])
-+
-+(define_insn "*xor_not<mode>"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+        (not:X (xor:X (match_operand:X 1 "register_operand" "r")
-+                      (match_operand:X 2 "register_operand" "r"))))]
-+  "TARGET_ZBB"
-+  "xnor\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")
-+   (set_attr "mode" "<X:MODE>")])
-+
- (define_insn "<bitmanip_optab>si2"
-   [(set (match_operand:SI 0 "register_operand" "=r")
--	(clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))]
-+        (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))]
-   "TARGET_ZBB"
-   { return TARGET_64BIT ? "<bitmanip_insn>w\t%0,%1" : "<bitmanip_insn>\t%0,%1"; }
--  [(set_attr "type" "bitmanip")])
-+  [(set_attr "type" "bitmanip")
-+   (set_attr "mode" "SI")])
- 
--;; TODO: In theory zero_extend should be OK to combine too, since the output
--;;       range is 0 ~ 32, zero_extend or sign_extend will get same result.
- (define_insn "*<bitmanip_optab>disi2"
-   [(set (match_operand:DI 0 "register_operand" "=r")
--	(sign_extend:DI
--	  (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))]
-+        (sign_extend:DI
-+          (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))]
-   "TARGET_64BIT && TARGET_ZBB"
-   "<bitmanip_insn>w\t%0,%1"
--  [(set_attr "type" "bitmanip")])
-+  [(set_attr "type" "bitmanip")
-+   (set_attr "mode" "SI")])
- 
- (define_insn "<bitmanip_optab>di2"
-   [(set (match_operand:DI 0 "register_operand" "=r")
--	(clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))]
-+        (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))]
-   "TARGET_64BIT && TARGET_ZBB"
-   "<bitmanip_insn>\t%0,%1"
--  [(set_attr "type" "bitmanip")])
-+  [(set_attr "type" "bitmanip")
-+   (set_attr "mode" "DI")])
- 
--(define_insn "*<optab>_not<mode>"
--  [(set (match_operand:X 0 "register_operand" "=r")
--	(bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
--			    (match_operand:X 2 "register_operand" "r")))]
-+(define_insn "*zero_extendhi<GPR:mode>2_bitmanip"
-+  [(set (match_operand:GPR 0 "register_operand" "=r,r")
-+        (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
-   "TARGET_ZBB"
--  "<insn>n\t%0,%2,%1"
--  [(set_attr "type" "bitmanip")])
-+  "@
-+   zext.h\t%0,%1
-+   lhu\t%0,%1"
-+  [(set_attr "type" "bitmanip,load")
-+   (set_attr "mode" "<GPR:MODE>")])
- 
--(define_insn "*xor_not<mode>"
--  [(set (match_operand:X 0 "register_operand" "=r")
--	(not:X (xor:X (match_operand:X 1 "register_operand" "r")
--		      (match_operand:X 2 "register_operand" "r"))))]
-+(define_insn "*extend<SHORT:mode><SUPERQI:mode>2_zbb"
-+  [(set (match_operand:SUPERQI   0 "register_operand"     "=r,r")
-+	(sign_extend:SUPERQI
-+	    (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
-   "TARGET_ZBB"
--  "xnor\t%0,%1,%2"
--  [(set_attr "type" "bitmanip")])
-- 
--;;; ??? pack
-+  "@
-+   sext.<SHORT:size>\t%0,%1
-+   l<SHORT:size>\t%0,%1"
-+  [(set_attr "type" "bitmanip,load")
-+   (set_attr "mode" "<SUPERQI:MODE>")])
- 
--(define_insn "*zero_extendhi<GPR:mode>2_bitmanip"
--  [(set (match_operand:GPR 0 "register_operand" "=r,r")
--	(zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
-+(define_insn "*zero_extendhi<GPR:mode>2_zbb"
-+  [(set (match_operand:GPR    0 "register_operand"     "=r,r")
-+	(zero_extend:GPR
-+	    (match_operand:HI 1 "nonimmediate_operand" " r,m")))]
-   "TARGET_ZBB"
-   "@
-    zext.h\t%0,%1
-    lhu\t%0,%1"
--  [(set_attr "type" "bitmanip,load")])
-+  [(set_attr "type" "bitmanip,load")
-+   (set_attr "mode" "HI")])
- 
--(define_insn "*zero_extendsidi2_bitmanip"
--  [(set (match_operand:DI 0 "register_operand" "=r,r")
--	(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
--  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBA)"
--  "@
--   zext.w\t%0,%1
--   lwu\t%0,%1"
--  [(set_attr "type" "bitmanip,load")])
-+(define_insn "rotrsi3"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+	(rotatert:SI (match_operand:SI 1 "register_operand" "r")
-+		     (match_operand:QI 2 "arith_operand" "rI")))]
-+  "TARGET_ZBB"
-+  { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; }
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "rotrdi3"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(rotatert:DI (match_operand:DI 1 "register_operand" "r")
-+		     (match_operand:QI 2 "arith_operand" "rI")))]
-+  "TARGET_64BIT && TARGET_ZBB"
-+  "ror%i2\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "rotrsi3_sext"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r")
-+				     (match_operand:QI 2 "register_operand" "r"))))]
-+  "TARGET_64BIT && TARGET_ZBB"
-+  "rorw\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "rotlsi3"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+	(rotate:SI (match_operand:SI 1 "register_operand" "r")
-+		   (match_operand:QI 2 "register_operand" "r")))]
-+  "TARGET_ZBB"
-+  { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; }
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "rotldi3"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(rotate:DI (match_operand:DI 1 "register_operand" "r")
-+		   (match_operand:QI 2 "register_operand" "r")))]
-+  "TARGET_64BIT && TARGET_ZBB"
-+  "rol\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "rotlsi3_sext"
-+  [(set (match_operand:DI 0 "register_operand" "=r")
-+	(sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
-+				   (match_operand:QI 2 "register_operand" "r"))))]
-+  "TARGET_64BIT && TARGET_ZBB"
-+  "rolw\t%0,%1,%2"
-+  [(set_attr "type" "bitmanip")])
-+
-+(define_insn "bswap<mode>2"
-+  [(set (match_operand:X 0 "register_operand" "=r")
-+        (bswap:X (match_operand:X 1 "register_operand" "r")))]
-+  "TARGET_64BIT && TARGET_ZBB"
-+  "rev8\t%0,%1"
-+  [(set_attr "type" "bitmanip")])
- 
- (define_insn "<bitmanip_optab><mode>3"
-   [(set (match_operand:X 0 "register_operand" "=r")
--	(any_minmax:X (match_operand:X 1 "register_operand" "r")
--		      (match_operand:X 2 "register_operand" "r")))]
-+        (bitmanip_minmax:X (match_operand:X 1 "register_operand" "r")
-+			   (match_operand:X 2 "register_operand" "r")))]
-   "TARGET_ZBB"
-   "<bitmanip_insn>\t%0,%1,%2"
-   [(set_attr "type" "bitmanip")])
- 
-+;; ZBS extension.
-+
- (define_insn "*bset<mode>"
-   [(set (match_operand:X 0 "register_operand" "=r")
- 	(ior:X (ashift:X (const_int 1)
-@@ -155,41 +288,6 @@
-   "bseti\t%0,%1,%S2"
-   [(set_attr "type" "bitmanip")])
- 
--(define_insn "*bsetw"
--  [(set (match_operand:DI 0 "register_operand" "=r")
--	(sign_extend:DI
--	 (subreg:SI
--	  (ior:DI (subreg:DI
--		   (ashift:SI (const_int 1)
--			      (match_operand:QI 2 "register_operand" "r")) 0)
--		  (match_operand:DI 1 "register_operand" "r")) 0)))]
--  "TARGET_64BIT && TARGET_ZBS"
--  "bsetw\t%0,%1,%2"
--  [(set_attr "type" "bitmanip")])
--
--(define_insn "*bsetw_mask"
--  [(set (match_operand:DI 0 "register_operand" "=r")
--	(sign_extend:DI
--	 (subreg:SI
--	  (ior:DI (subreg:DI
--		   (ashift:SI
--		    (const_int 1)
--		    (subreg:QI
--		     (and:DI (match_operand:DI 2 "register_operand" "r")
--			     (match_operand 3 "const31_operand" "i")) 0)) 0)
--		  (match_operand:DI 1 "register_operand" "r")) 0)))]
--  "TARGET_64BIT && TARGET_ZBS"
--  "bsetw\t%0,%1,%2"
--  [(set_attr "type" "bitmanip")])
--
--(define_insn "*bsetiw"
--  [(set (match_operand:DI 0 "register_operand" "=r")
--	(ior:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
--		(match_operand 2 "single_bit_mask_operand" "i")))]
--  "TARGET_64BIT && TARGET_ZBS"
--  "bsetiw\t%0,%1,%S2"
--  [(set_attr "type" "bitmanip")])
--
- (define_insn "*bclr<mode>"
-   [(set (match_operand:X 0 "register_operand" "=r")
- 	(and:X (rotate:X (const_int -2)
-@@ -207,27 +305,6 @@
-   "bclri\t%0,%1,%T2"
-   [(set_attr "type" "bitmanip")])
- 
--(define_insn "*bclrw"
--  [(set (match_operand:DI 0 "register_operand" "=r")
--	(sign_extend:DI
--	 (subreg:SI
--	  (and:DI
--	   (not:DI (subreg:DI
--		    (ashift:SI (const_int 1)
--			       (match_operand:QI 2 "register_operand" "r")) 0))
--	   (match_operand:DI 1 "register_operand" "r")) 0)))]
--  "TARGET_64BIT && TARGET_ZBS"
--  "bclrw\t%0,%1,%2"
--  [(set_attr "type" "bitmanip")])
--
--(define_insn "*bclriw"
--  [(set (match_operand:DI 0 "register_operand" "=r")
--	(and:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
--		(match_operand 2 "not_single_bit_mask_operand" "i")))]
--  "TARGET_64BIT && TARGET_ZBS"
--  "bclriw\t%0,%1,%T2"
--  [(set_attr "type" "bitmanip")])
--
- (define_insn "*binv<mode>"
-   [(set (match_operand:X 0 "register_operand" "=r")
- 	(xor:X (ashift:X (const_int 1)
-@@ -245,26 +322,6 @@
-   "binvi\t%0,%1,%S2"
-   [(set_attr "type" "bitmanip")])
- 
--(define_insn "*binvw"
--  [(set (match_operand:DI 0 "register_operand" "=r")
--	(sign_extend:DI
--	 (subreg:SI
--	  (xor:DI (subreg:DI
--		   (ashift:SI (const_int 1)
--			      (match_operand:QI 2 "register_operand" "r")) 0)
--		  (match_operand:DI 1 "register_operand" "r")) 0)))]
--  "TARGET_64BIT && TARGET_ZBS"
--  "binvw\t%0,%1,%2"
--  [(set_attr "type" "bitmanip")])
--
--(define_insn "*binviw"
--  [(set (match_operand:DI 0 "register_operand" "=r")
--	(xor:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
--		(match_operand 2 "single_bit_mask_operand" "i")))]
--  "TARGET_64BIT && TARGET_ZBS"
--  "binviw\t%0,%1,%S2"
--  [(set_attr "type" "bitmanip")])
--
- (define_insn "*bext<mode>"
-   [(set (match_operand:X 0 "register_operand" "=r")
- 	(zero_extract:X (match_operand:X 1 "register_operand" "r")
-@@ -282,161 +339,4 @@
- 			(match_operand 2 "immediate_operand" "i")))]
-   "TARGET_ZBS"
-   "bexti\t%0,%1,%2"
--  [(set_attr "type" "bitmanip")])
--
--(define_insn "*bextw"
--  [(set (match_operand:DI 0 "register_operand" "=r")
--	(and:DI
--	 (subreg:DI
--	  (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
--		       (match_operand:QI 2 "register_operand" "r")) 0)
--	 (const_int 1)))]
--  "TARGET_64BIT && TARGET_ZBS"
--  "bextw\t%0,%1,%2"
--  [(set_attr "type" "bitmanip")])
--
--;;; ??? s[lr]o*
--
--(define_insn "rotrsi3"
--  [(set (match_operand:SI 0 "register_operand" "=r")
--	(rotatert:SI (match_operand:SI 1 "register_operand" "r")
--		     (match_operand:QI 2 "arith_operand" "rI")))]
--  "TARGET_ZBB"
--  { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; }
--  [(set_attr "type" "bitmanip")])
--
--(define_insn "rotrdi3"
--  [(set (match_operand:DI 0 "register_operand" "=r")
--	(rotatert:DI (match_operand:DI 1 "register_operand" "r")
--		     (match_operand:QI 2 "arith_operand" "rI")))]
--  "TARGET_64BIT && TARGET_ZBB"
--  "ror%i2\t%0,%1,%2"
--  [(set_attr "type" "bitmanip")])
--
--(define_expand "riscv_rolw"
--  [(match_operand:SI 0 "register_operand" "=r")
--   (match_operand:SI 1 "register_operand" "r")
--   (match_operand:SI 2 "register_operand" "r")]
--  "TARGET_64BIT && TARGET_ZBB"
--{
--  emit_insn (gen_rotlsi3 (operands[0], operands[1], operands[2]));
--  DONE;
--})
--
--(define_insn "rotlsi3"
--  [(set (match_operand:SI 0 "register_operand" "=r")
--	(rotate:SI (match_operand:SI 1 "register_operand" "r")
--		   (match_operand:QI 2 "register_operand" "r")))]
--  "TARGET_ZBB"
--  { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; }
--  [(set_attr "type" "bitmanip")])
--
--(define_insn "rotldi3"
--  [(set (match_operand:DI 0 "register_operand" "=r")
--	(rotate:DI (match_operand:DI 1 "register_operand" "r")
--		   (match_operand:QI 2 "register_operand" "r")))]
--  "TARGET_64BIT && TARGET_ZBB"
--  "rol\t%0,%1,%2"
--  [(set_attr "type" "bitmanip")])
--
--(define_insn "rotlsi3_sext"
--  [(set (match_operand:DI 0 "register_operand" "=r")
--	(sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
--				   (match_operand:QI 2 "register_operand" "r"))))]
--  "TARGET_64BIT && TARGET_ZBB"
--  "rolw\t%0,%1,%2"
--  [(set_attr "type" "bitmanip")])
--
--;;; ??? grev
--
--(define_insn "bswapsi2"
--  [(set (match_operand:SI 0 "register_operand" "=r")
--        (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
--  "TARGET_ZBB"
--{
--  if (TARGET_64BIT)
--    return TARGET_ZBB ? "rev8\t%0,%1\n\tsrai\t%0,%0,32" : "rev8.w\t%0,%1";
--  else
--    return "rev8\t%0,%1";
--}
--  [(set_attr "type" "bitmanip")])
--
--(define_insn "bswapdi2"
--  [(set (match_operand:DI 0 "register_operand" "=r")
--	(bswap:DI (match_operand:DI 1 "register_operand" "r")))]
--  "TARGET_64BIT && TARGET_ZBB"
--  "rev8\t%0,%1"
--  [(set_attr "type" "bitmanip")])
--
--;;; ??? shfl/unshfl
--
--;;; ??? bext/bdep
--
--;;; ??? clmul
--
--;;; ??? crc
--
--;;; ??? bmat
--
--;; ??? Can we do this by using the % communtative constraint?
--
--;;; ??? cmov
--
--;;; ??? fs[lr]
--
--(define_insn "*shNadd"
--  [(set (match_operand:X 0 "register_operand" "=r")
--	(plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
--			  (match_operand:QI 2 "immediate_operand" "I"))
--		(match_operand:X 3 "register_operand" "r")))]
--  "TARGET_ZBA
--   && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)"
--  "sh%2add\t%0,%1,%3"
--  [(set_attr "type" "bitmanip")])
--
--(define_insn "*shNadduw"
--  [(set (match_operand:DI 0 "register_operand" "=r")
--	(plus:DI
--	 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
--			    (match_operand:QI 2 "immediate_operand" "I"))
--		 (match_operand 3 "immediate_operand" ""))
--	 (match_operand:DI 4 "register_operand" "r")))]
--  "TARGET_64BIT && TARGET_ZBA
--   && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
--   && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
--  "sh%2add.uw\t%0,%1,%4"
--  [(set_attr "type" "bitmanip")])
--
--(define_insn "*add.uw"
--  [(set (match_operand:DI 0 "register_operand" "=r")
--	(plus:DI (zero_extend:DI
--		  (match_operand:SI 1 "register_operand" "r"))
--		 (match_operand:DI 2 "register_operand" "r")))]
--  "TARGET_64BIT && TARGET_ZBA"
--  "add.uw\t%0,%1,%2"
--  [(set_attr "type" "bitmanip")])
--
--(define_insn "*slliuw"
--  [(set (match_operand:DI 0 "register_operand" "=r")
--	(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
--			   (match_operand:QI 2 "immediate_operand" "I"))
--		(match_operand 3 "immediate_operand" "")))]
--  "TARGET_64BIT && TARGET_ZBA
--   && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
--  "slli.uw\t%0,%1,%2"
--  [(set_attr "type" "bitmanip")])
--
--;; ??? bfxp
--
--;; sext
--
--(define_insn "*extend<SHORT:mode><SUPERQI:mode>2_bitmanip"
--  [(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
--	(sign_extend:SUPERQI
--	    (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
--  "TARGET_ZBB"
--  "@
--   sext.<SHORT:size>\t%0,%1
--   l<SHORT:size>\t%0,%1"
--  [(set_attr "type" "bitmanip")
--   (set_attr "length" "4")])
-+  [(set_attr "type" "bitmanip")])
-\ No newline at end of file
--- 
-2.33.1
-

+ 0 - 208
recipes-devtools/gcc/gcc/0017-Implement-instruction-patterns-for-ZBA-extension.patch

@@ -1,208 +0,0 @@
-From 3b7112d4b773768af0da81e7c9575fc9a0d90062 Mon Sep 17 00:00:00 2001
-From: "yilun.xie" <yilun.xie@starfivetech.com>
-Date: Thu, 18 Nov 2021 14:42:41 +0800
-Subject: [PATCH 17/26] Implement instruction patterns for ZBA extension
-
----
- gcc/config/riscv/riscv.md                     | 12 +++++--
- gcc/testsuite/gcc.target/riscv/zba-adduw.c    | 12 +++++++
- .../gcc.target/riscv/zba-shNadd-01.c          | 19 ++++++++++++
- .../gcc.target/riscv/zba-shNadd-02.c          | 19 ++++++++++++
- .../gcc.target/riscv/zba-shNadd-03.c          | 31 +++++++++++++++++++
- gcc/testsuite/gcc.target/riscv/zba-slliuw.c   | 11 +++++++
- gcc/testsuite/gcc.target/riscv/zba-zextw.c    | 10 ++++++
- 7 files changed, 111 insertions(+), 3 deletions(-)
- create mode 100644 gcc/testsuite/gcc.target/riscv/zba-adduw.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zba-slliuw.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zba-zextw.c
-
-diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
-index 26003ac5df7..34702af3aff 100644
---- a/gcc/config/riscv/riscv.md
-+++ b/gcc/config/riscv/riscv.md
-@@ -1057,11 +1057,16 @@
- 
- ;; Extension insns.
- 
--(define_insn_and_split "zero_extendsidi2"
-+(define_expand "zero_extendsidi2"
-+  [(set (match_operand:DI 0 "register_operand")
-+	(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
-+  "TARGET_64BIT")
-+
-+(define_insn_and_split "*zero_extendsidi2_internal"
-   [(set (match_operand:DI     0 "register_operand"     "=r,r")
- 	(zero_extend:DI
- 	    (match_operand:SI 1 "nonimmediate_operand" " r,m")))]
--  "TARGET_64BIT"
-+  "TARGET_64BIT && !(TARGET_ZBA || TARGET_ZBB)"
-   "@
-    #
-    lwu\t%0,%1"
-@@ -1833,7 +1838,7 @@
- 			   (match_operand:QI 2 "immediate_operand" "I"))
- 		(match_operand 3 "immediate_operand" "")))
-    (clobber (match_scratch:DI 4 "=&r"))]
--  "TARGET_64BIT
-+  "TARGET_64BIT && !TARGET_ZBA
-    && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)"
-   "#"
-   "&& reload_completed"
-@@ -2642,6 +2647,7 @@
-   "<load>\t%3, %1\;<load>\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0"
-   [(set_attr "length" "12")])
- 
-+(include "bitmanip.md")
- (include "sync.md")
- (include "peephole.md")
- (include "pic.md")
-diff --git a/gcc/testsuite/gcc.target/riscv/zba-adduw.c b/gcc/testsuite/gcc.target/riscv/zba-adduw.c
-new file mode 100644
-index 00000000000..480d62c884d
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zba-adduw.c
-@@ -0,0 +1,12 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
-+
-+int foo(int n, unsigned char *arr, unsigned y){
-+  int s = 0;
-+  unsigned x = 0;
-+  for (;x<n;x++)
-+    s += arr[x+y];
-+  return s;
-+}
-+
-+/* { dg-final { scan-assembler "add.uw" } } */
-\ No newline at end of file
-diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
-new file mode 100644
-index 00000000000..9893fb6c451
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c
-@@ -0,0 +1,19 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
-+
-+long test_1(long a, long b)
-+{
-+  return a + (b << 1);
-+}
-+long test_2(long a, long b)
-+{
-+  return a + (b << 2);
-+}
-+long test_3(long a, long b)
-+{
-+  return a + (b << 3);
-+}
-+
-+/* { dg-final { scan-assembler-times "sh1add" 1 } } */
-+/* { dg-final { scan-assembler-times "sh2add" 1 } } */
-+/* { dg-final { scan-assembler-times "sh3add" 1 } } */
-\ No newline at end of file
-diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
-new file mode 100644
-index 00000000000..f025849dc27
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c
-@@ -0,0 +1,19 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv32gc_zba -mabi=ilp32 -O2" } */
-+
-+long test_1(long a, long b)
-+{
-+  return a + (b << 1);
-+}
-+long test_2(long a, long b)
-+{
-+  return a + (b << 2);
-+}
-+long test_3(long a, long b)
-+{
-+  return a + (b << 3);
-+}
-+
-+/* { dg-final { scan-assembler-times "sh1add" 1 } } */
-+/* { dg-final { scan-assembler-times "sh2add" 1 } } */
-+/* { dg-final { scan-assembler-times "sh3add" 1 } } */
-\ No newline at end of file
-diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
-new file mode 100644
-index 00000000000..ef75e7fc486
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c
-@@ -0,0 +1,31 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
-+
-+/* RV64 only.  */
-+int foos(short *x, int n){
-+  return x[n];
-+}
-+int fooi(int *x, int n){
-+  return x[n];
-+}
-+int fooll(long long *x, int n){
-+  return x[n];
-+}
-+
-+/* RV64 only.  */
-+int ufoos(short *x, unsigned int n){
-+  return x[n];
-+}
-+int ufooi(int *x, unsigned int n){
-+  return x[n];
-+}
-+int ufooll(long long *x, unsigned int n){
-+  return x[n];
-+}
-+
-+/* { dg-final { scan-assembler-times "sh1add\t" 1 } } */
-+/* { dg-final { scan-assembler-times "sh2add\t" 1 } } */
-+/* { dg-final { scan-assembler-times "sh3add\t" 1 } } */
-+/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */
-+/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */
-+/* { dg-final { scan-assembler-times "sh3add.uw" 1 } } */
-\ No newline at end of file
-diff --git a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
-new file mode 100644
-index 00000000000..55ebc1c81ce
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
-@@ -0,0 +1,11 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
-+
-+long
-+foo (long i)
-+{
-+  return (long)(unsigned int)i << 10;
-+}
-+/* XXX: This pattern need combine improvement or intermediate instruction
-+ *      from zbs.   */
-+/* { dg-final { scan-assembler-not "slli.uw" } } */
-\ No newline at end of file
-diff --git a/gcc/testsuite/gcc.target/riscv/zba-zextw.c b/gcc/testsuite/gcc.target/riscv/zba-zextw.c
-new file mode 100644
-index 00000000000..e8cccd0e374
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zba-zextw.c
-@@ -0,0 +1,10 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
-+
-+long
-+foo (long i)
-+{
-+  return (long)(unsigned int)i;
-+}
-+/* XXX: This pattern require combine improvement.   */
-+/* { dg-final { scan-assembler-not "slli.uw" } } */
-\ No newline at end of file
--- 
-2.33.1
-

+ 8 - 8
recipes-devtools/gcc/gcc/0025-Search-target-sysroot-gcc-version-specific-dirs-with.patch → recipes-devtools/gcc/gcc/0017-Search-target-sysroot-gcc-version-specific-dirs-with.patch

@@ -1,4 +1,4 @@
-From c55e24459370ad96577496ecd87475e3a9de7dad Mon Sep 17 00:00:00 2001
+From 33a1f07a4417247dc24819d4e583ca09f56d5a7b Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Mon, 7 Dec 2015 23:41:45 +0000
 Subject: [PATCH] Search target sysroot gcc version specific dirs with
@@ -47,14 +47,14 @@ RP 2015/7/31
 
 Signed-off-by: Khem Raj <raj.khem@gmail.com>
 ---
- gcc/gcc.c | 29 ++++++++++++++++++++++++++++-
+ gcc/gcc.cc | 29 ++++++++++++++++++++++++++++-
  1 file changed, 28 insertions(+), 1 deletion(-)
 
-diff --git a/gcc/gcc.c b/gcc/gcc.c
-index aa6fbe43965..f8a71a13826 100644
---- a/gcc/gcc.c
-+++ b/gcc/gcc.c
-@@ -2811,7 +2811,7 @@ for_each_path (const struct path_prefix *paths,
+diff --git a/gcc/gcc.cc b/gcc/gcc.cc
+index 5569a39a14a..4598f6cd7c9 100644
+--- a/gcc/gcc.cc
++++ b/gcc/gcc.cc
+@@ -2817,7 +2817,7 @@ for_each_path (const struct path_prefix *paths,
        if (path == NULL)
  	{
  	  len = paths->max_len + extra_space + 1;
@@ -63,7 +63,7 @@ index aa6fbe43965..f8a71a13826 100644
  	  path = XNEWVEC (char, len);
  	}
  
-@@ -2823,6 +2823,33 @@ for_each_path (const struct path_prefix *paths,
+@@ -2829,6 +2829,33 @@ for_each_path (const struct path_prefix *paths,
  	  /* Look first in MACHINE/VERSION subdirectory.  */
  	  if (!skip_multi_dir)
  	    {

+ 8 - 8
recipes-devtools/gcc/gcc/0028-Add-ssp_nonshared-to-link-commandline-for-musl-targe.patch → recipes-devtools/gcc/gcc/0018-Add-ssp_nonshared-to-link-commandline-for-musl-targe.patch

@@ -1,4 +1,4 @@
-From 745a2ac7825c73102b888226c54397d21512f86b Mon Sep 17 00:00:00 2001
+From d7dc2861840e88a4592817a398a054a886c3f3ee Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Tue, 27 Jun 2017 18:10:54 -0700
 Subject: [PATCH] Add ssp_nonshared to link commandline for musl targets
@@ -23,11 +23,11 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  3 files changed, 27 insertions(+)
 
 diff --git a/gcc/config/linux.h b/gcc/config/linux.h
-index 87efc5f69fe..3c7b7c538b9 100644
+index 58143dff731..d2409ccac26 100644
 --- a/gcc/config/linux.h
 +++ b/gcc/config/linux.h
-@@ -195,6 +195,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-     { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 },		\
+@@ -208,6 +208,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+     { GCC_INCLUDE_DIRVAR, "GCC", 0, 1, 0, 0 },		\
      { 0, 0, 0, 0, 0, 0 }				\
    }
 +#ifdef TARGET_LIBC_PROVIDES_SSP
@@ -41,10 +41,10 @@ index 87efc5f69fe..3c7b7c538b9 100644
  
  #if (DEFAULT_LIBC == LIBC_UCLIBC) && defined (SINGLE_LIBC) /* uClinux */
 diff --git a/gcc/config/rs6000/linux.h b/gcc/config/rs6000/linux.h
-index 47c9d9ac0b6..d065f88b377 100644
+index 8c9039ac1e5..259cd485973 100644
 --- a/gcc/config/rs6000/linux.h
 +++ b/gcc/config/rs6000/linux.h
-@@ -94,6 +94,16 @@
+@@ -99,6 +99,16 @@
  					 " -m elf32ppclinux")
  #endif
  
@@ -62,10 +62,10 @@ index 47c9d9ac0b6..d065f88b377 100644
  #define LINK_OS_LINUX_SPEC LINK_OS_LINUX_EMUL " %{!shared: %{!static: \
    %{!static-pie: \
 diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h
-index a11e01faa3d..ce464f3626b 100644
+index 364c1a5b155..e33d9ae98e0 100644
 --- a/gcc/config/rs6000/linux64.h
 +++ b/gcc/config/rs6000/linux64.h
-@@ -369,6 +369,16 @@ extern int dot_symbols;
+@@ -372,6 +372,16 @@ extern int dot_symbols;
  					   " -m elf64ppc")
  #endif
  

+ 0 - 119
recipes-devtools/gcc/gcc/0018-Cost-model-for-zba-extension.patch

@@ -1,119 +0,0 @@
-From b58a42aac28becb118a8482d41c4188e00ad0c3a Mon Sep 17 00:00:00 2001
-From: "yilun.xie" <yilun.xie@starfivetech.com>
-Date: Thu, 18 Nov 2021 14:55:04 +0800
-Subject: [PATCH 18/26] Cost model for zba extension
-
----
- gcc/config/riscv/riscv.c | 82 ++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 82 insertions(+)
-
-diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
-index 17cdf705c32..7d5e22d9fe2 100644
---- a/gcc/config/riscv/riscv.c
-+++ b/gcc/config/riscv/riscv.c
-@@ -1680,6 +1680,10 @@ riscv_extend_cost (rtx op, bool unsigned_p)
-     /* We can use ANDI.  */
-     return COSTS_N_INSNS (1);
- 
-+  /* ZBA provide zext.w.  */
-+  if (TARGET_ZBA && TARGET_64BIT && unsigned_p && GET_MODE (op) == SImode)
-+    return COSTS_N_INSNS (1);
-+
-   if (!unsigned_p && GET_MODE (op) == SImode)
-     /* We can use SEXT.W.  */
-     return COSTS_N_INSNS (1);
-@@ -1753,6 +1757,22 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
-       return false;
- 
-     case AND:
-+      /* slli.uw pattern for zba.  */
-+      if (TARGET_ZBA && TARGET_64BIT && mode == DImode
-+	  && GET_CODE (XEXP (x, 0)) == ASHIFT)
-+	{
-+	  rtx and_rhs = XEXP (x, 1);
-+	  rtx ashift_lhs = XEXP (XEXP (x, 0), 0);
-+	  rtx ashift_rhs = XEXP (XEXP (x, 0), 1);
-+	  if (REG_P (ashift_lhs)
-+	      && CONST_INT_P (ashift_rhs)
-+	      && CONST_INT_P (and_rhs)
-+	      && ((INTVAL (and_rhs) >> INTVAL (ashift_rhs)) == 0xffffffff))
-+	    *total = COSTS_N_INSNS (1);
-+	    return true;
-+	}
-+      gcc_fallthrough ();
-+
-     case IOR:
-     case XOR:
-       /* Double-word operations use two single-word operations.  */
-@@ -1844,6 +1864,68 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
- 
-     case MINUS:
-     case PLUS:
-+      /* add.uw pattern for zba.  */
-+      if (TARGET_ZBA
-+	  && (TARGET_64BIT && (mode == DImode))
-+	  && GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
-+	  && REG_P (XEXP (XEXP (x, 0), 0))
-+	  && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
-+	{
-+	  *total = COSTS_N_INSNS (1);
-+	  return true;
-+	}
-+      /* shNadd pattern for zba.  */
-+      if (TARGET_ZBA
-+	  && ((!TARGET_64BIT && (mode == SImode)) ||
-+	      (TARGET_64BIT && (mode == DImode)))
-+	  && (GET_CODE (XEXP (x, 0)) == ASHIFT)
-+	  && REG_P (XEXP (XEXP (x, 0), 0))
-+	  && CONST_INT_P (XEXP (XEXP (x, 0), 0))
-+	  && IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 0)), 1, 3))
-+	{
-+	  *total = COSTS_N_INSNS (1);
-+	  return true;
-+	}
-+      /* shNadd.uw pattern for zba.
-+	 [(set (match_operand:DI 0 "register_operand" "=r")
-+	       (plus:DI
-+		 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
-+				    (match_operand:QI 2 "immediate_operand" "I"))
-+			 (match_operand 3 "immediate_operand" ""))
-+		 (match_operand:DI 4 "register_operand" "r")))]
-+	 "TARGET_64BIT && TARGET_ZBA
-+	  && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
-+	  && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
-+      */
-+      if (TARGET_ZBA
-+	  && (TARGET_64BIT && (mode == DImode))
-+	  && (GET_CODE (XEXP (x, 0)) == AND)
-+	  && (REG_P (XEXP (x, 1))))
-+	{
-+	  do {
-+	    rtx and_lhs = XEXP (XEXP (x, 0), 0);
-+	    rtx and_rhs = XEXP (XEXP (x, 0), 1);
-+	    if (GET_CODE (and_lhs) != ASHIFT)
-+	      break;
-+	    if (!CONST_INT_P (and_rhs))
-+	      break;
-+
-+	    rtx ashift_lhs = XEXP (and_lhs, 0);
-+	    rtx ashift_rhs = XEXP (and_lhs, 1);
-+
-+	    if (!CONST_INT_P (ashift_rhs)
-+		|| !IN_RANGE (INTVAL (ashift_rhs), 1, 3))
-+	      break;
-+
-+	    if (CONST_INT_P (and_rhs)
-+		&& ((INTVAL (and_rhs) >> INTVAL (ashift_rhs)) == 0xffffffff))
-+	      {
-+		*total = COSTS_N_INSNS (1);
-+		return true;
-+	      }
-+	  } while (false);
-+	}
-+
-       if (float_mode_p)
- 	*total = tune_param->fp_add[mode == DFmode];
-       else
--- 
-2.33.1
-

+ 0 - 57
recipes-devtools/gcc/gcc/0019-Ensure-target-gcc-headers-can-be-included.patch

@@ -1,57 +0,0 @@
-From 9b4eb0e18a953d79d20c78d3ba741af6d71ab9ca Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Fri, 20 Feb 2015 10:25:11 +0000
-Subject: [PATCH] Ensure target gcc headers can be included
-
-There are a few headers installed as part of the OpenEmbedded
-gcc-runtime target (omp.h, ssp/*.h). Being installed from a recipe
-built for the target architecture, these are within the target
-sysroot and not cross/nativesdk; thus they weren't able to be
-found by gcc with the existing search paths. Add support for
-picking up these headers under the sysroot supplied on the gcc
-command line in order to resolve this.
-
-Upstream-Status: Pending
-
-Signed-off-by: Paul Eggleton <paul.eggleton@linux.intel.com>
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
----
- gcc/Makefile.in  | 2 ++
- gcc/cppdefault.c | 4 ++++
- 2 files changed, 6 insertions(+)
-
-diff --git a/gcc/Makefile.in b/gcc/Makefile.in
-index 59c45c81393..9b17d120aa1 100644
---- a/gcc/Makefile.in
-+++ b/gcc/Makefile.in
-@@ -630,6 +630,7 @@ libexecdir = @libexecdir@
- 
- # Directory in which the compiler finds libraries etc.
- libsubdir = $(libdir)/gcc/$(real_target_noncanonical)/$(version)$(accel_dir_suffix)
-+libsubdir_target = $(target_noncanonical)/$(version)
- # Directory in which the compiler finds executables
- libexecsubdir = $(libexecdir)/gcc/$(real_target_noncanonical)/$(version)$(accel_dir_suffix)
- # Directory in which all plugin resources are installed
-@@ -3016,6 +3017,7 @@ CFLAGS-intl.o += -DLOCALEDIR=\"$(localedir)\"
- 
- PREPROCESSOR_DEFINES = \
-   -DGCC_INCLUDE_DIR=\"$(libsubdir)/include\" \
-+  -DGCC_INCLUDE_SUBDIR_TARGET=\"$(libsubdir_target)/include\" \
-   -DFIXED_INCLUDE_DIR=\"$(libsubdir)/include-fixed\" \
-   -DGPLUSPLUS_INCLUDE_DIR=\"$(gcc_gxx_include_dir)\" \
-   -DGPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT=$(gcc_gxx_include_dir_add_sysroot) \
-diff --git a/gcc/cppdefault.c b/gcc/cppdefault.c
-index c503d14fc3f..d54d6ce0076 100644
---- a/gcc/cppdefault.c
-+++ b/gcc/cppdefault.c
-@@ -64,6 +64,10 @@ const struct default_include cpp_include_defaults[]
-     /* This is the dir for gcc's private headers.  */
-     { GCC_INCLUDE_DIR, "GCC", 0, 0, 0, 0 },
- #endif
-+#ifdef GCC_INCLUDE_SUBDIR_TARGET
-+    /* This is the dir for gcc's private headers under the specified sysroot.  */
-+    { STANDARD_STARTFILE_PREFIX_2 GCC_INCLUDE_SUBDIR_TARGET, "GCC", 0, 0, 1, 0 },
-+#endif
- #ifdef LOCAL_INCLUDE_DIR
-     /* /usr/local/include comes before the fixincluded header files.  */
-     { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 },

+ 0 - 274
recipes-devtools/gcc/gcc/0019-Implement-instruction-patterns-for-ZBB-extension.patch

@@ -1,274 +0,0 @@
-From adb47e7bb51c1725f36b9b92ba5b0bd2f7a1d74d Mon Sep 17 00:00:00 2001
-From: "yilun.xie" <yilun.xie@starfivetech.com>
-Date: Thu, 18 Nov 2021 15:16:54 +0800
-Subject: [PATCH 19/26] Implement instruction patterns for ZBB extension
-
----
- gcc/config/riscv/riscv.md                     | 21 ++++++++++---
- .../gcc.target/riscv/zbb-andn-orn-xnor-01.c   | 21 +++++++++++++
- .../gcc.target/riscv/zbb-andn-orn-xnor-02.c   | 21 +++++++++++++
- gcc/testsuite/gcc.target/riscv/zbb-min-max.c  | 31 +++++++++++++++++++
- .../gcc.target/riscv/zbb-rol-ror-01.c         | 16 ++++++++++
- .../gcc.target/riscv/zbb-rol-ror-02.c         | 16 ++++++++++
- .../gcc.target/riscv/zbb-rol-ror-03.c         | 17 ++++++++++
- gcc/testsuite/gcc.target/riscv/zbbw.c         | 25 +++++++++++++++
- 8 files changed, 163 insertions(+), 5 deletions(-)
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-min-max.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbbw.c
-
-diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
-index 34702af3aff..143a83eec83 100644
---- a/gcc/config/riscv/riscv.md
-+++ b/gcc/config/riscv/riscv.md
-@@ -170,7 +170,7 @@
- (define_attr "type"
-   "unknown,branch,jump,call,load,fpload,store,fpstore,
-    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
--   fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip"
-+   fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate"
-   (cond [(eq_attr "got" "load") (const_string "load")
- 
- 	 ;; If a doubleword move uses these expensive instructions,
-@@ -1081,11 +1081,17 @@
-   [(set_attr "move_type" "shift_shift,load")
-    (set_attr "mode" "DI")])
- 
--(define_insn_and_split "zero_extendhi<GPR:mode>2"
-+(define_expand "zero_extendhi<GPR:mode>2"
-+  [(set (match_operand:GPR    0 "register_operand")
-+	(zero_extend:GPR
-+	    (match_operand:HI 1 "nonimmediate_operand")))]
-+  "")
-+
-+(define_insn_and_split "*zero_extendhi<GPR:mode>2"
-   [(set (match_operand:GPR    0 "register_operand"     "=r,r")
- 	(zero_extend:GPR
- 	    (match_operand:HI 1 "nonimmediate_operand" " r,m")))]
--  ""
-+  "!TARGET_ZBB"
-   "@
-    #
-    lhu\t%0,%1"
-@@ -1132,11 +1138,16 @@
-   [(set_attr "move_type" "move,load")
-    (set_attr "mode" "DI")])
- 
--(define_insn_and_split "extend<SHORT:mode><SUPERQI:mode>2"
-+(define_expand "extend<SHORT:mode><SUPERQI:mode>2"
-+  [(set (match_operand:SUPERQI 0 "register_operand")
-+	(sign_extend:SUPERQI (match_operand:SHORT 1 "nonimmediate_operand")))]
-+  "")
-+
-+(define_insn_and_split "*extend<SHORT:mode><SUPERQI:mode>2"
-   [(set (match_operand:SUPERQI   0 "register_operand"     "=r,r")
- 	(sign_extend:SUPERQI
- 	    (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
--  ""
-+  "!TARGET_ZBB"
-   "@
-    #
-    l<SHORT:size>\t%0,%1"
-diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
-new file mode 100644
-index 00000000000..0037dea5647
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c
-@@ -0,0 +1,21 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
-+
-+unsigned long long foo1(unsigned long long rs1, unsigned long long rs2)
-+{
-+return rs1 & ~rs2;
-+}
-+
-+unsigned long long foo2(unsigned long long rs1, unsigned long long rs2)
-+{
-+return rs1 | ~rs2;
-+}
-+
-+unsigned long long foo3(unsigned long long rs1, unsigned long long rs2)
-+{
-+return rs1 ^ ~rs2;
-+}
-+
-+/* { dg-final { scan-assembler-times "andn" 2 } } */
-+/* { dg-final { scan-assembler-times "orn" 2 } } */
-+/* { dg-final { scan-assembler-times "xnor" 2 } } */
-\ No newline at end of file
-diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
-new file mode 100644
-index 00000000000..b0c1e40c554
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c
-@@ -0,0 +1,21 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */
-+
-+unsigned int foo1(unsigned int rs1, unsigned int rs2)
-+{
-+return rs1 & ~rs2;
-+}
-+
-+unsigned int foo2(unsigned  int rs1, unsigned  int rs2)
-+{
-+return rs1 | ~rs2;
-+}
-+
-+unsigned int foo3(unsigned int rs1, unsigned int rs2)
-+{
-+return rs1 ^ ~rs2;
-+}
-+
-+/* { dg-final { scan-assembler-times "andn" 2 } } */
-+/* { dg-final { scan-assembler-times "orn" 2 } } */
-+/* { dg-final { scan-assembler-times "xnor" 2 } } */
-\ No newline at end of file
-diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max.c
-new file mode 100644
-index 00000000000..dc72bb4ad71
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max.c
-@@ -0,0 +1,31 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
-+
-+long
-+foo1 (long i, long j)
-+{
-+  return i < j ? i : j;
-+}
-+
-+long
-+foo2 (long i, long j)
-+{
-+  return i > j ? i : j;
-+}
-+
-+unsigned long
-+foo3 (unsigned long i, unsigned long j)
-+{
-+  return i < j ? i : j;
-+}
-+
-+unsigned long
-+foo4 (unsigned long i, unsigned long j)
-+{
-+  return i > j ? i : j;
-+}
-+
-+/* { dg-final { scan-assembler-times "min" 3 } } */
-+/* { dg-final { scan-assembler-times "max" 3 } } */
-+/* { dg-final { scan-assembler-times "minu" 1 } } */
-+/* { dg-final { scan-assembler-times "maxu" 1 } } */
-\ No newline at end of file
-diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
-new file mode 100644
-index 00000000000..958966289df
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c
-@@ -0,0 +1,16 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
-+
-+unsigned long foo1(unsigned long rs1, unsigned long rs2)
-+{
-+    long shamt = rs2 & (64 - 1);
-+    return (rs1 << shamt) | (rs1 >> ((64 - shamt) & (64 - 1)));
-+}
-+unsigned long foo2(unsigned long rs1, unsigned long rs2)
-+{
-+    unsigned long shamt = rs2 & (64 - 1);
-+    return (rs1 >> shamt) | (rs1 << ((64 - shamt) & (64 - 1)));
-+}
-+
-+/* { dg-final { scan-assembler-times "rol" 2 } } */
-+/* { dg-final { scan-assembler-times "ror" 2 } } */
-\ No newline at end of file
-diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
-new file mode 100644
-index 00000000000..24b482f2145
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c
-@@ -0,0 +1,16 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */
-+
-+unsigned int foo1(unsigned int rs1, unsigned int rs2)
-+{
-+    unsigned int shamt = rs2 & (32 - 1);
-+    return (rs1 << shamt) | (rs1 >> ((32 - shamt) & (32 - 1)));
-+}
-+unsigned int foo2(unsigned int rs1, unsigned int rs2)
-+{
-+    unsigned int shamt = rs2 & (32 - 1);
-+    return (rs1 >> shamt) | (rs1 << ((32 - shamt) & (32 - 1)));
-+}
-+
-+/* { dg-final { scan-assembler-times "rol" 2 } } */
-+/* { dg-final { scan-assembler-times "ror" 2 } } */
-\ No newline at end of file
-diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
-new file mode 100644
-index 00000000000..ffde7c9cd58
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c
-@@ -0,0 +1,17 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
-+
-+/* RV64 only*/
-+unsigned int rol(unsigned int rs1, unsigned int rs2)
-+{
-+    int shamt = rs2 & (32 - 1);
-+    return (rs1 << shamt) | (rs1 >> ((64 - shamt) & (32 - 1)));
-+}
-+unsigned int ror(unsigned int rs1, unsigned int rs2)
-+{
-+    int shamt = rs2 & (64 - 1);
-+    return (rs1 >> shamt) | (rs1 << ((32 - shamt) & (32 - 1)));
-+}
-+
-+/* { dg-final { scan-assembler-times "rolw" 1 } } */
-+/* { dg-final { scan-assembler-times "rorw" 1 } } */
-\ No newline at end of file
-diff --git a/gcc/testsuite/gcc.target/riscv/zbbw.c b/gcc/testsuite/gcc.target/riscv/zbbw.c
-new file mode 100644
-index 00000000000..ed88ca5cceb
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zbbw.c
-@@ -0,0 +1,25 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
-+
-+int
-+clz (int i)
-+{
-+  return __builtin_clz (i);
-+}
-+
-+int
-+ctz (int i)
-+{
-+  return __builtin_ctz (i);
-+}
-+
-+int
-+popcount (int i)
-+{
-+  return __builtin_popcount (i);
-+}
-+
-+
-+/* { dg-final { scan-assembler-times "clzw" 1 } } */
-+/* { dg-final { scan-assembler-times "ctzw" 1 } } */
-+/* { dg-final { scan-assembler-times "cpopw" 1 } } */
-\ No newline at end of file
--- 
-2.33.1
-

+ 3 - 3
recipes-devtools/gcc/gcc/0033-Re-introduce-spe-commandline-options.patch → recipes-devtools/gcc/gcc/0019-Re-introduce-spe-commandline-options.patch

@@ -1,4 +1,4 @@
-From 0b900d6410b7c1938e86eceb87b032fd538566a9 Mon Sep 17 00:00:00 2001
+From bf0d7c463e1fab62804556099b56319fe94be1eb Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Wed, 6 Jun 2018 12:10:22 -0700
 Subject: [PATCH] Re-introduce spe commandline options
@@ -14,10 +14,10 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 13 insertions(+)
 
 diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
-index 0dbdf753673..b273eb65c35 100644
+index 4931d781c4e..3fb87b6f7d5 100644
 --- a/gcc/config/rs6000/rs6000.opt
 +++ b/gcc/config/rs6000/rs6000.opt
-@@ -352,6 +352,19 @@ mdebug=
+@@ -348,6 +348,19 @@ mdebug=
  Target RejectNegative Joined
  -mdebug=	Enable debug output.
  

+ 0 - 48
recipes-devtools/gcc/gcc/0020-Cost-model-for-zbb-extension.patch

@@ -1,48 +0,0 @@
-From c1eaf07b4e8a7ea6c3f053003a8ebd9a1e933f22 Mon Sep 17 00:00:00 2001
-From: "yilun.xie" <yilun.xie@starfivetech.com>
-Date: Thu, 18 Nov 2021 15:37:45 +0800
-Subject: [PATCH 20/26] Cost model for zbb extension
-
----
- gcc/config/riscv/riscv.c | 18 ++++++++++++++++++
- 1 file changed, 18 insertions(+)
-
-diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
-index 7d5e22d9fe2..bf91d8c7371 100644
---- a/gcc/config/riscv/riscv.c
-+++ b/gcc/config/riscv/riscv.c
-@@ -1684,6 +1684,16 @@ riscv_extend_cost (rtx op, bool unsigned_p)
-   if (TARGET_ZBA && TARGET_64BIT && unsigned_p && GET_MODE (op) == SImode)
-     return COSTS_N_INSNS (1);
- 
-+  /* ZBB provide zext.h, sext.b and sext.h.  */
-+  if (TARGET_ZBB)
-+    {
-+      if (!unsigned_p && GET_MODE (op) == QImode)
-+	return COSTS_N_INSNS (1);
-+
-+      if (GET_MODE (op) == HImode)
-+	return COSTS_N_INSNS (1);
-+    }
-+
-   if (!unsigned_p && GET_MODE (op) == SImode)
-     /* We can use SEXT.W.  */
-     return COSTS_N_INSNS (1);
-@@ -1775,6 +1785,14 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
- 
-     case IOR:
-     case XOR:
-+      /* orn, andn and xorn pattern for zbb.  */
-+      if (TARGET_ZBB
-+	  && GET_CODE (XEXP (x, 0)) == NOT)
-+	{
-+	  *total = riscv_binary_cost (x, 1, 2);
-+	  return true;
-+	}
-+
-       /* Double-word operations use two single-word operations.  */
-       *total = riscv_binary_cost (x, 1, 2);
-       return false;
--- 
-2.33.1
-

+ 14 - 14
recipes-devtools/gcc/gcc/0034-libgcc_s-Use-alias-for-__cpu_indicator_init-instead-.patch → recipes-devtools/gcc/gcc/0020-libgcc_s-Use-alias-for-__cpu_indicator_init-instead-.patch

@@ -1,4 +1,4 @@
-From ea9154338cb3acbd75945fddde4202e73c20dd1a Mon Sep 17 00:00:00 2001
+From a32c75b37209d6836eaaa943dc6b1207acba5d27 Mon Sep 17 00:00:00 2001
 From: Szabolcs Nagy <nsz@port70.net>
 Date: Sat, 24 Oct 2015 20:09:53 +0000
 Subject: [PATCH] libgcc_s: Use alias for __cpu_indicator_init instead of
@@ -33,30 +33,30 @@ Upstream-Status: Pending
 
 Signed-off-by: Khem Raj <raj.khem@gmail.com>
 ---
- gcc/config/i386/i386-expand.c | 4 ++--
- libgcc/config/i386/cpuinfo.c  | 6 +++---
- libgcc/config/i386/t-linux    | 2 +-
+ gcc/config/i386/i386-expand.cc | 4 ++--
+ libgcc/config/i386/cpuinfo.c   | 6 +++---
+ libgcc/config/i386/t-linux     | 2 +-
  3 files changed, 6 insertions(+), 6 deletions(-)
 
-diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
-index ac69eed4d32..ffaa44a16fc 100644
---- a/gcc/config/i386/i386-expand.c
-+++ b/gcc/config/i386/i386-expand.c
-@@ -11038,10 +11038,10 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
+diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
+index 68978ef8dc2..0c71f36b572 100644
+--- a/gcc/config/i386/i386-expand.cc
++++ b/gcc/config/i386/i386-expand.cc
+@@ -12321,10 +12321,10 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
      {
      case IX86_BUILTIN_CPU_INIT:
        {
--	/* Make it call __cpu_indicator_init in libgcc. */
-+	/* Make it call __cpu_indicator_init_local in libgcc.a. */
+-	/* Make it call __cpu_indicator_init in libgcc.  */
++	/* Make it call __cpu_indicator_init_local in libgcc.a.  */
  	tree call_expr, fndecl, type;
-         type = build_function_type_list (integer_type_node, NULL_TREE); 
+ 	type = build_function_type_list (integer_type_node, NULL_TREE);
 -	fndecl = build_fn_decl ("__cpu_indicator_init", type);
 +	fndecl = build_fn_decl ("__cpu_indicator_init_local", type);
- 	call_expr = build_call_expr (fndecl, 0); 
+ 	call_expr = build_call_expr (fndecl, 0);
  	return expand_expr (call_expr, target, mode, EXPAND_NORMAL);
        }
 diff --git a/libgcc/config/i386/cpuinfo.c b/libgcc/config/i386/cpuinfo.c
-index ef463848f9d..1a3de052c80 100644
+index dab1d98060f..cf824b4114a 100644
 --- a/libgcc/config/i386/cpuinfo.c
 +++ b/libgcc/config/i386/cpuinfo.c
 @@ -63,7 +63,7 @@ __cpu_indicator_init (void)

+ 0 - 26
recipes-devtools/gcc/gcc/0021-Use-SYSTEMLIBS_DIR-replacement-instead-of-hardcoding.patch

@@ -1,26 +0,0 @@
-From 7faad21154a76b200efcced9e12945057c94dff3 Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Tue, 28 Apr 2015 23:15:27 -0700
-Subject: [PATCH] Use SYSTEMLIBS_DIR replacement instead of hardcoding
- base_libdir
-
-Upstream-Status: Pending
-
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
----
- gcc/config/aarch64/aarch64-linux.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/gcc/config/aarch64/aarch64-linux.h b/gcc/config/aarch64/aarch64-linux.h
-index 7f2529a2a1d..5303b39186f 100644
---- a/gcc/config/aarch64/aarch64-linux.h
-+++ b/gcc/config/aarch64/aarch64-linux.h
-@@ -21,7 +21,7 @@
- #ifndef GCC_AARCH64_LINUX_H
- #define GCC_AARCH64_LINUX_H
- 
--#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
-+#define GLIBC_DYNAMIC_LINKER  SYSTEMLIBS_DIR "ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
- 
- #undef MUSL_DYNAMIC_LINKER
- #define MUSL_DYNAMIC_LINKER "/lib/ld-musl-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"

+ 0 - 108
recipes-devtools/gcc/gcc/0021-Use-li-and-rori-to-load-constants.patch

@@ -1,108 +0,0 @@
-From b302f25e1f472cfe8b8e1867fc7499757c6ec4f0 Mon Sep 17 00:00:00 2001
-From: "yilun.xie" <yilun.xie@starfivetech.com>
-Date: Thu, 18 Nov 2021 15:47:00 +0800
-Subject: [PATCH 21/26] Use li and rori to load constants
-
----
- gcc/config/riscv/riscv.c                     | 41 ++++++++++++++++++++
- gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c | 35 +++++++++++++++++
- 2 files changed, 76 insertions(+)
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c
-
-diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
-index bf91d8c7371..9e45c1ff9be 100644
---- a/gcc/config/riscv/riscv.c
-+++ b/gcc/config/riscv/riscv.c
-@@ -439,6 +439,47 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
- 	}
-     }
- 
-+  if (cost > 2 && TARGET_64BIT && TARGET_ZBB)
-+    {
-+      int leading_ones = clz_hwi (~value);
-+      int trailing_ones = ctz_hwi (~value);
-+
-+      /* If all bits are one except a few that are zero, and the zero bits
-+	 are within a range of 11 bits, and at least one of the upper 32-bits
-+	 is a zero, then we can generate a constant by loading a small
-+	 negative constant and rotating.  */
-+      if (leading_ones < 32
-+	  && ((64 - leading_ones - trailing_ones) < 12))
-+	{
-+	  codes[0].code = UNKNOWN;
-+	  /* The sign-bit might be zero, so just rotate to be safe.  */
-+	  codes[0].value = (((unsigned HOST_WIDE_INT) value >> trailing_ones)
-+			    | (value << (64 - trailing_ones)));
-+	  codes[1].code = ROTATERT;
-+	  codes[1].value = 64 - trailing_ones;
-+	  cost = 2;
-+	}
-+      /* Handle the case where the 11 bit range of zero bits wraps around.  */
-+      else
-+	{
-+	  int upper_trailing_ones = ctz_hwi (~value >> 32);
-+	  int lower_leading_ones = clz_hwi (~value << 32);
-+
-+	  if (upper_trailing_ones < 32 && lower_leading_ones < 32
-+	      && ((64 - upper_trailing_ones - lower_leading_ones) < 12))
-+	    {
-+	      codes[0].code = UNKNOWN;
-+	      /* The sign-bit might be zero, so just rotate to be safe.  */
-+	      codes[0].value = ((value << (32 - upper_trailing_ones))
-+				| ((unsigned HOST_WIDE_INT) value
-+				   >> (32 + upper_trailing_ones)));
-+	      codes[1].code = ROTATERT;
-+	      codes[1].value = 32 - upper_trailing_ones;
-+	      cost = 2;
-+	    }
-+	}
-+    }
-+
-   gcc_assert (cost <= RISCV_MAX_INTEGER_OPS);
-   return cost;
- }
-diff --git a/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c b/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c
-new file mode 100644
-index 00000000000..ab8138cd874
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c
-@@ -0,0 +1,35 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */
-+
-+long
-+li_rori (void)
-+{
-+  return 0xffff77ffffffffffL;
-+}
-+
-+long
-+li_rori_2 (void)
-+{
-+  return 0x77ffffffffffffffL;
-+}
-+
-+long
-+li_rori_3 (void)
-+{
-+  return 0xfffffffeefffffffL;
-+}
-+
-+long
-+li_rori_4 (void)
-+{
-+  return 0x5ffffffffffffff5L;
-+}
-+
-+long
-+li_rori_5 (void)
-+{
-+  return 0xaffffffffffffffaL;
-+}
-+
-+
-+/* { dg-final { scan-assembler-times "rori\t" 5 } } */
-\ No newline at end of file
--- 
-2.33.1
-

+ 36 - 36
recipes-devtools/gcc/gcc/0035-gentypes-genmodes-Do-not-use-__LINE__-for-maintainin.patch → recipes-devtools/gcc/gcc/0021-gentypes-genmodes-Do-not-use-__LINE__-for-maintainin.patch

@@ -1,4 +1,4 @@
-From 520411cf364ee4b0b5a8f0857498aaabd790afb3 Mon Sep 17 00:00:00 2001
+From 4efc42b99c96b026f560b0918de7e237ac3dc8d1 Mon Sep 17 00:00:00 2001
 From: Richard Purdie <richard.purdie@linuxfoundation.org>
 Date: Tue, 10 Mar 2020 08:26:53 -0700
 Subject: [PATCH] gentypes/genmodes: Do not use __LINE__ for maintaining
@@ -12,15 +12,15 @@ Upstream-Status: Inappropriate [OE Reproducibility specific]
 Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
 Signed-off-by: Khem Raj <raj.khem@gmail.com>
 ---
- gcc/gengtype.c |  6 +++---
- gcc/genmodes.c | 32 ++++++++++++++++----------------
+ gcc/gengtype.cc |  6 +++---
+ gcc/genmodes.cc | 32 ++++++++++++++++----------------
  2 files changed, 19 insertions(+), 19 deletions(-)
 
-diff --git a/gcc/gengtype.c b/gcc/gengtype.c
-index 5f50242e857..cbaca9b8cd0 100644
---- a/gcc/gengtype.c
-+++ b/gcc/gengtype.c
-@@ -991,7 +991,7 @@ create_field_at (pair_p next, type_p type, const char *name, options_p opt,
+diff --git a/gcc/gengtype.cc b/gcc/gengtype.cc
+index 386ae1b0506..9762e914296 100644
+--- a/gcc/gengtype.cc
++++ b/gcc/gengtype.cc
+@@ -1006,7 +1006,7 @@ create_field_at (pair_p next, type_p type, const char *name, options_p opt,
  /* Create a fake field with the given type and name.  NEXT is the next
     field in the chain.  */
  #define create_field(next,type,name) \
@@ -29,7 +29,7 @@ index 5f50242e857..cbaca9b8cd0 100644
  
  /* Like create_field, but the field is only valid when condition COND
     is true.  */
-@@ -1024,7 +1024,7 @@ create_optional_field_ (pair_p next, type_p type, const char *name,
+@@ -1039,7 +1039,7 @@ create_optional_field_ (pair_p next, type_p type, const char *name,
  }
  
  #define create_optional_field(next,type,name,cond)	\
@@ -38,7 +38,7 @@ index 5f50242e857..cbaca9b8cd0 100644
  
  /* Reverse a linked list of 'struct pair's in place.  */
  pair_p
-@@ -5189,7 +5189,7 @@ main (int argc, char **argv)
+@@ -5238,7 +5238,7 @@ main (int argc, char **argv)
        /* These types are set up with #define or else outside of where
           we can see them.  We should initialize them before calling
           read_input_list.  */
@@ -47,11 +47,11 @@ index 5f50242e857..cbaca9b8cd0 100644
  	Call;} while (0)
        POS_HERE (do_scalar_typedef ("CUMULATIVE_ARGS", &pos));
        POS_HERE (do_scalar_typedef ("REAL_VALUE_TYPE", &pos));
-diff --git a/gcc/genmodes.c b/gcc/genmodes.c
-index c268ebc4c6e..4361f3f1563 100644
---- a/gcc/genmodes.c
-+++ b/gcc/genmodes.c
-@@ -438,7 +438,7 @@ complete_all_modes (void)
+diff --git a/gcc/genmodes.cc b/gcc/genmodes.cc
+index 59850bb070a..e187f8542a1 100644
+--- a/gcc/genmodes.cc
++++ b/gcc/genmodes.cc
+@@ -440,7 +440,7 @@ complete_all_modes (void)
  }
  
  /* For each mode in class CLASS, construct a corresponding complex mode.  */
@@ -60,7 +60,7 @@ index c268ebc4c6e..4361f3f1563 100644
  static void
  make_complex_modes (enum mode_class cl,
  		    const char *file, unsigned int line)
-@@ -497,7 +497,7 @@ make_complex_modes (enum mode_class cl,
+@@ -499,7 +499,7 @@ make_complex_modes (enum mode_class cl,
     having as many components as necessary.  ORDER is the sorting order
     of the mode, with smaller numbers indicating a higher priority.  */
  #define VECTOR_MODES_WITH_PREFIX(PREFIX, C, W, ORDER) \
@@ -69,16 +69,16 @@ index c268ebc4c6e..4361f3f1563 100644
  #define VECTOR_MODES(C, W) VECTOR_MODES_WITH_PREFIX (V, C, W, 0)
  static void ATTRIBUTE_UNUSED
  make_vector_modes (enum mode_class cl, const char *prefix, unsigned int width,
-@@ -549,7 +549,7 @@ make_vector_modes (enum mode_class cl, const char *prefix, unsigned int width,
- /* Create a vector of booleans called NAME with COUNT elements and
+@@ -552,7 +552,7 @@ make_vector_modes (enum mode_class cl, const char *prefix, unsigned int width,
     BYTESIZE bytes in total.  */
- #define VECTOR_BOOL_MODE(NAME, COUNT, BYTESIZE) \
--  make_vector_bool_mode (#NAME, COUNT, BYTESIZE, __FILE__, __LINE__)
-+  make_vector_bool_mode (#NAME, COUNT, BYTESIZE, __FILE__, 0)
+ #define VECTOR_BOOL_MODE(NAME, COUNT, COMPONENT, BYTESIZE)		\
+   make_vector_bool_mode (#NAME, COUNT, #COMPONENT, BYTESIZE,		\
+-			 __FILE__, __LINE__)
++			 __FILE__, 0)
  static void ATTRIBUTE_UNUSED
  make_vector_bool_mode (const char *name, unsigned int count,
- 		       unsigned int bytesize, const char *file,
-@@ -571,7 +571,7 @@ make_vector_bool_mode (const char *name, unsigned int count,
+ 		       const char *component, unsigned int bytesize,
+@@ -574,7 +574,7 @@ make_vector_bool_mode (const char *name, unsigned int count,
  /* Input.  */
  
  #define _SPECIAL_MODE(C, N) \
@@ -87,7 +87,7 @@ index c268ebc4c6e..4361f3f1563 100644
  #define RANDOM_MODE(N) _SPECIAL_MODE (RANDOM, N)
  #define CC_MODE(N) _SPECIAL_MODE (CC, N)
  
-@@ -584,7 +584,7 @@ make_special_mode (enum mode_class cl, const char *name,
+@@ -587,7 +587,7 @@ make_special_mode (enum mode_class cl, const char *name,
  
  #define INT_MODE(N, Y) FRACTIONAL_INT_MODE (N, -1U, Y)
  #define FRACTIONAL_INT_MODE(N, B, Y) \
@@ -96,7 +96,7 @@ index c268ebc4c6e..4361f3f1563 100644
  
  static void
  make_int_mode (const char *name,
-@@ -611,16 +611,16 @@ make_opaque_mode (const char *name,
+@@ -628,16 +628,16 @@ make_opaque_mode (const char *name,
  }
  
  #define FRACT_MODE(N, Y, F) \
@@ -117,7 +117,7 @@ index c268ebc4c6e..4361f3f1563 100644
  
  /* Create a fixed-point mode by setting CL, NAME, BYTESIZE, IBIT, FBIT,
     FILE, and LINE.  */
-@@ -641,7 +641,7 @@ make_fixed_point_mode (enum mode_class cl,
+@@ -658,7 +658,7 @@ make_fixed_point_mode (enum mode_class cl,
  
  #define FLOAT_MODE(N, Y, F)             FRACTIONAL_FLOAT_MODE (N, -1U, Y, F)
  #define FRACTIONAL_FLOAT_MODE(N, B, Y, F) \
@@ -126,7 +126,7 @@ index c268ebc4c6e..4361f3f1563 100644
  
  static void
  make_float_mode (const char *name,
-@@ -658,7 +658,7 @@ make_float_mode (const char *name,
+@@ -675,7 +675,7 @@ make_float_mode (const char *name,
  #define DECIMAL_FLOAT_MODE(N, Y, F)	\
  	FRACTIONAL_DECIMAL_FLOAT_MODE (N, -1U, Y, F)
  #define FRACTIONAL_DECIMAL_FLOAT_MODE(N, B, Y, F)	\
@@ -135,7 +135,7 @@ index c268ebc4c6e..4361f3f1563 100644
  
  static void
  make_decimal_float_mode (const char *name,
-@@ -673,7 +673,7 @@ make_decimal_float_mode (const char *name,
+@@ -690,7 +690,7 @@ make_decimal_float_mode (const char *name,
  }
  
  #define RESET_FLOAT_FORMAT(N, F) \
@@ -144,7 +144,7 @@ index c268ebc4c6e..4361f3f1563 100644
  static void ATTRIBUTE_UNUSED
  reset_float_format (const char *name, const char *format,
  		    const char *file, unsigned int line)
-@@ -694,7 +694,7 @@ reset_float_format (const char *name, const char *format,
+@@ -711,7 +711,7 @@ reset_float_format (const char *name, const char *format,
  
  /* __intN support.  */
  #define INT_N(M,PREC)				\
@@ -153,7 +153,7 @@ index c268ebc4c6e..4361f3f1563 100644
  static void ATTRIBUTE_UNUSED
  make_int_n (const char *m, int bitsize,
              const char *file, unsigned int line)
-@@ -723,7 +723,7 @@ make_int_n (const char *m, int bitsize,
+@@ -740,7 +740,7 @@ make_int_n (const char *m, int bitsize,
  /* Partial integer modes are specified by relation to a full integer
     mode.  */
  #define PARTIAL_INT_MODE(M,PREC,NAME)				\
@@ -162,16 +162,16 @@ index c268ebc4c6e..4361f3f1563 100644
  static void ATTRIBUTE_UNUSED
  make_partial_integer_mode (const char *base, const char *name,
  			   unsigned int precision,
-@@ -750,7 +750,7 @@ make_partial_integer_mode (const char *base, const char *name,
+@@ -767,7 +767,7 @@ make_partial_integer_mode (const char *base, const char *name,
  /* A single vector mode can be specified by naming its component
     mode and the number of components.  */
- #define VECTOR_MODE(C, M, N) \
--  make_vector_mode (MODE_##C, #M, N, __FILE__, __LINE__);
-+  make_vector_mode (MODE_##C, #M, N, __FILE__, 0);
+ #define VECTOR_MODE_WITH_PREFIX(PREFIX, C, M, N, ORDER) \
+-  make_vector_mode (MODE_##C, #PREFIX, #M, N, ORDER, __FILE__, __LINE__);
++  make_vector_mode (MODE_##C, #PREFIX, #M, N, ORDER, __FILE__, 0);
+ #define VECTOR_MODE(C, M, N) VECTOR_MODE_WITH_PREFIX(V, C, M, N, 0);
  static void ATTRIBUTE_UNUSED
  make_vector_mode (enum mode_class bclass,
- 		  const char *base,
-@@ -793,7 +793,7 @@ make_vector_mode (enum mode_class bclass,
+@@ -814,7 +814,7 @@ make_vector_mode (enum mode_class bclass,
  
  /* Adjustability.  */
  #define _ADD_ADJUST(A, M, X, C1, C2) \

+ 0 - 297
recipes-devtools/gcc/gcc/0022-Implement-instruction-patterns-for-ZBS-extension.patch

@@ -1,297 +0,0 @@
-From d3bc6ead74d78d367c0d6cc53efc57c05d8133e9 Mon Sep 17 00:00:00 2001
-From: "yilun.xie" <yilun.xie@starfivetech.com>
-Date: Thu, 18 Nov 2021 16:08:45 +0800
-Subject: [PATCH 22/26] Implement instruction patterns for ZBS extension
-
----
- gcc/config/riscv/predicates.md              | 22 +++++++++++
- gcc/config/riscv/riscv.c                    | 37 ++++++++++++++++++-
- gcc/config/riscv/riscv.h                    |  8 ++++
- gcc/testsuite/gcc.target/riscv/zba-slliuw.c |  4 +-
- gcc/testsuite/gcc.target/riscv/zbs-bclr.c   | 20 ++++++++++
- gcc/testsuite/gcc.target/riscv/zbs-bext.c   | 20 ++++++++++
- gcc/testsuite/gcc.target/riscv/zbs-binv.c   | 20 ++++++++++
- gcc/testsuite/gcc.target/riscv/zbs-bset.c   | 41 +++++++++++++++++++++
- 8 files changed, 168 insertions(+), 4 deletions(-)
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bclr.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bext.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-binv.c
- create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bset.c
-
-diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
-index 23211513554..7a079ebd175 100644
---- a/gcc/config/riscv/predicates.md
-+++ b/gcc/config/riscv/predicates.md
-@@ -74,6 +74,11 @@
-   if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
-     return false;
- 
-+  /* Check whether the constant can be loaded in a single
-+     instruction with zbs extensions.  */
-+  if (TARGET_64BIT && TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (INTVAL (op)))
-+    return false;
-+
-   /* Otherwise check whether the constant can be loaded in a single
-      instruction.  */
-   return !LUI_OPERAND (INTVAL (op)) && !SMALL_OPERAND (INTVAL (op));
-@@ -217,3 +222,20 @@
- {
-   return riscv_gpr_save_operation_p (op);
- })
-+
-+;; Predicates for the ZBS extension.
-+(define_predicate "single_bit_mask_operand"
-+  (and (match_code "const_int")
-+       (match_test "pow2p_hwi (INTVAL (op))")))
-+
-+(define_predicate "not_single_bit_mask_operand"
-+  (and (match_code "const_int")
-+       (match_test "pow2p_hwi (~INTVAL (op))")))
-+
-+(define_predicate "const31_operand"
-+  (and (match_code "const_int")
-+       (match_test "INTVAL (op) == 31")))
-+
-+(define_predicate "const63_operand"
-+  (and (match_code "const_int")
-+       (match_test "INTVAL (op) == 63")))
-\ No newline at end of file
-diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
-index 9e45c1ff9be..0978666a366 100644
---- a/gcc/config/riscv/riscv.c
-+++ b/gcc/config/riscv/riscv.c
-@@ -388,6 +388,14 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
-       return 1;
-     }
- 
-+  if (TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (value))
-+    {
-+      /* Simply BSETI.  */
-+      codes[0].code = UNKNOWN;
-+      codes[0].value = value;
-+      return 1;
-+    }
-+
-   /* End with ADDI.  When constructing HImode constants, do not generate any
-      intermediate value that is not itself a valid HImode constant.  The
-      XORI case below will handle those remaining HImode constants.  */
-@@ -2199,7 +2207,17 @@ riscv_output_move (rtx dest, rtx src)
- 	  }
- 
-       if (src_code == CONST_INT)
--	return "li\t%0,%1";
-+  	{
-+  	  if (SMALL_OPERAND (INTVAL (src)) || LUI_OPERAND (INTVAL (src)))
-+  	    return "li\t%0,%1";
-+  
-+  	  if (TARGET_ZBS
-+  	      && SINGLE_BIT_MASK_OPERAND (INTVAL (src)))
-+  	    return "bseti\t%0,zero,%S1";
-+  
-+  	  /* Should never reach here.  */
-+  	  abort ();
-+  	}
- 
-       if (src_code == HIGH)
- 	return "lui\t%0,%h1";
-@@ -3543,7 +3561,9 @@ riscv_memmodel_needs_release_fence (enum memmodel model)
-    'A'	Print the atomic operation suffix for memory model OP.
-    'F'	Print a FENCE if the memory model requires a release.
-    'z'	Print x0 if OP is zero, otherwise print OP normally.
--   'i'	Print i if the operand is not a register.  */
-+   'i'	Print i if the operand is not a register.
-+   'S'	Print shift-index of single-bit mask OP.
-+   'T'	Print shift-index of inverted single-bit mask OP.  */
- 
- static void
- riscv_print_operand (FILE *file, rtx op, int letter)
-@@ -3583,6 +3603,19 @@ riscv_print_operand (FILE *file, rtx op, int letter)
-         fputs ("i", file);
-       break;
- 
-+    case 'S':
-+      {
-+      rtx newop = GEN_INT (ctz_hwi (INTVAL (op)));
-+      output_addr_const (file, newop);
-+      break;
-+      }
-+    case 'T':
-+      {
-+      rtx newop = GEN_INT (ctz_hwi (~INTVAL (op)));
-+      output_addr_const (file, newop);
-+      break;
-+      }
-+
-     default:
-       switch (code)
- 	{
-diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
-index d17096e1dfa..ff6729aedac 100644
---- a/gcc/config/riscv/riscv.h
-+++ b/gcc/config/riscv/riscv.h
-@@ -521,6 +521,14 @@ enum reg_class
-   (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH)	\
-    || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
- 
-+/* If this is a single bit mask, then we can load it with bseti.  But this
-+   is not useful for any of the low 31 bits because we can use addi or lui
-+   to load them.  It is wrong for loading SImode 0x80000000 on rv64 because it
-+   needs to be sign-extended.  So we restrict this to the upper 32-bits
-+   only.  */
-+#define SINGLE_BIT_MASK_OPERAND(VALUE) \
-+  (pow2p_hwi (VALUE) && (ctz_hwi (VALUE) >= 32))
-+
- /* Stack layout; function entry, exit and calling.  */
- 
- #define STACK_GROWS_DOWNWARD 1
-diff --git a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
-index 55ebc1c81ce..2c86e446272 100644
---- a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
-+++ b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */
-+/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */
- 
- long
- foo (long i)
-@@ -8,4 +8,4 @@ foo (long i)
- }
- /* XXX: This pattern need combine improvement or intermediate instruction
-  *      from zbs.   */
--/* { dg-final { scan-assembler-not "slli.uw" } } */
-\ No newline at end of file
-+/* { dg-final { scan-assembler "slli.uw" } } */
-\ No newline at end of file
-diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bclr.c b/gcc/testsuite/gcc.target/riscv/zbs-bclr.c
-new file mode 100644
-index 00000000000..fdf75b039b9
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zbs-bclr.c
-@@ -0,0 +1,20 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
-+
-+/* bclr */
-+long
-+foo0 (long i, long j)
-+{
-+  return i & ~(1L << j);
-+}
-+
-+/* bclri */
-+long
-+foo1 (long i)
-+{
-+  return i & ~(1L << 20);
-+}
-+
-+/* { dg-final { scan-assembler-times "bclr\t" 1 } } */
-+/* { dg-final { scan-assembler-times "bclri\t" 1 } } */
-+/* { dg-final { scan-assembler-not "andi" } } */
-\ No newline at end of file
-diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext.c b/gcc/testsuite/gcc.target/riscv/zbs-bext.c
-new file mode 100644
-index 00000000000..766a7c4423a
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zbs-bext.c
-@@ -0,0 +1,20 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
-+
-+/* bext */
-+long
-+foo0 (long i, long j)
-+{
-+  return 1L & (i >> j);
-+}
-+
-+/* bexti */
-+long
-+foo1 (long i)
-+{
-+  return 1L & (i >> 20);
-+}
-+
-+/* { dg-final { scan-assembler-times "bexti\t" 1 } } */
-+/* { dg-final { scan-assembler-times "bext\t" 1 } } */
-+/* { dg-final { scan-assembler-not "andi" } } */
-\ No newline at end of file
-diff --git a/gcc/testsuite/gcc.target/riscv/zbs-binv.c b/gcc/testsuite/gcc.target/riscv/zbs-binv.c
-new file mode 100644
-index 00000000000..d90a6301103
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zbs-binv.c
-@@ -0,0 +1,20 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
-+
-+/* binv */
-+long
-+foo0 (long i, long j)
-+{
-+  return i ^ (1L << j);
-+}
-+
-+/* binvi */
-+long
-+foo1 (long i)
-+{
-+  return i ^ (1L << 20);
-+}
-+
-+/* { dg-final { scan-assembler-times "binv\t" 1 } } */
-+/* { dg-final { scan-assembler-times "binvi\t" 1 } } */
-+/* { dg-final { scan-assembler-not "andi" } } */
-\ No newline at end of file
-diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bset.c b/gcc/testsuite/gcc.target/riscv/zbs-bset.c
-new file mode 100644
-index 00000000000..c3107270153
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/riscv/zbs-bset.c
-@@ -0,0 +1,41 @@
-+/* { dg-do compile } */
-+/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
-+
-+/* bset */
-+long
-+sub0 (long i, long j)
-+{
-+  return i | (1L << j);
-+}
-+
-+/* bset_mask */
-+long
-+sub1 (long i, long j)
-+{
-+  return i | (1L << (j & 0x3f));
-+}
-+
-+/* bset_1 */
-+long
-+sub2 (long i)
-+{
-+  return 1L << i;
-+}
-+
-+/* bset_1_mask */
-+long
-+sub3 (long i)
-+{
-+  return 1L << (i & 0x3f);
-+}
-+
-+/* bseti */
-+long
-+sub4 (long i)
-+{
-+  return i | (1L << 20);
-+}
-+
-+/* { dg-final { scan-assembler-times "bset\t" 4 } } */
-+/* { dg-final { scan-assembler-times "bseti\t" 1 } } */
-+/* { dg-final { scan-assembler-not "andi" } } */
-\ No newline at end of file
--- 
-2.33.1
-

+ 0 - 25
recipes-devtools/gcc/gcc/0022-aarch64-Add-support-for-musl-ldso.patch

@@ -1,25 +0,0 @@
-From 96aa24a874331a318693e4fccc4bc4e7d3fbad2b Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Tue, 28 Apr 2015 23:18:39 -0700
-Subject: [PATCH] aarch64: Add support for musl ldso
-
-Upstream-Status: Pending
-
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
----
- gcc/config/aarch64/aarch64-linux.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/gcc/config/aarch64/aarch64-linux.h b/gcc/config/aarch64/aarch64-linux.h
-index 5303b39186f..4bcae7f3110 100644
---- a/gcc/config/aarch64/aarch64-linux.h
-+++ b/gcc/config/aarch64/aarch64-linux.h
-@@ -24,7 +24,7 @@
- #define GLIBC_DYNAMIC_LINKER  SYSTEMLIBS_DIR "ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
- 
- #undef MUSL_DYNAMIC_LINKER
--#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
-+#define MUSL_DYNAMIC_LINKER  SYSTEMLIBS_DIR "ld-musl-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
- 
- #undef  ASAN_CC1_SPEC
- #define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"

+ 2 - 2
recipes-devtools/gcc/gcc/0036-mingw32-Enable-operation_not_supported.patch → recipes-devtools/gcc/gcc/0022-mingw32-Enable-operation_not_supported.patch

@@ -1,4 +1,4 @@
-From 96d895c8d5dc895d24fe37aa2b4f201a2566b4cc Mon Sep 17 00:00:00 2001
+From 061cf79e7b6e89fdf0f2630ddaebbf1d7b271ac3 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Tue, 12 May 2020 10:39:09 -0700
 Subject: [PATCH] mingw32: Enable operation_not_supported
@@ -12,7 +12,7 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/libstdc++-v3/config/os/mingw32/error_constants.h b/libstdc++-v3/config/os/mingw32/error_constants.h
-index eca06a97014..933cfab49cf 100644
+index da5f4c2ac85..e855c86267c 100644
 --- a/libstdc++-v3/config/os/mingw32/error_constants.h
 +++ b/libstdc++-v3/config/os/mingw32/error_constants.h
 @@ -107,7 +107,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION

+ 0 - 88
recipes-devtools/gcc/gcc/0023-Cost-model-for-ZBS-extension.patch

@@ -1,88 +0,0 @@
-From 254eef43b7f99cc3308d02343c603286ba121816 Mon Sep 17 00:00:00 2001
-From: "yilun.xie" <yilun.xie@starfivetech.com>
-Date: Thu, 18 Nov 2021 16:13:59 +0800
-Subject: [PATCH 23/26] Cost model for ZBS extension
-
----
- gcc/config/riscv/riscv.c | 47 +++++++++++++++++++++++++++++++++++++++-
- 1 file changed, 46 insertions(+), 1 deletion(-)
-
-diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
-index 0978666a366..61666b8b2f6 100644
---- a/gcc/config/riscv/riscv.c
-+++ b/gcc/config/riscv/riscv.c
-@@ -1830,8 +1830,25 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
- 	    *total = COSTS_N_INSNS (1);
- 	    return true;
- 	}
--      gcc_fallthrough ();
-+      /* bclri pattern for zbs.  */
-+      if (TARGET_ZBS
-+	  && not_single_bit_mask_operand (XEXP (x, 1), VOIDmode))
-+	{
-+	  *total = COSTS_N_INSNS (1);
-+	  return true;
-+	}
-+      /* bclr pattern for zbs.  */
-+      if (TARGET_ZBS
-+	  && REG_P (XEXP (x, 1))
-+	  && GET_CODE (XEXP (x, 0)) == ROTATE
-+	  && CONST_INT_P (XEXP ((XEXP (x, 0)), 0))
-+	  && INTVAL (XEXP ((XEXP (x, 0)), 0)) == -2)
-+	{
-+	  *total = COSTS_N_INSNS (1);
-+	  return true;
-+	}
- 
-+      gcc_fallthrough ();
-     case IOR:
-     case XOR:
-       /* orn, andn and xorn pattern for zbb.  */
-@@ -1842,6 +1859,17 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
- 	  return true;
- 	}
- 
-+      /* bset[i] and binv[i] pattern for zbs.  */
-+      if ((GET_CODE (x) == IOR || GET_CODE (x) == XOR)
-+	  && TARGET_ZBS
-+	  && ((GET_CODE (XEXP (x, 0)) == ASHIFT
-+	      && CONST_INT_P (XEXP (XEXP (x, 0), 0)))
-+	      || single_bit_mask_operand (XEXP (x, 1), VOIDmode)))
-+	{
-+	  *total = COSTS_N_INSNS (1);
-+	  return true;
-+	}
-+
-       /* Double-word operations use two single-word operations.  */
-       *total = riscv_binary_cost (x, 1, 2);
-       return false;
-@@ -1857,9 +1885,26 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
- 	  *total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
- 	  return true;
- 	}
-+      /* bext pattern for zbs.  */
-+      if (TARGET_ZBS && outer_code == SET
-+	  && GET_CODE (XEXP (x, 1)) == CONST_INT
-+	  && INTVAL (XEXP (x, 1)) == 1)
-+	{
-+	  *total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
-+	  return true;
-+	}
-       return false;
- 
-     case ASHIFT:
-+      /* bset pattern for zbs.  */
-+      if (TARGET_ZBS
-+	  && CONST_INT_P (XEXP (x, 0))
-+	  && INTVAL (XEXP (x, 0)) == 1)
-+	{
-+	  *total = COSTS_N_INSNS (1);
-+	  return true;
-+	}
-+      gcc_fallthrough ();
-     case ASHIFTRT:
-     case LSHIFTRT:
-       *total = riscv_binary_cost (x, SINGLE_SHIFT_COST,
--- 
-2.33.1
-

+ 5 - 5
recipes-devtools/gcc/gcc/0037-libatomic-Do-not-enforce-march-on-aarch64.patch → recipes-devtools/gcc/gcc/0023-libatomic-Do-not-enforce-march-on-aarch64.patch

@@ -1,4 +1,4 @@
-From 36d4fdbc99e69f9d70a29e2bada40cc3c1534557 Mon Sep 17 00:00:00 2001
+From 52931ec7a708b58d68e69ce9eb99001ae9f099dd Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Wed, 13 May 2020 15:10:38 -0700
 Subject: [PATCH] libatomic: Do not enforce march on aarch64
@@ -17,7 +17,7 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  2 files changed, 2 deletions(-)
 
 diff --git a/libatomic/Makefile.am b/libatomic/Makefile.am
-index 0f3cd6f7121..c8124c1d5aa 100644
+index d88515e4a03..e0e2f8b442a 100644
 --- a/libatomic/Makefile.am
 +++ b/libatomic/Makefile.am
 @@ -125,7 +125,6 @@ libatomic_la_LIBADD = $(foreach s,$(SIZES),$(addsuffix _$(s)_.lo,$(SIZEOBJS)))
@@ -29,14 +29,14 @@ index 0f3cd6f7121..c8124c1d5aa 100644
  endif
  if ARCH_ARM_LINUX
 diff --git a/libatomic/Makefile.in b/libatomic/Makefile.in
-index 0a51bd55f01..6d5b1581706 100644
+index 80d25653dc7..7377689ab34 100644
 --- a/libatomic/Makefile.in
 +++ b/libatomic/Makefile.in
-@@ -432,7 +432,6 @@ M_SRC = $(firstword $(filter %/$(M_FILE), $(all_c_files)))
+@@ -434,7 +434,6 @@ M_SRC = $(firstword $(filter %/$(M_FILE), $(all_c_files)))
  libatomic_la_LIBADD = $(foreach s,$(SIZES),$(addsuffix \
  	_$(s)_.lo,$(SIZEOBJS))) $(am__append_1) $(am__append_2) \
  	$(am__append_3) $(am__append_4)
 -@ARCH_AARCH64_LINUX_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -march=armv8-a+lse
  @ARCH_ARM_LINUX_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -march=armv7-a+fp -DHAVE_KERNEL64
  @ARCH_I386_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -march=i586
- @ARCH_X86_64_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -mcx16
+ @ARCH_X86_64_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -mcx16 -mcx16

+ 31 - 0
recipes-devtools/gcc/gcc/0024-Fix-install-path-of-linux64.h.patch

@@ -0,0 +1,31 @@
+From 3e67c9c77e46132c252911bf1e5e4222dfd3aa34 Mon Sep 17 00:00:00 2001
+From: Andrei Gherzan <andrei.gherzan@huawei.com>
+Date: Wed, 22 Dec 2021 12:49:25 +0100
+Subject: [PATCH] Fix install path of linux64.h
+
+We add linux64.h to tm includes[1] as a relative path to B. This patch
+adapts the install path of linux64.h to match the include in tm.h.
+
+[1] 0016-Use-the-multilib-config-files-from-B-instead-of-usin.patch
+
+Signed-off-by: Andrei Gherzan <andrei.gherzan@huawei.com>
+
+Upstream-Status: Inappropriate [configuration]
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ gcc/Makefile.in | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/gcc/Makefile.in b/gcc/Makefile.in
+index 07fa63b6640..0def7394454 100644
+--- a/gcc/Makefile.in
++++ b/gcc/Makefile.in
+@@ -3706,6 +3706,8 @@ install-plugin: installdirs lang.install-plugin s-header-vars install-gengtype
+ 	  "$(srcdir)"/config/* | "$(srcdir)"/common/config/* \
+ 	  | "$(srcdir)"/c-family/* | "$(srcdir)"/*.def ) \
+ 	    base=`echo "$$path" | sed -e "s|$$srcdirstrip/||"`;; \
++	  */linux64.h ) \
++	    base=`dirname $$path`;;\
+ 	  *) base=`basename $$path` ;; \
+ 	  esac; \
+ 	  dest=$(plugin_includedir)/$$base; \

+ 0 - 31
recipes-devtools/gcc/gcc/0024-RISC-V-costs-handle-BSWAP.patch

@@ -1,31 +0,0 @@
-From 167a062d1a8162b9441a6c0327722e77c8afa01a Mon Sep 17 00:00:00 2001
-From: "yilun.xie" <yilun.xie@starfivetech.com>
-Date: Sun, 21 Nov 2021 21:56:18 -0800
-Subject: [PATCH 24/26] RISC-V: costs: handle BSWAP
-
----
- gcc/config/riscv/riscv.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
-index 61666b8b2f6..8e22e36eaaf 100644
---- a/gcc/config/riscv/riscv.c
-+++ b/gcc/config/riscv/riscv.c
-@@ -2110,6 +2110,14 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
-       *total = riscv_extend_cost (XEXP (x, 0), GET_CODE (x) == ZERO_EXTEND);
-       return false;
- 
-+    case BSWAP:
-+      if (TARGET_ZBB)
-+	{
-+	  *total = COSTS_N_INSNS (1);
-+	  return true;
-+	}
-+      return false;
-+
-     case FLOAT:
-     case UNSIGNED_FLOAT:
-     case FIX:
--- 
-2.33.1
-

+ 56 - 0
recipes-devtools/gcc/gcc/0025-Move-sched.h-include-ahead-of-user-headers.patch

@@ -0,0 +1,56 @@
+From 7422adfb471f4b4f2ec870124064632d55f72e50 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Mon, 11 Apr 2022 15:46:18 -0700
+Subject: [PATCH] Move sched.h include ahead of user headers
+
+Fix attempt to use poisoned calloc error, this moves the sched.h before
+using system.h from gcc headers which includes #pragma GCC poison calloc
+
+Fixes
+In file included from /mnt/b/yoe/master/build/tmp/work/cortexa72-yoe-linux-musl/gcc/12.0.1-r0/recipe-sysroot/usr/include/pthread.h:30,
+                 from /mnt/b/yoe/master/build/tmp/work/cortexa72-yoe-linux-musl/gcc/12.0.1-r0/recipe-sysroot/usr/include/c++/12.0.1/aarch64-yoe-linux-musl/bits/gthr-default.h:35,
+                 from /mnt/b/yoe/master/build/tmp/work/cortexa72-yoe-linux-musl/gcc/12.0.1-r0/recipe-sysroot/usr/include/c++/12.0.1/aarch64-yoe-linux-musl/bits/gthr.h:148,
+                 from /mnt/b/yoe/master/build/tmp/work/cortexa72-yoe-linux-musl/gcc/12.0.1-r0/recipe-sysroot/usr/include/c++/12.0.1/ext/atomicity.h:35,
+                 from /mnt/b/yoe/master/build/tmp/work/cortexa72-yoe-linux-musl/gcc/12.0.1-r0/recipe-sysroot/usr/include/c++/12.0.1/bits/shared_ptr_base.h:61,
+                 from /mnt/b/yoe/master/build/tmp/work/cortexa72-yoe-linux-musl/gcc/12.0.1-r0/recipe-sysroot/usr/include/c++/12.0.1/bits/shared_ptr.h:53,
+                 from /mnt/b/yoe/master/build/tmp/work/cortexa72-yoe-linux-musl/gcc/12.0.1-r0/recipe-sysroot/usr/include/c++/12.0.1/memory:77,
+                 from ../../../../../../../work-shared/gcc-12.0.1-r0/gcc-12-20220410/libcc1/deleter.hh:23,
+                 from ../../../../../../../work-shared/gcc-12.0.1-r0/gcc-12-20220410/libcc1/rpc.hh:25,
+                 from ../../../../../../../work-shared/gcc-12.0.1-r0/gcc-12-20220410/libcc1/libcc1plugin.cc:67:
+/mnt/b/yoe/master/build/tmp/work/cortexa72-yoe-linux-musl/gcc/12.0.1-r0/recipe-sysroot/usr/include/sched.h:84:7: error: attempt to use poisoned "calloc"
+   84 | void *calloc(size_t, size_t);
+      |       ^
+/mnt/b/yoe/master/build/tmp/work/cortexa72-yoe-linux-musl/gcc/12.0.1-r0/recipe-sysroot/usr/include/sched.h:124:36: error: attempt to use poisoned "calloc"
+  124 | #define CPU_ALLOC(n) ((cpu_set_t *)calloc(1,CPU_ALLOC_SIZE(n)))
+
+Upstream-Status: Pending
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ libcc1/libcc1plugin.cc | 1 +
+ libcc1/libcp1plugin.cc | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/libcc1/libcc1plugin.cc b/libcc1/libcc1plugin.cc
+index 12ab5a57c8d..fff9bfab18b 100644
+--- a/libcc1/libcc1plugin.cc
++++ b/libcc1/libcc1plugin.cc
+@@ -17,6 +17,7 @@
+    along with GCC; see the file COPYING3.  If not see
+    <http://www.gnu.org/licenses/>.  */
+ 
++#include <sched.h>
+ #include <cc1plugin-config.h>
+ 
+ #undef PACKAGE_NAME
+diff --git a/libcc1/libcp1plugin.cc b/libcc1/libcp1plugin.cc
+index 83dab7f58b1..0b83ce7a09d 100644
+--- a/libcc1/libcp1plugin.cc
++++ b/libcc1/libcp1plugin.cc
+@@ -18,6 +18,7 @@
+    along with GCC; see the file COPYING3.  If not see
+    <http://www.gnu.org/licenses/>.  */
+ 
++#include <sched.h>
+ #include <cc1plugin-config.h>
+ 
+ #undef PACKAGE_NAME

+ 0 - 54
recipes-devtools/gcc/gcc/0025-RISC-V-costs-support-shift-and-add-in-strength-reduc.patch

@@ -1,54 +0,0 @@
-From a545eb2c28726d0a574a7c6953a809362f6237e6 Mon Sep 17 00:00:00 2001
-From: "yilun.xie" <yilun.xie@starfivetech.com>
-Date: Tue, 23 Nov 2021 11:41:12 +0800
-Subject: [PATCH 25/26] RISC-V: costs: support shift-and-add in
- strength-reduction
-
----
- gcc/config/riscv/riscv.c | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
-diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
-index 8e22e36eaaf..f832fb44d7e 100644
---- a/gcc/config/riscv/riscv.c
-+++ b/gcc/config/riscv/riscv.c
-@@ -393,6 +393,15 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
-       /* Simply BSETI.  */
-       codes[0].code = UNKNOWN;
-       codes[0].value = value;
-+
-+      /* RISC-V sign-extends all 32bit values that life in a 32bit
-+	 register.  To avoid paradoxes, we thus need to use the
-+	 sign-extended (negative) representation for the value, if we
-+	 want to build 0x80000000 in SImode.  This will then expand
-+	 to an ADDI/LI instruction.  */
-+      if (mode == SImode && value == 0x80000000)
-+	    codes[0].value = -2147483648;
-+
-       return 1;
-     }
- 
-@@ -1998,6 +2007,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
- 	  *total = COSTS_N_INSNS (1);
- 	  return true;
- 	}
-+    /* Before strength-reduction, the shNadd can be expressed as the addition
-+	 of a multiplication with a power-of-two.  If this case is not handled,
-+	 the strength-reduction in expmed.c will calculate an inflated cost. */
-+      if (TARGET_ZBA
-+	  && ((!TARGET_64BIT && (mode == SImode)) ||
-+	      (TARGET_64BIT && (mode == DImode)))
-+	  && (GET_CODE (XEXP (x, 0)) == MULT)
-+	  && REG_P (XEXP (XEXP (x, 0), 0))
-+	  && CONST_INT_P (XEXP (XEXP (x, 0), 1))
-+	  && IN_RANGE (pow2p_hwi (INTVAL (XEXP (XEXP (x, 0), 1))), 1, 3))
-+	{
-+	  *total = COSTS_N_INSNS (1);
-+	  return true;
-+	}
-       /* shNadd.uw pattern for zba.
- 	 [(set (match_operand:DI 0 "register_operand" "=r")
- 	       (plus:DI
--- 
-2.33.1
-

+ 0 - 134
recipes-devtools/gcc/gcc/0026-Fix-various-_FOR_BUILD-and-related-variables.patch

@@ -1,134 +0,0 @@
-From cd5db101e3c4e72248f988a67ce28be8e24f66d4 Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Mon, 7 Dec 2015 23:42:45 +0000
-Subject: [PATCH] Fix various _FOR_BUILD and related variables
-
-When doing a FOR_BUILD thing, you have to override CFLAGS with
-CFLAGS_FOR_BUILD. And if you use C++, you also have to override
-CXXFLAGS with CXXFLAGS_FOR_BUILD.
-Without this, when building for mingw, you end up trying to use
-the mingw headers for a host build.
-
-The same goes for other variables as well, such as CPPFLAGS,
-CPP, and GMPINC.
-
-Upstream-Status: Pending
-
-Signed-off-by: Peter Seebach <peter.seebach@windriver.com>
-Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
----
- Makefile.in      | 6 ++++++
- Makefile.tpl     | 5 +++++
- gcc/Makefile.in  | 2 +-
- gcc/configure    | 2 +-
- gcc/configure.ac | 2 +-
- 5 files changed, 14 insertions(+), 3 deletions(-)
-
-diff --git a/Makefile.in b/Makefile.in
-index af19589fa95..d0116a23e1a 100644
---- a/Makefile.in
-+++ b/Makefile.in
-@@ -152,6 +152,7 @@ BUILD_EXPORTS = \
- 	CPP="$(CC_FOR_BUILD) -E"; export CPP; \
- 	CFLAGS="$(CFLAGS_FOR_BUILD)"; export CFLAGS; \
- 	CONFIG_SHELL="$(SHELL)"; export CONFIG_SHELL; \
-+	CPPFLAGS="$(CPPFLAGS_FOR_BUILD)"; export CPPFLAGS; \
- 	CXX="$(CXX_FOR_BUILD)"; export CXX; \
- 	CXXFLAGS="$(CXXFLAGS_FOR_BUILD)"; export CXXFLAGS; \
- 	GFORTRAN="$(GFORTRAN_FOR_BUILD)"; export GFORTRAN; \
-@@ -171,6 +172,9 @@ BUILD_EXPORTS = \
- # built for the build system to override those in BASE_FLAGS_TO_PASS.
- EXTRA_BUILD_FLAGS = \
- 	CFLAGS="$(CFLAGS_FOR_BUILD)" \
-+	CXXFLAGS="$(CXXFLAGS_FOR_BUILD)" \
-+	CPP="$(CC_FOR_BUILD) -E" \
-+	CPPFLAGS="$(CPPFLAGS_FOR_BUILD)" \
- 	LDFLAGS="$(LDFLAGS_FOR_BUILD)"
- 
- # This is the list of directories to built for the host system.
-@@ -188,6 +192,7 @@ HOST_SUBDIR = @host_subdir@
- HOST_EXPORTS = \
- 	$(BASE_EXPORTS) \
- 	CC="$(CC)"; export CC; \
-+	CPP="$(CC) -E"; export CPP; \
- 	ADA_CFLAGS="$(ADA_CFLAGS)"; export ADA_CFLAGS; \
- 	CFLAGS="$(CFLAGS)"; export CFLAGS; \
- 	CONFIG_SHELL="$(SHELL)"; export CONFIG_SHELL; \
-@@ -776,6 +781,7 @@ BASE_FLAGS_TO_PASS = \
- 	"CC_FOR_BUILD=$(CC_FOR_BUILD)" \
- 	"CFLAGS_FOR_BUILD=$(CFLAGS_FOR_BUILD)" \
- 	"CXX_FOR_BUILD=$(CXX_FOR_BUILD)" \
-+	"CXXFLAGS_FOR_BUILD=$(CXXFLAGS_FOR_BUILD)" \
- 	"EXPECT=$(EXPECT)" \
- 	"FLEX=$(FLEX)" \
- 	"INSTALL=$(INSTALL)" \
-diff --git a/Makefile.tpl b/Makefile.tpl
-index 6e0337fb48f..4fcac93d3d8 100644
---- a/Makefile.tpl
-+++ b/Makefile.tpl
-@@ -154,6 +154,7 @@ BUILD_EXPORTS = \
- 	CC="$(CC_FOR_BUILD)"; export CC; \
- 	CFLAGS="$(CFLAGS_FOR_BUILD)"; export CFLAGS; \
- 	CONFIG_SHELL="$(SHELL)"; export CONFIG_SHELL; \
-+	CPPFLAGS="$(CPPFLAGS_FOR_BUILD)"; export CPPFLAGS; \
- 	CXX="$(CXX_FOR_BUILD)"; export CXX; \
- 	CXXFLAGS="$(CXXFLAGS_FOR_BUILD)"; export CXXFLAGS; \
- 	GFORTRAN="$(GFORTRAN_FOR_BUILD)"; export GFORTRAN; \
-@@ -173,6 +174,9 @@ BUILD_EXPORTS = \
- # built for the build system to override those in BASE_FLAGS_TO_PASS.
- EXTRA_BUILD_FLAGS = \
- 	CFLAGS="$(CFLAGS_FOR_BUILD)" \
-+	CXXFLAGS="$(CXXFLAGS_FOR_BUILD)" \
-+	CPP="$(CC_FOR_BUILD) -E" \
-+	CPPFLAGS="$(CPPFLAGS_FOR_BUILD)" \
- 	LDFLAGS="$(LDFLAGS_FOR_BUILD)"
- 
- # This is the list of directories to built for the host system.
-@@ -190,6 +194,7 @@ HOST_SUBDIR = @host_subdir@
- HOST_EXPORTS = \
- 	$(BASE_EXPORTS) \
- 	CC="$(CC)"; export CC; \
-+	CPP="$(CC) -E"; export CPP; \
- 	ADA_CFLAGS="$(ADA_CFLAGS)"; export ADA_CFLAGS; \
- 	CFLAGS="$(CFLAGS)"; export CFLAGS; \
- 	CONFIG_SHELL="$(SHELL)"; export CONFIG_SHELL; \
-diff --git a/gcc/Makefile.in b/gcc/Makefile.in
-index 9b17d120aa1..3053d05903c 100644
---- a/gcc/Makefile.in
-+++ b/gcc/Makefile.in
-@@ -820,7 +820,7 @@ BUILD_LDFLAGS=@BUILD_LDFLAGS@
- BUILD_NO_PIE_FLAG = @BUILD_NO_PIE_FLAG@
- BUILD_LDFLAGS += $(BUILD_NO_PIE_FLAG)
- BUILD_CPPFLAGS= -I. -I$(@D) -I$(srcdir) -I$(srcdir)/$(@D) \
--		-I$(srcdir)/../include @INCINTL@ $(CPPINC) $(CPPFLAGS)
-+		-I$(srcdir)/../include @INCINTL@ $(CPPINC) $(CPPFLAGS_FOR_BUILD)
- 
- # Actual name to use when installing a native compiler.
- GCC_INSTALL_NAME := $(shell echo gcc|sed '$(program_transform_name)')
-diff --git a/gcc/configure b/gcc/configure
-index e663052cad2..b0906aa3e96 100755
---- a/gcc/configure
-+++ b/gcc/configure
-@@ -12699,7 +12699,7 @@ else
- 	CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \
- 	CXX="${CXX_FOR_BUILD}" CXXFLAGS="${CXXFLAGS_FOR_BUILD}" \
- 	LD="${LD_FOR_BUILD}" LDFLAGS="${LDFLAGS_FOR_BUILD}" \
--	GMPINC="" CPPFLAGS="${CPPFLAGS} -DGENERATOR_FILE" \
-+	GMPINC="" CPPFLAGS="${CPPFLAGS_FOR_BUILD} -DGENERATOR_FILE" \
- 	${realsrcdir}/configure \
- 		--enable-languages=${enable_languages-all} \
- 		${enable_obsolete+--enable-obsolete="$enable_obsolete"} \
-diff --git a/gcc/configure.ac b/gcc/configure.ac
-index 2b84875b028..bfbd8946e8a 100644
---- a/gcc/configure.ac
-+++ b/gcc/configure.ac
-@@ -2023,7 +2023,7 @@ else
- 	CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \
- 	CXX="${CXX_FOR_BUILD}" CXXFLAGS="${CXXFLAGS_FOR_BUILD}" \
- 	LD="${LD_FOR_BUILD}" LDFLAGS="${LDFLAGS_FOR_BUILD}" \
--	GMPINC="" CPPFLAGS="${CPPFLAGS} -DGENERATOR_FILE" \
-+	GMPINC="" CPPFLAGS="${CPPFLAGS_FOR_BUILD} -DGENERATOR_FILE" \
- 	${realsrcdir}/configure \
- 		--enable-languages=${enable_languages-all} \
- 		${enable_obsolete+--enable-obsolete="$enable_obsolete"} \

+ 0 - 35
recipes-devtools/gcc/gcc/0026-RISC-V-bitmanip-fix-constant-loading-for-1ULL-31-in-.patch

@@ -1,35 +0,0 @@
-From 4ecb7207eb15ac1a955cd6333d24bf7eecd33213 Mon Sep 17 00:00:00 2001
-From: "yilun.xie" <yilun.xie@starfivetech.com>
-Date: Tue, 23 Nov 2021 13:55:44 +0800
-Subject: [PATCH 26/26] RISC-V: bitmanip: fix constant-loading for (1ULL << 31)
- in DImode
-
----
- gcc/config/riscv/riscv.h | 11 ++++-------
- 1 file changed, 4 insertions(+), 7 deletions(-)
-
-diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
-index ff6729aedac..27ecc4830b2 100644
---- a/gcc/config/riscv/riscv.h
-+++ b/gcc/config/riscv/riscv.h
-@@ -521,13 +521,10 @@ enum reg_class
-   (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH)	\
-    || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
- 
--/* If this is a single bit mask, then we can load it with bseti.  But this
--   is not useful for any of the low 31 bits because we can use addi or lui
--   to load them.  It is wrong for loading SImode 0x80000000 on rv64 because it
--   needs to be sign-extended.  So we restrict this to the upper 32-bits
--   only.  */
--#define SINGLE_BIT_MASK_OPERAND(VALUE) \
--  (pow2p_hwi (VALUE) && (ctz_hwi (VALUE) >= 32))
-+/* If this is a single bit mask, then we can load it with bseti.  Special
-+   handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */
-+#define SINGLE_BIT_MASK_OPERAND(VALUE)					\
-+  (pow2p_hwi (VALUE))
- 
- /* Stack layout; function entry, exit and calling.  */
- 
--- 
-2.33.1
-

+ 92 - 0
recipes-devtools/gcc/gcc/0026-rust-recursion-limit.patch

@@ -0,0 +1,92 @@
+From 9234cdca6ee88badfc00297e72f13dac4e540c79 Mon Sep 17 00:00:00 2001
+From: Nick Clifton <nickc@redhat.com>
+Date: Fri, 1 Jul 2022 15:58:52 +0100
+Subject: [PATCH] Add a recursion limit to the demangle_const function in the
+ Rust demangler.
+
+libiberty/
+	PR demangler/105039
+	* rust-demangle.c (demangle_const): Add recursion limit.
+
+Upstream-Status: Backport [https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=9234cdca6ee88badfc00297e72f13dac4e540c79]
+---
+ libiberty/rust-demangle.c | 29 ++++++++++++++++++++---------
+ 1 file changed, 20 insertions(+), 9 deletions(-)
+
+diff --git a/libiberty/rust-demangle.c b/libiberty/rust-demangle.c
+index bb58d900e27..36afcfae278 100644
+--- a/libiberty/rust-demangle.c
++++ b/libiberty/rust-demangle.c
+@@ -126,7 +126,7 @@ parse_integer_62 (struct rust_demangler *rdm)
+     return 0;
+ 
+   x = 0;
+-  while (!eat (rdm, '_'))
++  while (!eat (rdm, '_') && !rdm->errored)
+     {
+       c = next (rdm);
+       x *= 62;
+@@ -1148,6 +1148,15 @@ demangle_const (struct rust_demangler *rdm)
+   if (rdm->errored)
+     return;
+ 
++  if (rdm->recursion != RUST_NO_RECURSION_LIMIT)
++    {
++      ++ rdm->recursion;
++      if (rdm->recursion > RUST_MAX_RECURSION_COUNT)
++	/* FIXME: There ought to be a way to report
++	   that the recursion limit has been reached.  */
++	goto fail_return;
++    }
++
+   if (eat (rdm, 'B'))
+     {
+       backref = parse_integer_62 (rdm);
+@@ -1158,7 +1167,7 @@ demangle_const (struct rust_demangler *rdm)
+           demangle_const (rdm);
+           rdm->next = old_next;
+         }
+-      return;
++      goto pass_return;
+     }
+ 
+   ty_tag = next (rdm);
+@@ -1167,7 +1176,7 @@ demangle_const (struct rust_demangler *rdm)
+     /* Placeholder. */
+     case 'p':
+       PRINT ("_");
+-      return;
++      goto pass_return;
+ 
+     /* Unsigned integer types. */
+     case 'h':
+@@ -1200,18 +1209,20 @@ demangle_const (struct rust_demangler *rdm)
+       break;
+ 
+     default:
+-      rdm->errored = 1;
+-      return;
++      goto fail_return;
+     }
+ 
+-  if (rdm->errored)
+-    return;
+-
+-  if (rdm->verbose)
++  if (!rdm->errored && rdm->verbose)
+     {
+       PRINT (": ");
+       PRINT (basic_type (ty_tag));
+     }
++
++ fail_return:
++  rdm->errored = 1;
++ pass_return:
++  if (rdm->recursion != RUST_NO_RECURSION_LIMIT)
++    -- rdm->recursion;
+ }
+ 
+ static void
+-- 
+2.31.1
+

+ 0 - 25
recipes-devtools/gcc/gcc/0027-nios2-Define-MUSL_DYNAMIC_LINKER.patch

@@ -1,25 +0,0 @@
-From 9bbce1b5a10caf636eee137e5a229e5434a6c8f5 Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Tue, 2 Feb 2016 10:26:10 -0800
-Subject: [PATCH] nios2: Define MUSL_DYNAMIC_LINKER
-
-Upstream-Status: Pending
-
-Signed-off-by: Marek Vasut <marex@denx.de>
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
----
- gcc/config/nios2/linux.h | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/gcc/config/nios2/linux.h b/gcc/config/nios2/linux.h
-index 08edf1521f6..15696d86241 100644
---- a/gcc/config/nios2/linux.h
-+++ b/gcc/config/nios2/linux.h
-@@ -30,6 +30,7 @@
- #define CPP_SPEC "%{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}"
- 
- #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-nios2.so.1"
-+#define MUSL_DYNAMIC_LINKER  "/lib/ld-musl-nios2.so.1"
- 
- #undef LINK_SPEC
- #define LINK_SPEC LINK_SPEC_ENDIAN \

+ 0 - 53
recipes-devtools/gcc/gcc/0028-define-__riscv_vector-macro.patch

@@ -1,53 +0,0 @@
-From 730b8fa4b7f04a53ce20e48ff205f638dc9a6ae4 Mon Sep 17 00:00:00 2001
-From: "max.ma" <max.ma@starfivetech.com>
-Date: Sun, 26 Dec 2021 21:28:53 -0800
-Subject: [PATCH 28/32] define __riscv_vector macro
-
----
- gcc/common/config/riscv/riscv-common.c | 1 +
- gcc/config/riscv/riscv-c.c             | 3 +++
- gcc/config/riscv/riscv.opt             | 2 ++
- 3 files changed, 6 insertions(+)
-
-diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
-index 0927554d506..ce0664a6d08 100644
---- a/gcc/common/config/riscv/riscv-common.c
-+++ b/gcc/common/config/riscv/riscv-common.c
-@@ -908,6 +908,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
-   {"f", &gcc_options::x_target_flags, MASK_HARD_FLOAT},
-   {"d", &gcc_options::x_target_flags, MASK_DOUBLE_FLOAT},
-   {"c", &gcc_options::x_target_flags, MASK_RVC},
-+  {"v", &gcc_options::x_target_flags, MASK_VECTOR},
- 
-   {"zicsr",    &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
-   {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
-diff --git a/gcc/config/riscv/riscv-c.c b/gcc/config/riscv/riscv-c.c
-index efd4a61ea29..44fbeaeb4b5 100644
---- a/gcc/config/riscv/riscv-c.c
-+++ b/gcc/config/riscv/riscv-c.c
-@@ -54,6 +54,9 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
-   if (TARGET_DIV && TARGET_MUL)
-     builtin_define ("__riscv_muldiv");
- 
-+  if (TARGET_VECTOR)
-+    builtin_define ("__riscv_vector");
-+
-   builtin_define_with_int_value ("__riscv_xlen", UNITS_PER_WORD * 8);
-   if (TARGET_HARD_FLOAT)
-     builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
-diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
-index 7f7e1c4f50b..3b7d5b591e6 100644
---- a/gcc/config/riscv/riscv.opt
-+++ b/gcc/config/riscv/riscv.opt
-@@ -146,6 +146,8 @@ Mask(RVC)
- 
- Mask(RVE)
- 
-+Mask(VECTOR)
-+
- mriscv-attribute
- Target Var(riscv_emit_attribute_p) Init(-1)
- Emit RISC-V ELF attribute.
--- 
-2.33.1
-

Some files were not shown because too many files changed in this diff