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dubhe: qemu: Update for V extension support

Update qemu version and qemu configs to prepare for the V extension patch.

Signed-off-by: Jun Yuan Tan <junyuan.tan@starfivetech.com>
Jun Yuan Tan 2 年之前
父節點
當前提交
11a023368b

+ 2 - 2
conf/machine/starfive-dubhe.conf

@@ -17,7 +17,7 @@ IMAGE_CLASSES += " qemuboot "
 QB_MACHINE = "-machine virt"
 QB_DEFAULT_KERNEL = "Image-initramfs-starfive-dubhe.bin"
 QB_DEFAULT_BIOS = "fw_payload.bin"
-QB_CPU = "-cpu rv64,x-h=true,x-b=true"
+QB_CPU = "-cpu rv64,x-h=true,x-b=true,x-v=true"
 QB_DEFAULT_FSTYPE = "cpio.gz"
 SERIAL_CONSOLES = "115200;ttyS0"
 QB_SYSTEM_NAME = "qemu-system-riscv64"
@@ -40,7 +40,7 @@ PREFERRED_PROVIDER_virtual/kernel ?= "linux-starfive-dev"
 RISCV_SBI_PLAT = "generic"
 RISCV_SBI_PAYLOAD = "Image-initramfs-starfive-dubhe.bin"
 
-QEMU_EXTRAOPTIONS:riscv64 = " -cpu rv64,x-b=true"
+QEMU_EXTRAOPTIONS:riscv64 = " -cpu rv64,x-b=true,x-v=true"
 
 GLIBCVERSION = "2.35"
 #

+ 1 - 0
recipes-devtools/qemu/qemu-native_6.0.0.bbappend

@@ -109,4 +109,5 @@ SRC_URI += "file://0001-softfloat-add-APIs-to-handle-alternative-sNaN-propag.pat
            file://0107-target-riscv-Force-to-set-mstatus_hs.-SD-VS-bits-in-.patch \
            file://0001-merge-riscv-bitmapip-b0p94-version.patch \
            file://0002-Add-four-cache-csr-instruction.patch \
+           file://0003-Fix-cache-instruction-bug.patch \
            "

+ 1 - 0
recipes-devtools/qemu/qemu-system-native_6.0.0.bbappend

@@ -109,4 +109,5 @@ SRC_URI += "file://0001-softfloat-add-APIs-to-handle-alternative-sNaN-propag.pat
            file://0107-target-riscv-Force-to-set-mstatus_hs.-SD-VS-bits-in-.patch \
            file://0001-merge-riscv-bitmapip-b0p94-version.patch \
            file://0002-Add-four-cache-csr-instruction.patch \
+           file://0003-Fix-cache-instruction-bug.patch \
            "

+ 53 - 0
recipes-devtools/qemu/qemu/0003-Fix-cache-instruction-bug.patch

@@ -0,0 +1,53 @@
+From 71ddb2f0d01d62eeef3578126656470742dd4160 Mon Sep 17 00:00:00 2001
+From: "yilun.xie" <yilun.xie@starfivetech.com>
+Date: Tue, 22 Mar 2022 02:26:39 -0700
+Subject: [PATCH 3/3] Fix cache instruction bug
+
+---
+ target/riscv/insn_trans/trans_rvi.c.inc | 18 +++++++++++-------
+ 1 file changed, 11 insertions(+), 7 deletions(-)
+
+diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
+index bdabeaf376..1784bbbfb8 100644
+--- a/target/riscv/insn_trans/trans_rvi.c.inc
++++ b/target/riscv/insn_trans/trans_rvi.c.inc
+@@ -532,24 +532,28 @@ static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
+ 
+ static bool trans_cflush_d_l1(DisasContext *ctx, arg_cflush_d_l1 *a)
+ {
+-    gen_helper_cflush_d_l1(cpu_gpr[a->rs1]);
++    if(a->rs1 != 0)
++        gen_helper_cflush_d_l1(cpu_gpr[a->rs1]);
+     return true;
+ }
+ 
+-static bool trans_cdiscard_d_l1(DisasContext *ctx, arg_cflush_d_l1 *a)
++static bool trans_cdiscard_d_l1(DisasContext *ctx, arg_cdiscard_d_l1 *a)
+ {
+-    gen_helper_cdiscard_d_l1(cpu_gpr[a->rs1]);
++    if(a->rs1 != 0)
++        gen_helper_cdiscard_d_l1(cpu_gpr[a->rs1]);
+     return true;
+ }
+ 
+-static bool trans_cflush_d_l2(DisasContext *ctx, arg_cflush_d_l1 *a)
++static bool trans_cflush_d_l2(DisasContext *ctx, arg_cflush_d_l2 *a)
+ {
+-    gen_helper_cflush_d_l2(cpu_gpr[a->rs1]);
++    if(a->rs1 != 0)
++        gen_helper_cflush_d_l2(cpu_gpr[a->rs1]);
+     return true;
+ }
+ 
+-static bool trans_cdiscard_d_l2(DisasContext *ctx, arg_cflush_d_l1 *a)
++static bool trans_cdiscard_d_l2(DisasContext *ctx, arg_cdiscard_d_l2 *a)
+ {
+-    gen_helper_cdiscard_d_l2(cpu_gpr[a->rs1]);
++    if(a->rs1 != 0)
++        gen_helper_cdiscard_d_l2(cpu_gpr[a->rs1]);
+     return true;
+ }
+\ No newline at end of file
+-- 
+2.33.1
+

+ 1 - 0
recipes-devtools/qemu/qemu_6.0.0.bbappend

@@ -109,4 +109,5 @@ SRC_URI += "file://0001-softfloat-add-APIs-to-handle-alternative-sNaN-propag.pat
            file://0107-target-riscv-Force-to-set-mstatus_hs.-SD-VS-bits-in-.patch \
            file://0001-merge-riscv-bitmapip-b0p94-version.patch \
            file://0002-Add-four-cache-csr-instruction.patch \
+           file://0003-Fix-cache-instruction-bug.patch \
            "