From d55020858c4dfa834deb17f3682e3adae9287ac3 Mon Sep 17 00:00:00 2001
From: "yilun.xie" <yilun.xie@starfivetech.com>
Date: Tue, 22 Mar 2022 02:26:39 -0700
Subject: [PATCH 2/6] Fix cache instruction bug

---
 target/riscv/insn_trans/trans_rvi.c.inc | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 4d8f2668de..0152aba689 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -1103,24 +1103,28 @@ static bool trans_csrrci(DisasContext *ctx, arg_csrrci * a)
 
 static bool trans_cflush_d_l1(DisasContext *ctx, arg_cflush_d_l1 *a)
 {
-    gen_helper_cflush_d_l1(cpu_gpr[a->rs1]);
+    if(a->rs1 != 0)
+        gen_helper_cflush_d_l1(cpu_gpr[a->rs1]);
     return true;
 }
 
-static bool trans_cdiscard_d_l1(DisasContext *ctx, arg_cflush_d_l1 *a)
+static bool trans_cdiscard_d_l1(DisasContext *ctx, arg_cdiscard_d_l1 *a)
 {
-    gen_helper_cdiscard_d_l1(cpu_gpr[a->rs1]);
+    if(a->rs1 != 0)
+        gen_helper_cdiscard_d_l1(cpu_gpr[a->rs1]);
     return true;
 }
 
-static bool trans_cflush_d_l2(DisasContext *ctx, arg_cflush_d_l1 *a)
+static bool trans_cflush_d_l2(DisasContext *ctx, arg_cflush_d_l2 *a)
 {
-    gen_helper_cflush_d_l2(cpu_gpr[a->rs1]);
+    if(a->rs1 != 0)
+        gen_helper_cflush_d_l2(cpu_gpr[a->rs1]);
     return true;
 }
 
-static bool trans_cdiscard_d_l2(DisasContext *ctx, arg_cflush_d_l1 *a)
+static bool trans_cdiscard_d_l2(DisasContext *ctx, arg_cdiscard_d_l2 *a)
 {
-    gen_helper_cdiscard_d_l2(cpu_gpr[a->rs1]);
+    if(a->rs1 != 0)
+        gen_helper_cdiscard_d_l2(cpu_gpr[a->rs1]);
     return true;
 }
\ No newline at end of file
-- 
2.25.1

