wave5.c 185 KB

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  1. /*
  2. * Copyright (c) 2019, Chips&Media
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions are met:
  7. *
  8. * 1. Redistributions of source code must retain the above copyright notice, this
  9. * list of conditions and the following disclaimer.
  10. * 2. Redistributions in binary form must reproduce the above copyright notice,
  11. * this list of conditions and the following disclaimer in the documentation
  12. * and/or other materials provided with the distribution.
  13. *
  14. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  15. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  16. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  17. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
  18. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  19. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  20. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  21. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  23. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24. */
  25. #include "product.h"
  26. #include "wave/wave5.h"
  27. #include "vpuerror.h"
  28. #include "wave/wave5_regdefine.h"
  29. #include "misc/debug.h"
  30. Uint32 Wave5VpuIsInit(Uint32 coreIdx)
  31. {
  32. Uint32 pc;
  33. pc = (Uint32)VpuReadReg(coreIdx, W5_VCPU_CUR_PC);
  34. return pc;
  35. }
  36. Int32 Wave5VpuIsBusy(Uint32 coreIdx)
  37. {
  38. return VpuReadReg(coreIdx, W5_VPU_BUSY_STATUS);
  39. }
  40. Int32 WaveVpuGetProductId(Uint32 coreIdx)
  41. {
  42. Uint32 productId = PRODUCT_ID_NONE;
  43. Uint32 val;
  44. if (coreIdx >= MAX_NUM_VPU_CORE)
  45. return PRODUCT_ID_NONE;
  46. val = VpuReadReg(coreIdx, W5_PRODUCT_NUMBER);
  47. switch (val) {
  48. case WAVE512_CODE: productId = PRODUCT_ID_512; break;
  49. case WAVE515_CODE: productId = PRODUCT_ID_515; break;
  50. case WAVE521_CODE: productId = PRODUCT_ID_521; break;
  51. case WAVE521C_CODE: productId = PRODUCT_ID_521; break;
  52. case WAVE511_CODE: productId = PRODUCT_ID_511; break;
  53. case WAVE521C_DUAL_CODE: productId = PRODUCT_ID_521; break;
  54. case WAVE517_CODE: productId = PRODUCT_ID_517; break;
  55. default:
  56. VLOG(ERR, "Check productId(%d)\n", val);
  57. break;
  58. }
  59. return productId;
  60. }
  61. void Wave5BitIssueCommand(CodecInst* instance, Uint32 cmd)
  62. {
  63. Uint32 instanceIndex = 0;
  64. Uint32 codecMode = 0;
  65. Uint32 coreIdx;
  66. if (instance == NULL) {
  67. return ;
  68. }
  69. instanceIndex = instance->instIndex;
  70. codecMode = instance->codecMode;
  71. coreIdx = instance->coreIdx;
  72. VpuWriteReg(coreIdx, W5_CMD_INSTANCE_INFO, (codecMode<<16)|(instanceIndex&0xffff));
  73. VpuWriteReg(coreIdx, W5_VPU_BUSY_STATUS, 1);
  74. VpuWriteReg(coreIdx, W5_COMMAND, cmd);
  75. if ((instance != NULL && instance->loggingEnable))
  76. vdi_log(coreIdx, cmd, 1);
  77. VpuWriteReg(coreIdx, W5_VPU_HOST_INT_REQ, 1);
  78. return;
  79. }
  80. static RetCode SendQuery(CodecInst* instance, QUERY_OPT queryOpt)
  81. {
  82. // Send QUERY cmd
  83. VpuWriteReg(instance->coreIdx, W5_QUERY_OPTION, queryOpt);
  84. VpuWriteReg(instance->coreIdx, W5_VPU_BUSY_STATUS, 1);
  85. Wave5BitIssueCommand(instance, W5_QUERY);
  86. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  87. if (instance->loggingEnable)
  88. vdi_log(instance->coreIdx, W5_QUERY, 2);
  89. return RETCODE_VPU_RESPONSE_TIMEOUT;
  90. }
  91. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE)
  92. return RETCODE_FAILURE;
  93. return RETCODE_SUCCESS;
  94. }
  95. RetCode Wave5VpuEncGiveCommand(CodecInst *pCodecInst, CodecCommand cmd, void *param)
  96. {
  97. RetCode ret = RETCODE_SUCCESS;
  98. switch (cmd) {
  99. default:
  100. ret = RETCODE_NOT_SUPPORTED_FEATURE;
  101. }
  102. return ret;
  103. }
  104. static RetCode SetupWave5Properties(Uint32 coreIdx)
  105. {
  106. VpuAttr* pAttr = &g_VpuCoreAttributes[coreIdx];
  107. Uint32 regVal;
  108. Uint8* str;
  109. RetCode ret = RETCODE_SUCCESS;
  110. VpuWriteReg(coreIdx, W5_QUERY_OPTION, GET_VPU_INFO);
  111. VpuWriteReg(coreIdx, W5_VPU_BUSY_STATUS, 1);
  112. VpuWriteReg(coreIdx, W5_COMMAND, W5_QUERY);
  113. VpuWriteReg(coreIdx, W5_VPU_HOST_INT_REQ, 1);
  114. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  115. return RETCODE_VPU_RESPONSE_TIMEOUT;
  116. }
  117. if (VpuReadReg(coreIdx, W5_RET_SUCCESS) == FALSE) {
  118. ret = RETCODE_QUERY_FAILURE;
  119. }
  120. else {
  121. regVal = VpuReadReg(coreIdx, W5_RET_PRODUCT_NAME);
  122. str = (Uint8*)&regVal;
  123. pAttr->productName[0] = str[3];
  124. pAttr->productName[1] = str[2];
  125. pAttr->productName[2] = str[1];
  126. pAttr->productName[3] = str[0];
  127. pAttr->productName[4] = 0;
  128. pAttr->productId = WaveVpuGetProductId(coreIdx);
  129. pAttr->productVersion = VpuReadReg(coreIdx, W5_RET_PRODUCT_VERSION);
  130. pAttr->fwVersion = VpuReadReg(coreIdx, W5_RET_FW_VERSION);
  131. pAttr->customerId = VpuReadReg(coreIdx, W5_RET_CUSTOMER_ID);
  132. pAttr->hwConfigDef0 = VpuReadReg(coreIdx, W5_RET_STD_DEF0);
  133. pAttr->hwConfigDef1 = VpuReadReg(coreIdx, W5_RET_STD_DEF1);
  134. pAttr->hwConfigFeature = VpuReadReg(coreIdx, W5_RET_CONF_FEATURE);
  135. pAttr->hwConfigDate = VpuReadReg(coreIdx, W5_RET_CONF_DATE);
  136. pAttr->hwConfigRev = VpuReadReg(coreIdx, W5_RET_CONF_REVISION);
  137. pAttr->hwConfigType = VpuReadReg(coreIdx, W5_RET_CONF_TYPE);
  138. pAttr->supportHEVC10bitEnc = (pAttr->hwConfigFeature>>3)&1;
  139. if ( pAttr->hwConfigRev > 167455 ) {//20190321
  140. pAttr->supportAVC10bitEnc = (pAttr->hwConfigFeature>>11)&1;
  141. } else {
  142. pAttr->supportAVC10bitEnc = pAttr->supportHEVC10bitEnc;
  143. }
  144. pAttr->supportGDIHW = TRUE;
  145. pAttr->supportDecoders = (1<<STD_HEVC);
  146. if (pAttr->productId == PRODUCT_ID_512) {
  147. pAttr->supportDecoders |= (1<<STD_VP9);
  148. }
  149. if (pAttr->productId == PRODUCT_ID_515) {
  150. pAttr->supportDecoders |= (1<<STD_VP9);
  151. pAttr->supportDecoders |= (1<<STD_AVS2);
  152. }
  153. pAttr->supportEncoders = 0;
  154. if (pAttr->productId == PRODUCT_ID_521) {
  155. pAttr->supportDecoders |= (1<<STD_AVC);
  156. pAttr->supportEncoders = (1<<STD_HEVC);
  157. pAttr->supportEncoders |= (1<<STD_AVC);
  158. pAttr->supportBackbone = TRUE;
  159. }
  160. if (pAttr->productId == PRODUCT_ID_511) {
  161. pAttr->supportDecoders |= (1<<STD_AVC);
  162. if ( (pAttr->hwConfigDef0>>16)&1 ) {
  163. pAttr->supportBackbone = TRUE;
  164. }
  165. }
  166. if (pAttr->productId == PRODUCT_ID_517) {
  167. pAttr->supportDecoders |= (1 << STD_VP9);
  168. pAttr->supportDecoders |= (1 << STD_AVS2);
  169. pAttr->supportDecoders |= (1 << STD_AVC);
  170. pAttr->supportDecoders |= (1 << STD_AV1);
  171. pAttr->supportBackbone = TRUE;
  172. }
  173. pAttr->support2AlignScaler = (BOOL)((pAttr->hwConfigDef0>>23)&0x01);
  174. pAttr->supportVcoreBackbone = (BOOL)((pAttr->hwConfigDef0>>22)&0x01);
  175. pAttr->supportCommandQueue = TRUE;
  176. pAttr->supportFBCBWOptimization = (BOOL)((pAttr->hwConfigDef1>>15)&0x01);
  177. pAttr->supportNewTimer = (BOOL)((pAttr->hwConfigDef1>>27)&0x01);
  178. pAttr->supportWTL = TRUE;
  179. pAttr->supportDualCore = (BOOL)((pAttr->hwConfigDef1>>26)&0x01);
  180. pAttr->supportTiled2Linear = FALSE;
  181. pAttr->supportMapTypes = FALSE;
  182. pAttr->support128bitBus = TRUE;
  183. pAttr->supportThumbnailMode = TRUE;
  184. pAttr->supportEndianMask = (Uint32)((1<<VDI_LITTLE_ENDIAN) | (1<<VDI_BIG_ENDIAN) | (1<<VDI_32BIT_LITTLE_ENDIAN) | (1<<VDI_32BIT_BIG_ENDIAN) | (0xffffUL<<16));
  185. pAttr->supportBitstreamMode = (1<<BS_MODE_INTERRUPT) | (1<<BS_MODE_PIC_END);
  186. pAttr->framebufferCacheType = FramebufCacheNone;
  187. pAttr->bitstreamBufferMargin = 0;
  188. pAttr->maxNumVcores = MAX_NUM_VCORE;
  189. pAttr->numberOfMemProtectRgns = 10;
  190. }
  191. return ret;
  192. }
  193. RetCode Wave5VpuGetVersion(Uint32 coreIdx, Uint32* versionInfo, Uint32* revision)
  194. {
  195. Uint32 regVal;
  196. VpuWriteReg(coreIdx, W5_QUERY_OPTION, GET_VPU_INFO);
  197. VpuWriteReg(coreIdx, W5_VPU_BUSY_STATUS, 1);
  198. VpuWriteReg(coreIdx, W5_COMMAND, W5_QUERY);
  199. VpuWriteReg(coreIdx, W5_VPU_HOST_INT_REQ, 1);
  200. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  201. VLOG(ERR, "Wave5VpuGetVersion timeout\n");
  202. return RETCODE_VPU_RESPONSE_TIMEOUT;
  203. }
  204. if (VpuReadReg(coreIdx, W5_RET_SUCCESS) == FALSE) {
  205. VLOG(ERR, "Wave5VpuGetVersion FALSE\n");
  206. return RETCODE_QUERY_FAILURE;
  207. }
  208. regVal = VpuReadReg(coreIdx, W5_RET_FW_VERSION);
  209. if (versionInfo != NULL) {
  210. *versionInfo = 0;
  211. }
  212. if (revision != NULL) {
  213. *revision = regVal;
  214. }
  215. return RETCODE_SUCCESS;
  216. }
  217. RetCode Wave5VpuInit(Uint32 coreIdx, void* firmware, Uint32 size)
  218. {
  219. vpu_buffer_t vb;
  220. PhysicalAddress codeBase, tempBase;
  221. Uint32 codeSize, tempSize;
  222. Uint32 i, regVal, remapSize;
  223. Uint32 hwOption = 0;
  224. RetCode ret = RETCODE_SUCCESS;
  225. vdi_get_common_memory(coreIdx, &vb);
  226. codeBase = vb.phys_addr;
  227. /* ALIGN TO 4KB */
  228. codeSize = (WAVE5_MAX_CODE_BUF_SIZE&~0xfff);
  229. if (codeSize < size*2) {
  230. return RETCODE_INSUFFICIENT_RESOURCE;
  231. }
  232. tempBase = vb.phys_addr + WAVE5_TEMPBUF_OFFSET;
  233. tempSize = WAVE5_TEMPBUF_SIZE;
  234. VLOG(INFO, "\nVPU INIT Start!!!\n");
  235. VpuWriteMem(coreIdx, codeBase, (unsigned char*)firmware, size*2, VDI_128BIT_LITTLE_ENDIAN);
  236. vdi_set_bit_firmware_to_pm(coreIdx, (Uint16*)firmware);
  237. regVal = 0;
  238. VpuWriteReg(coreIdx, W5_PO_CONF, regVal);
  239. /* clear registers */
  240. for (i=W5_CMD_REG_BASE; i<W5_CMD_REG_END; i+=4)
  241. {
  242. #if defined(SUPPORT_SW_UART) || defined(SUPPORT_SW_UART_V2)
  243. if (i == W5_SW_UART_STATUS)
  244. continue;
  245. #endif
  246. VpuWriteReg(coreIdx, i, 0x00);
  247. }
  248. /* remap page size */
  249. remapSize = (codeSize >> 12) &0x1ff;
  250. regVal = 0x80000000 | (WAVE5_UPPER_PROC_AXI_ID<<20) | (0 << 16) | (W5_REMAP_CODE_INDEX<<12) | (1<<11) | remapSize;
  251. VpuWriteReg(coreIdx, W5_VPU_REMAP_CTRL, regVal);
  252. VpuWriteReg(coreIdx, W5_VPU_REMAP_VADDR, 0x00000000); /* DO NOT CHANGE! */
  253. VpuWriteReg(coreIdx, W5_VPU_REMAP_PADDR, codeBase);
  254. VpuWriteReg(coreIdx, W5_ADDR_CODE_BASE, codeBase);
  255. VpuWriteReg(coreIdx, W5_CODE_SIZE, codeSize);
  256. VpuWriteReg(coreIdx, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID<<4) | 0);
  257. VpuWriteReg(coreIdx, W5_ADDR_TEMP_BASE, tempBase);
  258. VpuWriteReg(coreIdx, W5_TEMP_SIZE, tempSize);
  259. VpuWriteReg(coreIdx, W5_TIMEOUT_CNT, 0xffff);
  260. VpuWriteReg(coreIdx, W5_HW_OPTION, hwOption);
  261. /* Interrupt */
  262. // encoder
  263. regVal = (1<<INT_WAVE5_ENC_SET_PARAM);
  264. regVal |= (1<<INT_WAVE5_ENC_PIC);
  265. regVal |= (1<<INT_WAVE5_BSBUF_FULL);
  266. regVal |= (1<<INT_WAVE5_ENC_LOW_LATENCY);
  267. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  268. regVal |= (1<<INT_WAVE5_ENC_SRC_RELEASE);
  269. #endif
  270. // decoder
  271. regVal |= (1<<INT_WAVE5_INIT_SEQ);
  272. regVal |= (1<<INT_WAVE5_DEC_PIC);
  273. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  274. VpuWriteReg(coreIdx, W5_VPU_VINT_ENABLE, regVal);
  275. regVal = VpuReadReg(coreIdx, W5_VPU_RET_VPU_CONFIG0);
  276. if (((regVal>>16)&1) == 1) {
  277. regVal = ((WAVE5_PROC_AXI_ID << 28) |
  278. (WAVE5_PRP_AXI_ID << 24) |
  279. (WAVE5_FBD_Y_AXI_ID << 20) |
  280. (WAVE5_FBC_Y_AXI_ID << 16) |
  281. (WAVE5_FBD_C_AXI_ID << 12) |
  282. (WAVE5_FBC_C_AXI_ID << 8) |
  283. (WAVE5_PRI_AXI_ID << 4) |
  284. (WAVE5_SEC_AXI_ID << 0));
  285. vdi_fio_write_register(coreIdx, W5_BACKBONE_PROG_AXI_ID, regVal);
  286. }
  287. if (vdi_get_sram_memory(coreIdx, &vb) < 0) // get SRAM base/size
  288. return RETCODE_INSUFFICIENT_RESOURCE;
  289. VpuWriteReg(coreIdx, W5_ADDR_SEC_AXI, vb.phys_addr);
  290. VpuWriteReg(coreIdx, W5_SEC_AXI_SIZE, vb.size);
  291. VpuWriteReg(coreIdx, W5_VPU_BUSY_STATUS, 1);
  292. VpuWriteReg(coreIdx, W5_COMMAND, W5_INIT_VPU);
  293. VpuWriteReg(coreIdx, W5_VPU_REMAP_CORE_START, 1);
  294. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  295. VLOG(ERR, "VPU init(W5_VPU_REMAP_CORE_START) timeout\n");
  296. return RETCODE_VPU_RESPONSE_TIMEOUT;
  297. }
  298. regVal = VpuReadReg(coreIdx, W5_RET_SUCCESS);
  299. if (regVal == 0) {
  300. Uint32 reasonCode = VpuReadReg(coreIdx, W5_RET_FAIL_REASON);
  301. VLOG(ERR, "VPU init(W5_RET_SUCCESS) failed(%d) REASON CODE(%08x)\n", regVal, reasonCode);
  302. return RETCODE_FAILURE;
  303. }
  304. ret = SetupWave5Properties(coreIdx);
  305. return ret;
  306. }
  307. RetCode Wave5VpuBuildUpDecParam(CodecInst* instance, DecOpenParam* param)
  308. {
  309. RetCode ret = RETCODE_SUCCESS;
  310. DecInfo* pDecInfo;
  311. VpuAttr* pAttr = &g_VpuCoreAttributes[instance->coreIdx];
  312. Uint32 bsEndian = 0;
  313. vpu_buffer_t vb;
  314. pDecInfo = VPU_HANDLE_TO_DECINFO(instance);
  315. pDecInfo->streamRdPtrRegAddr = W5_RET_DEC_BS_RD_PTR;
  316. pDecInfo->streamWrPtrRegAddr = W5_BS_WR_PTR;
  317. pDecInfo->frameDisplayFlagRegAddr = W5_RET_DEC_DISP_IDC;
  318. pDecInfo->currentPC = W5_VCPU_CUR_PC;
  319. pDecInfo->busyFlagAddr = W5_VPU_BUSY_STATUS;
  320. if ((pAttr->supportDecoders&(1<<param->bitstreamFormat)) == 0)
  321. return RETCODE_NOT_SUPPORTED_FEATURE;
  322. switch (param->bitstreamFormat) {
  323. case STD_HEVC:
  324. pDecInfo->seqChangeMask = SEQ_CHANGE_ENABLE_ALL_HEVC;
  325. break;
  326. case STD_VP9:
  327. pDecInfo->seqChangeMask = SEQ_CHANGE_ENABLE_ALL_VP9;
  328. break;
  329. case STD_AVS2:
  330. pDecInfo->seqChangeMask = SEQ_CHANGE_ENABLE_ALL_AVS2;
  331. break;
  332. case STD_AVC:
  333. pDecInfo->seqChangeMask = SEQ_CHANGE_ENABLE_ALL_AVC;
  334. break;
  335. case STD_SVAC:
  336. pDecInfo->seqChangeMask = SEQ_CHANGE_ENABLE_ALL_SVAC;
  337. break;
  338. case STD_AV1:
  339. pDecInfo->seqChangeMask = SEQ_CHANGE_ENABLE_ALL_AV1;
  340. break;
  341. default:
  342. return RETCODE_NOT_SUPPORTED_FEATURE;
  343. }
  344. pDecInfo->scaleWidth = 0;
  345. pDecInfo->scaleHeight = 0;
  346. if (param->vbWork.size > 0) {
  347. pDecInfo->vbWork = param->vbWork;
  348. pDecInfo->workBufferAllocExt = TRUE;
  349. vdi_attach_dma_memory(instance->coreIdx, &param->vbWork);
  350. }
  351. else {
  352. if (instance->productId == PRODUCT_ID_512) {
  353. pDecInfo->vbWork.size = WAVE512DEC_WORKBUF_SIZE;
  354. }
  355. else if (instance->productId == PRODUCT_ID_515) {
  356. pDecInfo->vbWork.size = WAVE515DEC_WORKBUF_SIZE;
  357. }
  358. else if (instance->productId == PRODUCT_ID_517) {
  359. pDecInfo->vbWork.size = (Uint32)WAVE521DEC_WORKBUF_SIZE; // FIX ME
  360. }
  361. else if (instance->productId == PRODUCT_ID_521) {
  362. pDecInfo->vbWork.size = (Uint32)WAVE521DEC_WORKBUF_SIZE; // FIX ME
  363. }
  364. else if (instance->productId == PRODUCT_ID_511) {
  365. pDecInfo->vbWork.size = (Uint32)WAVE521DEC_WORKBUF_SIZE; // FIX ME
  366. }
  367. pDecInfo->workBufferAllocExt = FALSE;
  368. APIDPRINT("ALLOC MEM - WORK\n");
  369. if (vdi_allocate_dma_memory(instance->coreIdx, &pDecInfo->vbWork, DEC_WORK, instance->instIndex) < 0) {
  370. pDecInfo->vbWork.base = 0;
  371. pDecInfo->vbWork.phys_addr = 0;
  372. pDecInfo->vbWork.size = 0;
  373. pDecInfo->vbWork.virt_addr = 0;
  374. return RETCODE_INSUFFICIENT_RESOURCE;
  375. }
  376. }
  377. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_VCORE_INFO, 1);
  378. VpuWriteReg(instance->coreIdx, W5_CMD_NUM_CQ_DEPTH_M1, COMMAND_QUEUE_DEPTH -1 );
  379. vdi_get_common_memory(instance->coreIdx, &vb);
  380. pDecInfo->vbTemp.phys_addr = vb.phys_addr + WAVE5_TEMPBUF_OFFSET;
  381. pDecInfo->vbTemp.size = WAVE5_TEMPBUF_SIZE;
  382. vdi_clear_memory(instance->coreIdx, pDecInfo->vbWork.phys_addr, pDecInfo->vbWork.size, 0);
  383. VpuWriteReg(instance->coreIdx, W5_ADDR_WORK_BASE, pDecInfo->vbWork.phys_addr);
  384. VpuWriteReg(instance->coreIdx, W5_WORK_SIZE, pDecInfo->vbWork.size);
  385. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_BS_START_ADDR, pDecInfo->streamBufStartAddr);
  386. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_BS_SIZE, pDecInfo->streamBufSize);
  387. bsEndian = vdi_convert_endian(instance->coreIdx, param->streamEndian);
  388. /* NOTE: When endian mode is 0, SDMA reads MSB first */
  389. bsEndian = (~bsEndian&VDI_128BIT_ENDIAN_MASK);
  390. VpuWriteReg(instance->coreIdx, W5_CMD_BS_PARAM, bsEndian);
  391. VpuWriteReg(instance->coreIdx, W5_VPU_BUSY_STATUS, 1);
  392. VpuWriteReg(instance->coreIdx, W5_RET_SUCCESS, 0); //for debug
  393. Wave5BitIssueCommand(instance, W5_CREATE_INSTANCE);
  394. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) { // Check QUEUE_DONE
  395. if (instance->loggingEnable)
  396. vdi_log(instance->coreIdx, W5_CREATE_INSTANCE, 2);
  397. vdi_free_dma_memory(instance->coreIdx, &pDecInfo->vbWork, DEC_WORK, instance->instIndex);
  398. return RETCODE_VPU_RESPONSE_TIMEOUT;
  399. }
  400. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE) { // FAILED for adding into VCPU QUEUE
  401. vdi_free_dma_memory(instance->coreIdx, &pDecInfo->vbWork, DEC_WORK, instance->instIndex);
  402. ret = RETCODE_FAILURE;
  403. }
  404. pDecInfo->productCode = VpuReadReg(instance->coreIdx, W5_PRODUCT_NUMBER);
  405. return ret;
  406. }
  407. RetCode Wave5VpuDecInitSeq(CodecInst* instance)
  408. {
  409. RetCode ret = RETCODE_SUCCESS;
  410. DecInfo* pDecInfo;
  411. Uint32 cmdOption = INIT_SEQ_NORMAL, bsOption;
  412. Uint32 regVal;
  413. if (instance == NULL)
  414. return RETCODE_INVALID_PARAM;
  415. pDecInfo = VPU_HANDLE_TO_DECINFO(instance);
  416. if (pDecInfo->thumbnailMode)
  417. cmdOption = INIT_SEQ_W_THUMBNAIL;
  418. /* Set attributes of bitstream buffer controller */
  419. bsOption = 0;
  420. switch (pDecInfo->openParam.bitstreamMode) {
  421. case BS_MODE_INTERRUPT:
  422. if(pDecInfo->seqInitEscape == TRUE)
  423. bsOption = BSOPTION_ENABLE_EXPLICIT_END;
  424. break;
  425. case BS_MODE_PIC_END:
  426. bsOption = BSOPTION_ENABLE_EXPLICIT_END;
  427. break;
  428. default:
  429. return RETCODE_INVALID_PARAM;
  430. }
  431. if (pDecInfo->streamEndflag == 1)
  432. bsOption = 3;
  433. VpuWriteReg(instance->coreIdx, W5_BS_RD_PTR, pDecInfo->streamRdPtr);
  434. VpuWriteReg(instance->coreIdx, W5_BS_WR_PTR, pDecInfo->streamWrPtr);
  435. if (instance->codecMode == W_AV1_DEC) {
  436. bsOption |= ((pDecInfo->openParam.av1Format) << 2);
  437. }
  438. VpuWriteReg(instance->coreIdx, W5_BS_OPTION, (1UL<<31) | bsOption);
  439. VpuWriteReg(instance->coreIdx, W5_COMMAND_OPTION, cmdOption);
  440. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_USER_MASK, pDecInfo->userDataEnable);
  441. Wave5BitIssueCommand(instance, W5_INIT_SEQ);
  442. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) { // Check QUEUE_DONE
  443. if (instance->loggingEnable)
  444. vdi_log(instance->coreIdx, W5_INIT_SEQ, 2);
  445. return RETCODE_VPU_RESPONSE_TIMEOUT;
  446. }
  447. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_STATUS);
  448. pDecInfo->instanceQueueCount = (regVal>>16)&0xff;
  449. pDecInfo->reportQueueCount = (regVal & 0xffff);
  450. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE) { // FAILED for adding a command into VCPU QUEUE
  451. regVal = VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON);
  452. if (regVal != WAVE5_QUEUEING_FAIL)
  453. VLOG(ERR, "FAIL_REASON = 0x%x\n", regVal);
  454. if ( regVal == WAVE5_QUEUEING_FAIL)
  455. ret = RETCODE_QUEUEING_FAILURE;
  456. else if (regVal == WAVE5_SYSERR_ACCESS_VIOLATION_HW)
  457. ret = RETCODE_MEMORY_ACCESS_VIOLATION;
  458. else if (regVal == WAVE5_SYSERR_WATCHDOG_TIMEOUT)
  459. ret = RETCODE_VPU_RESPONSE_TIMEOUT;
  460. else if (regVal == WAVE5_SYSERR_DEC_VLC_BUF_FULL)
  461. ret = RETCODE_VLC_BUF_FULL;
  462. else if (regVal == WAVE5_ERROR_FW_FATAL)
  463. ret = RETCODE_ERROR_FW_FATAL;
  464. else
  465. ret = RETCODE_FAILURE;
  466. }
  467. return ret;
  468. }
  469. static void GetDecSequenceResult(CodecInst* instance, DecInitialInfo* info)
  470. {
  471. DecInfo* pDecInfo = &instance->CodecInfo->decInfo;
  472. Uint32 regVal;
  473. Uint32 profileCompatibilityFlag;
  474. Uint32 left, right, top, bottom;
  475. Uint32 progressiveFlag, interlacedFlag, outputBitDepthMinus8, frameMbsOnlyFlag = 0;
  476. pDecInfo->streamRdPtr = info->rdPtr = ProductVpuDecGetRdPtr(instance);
  477. pDecInfo->frameDisplayFlag = VpuReadReg(instance->coreIdx, W5_RET_DEC_DISP_IDC);
  478. /*regVal = VpuReadReg(instance->coreIdx, W4_BS_OPTION);
  479. pDecInfo->streamEndflag = (regVal&0x02) ? TRUE : FALSE;*/
  480. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_PIC_SIZE);
  481. info->picWidth = ( (regVal >> 16) & 0xffff );
  482. info->picHeight = ( regVal & 0xffff );
  483. info->minFrameBufferCount = VpuReadReg(instance->coreIdx, W5_RET_DEC_NUM_REQUIRED_FB);
  484. info->frameBufDelay = VpuReadReg(instance->coreIdx, W5_RET_DEC_NUM_REORDER_DELAY);
  485. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_CROP_LEFT_RIGHT);
  486. left = (regVal >> 16) & 0xffff;
  487. right = regVal & 0xffff;
  488. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_CROP_TOP_BOTTOM);
  489. top = (regVal >> 16) & 0xffff;
  490. bottom = regVal & 0xffff;
  491. info->picCropRect.left = left;
  492. info->picCropRect.right = info->picWidth - right;
  493. info->picCropRect.top = top;
  494. info->picCropRect.bottom = info->picHeight - bottom;
  495. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_SEQ_PARAM);
  496. info->level = regVal & 0xff;
  497. interlacedFlag = (regVal>>10) & 0x1;
  498. progressiveFlag = (regVal>>11) & 0x1;
  499. profileCompatibilityFlag = (regVal>>12)&0xff;
  500. info->profile = (regVal >> 24)&0x1f;
  501. info->tier = (regVal >> 29)&0x01;
  502. outputBitDepthMinus8 = (regVal >> 30)&0x03;
  503. if (instance->codecMode == W_AVC_DEC) {
  504. frameMbsOnlyFlag = (regVal >> 8) & 0x01;
  505. info->constraint_set_flag[0] = (regVal >> 16) & 0x01;
  506. info->constraint_set_flag[1] = (regVal >> 17) & 0x01;
  507. info->constraint_set_flag[2] = (regVal >> 18) & 0x01;
  508. info->constraint_set_flag[3] = (regVal >> 19) & 0x01;
  509. }
  510. info->fRateNumerator = VpuReadReg(instance->coreIdx, W5_RET_DEC_FRAME_RATE_NR);
  511. info->fRateDenominator = VpuReadReg(instance->coreIdx, W5_RET_DEC_FRAME_RATE_DR);
  512. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_COLOR_SAMPLE_INFO);
  513. info->lumaBitdepth = (regVal>>0)&0x0f;
  514. info->chromaBitdepth = (regVal>>4)&0x0f;
  515. info->chromaFormatIDC = (regVal>>8)&0x0f;
  516. info->aspectRateInfo = (regVal>>16)&0xff;
  517. info->isExtSAR = (info->aspectRateInfo == 255 ? TRUE : FALSE);
  518. if (info->isExtSAR == TRUE) {
  519. info->aspectRateInfo = VpuReadReg(instance->coreIdx, W5_RET_DEC_ASPECT_RATIO); /* [0:15] - vertical size, [16:31] - horizontal size */
  520. }
  521. info->bitRate = VpuReadReg(instance->coreIdx, W5_RET_DEC_BIT_RATE);
  522. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_SUB_LAYER_INFO);
  523. info->maxSubLayers = (regVal>>8)&0xff;
  524. if ( instance->codecMode == W_HEVC_DEC ) {
  525. /* Guessing Profile */
  526. if (info->profile == 0) {
  527. if ((profileCompatibilityFlag&0x06) == 0x06) info->profile = 1; /* Main profile */
  528. else if ((profileCompatibilityFlag&0x04) == 0x04) info->profile = 2; /* Main10 profile */
  529. else if ((profileCompatibilityFlag&0x08) == 0x08) info->profile = 3; /* Main Still Picture profile */
  530. else info->profile = 1; /* For old version HM */
  531. }
  532. if (progressiveFlag == 1 && interlacedFlag == 0)
  533. info->interlace = 0;
  534. else
  535. info->interlace = 1;
  536. }
  537. else if (instance->codecMode == W_AVS2_DEC) {
  538. if ((info->lumaBitdepth == 10) && (outputBitDepthMinus8 == 2))
  539. info->outputBitDepth = 10;
  540. else
  541. info->outputBitDepth = 8;
  542. if (progressiveFlag == 1)
  543. info->interlace = 0;
  544. else
  545. info->interlace = 1;
  546. }
  547. else if (instance->codecMode == W_AVC_DEC) {
  548. if (frameMbsOnlyFlag == 1)
  549. info->interlace = 0;
  550. else
  551. info->interlace = 0; // AVC on WAVE5 can't support interlace
  552. }
  553. info->vlcBufSize = VpuReadReg(instance->coreIdx, W5_RET_VLC_BUF_SIZE);
  554. info->paramBufSize = VpuReadReg(instance->coreIdx, W5_RET_PARAM_BUF_SIZE);
  555. pDecInfo->vlcBufSize = info->vlcBufSize;
  556. pDecInfo->paramBufSize = info->paramBufSize;
  557. return;
  558. }
  559. RetCode Wave5VpuDecGetSeqInfo(CodecInst* instance, DecInitialInfo* info)
  560. {
  561. RetCode ret = RETCODE_SUCCESS;
  562. Uint32 regVal, i;
  563. DecInfo* pDecInfo;
  564. pDecInfo = VPU_HANDLE_TO_DECINFO(instance);
  565. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_ADDR_REPORT_BASE, pDecInfo->userDataBufAddr);
  566. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_REPORT_SIZE, pDecInfo->userDataBufSize);
  567. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_REPORT_PARAM, VPU_USER_DATA_ENDIAN&VDI_128BIT_ENDIAN_MASK);
  568. // Send QUERY cmd
  569. ret = SendQuery(instance, GET_RESULT);
  570. if (ret != RETCODE_SUCCESS) {
  571. regVal = VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON);
  572. if (regVal != WAVE5_QUEUEING_FAIL)
  573. VLOG(ERR, "FAIL_REASON = 0x%x\n", regVal);
  574. if (regVal == WAVE5_RESULT_NOT_READY)
  575. return RETCODE_REPORT_NOT_READY;
  576. else if (regVal == WAVE5_SYSERR_ACCESS_VIOLATION_HW)
  577. return RETCODE_MEMORY_ACCESS_VIOLATION;
  578. else if (regVal == WAVE5_SYSERR_WATCHDOG_TIMEOUT)
  579. return RETCODE_VPU_RESPONSE_TIMEOUT;
  580. else if (regVal == WAVE5_SYSERR_DEC_VLC_BUF_FULL)
  581. return RETCODE_VLC_BUF_FULL;
  582. else if (regVal == WAVE5_ERROR_FW_FATAL)
  583. return RETCODE_ERROR_FW_FATAL;
  584. else
  585. return RETCODE_QUERY_FAILURE;
  586. }
  587. if (instance->loggingEnable)
  588. vdi_log(instance->coreIdx, W5_INIT_SEQ, 0);
  589. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_STATUS);
  590. pDecInfo->instanceQueueCount = (regVal>>16)&0xff;
  591. pDecInfo->reportQueueCount = (regVal & 0xffff);
  592. if (VpuReadReg(instance->coreIdx, W5_RET_DEC_DECODING_SUCCESS) != 1) {
  593. #ifdef SUPPORT_SW_UART
  594. ret = RETCODE_FAILURE;
  595. #else
  596. info->seqInitErrReason = VpuReadReg(instance->coreIdx, W5_RET_DEC_ERR_INFO);
  597. ret = RETCODE_FAILURE;
  598. #endif
  599. }
  600. else {
  601. #ifdef SUPPORT_SW_UART
  602. info->warnInfo = 0;
  603. #else
  604. info->warnInfo = VpuReadReg(instance->coreIdx, W5_RET_DEC_WARN_INFO);
  605. #endif
  606. }
  607. // Get Sequence Info
  608. info->userDataSize = 0;
  609. info->userDataNum = 0;
  610. info->userDataBufFull= 0;
  611. info->userDataHeader = VpuReadReg(instance->coreIdx, W5_RET_DEC_USERDATA_IDC);
  612. if (info->userDataHeader != 0) {
  613. regVal = info->userDataHeader;
  614. for (i=0; i<32; i++) {
  615. if (i == 1) {
  616. if (regVal & (1<<i))
  617. info->userDataBufFull = 1;
  618. }
  619. else {
  620. if (regVal & (1<<i))
  621. info->userDataNum++;
  622. }
  623. }
  624. info->userDataSize = pDecInfo->userDataBufSize;
  625. }
  626. if (instance->codecMode == W_SVAC_DEC) {
  627. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_SUB_LAYER_INFO);
  628. info->spatialSvcEnable = (regVal>>16)&0x1;
  629. info->spatialSvcMode = (regVal>>17)&0x1;
  630. }
  631. GetDecSequenceResult(instance, info);
  632. return ret;
  633. }
  634. RetCode Wave5VpuDecRegisterFramebuffer(CodecInst* inst, FrameBuffer* fbArr, TiledMapType mapType, Uint32 count)
  635. {
  636. RetCode ret = RETCODE_SUCCESS;
  637. DecInfo* pDecInfo = &inst->CodecInfo->decInfo;
  638. DecInitialInfo* sequenceInfo = &inst->CodecInfo->decInfo.initialInfo;
  639. Int32 q, j, i, remain, idx, svcBLbaseIdx;
  640. Uint32 mvCount;
  641. Uint32 k;
  642. Int32 coreIdx, startNo, endNo;
  643. Uint32 regVal, cbcrInterleave, nv21, picSize;
  644. Uint32 endian, yuvFormat = 0;
  645. Uint32 addrY, addrCb, addrCr;
  646. Uint32 mvColSize, fbcYTblSize, fbcCTblSize;
  647. vpu_buffer_t vbBuffer;
  648. Uint32 stride;
  649. Uint32 colorFormat = 0;
  650. Uint32 outputFormat = 0;
  651. Uint32 axiID;
  652. Uint32 initPicWidth = 0, initPicHeight = 0;
  653. Uint32 scalerFlag = 0;
  654. Uint32 pixelOrder=1;
  655. Uint32 bwbFlag = (mapType == LINEAR_FRAME_MAP) ? 1 : 0;
  656. coreIdx = inst->coreIdx;
  657. axiID = pDecInfo->openParam.virtAxiID;
  658. cbcrInterleave = pDecInfo->openParam.cbcrInterleave;
  659. nv21 = pDecInfo->openParam.nv21;
  660. mvColSize = fbcYTblSize = fbcCTblSize = 0;
  661. initPicWidth = pDecInfo->initialInfo.picWidth;
  662. initPicHeight = pDecInfo->initialInfo.picHeight;
  663. if (inst->codecMode == W_SVAC_DEC && mapType == COMPRESSED_FRAME_MAP_SVAC_SVC_BL) {
  664. initPicWidth = pDecInfo->initialInfo.picWidth>>1; // BL size is half as EL
  665. initPicHeight = pDecInfo->initialInfo.picHeight>>1;
  666. svcBLbaseIdx = count;
  667. }
  668. else
  669. svcBLbaseIdx = 0;
  670. if (mapType >= COMPRESSED_FRAME_MAP) {
  671. cbcrInterleave = 0;
  672. nv21 = 0;
  673. switch (inst->codecMode) {
  674. case W_HEVC_DEC: mvColSize = WAVE5_DEC_HEVC_MVCOL_BUF_SIZE(initPicWidth, initPicHeight); break;
  675. case W_VP9_DEC: mvColSize = WAVE5_DEC_VP9_MVCOL_BUF_SIZE(initPicWidth, initPicHeight); break;
  676. case W_AVS2_DEC: mvColSize = WAVE5_DEC_AVS2_MVCOL_BUF_SIZE(initPicWidth, initPicHeight); break;
  677. case W_SVAC_DEC: mvColSize = 0; break; // case of SVAC, mvColbuffer included in WorkBuffer due to sequence change.
  678. case W_AVC_DEC: mvColSize = WAVE5_DEC_AVC_MVCOL_BUF_SIZE(initPicWidth, initPicHeight); break;
  679. case W_AV1_DEC: mvColSize = WAVE5_DEC_AV1_MVCOL_BUF_SIZE(initPicWidth, initPicHeight); break;
  680. default:
  681. return RETCODE_NOT_SUPPORTED_FEATURE;
  682. }
  683. mvColSize = VPU_ALIGN16(mvColSize);
  684. vbBuffer.phys_addr = 0;
  685. if (inst->codecMode == W_HEVC_DEC || inst->codecMode == W_AVS2_DEC || inst->codecMode == W_VP9_DEC || inst->codecMode == W_AVC_DEC || inst->codecMode == W_AV1_DEC) {
  686. vbBuffer.size = ((mvColSize+4095)&~4095)+4096; /* 4096 is a margin */
  687. mvCount = count;
  688. APIDPRINT("ALLOC MEM - MV\n");
  689. for (k=0 ; k<mvCount ; k++) {
  690. if ( pDecInfo->vbMV[k].size == 0) {
  691. if (vdi_allocate_dma_memory(inst->coreIdx, &vbBuffer, DEC_MV, inst->instIndex) < 0)
  692. return RETCODE_INSUFFICIENT_RESOURCE;
  693. pDecInfo->vbMV[k] = vbBuffer;
  694. }
  695. }
  696. }
  697. if (pDecInfo->productCode == WAVE521C_DUAL_CODE) {
  698. Uint32 bgs_width = (pDecInfo->initialInfo.lumaBitdepth >8 ? 256 : 512);
  699. Uint32 ot_bg_width = 1024;
  700. Uint32 frm_width = VPU_CEIL(initPicWidth, 16);
  701. Uint32 frm_height = VPU_CEIL(initPicHeight, 16);
  702. Uint32 comp_frm_width = VPU_CEIL(VPU_CEIL(frm_width , 16) + 16, 16); // valid_width = align(width, 16), comp_frm_width = align(valid_width+pad_x, 16)
  703. Uint32 ot_frm_width = VPU_CEIL(comp_frm_width, ot_bg_width); // 1024 = offset table BG width
  704. // sizeof_offset_table()
  705. Uint32 ot_bg_height = 32;
  706. Uint32 bgs_height = (1<<14) / bgs_width / (pDecInfo->initialInfo.lumaBitdepth >8 ? 2 : 1);
  707. Uint32 comp_frm_height = VPU_CEIL(VPU_CEIL(frm_height, 4) + 4, bgs_height);
  708. Uint32 ot_frm_height = VPU_CEIL(comp_frm_height, ot_bg_height);
  709. fbcYTblSize = (ot_frm_width/16) * (ot_frm_height/4) *2;
  710. }
  711. else {
  712. switch (inst->codecMode) {
  713. case W_HEVC_DEC: fbcYTblSize = WAVE5_FBC_LUMA_TABLE_SIZE(initPicWidth, initPicHeight); break;
  714. case W_VP9_DEC: fbcYTblSize = WAVE5_FBC_LUMA_TABLE_SIZE(VPU_ALIGN64(initPicWidth), VPU_ALIGN64(initPicHeight)); break;
  715. case W_AVS2_DEC: fbcYTblSize = WAVE5_FBC_LUMA_TABLE_SIZE(initPicWidth, initPicHeight); break;
  716. case W_SVAC_DEC: fbcYTblSize = WAVE5_FBC_LUMA_TABLE_SIZE(VPU_ALIGN128(initPicWidth), VPU_ALIGN128(initPicHeight)); break;
  717. case W_AVC_DEC: fbcYTblSize = WAVE5_FBC_LUMA_TABLE_SIZE(initPicWidth, initPicHeight); break;
  718. case W_AV1_DEC: fbcYTblSize = WAVE5_FBC_LUMA_TABLE_SIZE(VPU_ALIGN16(initPicWidth), VPU_ALIGN8(initPicHeight)); break;
  719. default:
  720. return RETCODE_NOT_SUPPORTED_FEATURE;
  721. }
  722. fbcYTblSize = VPU_ALIGN16(fbcYTblSize);
  723. }
  724. vbBuffer.phys_addr = 0;
  725. vbBuffer.size = ((fbcYTblSize+4095)&~4095)+4096;
  726. APIDPRINT("ALLOC MEM - FBC Y TBL\n");
  727. for (k=0 ; k<count ; k++) {
  728. if ( pDecInfo->vbFbcYTbl[k+svcBLbaseIdx].size == 0) {
  729. if (vdi_allocate_dma_memory(inst->coreIdx, &vbBuffer, DEC_FBCY_TBL, inst->instIndex) < 0)
  730. return RETCODE_INSUFFICIENT_RESOURCE;
  731. pDecInfo->vbFbcYTbl[k+svcBLbaseIdx] = vbBuffer;
  732. }
  733. }
  734. if (pDecInfo->productCode == WAVE521C_DUAL_CODE) {
  735. Uint32 bgs_width = (pDecInfo->initialInfo.chromaBitdepth >8 ? 256 : 512);
  736. Uint32 ot_bg_width = 1024;
  737. Uint32 frm_width = VPU_CEIL(initPicWidth, 16);
  738. Uint32 frm_height = VPU_CEIL(initPicHeight, 16);
  739. Uint32 comp_frm_width = VPU_CEIL(VPU_CEIL(frm_width/2 , 16) + 16, 16); // valid_width = align(width, 16), comp_frm_width = align(valid_width+pad_x, 16)
  740. Uint32 ot_frm_width = VPU_CEIL(comp_frm_width, ot_bg_width); // 1024 = offset table BG width
  741. // sizeof_offset_table()
  742. Uint32 ot_bg_height = 32;
  743. Uint32 bgs_height = (1<<14) / bgs_width / (pDecInfo->initialInfo.chromaBitdepth >8 ? 2 : 1);
  744. Uint32 comp_frm_height = VPU_CEIL(VPU_CEIL(frm_height, 4) + 4, bgs_height);
  745. Uint32 ot_frm_height = VPU_CEIL(comp_frm_height, ot_bg_height);
  746. fbcCTblSize = (ot_frm_width/16) * (ot_frm_height/4) *2;
  747. }
  748. else {
  749. switch (inst->codecMode) {
  750. case W_HEVC_DEC: fbcCTblSize = WAVE5_FBC_CHROMA_TABLE_SIZE(initPicWidth, initPicHeight); break;
  751. case W_VP9_DEC: fbcCTblSize = WAVE5_FBC_CHROMA_TABLE_SIZE(VPU_ALIGN64(initPicWidth), VPU_ALIGN64(initPicHeight)); break;
  752. case W_AVS2_DEC: fbcCTblSize = WAVE5_FBC_CHROMA_TABLE_SIZE(initPicWidth, initPicHeight); break;
  753. case W_SVAC_DEC: fbcCTblSize = WAVE5_FBC_CHROMA_TABLE_SIZE(VPU_ALIGN64(initPicWidth), VPU_ALIGN64(initPicHeight)); break;
  754. case W_AVC_DEC: fbcCTblSize = WAVE5_FBC_CHROMA_TABLE_SIZE(initPicWidth, initPicHeight); break;
  755. case W_AV1_DEC: fbcCTblSize = WAVE5_FBC_CHROMA_TABLE_SIZE(VPU_ALIGN16(initPicWidth), VPU_ALIGN8(initPicHeight)); break;
  756. default:
  757. return RETCODE_NOT_SUPPORTED_FEATURE;
  758. }
  759. fbcCTblSize = VPU_ALIGN16(fbcCTblSize);
  760. }
  761. vbBuffer.phys_addr = 0;
  762. vbBuffer.size = ((fbcCTblSize+4095)&~4095)+4096;
  763. APIDPRINT("ALLOC MEM - FBC C TBL\n");
  764. for (k=0 ; k<count ; k++) {
  765. if ( pDecInfo->vbFbcCTbl[k+svcBLbaseIdx].size == 0) {
  766. if (vdi_allocate_dma_memory(inst->coreIdx, &vbBuffer, DEC_FBCC_TBL, inst->instIndex) < 0)
  767. return RETCODE_INSUFFICIENT_RESOURCE;
  768. pDecInfo->vbFbcCTbl[k+svcBLbaseIdx] = vbBuffer;
  769. }
  770. }
  771. picSize = (initPicWidth<<16)|(initPicHeight);
  772. // Allocate TaskBuffer
  773. vbBuffer.size = (Uint32)((pDecInfo->vlcBufSize * VLC_BUF_NUM) + (pDecInfo->paramBufSize * COMMAND_QUEUE_DEPTH));
  774. vbBuffer.phys_addr = 0;
  775. if (vdi_allocate_dma_memory(inst->coreIdx, &vbBuffer, DEC_TASK, inst->instIndex) < 0)
  776. return RETCODE_INSUFFICIENT_RESOURCE;
  777. pDecInfo->vbTask = vbBuffer;
  778. VpuWriteReg(coreIdx, W5_CMD_SET_FB_ADDR_TASK_BUF, pDecInfo->vbTask.phys_addr);
  779. VpuWriteReg(coreIdx, W5_CMD_SET_FB_TASK_BUF_SIZE, vbBuffer.size);
  780. }
  781. else
  782. {
  783. picSize = (initPicWidth<<16)|(initPicHeight);
  784. if (pDecInfo->scalerEnable == TRUE) {
  785. picSize = (pDecInfo->scaleWidth << 16) | (pDecInfo->scaleHeight);
  786. }
  787. }
  788. endian = vdi_convert_endian(coreIdx, fbArr[0].endian);
  789. VpuWriteReg(coreIdx, W5_PIC_SIZE, picSize);
  790. yuvFormat = 0; /* YUV420 8bit */
  791. if (mapType == LINEAR_FRAME_MAP) {
  792. BOOL justified = WTL_RIGHT_JUSTIFIED;
  793. Uint32 formatNo = WTL_PIXEL_8BIT;
  794. switch (pDecInfo->wtlFormat) {
  795. case FORMAT_420_P10_16BIT_MSB:
  796. case FORMAT_422_P10_16BIT_MSB:
  797. justified = WTL_RIGHT_JUSTIFIED;
  798. formatNo = WTL_PIXEL_16BIT;
  799. break;
  800. case FORMAT_420_P10_16BIT_LSB:
  801. case FORMAT_422_P10_16BIT_LSB:
  802. justified = WTL_LEFT_JUSTIFIED;
  803. formatNo = WTL_PIXEL_16BIT;
  804. break;
  805. case FORMAT_420_P10_32BIT_MSB:
  806. case FORMAT_422_P10_32BIT_MSB:
  807. justified = WTL_RIGHT_JUSTIFIED;
  808. formatNo = WTL_PIXEL_32BIT;
  809. break;
  810. case FORMAT_420_P10_32BIT_LSB:
  811. case FORMAT_422_P10_32BIT_LSB:
  812. justified = WTL_LEFT_JUSTIFIED;
  813. formatNo = WTL_PIXEL_32BIT;
  814. break;
  815. default:
  816. break;
  817. }
  818. yuvFormat = justified<<2 | formatNo;
  819. }
  820. stride = fbArr[0].stride;
  821. if (mapType >= COMPRESSED_FRAME_MAP) {
  822. if ( pDecInfo->chFbcFrameIdx != -1 )
  823. stride = fbArr[pDecInfo->chFbcFrameIdx].stride;
  824. } else {
  825. if ( pDecInfo->chBwbFrameIdx != -1 )
  826. stride = fbArr[pDecInfo->chBwbFrameIdx].stride;
  827. }
  828. if (mapType == LINEAR_FRAME_MAP) {
  829. scalerFlag = pDecInfo->scalerEnable;
  830. switch (pDecInfo->wtlFormat) {
  831. case FORMAT_422:
  832. case FORMAT_422_P10_16BIT_MSB:
  833. case FORMAT_422_P10_16BIT_LSB:
  834. case FORMAT_422_P10_32BIT_MSB:
  835. case FORMAT_422_P10_32BIT_LSB:
  836. colorFormat = 1;
  837. outputFormat = 0;
  838. outputFormat |= (nv21 << 1);
  839. outputFormat |= (cbcrInterleave << 0);
  840. break;
  841. default:
  842. colorFormat = 0;
  843. outputFormat = 0;
  844. outputFormat |= (nv21 << 1);
  845. outputFormat |= (cbcrInterleave << 0);
  846. break;
  847. }
  848. }
  849. regVal =
  850. (scalerFlag << 29) |
  851. (bwbFlag << 28) |
  852. (axiID << 24) |
  853. (pixelOrder << 23) | /* PIXEL ORDER in 128bit. first pixel in low address */
  854. (yuvFormat << 20) |
  855. (colorFormat << 19) |
  856. (outputFormat << 16) |
  857. (stride);
  858. VpuWriteReg(coreIdx, W5_COMMON_PIC_INFO, regVal); //// 0x008012c0
  859. remain = count;
  860. q = (remain+7)/8;
  861. idx = 0;
  862. for (j=0; j<q; j++) {
  863. regVal = (endian<<16) | (j==q-1)<<4 | ((j==0)<<3);//lint !e514
  864. regVal |= (pDecInfo->openParam.bwOptimization<<26);
  865. regVal |= (pDecInfo->initialInfo.spatialSvcEnable == TRUE ) ? (mapType == COMPRESSED_FRAME_MAP_SVAC_SVC_BL ? 0 : 1<<27) : 0 ;
  866. regVal |= (pDecInfo->initialInfo.spatialSvcEnable<<28);
  867. VpuWriteReg(coreIdx, W5_SFB_OPTION, regVal);
  868. startNo = j*8;
  869. endNo = startNo + (remain>=8 ? 8 : remain) - 1;
  870. VpuWriteReg(coreIdx, W5_SET_FB_NUM, (startNo<<8)|endNo);
  871. for (i=0; i<8 && i<remain; i++) {
  872. if (mapType == LINEAR_FRAME_MAP && pDecInfo->openParam.cbcrOrder == CBCR_ORDER_REVERSED) {
  873. addrY = fbArr[i+startNo].bufY;
  874. addrCb = fbArr[i+startNo].bufCr;
  875. addrCr = fbArr[i+startNo].bufCb;
  876. }
  877. else {
  878. addrY = fbArr[i+startNo].bufY;
  879. addrCb = fbArr[i+startNo].bufCb;
  880. addrCr = fbArr[i+startNo].bufCr;
  881. }
  882. VpuWriteReg(coreIdx, W5_ADDR_LUMA_BASE0 + (i<<4), addrY);
  883. VpuWriteReg(coreIdx, W5_ADDR_CB_BASE0 + (i<<4), addrCb);
  884. APIDPRINT("REGISTER FB[%02d] Y(0x%08x), Cb(0x%08x) ", i, addrY, addrCb);
  885. if (mapType >= COMPRESSED_FRAME_MAP) {
  886. VpuWriteReg(coreIdx, W5_ADDR_FBC_Y_OFFSET0 + (i<<4), pDecInfo->vbFbcYTbl[idx+svcBLbaseIdx].phys_addr); /* Luma FBC offset table */
  887. VpuWriteReg(coreIdx, W5_ADDR_FBC_C_OFFSET0 + (i<<4), pDecInfo->vbFbcCTbl[idx+svcBLbaseIdx].phys_addr); /* Chroma FBC offset table */
  888. VpuWriteReg(coreIdx, W5_ADDR_MV_COL0 + (i<<2), pDecInfo->vbMV[idx+svcBLbaseIdx].phys_addr);
  889. APIDPRINT("Yo(0x%08x) Co(0x%08x), Mv(0x%08x)\n",
  890. pDecInfo->vbFbcYTbl[idx].phys_addr,
  891. pDecInfo->vbFbcCTbl[idx].phys_addr,
  892. pDecInfo->vbMV[idx].phys_addr);
  893. }
  894. else {
  895. VpuWriteReg(coreIdx, W5_ADDR_CR_BASE0 + (i<<4), addrCr);
  896. VpuWriteReg(coreIdx, W5_ADDR_FBC_C_OFFSET0 + (i<<4), 0);
  897. VpuWriteReg(coreIdx, W5_ADDR_MV_COL0 + (i<<2), 0);
  898. APIDPRINT("Cr(0x%08x)\n", addrCr);
  899. }
  900. idx++;
  901. }
  902. remain -= i;
  903. Wave5BitIssueCommand(inst, W5_SET_FB);
  904. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  905. return RETCODE_VPU_RESPONSE_TIMEOUT;
  906. }
  907. }
  908. regVal = VpuReadReg(coreIdx, W5_RET_SUCCESS);
  909. if (regVal == 0) {
  910. return RETCODE_FAILURE;
  911. }
  912. if (ConfigSecAXIWave(coreIdx, inst->codecMode,
  913. &pDecInfo->secAxiInfo, initPicWidth, initPicHeight,
  914. sequenceInfo->profile, sequenceInfo->level) == 0) {
  915. return RETCODE_INSUFFICIENT_RESOURCE;
  916. }
  917. return ret;
  918. }
  919. RetCode Wave5VpuDecUpdateFramebuffer(CodecInst* inst, FrameBuffer* fbcFb, FrameBuffer* linearFb, Int32 mvIndex, Int32 picWidth, Int32 picHeight)
  920. {
  921. RetCode ret = RETCODE_SUCCESS;
  922. DecInfo* pDecInfo = &inst->CodecInfo->decInfo;
  923. DecInitialInfo* sequenceInfo = &inst->CodecInfo->decInfo.initialInfo;
  924. Int8 fbcIndex, linearIndex;
  925. Uint32 coreIdx, regVal;
  926. Uint32 mvColSize, fbcYTblSize, fbcCTblSize;
  927. Uint32 linearStride, fbcStride;
  928. vpu_buffer_t* pvbMv = NULL;
  929. vpu_buffer_t* pvbFbcYOffset = NULL;
  930. vpu_buffer_t* pvbFbcCOffset = NULL;
  931. CodStd codec;
  932. unsigned long fbcYoffsetAddr = 0;
  933. unsigned long fbcCoffsetAddr = 0;
  934. coreIdx = inst->coreIdx;
  935. linearIndex = (linearFb == NULL) ? -1 : linearFb->myIndex - pDecInfo->numFbsForDecoding;
  936. fbcIndex = (fbcFb == NULL) ? -1 : fbcFb->myIndex;
  937. mvColSize = fbcYTblSize = fbcCTblSize = 0;
  938. codec = pDecInfo->openParam.bitstreamFormat;
  939. if (codec != STD_VP9) {
  940. return RETCODE_NOT_SUPPORTED_FEATURE;
  941. }
  942. mvColSize = WAVE5_DEC_VP9_MVCOL_BUF_SIZE(picWidth, picHeight);
  943. if ((fbcFb != NULL) && (fbcIndex >= 0)) {
  944. pDecInfo->frameBufPool[fbcIndex] = *fbcFb;
  945. }
  946. if ((linearFb != NULL) && (linearIndex >= 0)) {
  947. pDecInfo->frameBufPool[pDecInfo->numFbsForDecoding + linearIndex] = *linearFb;
  948. }
  949. if (mvIndex >= 0) {
  950. pvbMv = &pDecInfo->vbMV[mvIndex];
  951. vdi_free_dma_memory(inst->coreIdx, pvbMv, DEC_MV, inst->instIndex);
  952. pvbMv->size = ((mvColSize+4095)&~4095) + 4096;
  953. if (vdi_allocate_dma_memory(inst->coreIdx, pvbMv, DEC_MV, inst->instIndex) < 0) {
  954. return RETCODE_INSUFFICIENT_RESOURCE;
  955. }
  956. }
  957. /* Reallocate FBC offset tables */
  958. if (codec == STD_HEVC){
  959. fbcYTblSize = WAVE5_FBC_LUMA_TABLE_SIZE(picWidth, picHeight);
  960. }
  961. else if (codec == STD_VP9) {
  962. //VP9 Decoded size : 64 aligned.
  963. fbcYTblSize = WAVE5_FBC_LUMA_TABLE_SIZE(VPU_ALIGN64(picWidth), VPU_ALIGN64(picHeight));
  964. }
  965. else if (codec == STD_AVS2){
  966. fbcYTblSize = WAVE5_FBC_LUMA_TABLE_SIZE(picWidth, picHeight);
  967. }
  968. else if (codec == STD_AVC){
  969. fbcYTblSize = WAVE5_FBC_LUMA_TABLE_SIZE(picWidth, picHeight); // FIX ME
  970. }
  971. else if (codec == STD_AV1){
  972. fbcYTblSize = WAVE5_FBC_LUMA_TABLE_SIZE(VPU_ALIGN64(picWidth), VPU_ALIGN64(picHeight));
  973. }
  974. else {
  975. /* Unknown codec */
  976. return RETCODE_NOT_SUPPORTED_FEATURE;
  977. }
  978. if (fbcIndex >= 0) {
  979. pvbFbcYOffset = &pDecInfo->vbFbcYTbl[fbcIndex];
  980. vdi_free_dma_memory(inst->coreIdx, pvbFbcYOffset, DEC_FBCY_TBL, inst->instIndex);
  981. pvbFbcYOffset->phys_addr = 0;
  982. pvbFbcYOffset->size = ((fbcYTblSize+4095)&~4095)+4096;
  983. if (vdi_allocate_dma_memory(inst->coreIdx, pvbFbcYOffset, DEC_FBCY_TBL, inst->instIndex) < 0) {
  984. return RETCODE_INSUFFICIENT_RESOURCE;
  985. }
  986. fbcYoffsetAddr = pvbFbcYOffset->phys_addr;
  987. }
  988. if (codec == STD_HEVC) {
  989. fbcCTblSize = WAVE5_FBC_CHROMA_TABLE_SIZE(picWidth, picHeight);
  990. }
  991. else if (codec == STD_VP9) {
  992. fbcCTblSize = WAVE5_FBC_CHROMA_TABLE_SIZE(VPU_ALIGN64(picWidth), VPU_ALIGN64(picHeight));
  993. }
  994. else if (codec == STD_AVS2) {
  995. fbcCTblSize = WAVE5_FBC_CHROMA_TABLE_SIZE(picWidth, picHeight);
  996. }
  997. else if (codec == STD_AVC) {
  998. fbcCTblSize = WAVE5_FBC_CHROMA_TABLE_SIZE(picWidth, picHeight); // FIX ME
  999. }
  1000. else if (codec == STD_AV1) {
  1001. fbcCTblSize = WAVE5_FBC_CHROMA_TABLE_SIZE(VPU_ALIGN64(picWidth), VPU_ALIGN64(picHeight));
  1002. }
  1003. else {
  1004. /* Unknown codec */
  1005. return RETCODE_NOT_SUPPORTED_FEATURE;
  1006. }
  1007. if (fbcIndex >= 0) {
  1008. pvbFbcCOffset = &pDecInfo->vbFbcCTbl[fbcIndex];
  1009. vdi_free_dma_memory(inst->coreIdx, pvbFbcCOffset, DEC_FBCC_TBL, inst->instIndex);
  1010. pvbFbcCOffset->phys_addr = 0;
  1011. pvbFbcCOffset->size = ((fbcCTblSize+4095)&~4095)+4096;
  1012. if (vdi_allocate_dma_memory(inst->coreIdx, pvbFbcCOffset, DEC_FBCC_TBL, inst->instIndex) < 0) {
  1013. return RETCODE_INSUFFICIENT_RESOURCE;
  1014. }
  1015. fbcCoffsetAddr = pvbFbcCOffset->phys_addr;
  1016. }
  1017. linearStride = linearFb == NULL ? 0 : linearFb->stride;
  1018. fbcStride = fbcFb == NULL ? 0 : fbcFb->stride;
  1019. regVal = linearStride<<16 | fbcStride;
  1020. VpuWriteReg(coreIdx, W5_CMD_SET_FB_STRIDE, regVal);
  1021. regVal = (picWidth<<16) | picHeight;
  1022. if (pDecInfo->scalerEnable == TRUE) {
  1023. regVal = (pDecInfo->scaleWidth << 16) | (pDecInfo->scaleHeight);
  1024. }
  1025. VpuWriteReg(coreIdx, W5_PIC_SIZE, regVal);
  1026. VLOG(INFO, "fbcIndex(%d), linearIndex(%d), mvIndex(%d)\n", fbcIndex, linearIndex, mvIndex);
  1027. regVal = (mvIndex&0xff) << 16 | (linearIndex&0xff) << 8 | (fbcIndex&0xff);
  1028. VpuWriteReg(coreIdx, W5_CMD_SET_FB_INDEX, regVal);
  1029. VpuWriteReg(coreIdx, W5_ADDR_LUMA_BASE, linearFb == NULL ? 0 : linearFb->bufY);
  1030. VpuWriteReg(coreIdx, W5_ADDR_CB_BASE, linearFb == NULL ? 0 : linearFb->bufCb);
  1031. VpuWriteReg(coreIdx, W5_ADDR_CR_BASE, linearFb == NULL ? 0 : linearFb->bufCr);
  1032. VpuWriteReg(coreIdx, W5_ADDR_MV_COL, pvbMv == NULL ? 0 : pvbMv->phys_addr);
  1033. VpuWriteReg(coreIdx, W5_ADDR_FBC_Y_BASE, fbcFb == NULL ? 0 : fbcFb->bufY);
  1034. VpuWriteReg(coreIdx, W5_ADDR_FBC_C_BASE, fbcFb == NULL ? 0 : fbcFb->bufCb);
  1035. VpuWriteReg(coreIdx, W5_ADDR_FBC_Y_OFFSET, fbcYoffsetAddr);
  1036. VpuWriteReg(coreIdx, W5_ADDR_FBC_C_OFFSET, fbcCoffsetAddr);
  1037. VpuWriteReg(coreIdx, W5_SFB_OPTION, 1); /* UPDATE FRAMEBUFFER */
  1038. Wave5BitIssueCommand(inst, W5_SET_FB);
  1039. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  1040. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1041. }
  1042. regVal = VpuReadReg(coreIdx, W5_RET_SUCCESS);
  1043. if (regVal == 0) {
  1044. return RETCODE_FAILURE;
  1045. }
  1046. if (ConfigSecAXIWave(coreIdx, inst->codecMode,
  1047. &pDecInfo->secAxiInfo, pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight,
  1048. sequenceInfo->profile, sequenceInfo->level) == 0) {
  1049. return RETCODE_INSUFFICIENT_RESOURCE;
  1050. }
  1051. return ret;
  1052. }
  1053. RetCode Wave5VpuDecode(CodecInst* instance, DecParam* option)
  1054. {
  1055. Uint32 modeOption = DEC_PIC_NORMAL, bsOption, regVal;
  1056. DecOpenParam* pOpenParam;
  1057. Int32 forceLatency = -1;
  1058. Int32 rdptr_valid = 0;
  1059. DecInfo* pDecInfo = &instance->CodecInfo->decInfo;
  1060. pOpenParam = &pDecInfo->openParam;
  1061. if (pDecInfo->thumbnailMode) {
  1062. modeOption = DEC_PIC_W_THUMBNAIL;
  1063. }
  1064. else if (option->skipframeMode) {
  1065. switch (option->skipframeMode) {
  1066. case WAVE_SKIPMODE_NON_IRAP:
  1067. modeOption = SKIP_NON_IRAP;
  1068. forceLatency = 0;
  1069. break;
  1070. case WAVE_SKIPMODE_NON_REF:
  1071. modeOption = SKIP_NON_REF_PIC;
  1072. break;
  1073. default:
  1074. // skip off
  1075. break;
  1076. }
  1077. }
  1078. if (instance->codecMode == W_SVAC_DEC) {
  1079. switch (option->selSvacLayer) {
  1080. case SEL_SVAC_ALL_LAYER:
  1081. break;
  1082. case SEL_SVAC_BL:
  1083. modeOption |= SKIP_SVAC_EL;
  1084. break;
  1085. case SEL_SVAC_EL:
  1086. modeOption |= SKIP_SVAC_BL;
  1087. break;
  1088. default:
  1089. break;
  1090. }
  1091. }
  1092. if (option->craAsBlaFlag == TRUE) {
  1093. modeOption |= (1<<5);
  1094. }
  1095. // set disable reorder
  1096. if (pDecInfo->reorderEnable == FALSE) {
  1097. forceLatency = 0;
  1098. }
  1099. /* Set attributes of bitstream buffer controller */
  1100. bsOption = 0;
  1101. regVal = 0;
  1102. switch (pOpenParam->bitstreamMode) {
  1103. case BS_MODE_INTERRUPT:
  1104. bsOption = 0;
  1105. break;
  1106. case BS_MODE_PIC_END:
  1107. bsOption = BSOPTION_ENABLE_EXPLICIT_END;
  1108. break;
  1109. default:
  1110. return RETCODE_INVALID_PARAM;
  1111. }
  1112. VpuWriteReg(instance->coreIdx, W5_BS_RD_PTR, pDecInfo->streamRdPtr);
  1113. VpuWriteReg(instance->coreIdx, W5_BS_WR_PTR, pDecInfo->streamWrPtr);
  1114. if (pDecInfo->streamEndflag == 1)
  1115. bsOption = 3; // (streamEndFlag<<1) | EXPLICIT_END
  1116. if (pOpenParam->bitstreamMode == BS_MODE_PIC_END || pDecInfo->rdPtrValidFlag == TRUE)
  1117. rdptr_valid = 1;
  1118. if (instance->codecMode == W_AV1_DEC) {
  1119. bsOption |= ((pOpenParam->av1Format) << 2);
  1120. }
  1121. VpuWriteReg(instance->coreIdx, W5_BS_OPTION, (rdptr_valid<<31) | bsOption);
  1122. pDecInfo->rdPtrValidFlag = FALSE; // reset rdptrValidFlag.
  1123. /* Secondary AXI */
  1124. regVal = (pDecInfo->secAxiInfo.u.wave.useBitEnable<<0) |
  1125. (pDecInfo->secAxiInfo.u.wave.useIpEnable<<9) |
  1126. (pDecInfo->secAxiInfo.u.wave.useLfRowEnable<<15);
  1127. regVal |= (pDecInfo->secAxiInfo.u.wave.useSclEnable<<5);
  1128. VpuWriteReg(instance->coreIdx, W5_USE_SEC_AXI, regVal);
  1129. /* Set attributes of User buffer */
  1130. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_USER_MASK, pDecInfo->userDataEnable);
  1131. if (pDecInfo->tempIdSelectMode == FALSE)
  1132. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_TEMPORAL_ID_PLUS1, pDecInfo->tempIdSelectMode<<8 | (pDecInfo->targetSubLayerId+1));
  1133. else
  1134. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_REL_TEMPORAL_ID, pDecInfo->tempIdSelectMode<<8 | pDecInfo->relTargetLayerId);
  1135. VpuWriteReg(instance->coreIdx, W5_CMD_SEQ_CHANGE_ENABLE_FLAG, pDecInfo->seqChangeMask);
  1136. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1, forceLatency+1);
  1137. VpuWriteReg(instance->coreIdx, W5_COMMAND_OPTION, modeOption);
  1138. Wave5BitIssueCommand(instance, W5_DEC_PIC);
  1139. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) { // Check QUEUE_DONE
  1140. if (instance->loggingEnable)
  1141. vdi_log(instance->coreIdx, W5_DEC_PIC, 2);
  1142. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1143. }
  1144. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_STATUS);
  1145. pDecInfo->instanceQueueCount = (regVal>>16)&0xff;
  1146. pDecInfo->reportQueueCount = (regVal & 0xffff);
  1147. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE) { // FAILED for adding a command into VCPU QUEUE
  1148. regVal = VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON);
  1149. if (regVal != WAVE5_QUEUEING_FAIL)
  1150. VLOG(ERR, "FAIL_REASON = 0x%x\n", regVal);
  1151. if ( regVal == WAVE5_QUEUEING_FAIL)
  1152. return RETCODE_QUEUEING_FAILURE;
  1153. else if (regVal == WAVE5_SYSERR_ACCESS_VIOLATION_HW)
  1154. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1155. else if (regVal == WAVE5_SYSERR_WATCHDOG_TIMEOUT)
  1156. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1157. else if (regVal == WAVE5_SYSERR_DEC_VLC_BUF_FULL)
  1158. return RETCODE_VLC_BUF_FULL;
  1159. else if (regVal == WAVE5_ERROR_FW_FATAL)
  1160. return RETCODE_ERROR_FW_FATAL;
  1161. else
  1162. return RETCODE_FAILURE;
  1163. }
  1164. return RETCODE_SUCCESS;
  1165. }
  1166. RetCode Wave5VpuDecGetResult(CodecInst* instance, DecOutputInfo* result)
  1167. {
  1168. RetCode ret = RETCODE_SUCCESS;
  1169. Uint32 regVal, index, nalUnitType;
  1170. DecInfo* pDecInfo;
  1171. vpu_instance_pool_t* instancePool = NULL;
  1172. pDecInfo = VPU_HANDLE_TO_DECINFO(instance);
  1173. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_ADDR_REPORT_BASE, pDecInfo->userDataBufAddr);
  1174. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_REPORT_SIZE, pDecInfo->userDataBufSize);
  1175. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_REPORT_PARAM, VPU_USER_DATA_ENDIAN&VDI_128BIT_ENDIAN_MASK);
  1176. // Send QUERY cmd
  1177. ret = SendQuery(instance, GET_RESULT);
  1178. if (ret != RETCODE_SUCCESS) {
  1179. regVal = VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON);
  1180. if (regVal != WAVE5_QUEUEING_FAIL)
  1181. VLOG(ERR, "FAIL_REASON = 0x%x\n", regVal);
  1182. if (regVal == WAVE5_RESULT_NOT_READY)
  1183. return RETCODE_REPORT_NOT_READY;
  1184. else if (regVal == WAVE5_SYSERR_ACCESS_VIOLATION_HW)
  1185. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1186. else if (regVal == WAVE5_SYSERR_WATCHDOG_TIMEOUT)
  1187. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1188. else if (regVal == WAVE5_SYSERR_DEC_VLC_BUF_FULL)
  1189. return RETCODE_VLC_BUF_FULL;
  1190. else if (regVal == WAVE5_ERROR_FW_FATAL)
  1191. return RETCODE_ERROR_FW_FATAL;
  1192. else
  1193. return RETCODE_QUERY_FAILURE;
  1194. }
  1195. if (instance->loggingEnable)
  1196. vdi_log(instance->coreIdx, W5_DEC_PIC, 0);
  1197. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_STATUS);
  1198. pDecInfo->instanceQueueCount = (regVal>>16)&0xff;
  1199. pDecInfo->reportQueueCount = (regVal & 0xffff);
  1200. result->decodingSuccess = VpuReadReg(instance->coreIdx, W5_RET_DEC_DECODING_SUCCESS);
  1201. #ifdef SUPPORT_SW_UART
  1202. #else
  1203. if (result->decodingSuccess == FALSE) {
  1204. result->errorReason = VpuReadReg(instance->coreIdx, W5_RET_DEC_ERR_INFO);
  1205. }
  1206. else {
  1207. result->warnInfo = VpuReadReg(instance->coreIdx, W5_RET_DEC_WARN_INFO);
  1208. }
  1209. #endif
  1210. result->decOutputExtData.userDataSize = 0;
  1211. result->decOutputExtData.userDataNum = 0;
  1212. result->decOutputExtData.userDataBufFull= 0;
  1213. result->decOutputExtData.userDataHeader = VpuReadReg(instance->coreIdx, W5_RET_DEC_USERDATA_IDC);
  1214. if (result->decOutputExtData.userDataHeader != 0) {
  1215. regVal = result->decOutputExtData.userDataHeader;
  1216. for (index=0; index<32; index++) {
  1217. if (index == 1) {
  1218. if (regVal & (1<<index))
  1219. result->decOutputExtData.userDataBufFull = 1;
  1220. }
  1221. else {
  1222. if (regVal & (1<<index))
  1223. result->decOutputExtData.userDataNum++;
  1224. }
  1225. }
  1226. result->decOutputExtData.userDataSize = pDecInfo->userDataBufSize;
  1227. }
  1228. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_PIC_TYPE);
  1229. if (instance->codecMode == W_VP9_DEC) {
  1230. if (regVal&0x01) result->picType = PIC_TYPE_I;
  1231. else if (regVal&0x02) result->picType = PIC_TYPE_P;
  1232. else if (regVal&0x04) result->picType = PIC_TYPE_REPEAT;
  1233. else result->picType = PIC_TYPE_MAX;
  1234. }
  1235. else if (instance->codecMode == W_HEVC_DEC) {
  1236. if (regVal&0x04) result->picType = PIC_TYPE_B;
  1237. else if (regVal&0x02) result->picType = PIC_TYPE_P;
  1238. else if (regVal&0x01) result->picType = PIC_TYPE_I;
  1239. else result->picType = PIC_TYPE_MAX;
  1240. }
  1241. else if (instance->codecMode == W_AVC_DEC) {
  1242. if (regVal&0x04) result->picType = PIC_TYPE_B;
  1243. else if (regVal&0x02) result->picType = PIC_TYPE_P;
  1244. else if (regVal&0x01) result->picType = PIC_TYPE_I;
  1245. else result->picType = PIC_TYPE_MAX;
  1246. }
  1247. else if (instance->codecMode == W_SVAC_DEC) {
  1248. if (regVal&0x01) result->picType = PIC_TYPE_KEY;
  1249. else if(regVal&0x02) result->picType = PIC_TYPE_INTER;
  1250. else result->picType = PIC_TYPE_MAX;
  1251. }
  1252. else if (instance->codecMode == W_AV1_DEC) {
  1253. switch (regVal & 0x07) {
  1254. case 0: result->picType = PIC_TYPE_KEY; break;
  1255. case 1: result->picType = PIC_TYPE_INTER; break;
  1256. case 2: result->picType = PIC_TYPE_AV1_INTRA; break;
  1257. case 3: result->picType = PIC_TYPE_AV1_SWITCH; break;
  1258. default:
  1259. result->picType = PIC_TYPE_MAX; break;
  1260. }
  1261. }
  1262. else { // AVS2
  1263. switch(regVal&0x07) {
  1264. case 0: result->picType = PIC_TYPE_I; break;
  1265. case 1: result->picType = PIC_TYPE_P; break;
  1266. case 2: result->picType = PIC_TYPE_B; break;
  1267. case 3: result->picType = PIC_TYPE_AVS2_F; break;
  1268. case 4: result->picType = PIC_TYPE_AVS2_S; break;
  1269. case 5: result->picType = PIC_TYPE_AVS2_G; break;
  1270. case 6: result->picType = PIC_TYPE_AVS2_GB;break;
  1271. default:
  1272. result->picType = PIC_TYPE_MAX; break;
  1273. }
  1274. }
  1275. result->outputFlag = (regVal>>31)&0x1;
  1276. nalUnitType = (regVal & 0x3f0) >> 4;
  1277. if ((nalUnitType == 19 || nalUnitType == 20) && result->picType == PIC_TYPE_I) {
  1278. /* IDR_W_RADL, IDR_N_LP */
  1279. result->picType = PIC_TYPE_IDR;
  1280. }
  1281. result->nalType = nalUnitType;
  1282. result->ctuSize = 16<<((regVal>>10)&0x3);
  1283. index = VpuReadReg(instance->coreIdx, W5_RET_DEC_DISPLAY_INDEX);
  1284. result->indexFrameDisplay = index;
  1285. result->indexFrameDisplayForTiled = index;
  1286. index = VpuReadReg(instance->coreIdx, W5_RET_DEC_DECODED_INDEX);
  1287. result->indexFrameDecoded = index;
  1288. result->indexFrameDecodedForTiled = index;
  1289. if (instance->codecMode == W_HEVC_DEC) {
  1290. result->decodedPOC = -1;
  1291. result->displayPOC = -1;
  1292. if (result->indexFrameDecoded >= 0 || result->indexFrameDecoded == DECODED_IDX_FLAG_SKIP)
  1293. result->decodedPOC = VpuReadReg(instance->coreIdx, W5_RET_DEC_PIC_POC);
  1294. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_SUB_LAYER_INFO);
  1295. result->temporalId = regVal & 0xff;
  1296. }
  1297. else if (instance->codecMode == W_SVAC_DEC) {
  1298. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_SUB_LAYER_INFO);
  1299. result->temporalId = regVal & 0xff;
  1300. result->svacInfo.spatialSvcFlag = (regVal >> 16) & 0x1;
  1301. result->svacInfo.spatialSvcMode = (regVal >> 17) & 0x1;
  1302. result->svacInfo.spatialSvcLayer= (regVal >> 18) & 0x1;
  1303. }
  1304. else if (instance->codecMode == W_AVS2_DEC) {
  1305. result->avs2Info.decodedPOI = -1;
  1306. result->avs2Info.displayPOI = -1;
  1307. if (result->indexFrameDecoded >= 0)
  1308. result->avs2Info.decodedPOI = VpuReadReg(instance->coreIdx, W5_RET_DEC_PIC_POC);
  1309. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_SUB_LAYER_INFO);
  1310. result->temporalId = regVal & 0xff;
  1311. }
  1312. else if (instance->codecMode == W_AVC_DEC) {
  1313. result->decodedPOC = -1;
  1314. result->displayPOC = -1;
  1315. if (result->indexFrameDecoded >= 0 || result->indexFrameDecoded == DECODED_IDX_FLAG_SKIP)
  1316. result->decodedPOC = VpuReadReg(instance->coreIdx, W5_RET_DEC_PIC_POC);
  1317. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_SUB_LAYER_INFO);
  1318. result->temporalId = regVal & 0xff;
  1319. }
  1320. else if (instance->codecMode == W_AV1_DEC) {
  1321. result->decodedPOC = -1;
  1322. result->displayPOC = -1;
  1323. if (result->indexFrameDecoded >= 0 || result->indexFrameDecoded == DECODED_IDX_FLAG_SKIP)
  1324. result->decodedPOC = VpuReadReg(instance->coreIdx, W5_RET_DEC_PIC_POC);
  1325. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_SUB_LAYER_INFO);
  1326. result->temporalId = regVal & 0xff;
  1327. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_PIC_PARAM);
  1328. result->av1Info.enableIntraBlockCopy = (regVal >> 0) & 0x1;
  1329. result->av1Info.enableScreenContents = (regVal >> 1) & 0x1;
  1330. }
  1331. result->sequenceChanged = VpuReadReg(instance->coreIdx, W5_RET_DEC_NOTIFICATION);
  1332. /*
  1333. * If current picture is the last of the current sequence and sequence-change flag is not 0, then
  1334. * the width and height of the current picture is set to the width and height of the current sequence.
  1335. */
  1336. if (result->sequenceChanged == 0) {
  1337. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_PIC_SIZE);
  1338. result->decPicWidth = regVal>>16;
  1339. result->decPicHeight = regVal&0xffff;
  1340. }
  1341. else {
  1342. if (result->indexFrameDecoded < 0) {
  1343. result->decPicWidth = 0;
  1344. result->decPicHeight = 0;
  1345. }
  1346. else {
  1347. result->decPicWidth = pDecInfo->initialInfo.picWidth;
  1348. result->decPicHeight = pDecInfo->initialInfo.picHeight;
  1349. }
  1350. if ( instance->codecMode == W_VP9_DEC ) {
  1351. if ( result->sequenceChanged & SEQ_CHANGE_INTER_RES_CHANGE) {
  1352. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_PIC_SIZE);
  1353. result->decPicWidth = regVal>>16;
  1354. result->decPicHeight = regVal&0xffff;
  1355. result->indexInterFrameDecoded = VpuReadReg(instance->coreIdx, W5_RET_DEC_REALLOC_INDEX);
  1356. }
  1357. }
  1358. osal_memcpy((void*)&pDecInfo->newSeqInfo, (void*)&pDecInfo->initialInfo, sizeof(DecInitialInfo));
  1359. GetDecSequenceResult(instance, &pDecInfo->newSeqInfo);
  1360. }
  1361. result->numOfErrMBs = VpuReadReg(instance->coreIdx, W5_RET_DEC_ERR_CTB_NUM)>>16;
  1362. result->numOfTotMBs = VpuReadReg(instance->coreIdx, W5_RET_DEC_ERR_CTB_NUM)&0xffff;
  1363. result->bytePosFrameStart = VpuReadReg(instance->coreIdx, W5_RET_DEC_AU_START_POS);
  1364. result->bytePosFrameEnd = VpuReadReg(instance->coreIdx, W5_RET_DEC_AU_END_POS);
  1365. pDecInfo->prevFrameEndPos = result->bytePosFrameEnd;
  1366. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_RECOVERY_POINT);
  1367. result->h265RpSei.recoveryPocCnt = regVal & 0xFFFF; // [15:0]
  1368. result->h265RpSei.exactMatchFlag = (regVal >> 16)&0x01; // [16]
  1369. result->h265RpSei.brokenLinkFlag = (regVal >> 17)&0x01; // [17]
  1370. result->h265RpSei.exist = (regVal >> 18)&0x01; // [18]
  1371. if(result->h265RpSei.exist == 0) {
  1372. result->h265RpSei.recoveryPocCnt = 0;
  1373. result->h265RpSei.exactMatchFlag = 0;
  1374. result->h265RpSei.brokenLinkFlag = 0;
  1375. }
  1376. result->decHostCmdTick = VpuReadReg(instance->coreIdx, W5_RET_DEC_HOST_CMD_TICK);
  1377. result->decSeekStartTick = VpuReadReg(instance->coreIdx, W5_RET_DEC_SEEK_START_TICK);
  1378. result->decSeekEndTick = VpuReadReg(instance->coreIdx, W5_RET_DEC_SEEK_END__TICK);
  1379. result->decParseStartTick = VpuReadReg(instance->coreIdx, W5_RET_DEC_PARSING_START_TICK);
  1380. result->decParseEndTick = VpuReadReg(instance->coreIdx, W5_RET_DEC_PARSING_END_TICK);
  1381. result->decDecodeStartTick = VpuReadReg(instance->coreIdx, W5_RET_DEC_DECODING_START_TICK);
  1382. result->decDecodeEndTick = VpuReadReg(instance->coreIdx, W5_RET_DEC_DECODING_ENC_TICK);
  1383. instancePool = vdi_get_instance_pool(instance->coreIdx);
  1384. if (pDecInfo->firstCycleCheck == FALSE) {
  1385. result->frameCycle = (result->decDecodeEndTick - result->decHostCmdTick)*pDecInfo->cyclePerTick;
  1386. instancePool->lastPerformanceCycles = result->decDecodeEndTick;
  1387. pDecInfo->firstCycleCheck = TRUE;
  1388. }
  1389. else {
  1390. if ( result->indexFrameDecodedForTiled != -1 ) {
  1391. result->frameCycle = (result->decDecodeEndTick - instancePool->lastPerformanceCycles)*pDecInfo->cyclePerTick;
  1392. instancePool->lastPerformanceCycles = result->decDecodeEndTick;
  1393. if (instancePool->lastPerformanceCycles < result->decHostCmdTick)
  1394. result->frameCycle = (result->decDecodeEndTick - result->decHostCmdTick);
  1395. }
  1396. }
  1397. result->seekCycle = (result->decSeekEndTick - result->decSeekStartTick)*pDecInfo->cyclePerTick;
  1398. result->parseCycle = (result->decParseEndTick - result->decParseStartTick)*pDecInfo->cyclePerTick;
  1399. result->DecodedCycle = (result->decDecodeEndTick - result->decDecodeStartTick)*pDecInfo->cyclePerTick;
  1400. if (0 == pDecInfo->instanceQueueCount && 0 == pDecInfo->reportQueueCount) {
  1401. // No remaining command. Reset frame cycle.
  1402. pDecInfo->firstCycleCheck = FALSE;
  1403. }
  1404. if ( result->sequenceChanged && (instance->codecMode != W_VP9_DEC)) {
  1405. pDecInfo->scaleWidth = pDecInfo->newSeqInfo.picWidth;
  1406. pDecInfo->scaleHeight = pDecInfo->newSeqInfo.picHeight;
  1407. }
  1408. return RETCODE_SUCCESS;
  1409. }
  1410. RetCode Wave5VpuDecFlush(CodecInst* instance, FramebufferIndex* framebufferIndexes, Uint32 size)
  1411. {
  1412. RetCode ret = RETCODE_SUCCESS;
  1413. Wave5BitIssueCommand(instance, W5_FLUSH_INSTANCE);
  1414. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1)
  1415. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1416. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE) {
  1417. Uint32 regVal;
  1418. regVal = VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON);
  1419. if (regVal != WAVE5_QUEUEING_FAIL)
  1420. VLOG(ERR, "FAIL_REASON = 0x%x\n", regVal);
  1421. if (regVal == WAVE5_VPU_STILL_RUNNING)
  1422. return RETCODE_VPU_STILL_RUNNING;
  1423. else if (regVal == WAVE5_SYSERR_ACCESS_VIOLATION_HW)
  1424. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1425. else if (regVal == WAVE5_SYSERR_WATCHDOG_TIMEOUT)
  1426. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1427. else if (regVal == WAVE5_SYSERR_DEC_VLC_BUF_FULL)
  1428. return RETCODE_VLC_BUF_FULL;
  1429. else if (regVal == WAVE5_ERROR_FW_FATAL)
  1430. return RETCODE_ERROR_FW_FATAL;
  1431. else
  1432. return RETCODE_QUERY_FAILURE;
  1433. }
  1434. else {
  1435. DecInfo* pDecInfo = VPU_HANDLE_TO_DECINFO(instance);
  1436. pDecInfo->instanceQueueCount = 0;
  1437. pDecInfo->reportQueueCount = 0;
  1438. }
  1439. return ret;
  1440. }
  1441. RetCode Wave5VpuReInit(Uint32 coreIdx, void* firmware, Uint32 size)
  1442. {
  1443. vpu_buffer_t vb;
  1444. PhysicalAddress codeBase, tempBase;
  1445. PhysicalAddress oldCodeBase, tempSize;
  1446. Uint32 codeSize;
  1447. Uint32 regVal, remapSize;
  1448. vdi_get_common_memory(coreIdx, &vb);
  1449. codeBase = vb.phys_addr;
  1450. /* ALIGN TO 4KB */
  1451. codeSize = (WAVE5_MAX_CODE_BUF_SIZE&~0xfff);
  1452. if (codeSize < size*2) {
  1453. return RETCODE_INSUFFICIENT_RESOURCE;
  1454. }
  1455. tempBase = vb.phys_addr + WAVE5_TEMPBUF_OFFSET;
  1456. tempSize = WAVE5_TEMPBUF_SIZE;
  1457. oldCodeBase = VpuReadReg(coreIdx, W5_VPU_REMAP_PADDR);
  1458. if (oldCodeBase != codeBase) {
  1459. VpuAttr* pAttr = &g_VpuCoreAttributes[coreIdx];
  1460. VpuWriteMem(coreIdx, codeBase, (unsigned char*)firmware, size*2, VDI_128BIT_LITTLE_ENDIAN);
  1461. vdi_set_bit_firmware_to_pm(coreIdx, (Uint16*)firmware);
  1462. regVal = 0;
  1463. VpuWriteReg(coreIdx, W5_PO_CONF, regVal);
  1464. if (pAttr->supportBackbone == TRUE) {
  1465. if (pAttr->supportDualCore == TRUE) {
  1466. // check CORE0
  1467. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE0, 0x7);
  1468. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_BACKBONE_BUS_STATUS_VCORE0) == -1) {
  1469. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00);
  1470. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1471. }
  1472. // check CORE1
  1473. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE1, 0x7);
  1474. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_BACKBONE_BUS_STATUS_VCORE1) == -1) {
  1475. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE1, 0x00);
  1476. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1477. }
  1478. }
  1479. else {
  1480. if (pAttr->supportVcoreBackbone == TRUE) {
  1481. // Step1 : disable request
  1482. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE0, 0x7);
  1483. // Step2 : Waiting for completion of bus transaction
  1484. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_BACKBONE_BUS_STATUS_VCORE0) == -1) {
  1485. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00);
  1486. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1487. }
  1488. }
  1489. else {
  1490. // Step1 : disable request
  1491. vdi_fio_write_register(coreIdx, W5_COMBINED_BACKBONE_BUS_CTRL, 0x7);
  1492. // Step2 : Waiting for completion of bus transaction
  1493. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_COMBINED_BACKBONE_BUS_STATUS) == -1) {
  1494. vdi_fio_write_register(coreIdx, W5_COMBINED_BACKBONE_BUS_CTRL, 0x00);
  1495. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1496. }
  1497. }
  1498. }
  1499. }
  1500. else {
  1501. // Step1 : disable request
  1502. vdi_fio_write_register(coreIdx, W5_GDI_BUS_CTRL, 0x100);
  1503. // Step2 : Waiting for completion of bus transaction
  1504. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_GDI_BUS_STATUS) == -1) {
  1505. vdi_fio_write_register(coreIdx, W5_GDI_BUS_CTRL, 0x00);
  1506. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1507. }
  1508. }
  1509. // Step3 : Waiting for completion of VCPU bus transaction
  1510. if (vdi_wait_vcpu_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_VCPU_STATUS) == -1) {
  1511. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1512. }
  1513. /* Reset All blocks */
  1514. regVal = 0x7ffffff;
  1515. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, regVal); // Reset All blocks
  1516. /* Waiting reset done */
  1517. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_RESET_STATUS) == -1) {
  1518. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, 0);
  1519. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1520. }
  1521. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, 0);
  1522. // Step3 : must clear GDI_BUS_CTRL after done SW_RESET
  1523. if (pAttr->supportBackbone == TRUE) {
  1524. if (pAttr->supportDualCore == TRUE) {
  1525. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00);
  1526. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE1, 0x00);
  1527. }
  1528. else {
  1529. if (pAttr->supportVcoreBackbone == TRUE) {
  1530. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00);
  1531. }
  1532. else {
  1533. vdi_fio_write_register(coreIdx, W5_COMBINED_BACKBONE_BUS_CTRL, 0x00);
  1534. }
  1535. }
  1536. }
  1537. else {
  1538. vdi_fio_write_register(coreIdx, W5_GDI_BUS_CTRL, 0x00);
  1539. }
  1540. /* remap page size */
  1541. remapSize = (codeSize >> 12) &0x1ff;
  1542. regVal = 0x80000000 | (WAVE5_UPPER_PROC_AXI_ID<<20) | (W5_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remapSize;
  1543. VpuWriteReg(coreIdx, W5_VPU_REMAP_CTRL, regVal);
  1544. VpuWriteReg(coreIdx, W5_VPU_REMAP_VADDR, 0x00000000); /* DO NOT CHANGE! */
  1545. VpuWriteReg(coreIdx, W5_VPU_REMAP_PADDR, codeBase);
  1546. VpuWriteReg(coreIdx, W5_ADDR_CODE_BASE, codeBase);
  1547. VpuWriteReg(coreIdx, W5_CODE_SIZE, codeSize);
  1548. VpuWriteReg(coreIdx, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID<<4) | 0);
  1549. VpuWriteReg(coreIdx, W5_ADDR_TEMP_BASE, tempBase);
  1550. VpuWriteReg(coreIdx, W5_TEMP_SIZE, tempSize);
  1551. VpuWriteReg(coreIdx, W5_TIMEOUT_CNT, 0);
  1552. VpuWriteReg(coreIdx, W5_HW_OPTION, 0);
  1553. /* Interrupt */
  1554. // encoder
  1555. regVal = (1<<INT_WAVE5_ENC_SET_PARAM);
  1556. regVal |= (1<<INT_WAVE5_ENC_PIC);
  1557. regVal |= (1<<INT_WAVE5_BSBUF_FULL);
  1558. regVal |= (1<<INT_WAVE5_ENC_LOW_LATENCY);
  1559. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  1560. regVal |= (1<<INT_WAVE5_ENC_SRC_RELEASE);
  1561. #endif
  1562. // decoder
  1563. regVal = (1<<INT_WAVE5_INIT_SEQ);
  1564. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1565. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1566. VpuWriteReg(coreIdx, W5_VPU_VINT_ENABLE, regVal);
  1567. regVal = ((WAVE5_PROC_AXI_ID<<28) |
  1568. (WAVE5_PRP_AXI_ID<<24) |
  1569. (WAVE5_FBD_Y_AXI_ID<<20) |
  1570. (WAVE5_FBC_Y_AXI_ID<<16) |
  1571. (WAVE5_FBD_C_AXI_ID<<12) |
  1572. (WAVE5_FBC_C_AXI_ID<<8) |
  1573. (WAVE5_PRI_AXI_ID<<4) |
  1574. (WAVE5_SEC_AXI_ID<<0));
  1575. vdi_fio_write_register(coreIdx, W5_BACKBONE_PROG_AXI_ID, regVal);
  1576. if (vdi_get_sram_memory(coreIdx, &vb) < 0) // get SRAM base/size
  1577. return RETCODE_INSUFFICIENT_RESOURCE;
  1578. VpuWriteReg(coreIdx, W5_ADDR_SEC_AXI, vb.phys_addr);
  1579. VpuWriteReg(coreIdx, W5_SEC_AXI_SIZE, vb.size);
  1580. VpuWriteReg(coreIdx, W5_VPU_BUSY_STATUS, 1);
  1581. VpuWriteReg(coreIdx, W5_COMMAND, W5_INIT_VPU);
  1582. VpuWriteReg(coreIdx, W5_VPU_HOST_INT_REQ, 1);
  1583. VpuWriteReg(coreIdx, W5_VPU_REMAP_CORE_START, 1);
  1584. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  1585. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1586. }
  1587. regVal = VpuReadReg(coreIdx, W5_RET_SUCCESS);
  1588. if (regVal == 0)
  1589. return RETCODE_FAILURE;
  1590. }
  1591. SetupWave5Properties(coreIdx);
  1592. return RETCODE_SUCCESS;
  1593. }
  1594. RetCode Wave5VpuSleepWake(Uint32 coreIdx, int iSleepWake, const Uint16* code, Uint32 size, BOOL reset)
  1595. {
  1596. Uint32 regVal;
  1597. vpu_buffer_t vb;
  1598. PhysicalAddress codeBase, tempBase;
  1599. Uint32 codeSize, tempSize;
  1600. Uint32 remapSize;
  1601. if(iSleepWake==1) //saves
  1602. {
  1603. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  1604. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1605. }
  1606. VpuWriteReg(coreIdx, W5_VPU_BUSY_STATUS, 1);
  1607. VpuWriteReg(coreIdx, W5_COMMAND, W5_SLEEP_VPU);
  1608. VpuWriteReg(coreIdx, W5_VPU_HOST_INT_REQ, 1);
  1609. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1)
  1610. {
  1611. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1612. }
  1613. regVal = VpuReadReg(coreIdx, W5_RET_SUCCESS);
  1614. if (regVal == 0)
  1615. {
  1616. APIDPRINT("SLEEP_VPU failed [0x%x]", VpuReadReg(coreIdx, W5_RET_FAIL_REASON));
  1617. return RETCODE_FAILURE;
  1618. }
  1619. }
  1620. else //restore
  1621. {
  1622. Uint32 hwOption = 0;
  1623. vdi_get_common_memory(coreIdx, &vb);
  1624. codeBase = vb.phys_addr;
  1625. /* ALIGN TO 4KB */
  1626. codeSize = (WAVE5_MAX_CODE_BUF_SIZE&~0xfff);
  1627. if (codeSize < size*2) {
  1628. return RETCODE_INSUFFICIENT_RESOURCE;
  1629. }
  1630. tempBase = vb.phys_addr + WAVE5_TEMPBUF_OFFSET;
  1631. tempSize = WAVE5_TEMPBUF_SIZE;
  1632. regVal = 0;
  1633. VpuWriteReg(coreIdx, W5_PO_CONF, regVal);
  1634. /* SW_RESET_SAFETY */
  1635. regVal = W5_RST_BLOCK_ALL;
  1636. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, regVal); // Reset All blocks
  1637. /* Waiting reset done */
  1638. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_RESET_STATUS) == -1) {
  1639. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, 0);
  1640. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1641. }
  1642. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, 0);
  1643. /* remap page size */
  1644. remapSize = (codeSize >> 12) &0x1ff;
  1645. regVal = 0x80000000 | (WAVE5_UPPER_PROC_AXI_ID<<20) | (W5_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remapSize;
  1646. VpuWriteReg(coreIdx, W5_VPU_REMAP_CTRL, regVal);
  1647. VpuWriteReg(coreIdx, W5_VPU_REMAP_VADDR, 0x00000000); /* DO NOT CHANGE! */
  1648. VpuWriteReg(coreIdx, W5_VPU_REMAP_PADDR, codeBase);
  1649. VpuWriteReg(coreIdx, W5_ADDR_CODE_BASE, codeBase);
  1650. VpuWriteReg(coreIdx, W5_CODE_SIZE, codeSize);
  1651. VpuWriteReg(coreIdx, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID<<4) | 0);
  1652. VpuWriteReg(coreIdx, W5_ADDR_TEMP_BASE, tempBase);
  1653. VpuWriteReg(coreIdx, W5_TEMP_SIZE, tempSize);
  1654. VpuWriteReg(coreIdx, W5_TIMEOUT_CNT, 0);
  1655. VpuWriteReg(coreIdx, W5_HW_OPTION, hwOption);
  1656. // encoder
  1657. regVal = (1<<INT_WAVE5_ENC_SET_PARAM);
  1658. regVal |= (1<<INT_WAVE5_ENC_PIC);
  1659. regVal |= (1<<INT_WAVE5_BSBUF_FULL);
  1660. regVal |= (1<<INT_WAVE5_ENC_LOW_LATENCY);
  1661. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  1662. regVal |= (1<<INT_WAVE5_ENC_SRC_RELEASE);
  1663. #endif
  1664. // decoder
  1665. regVal = (1<<INT_WAVE5_INIT_SEQ);
  1666. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1667. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1668. VpuWriteReg(coreIdx, W5_VPU_VINT_ENABLE, regVal);
  1669. regVal = ((WAVE5_PROC_AXI_ID<<28) |
  1670. (WAVE5_PRP_AXI_ID<<24) |
  1671. (WAVE5_FBD_Y_AXI_ID<<20) |
  1672. (WAVE5_FBC_Y_AXI_ID<<16) |
  1673. (WAVE5_FBD_C_AXI_ID<<12) |
  1674. (WAVE5_FBC_C_AXI_ID<<8) |
  1675. (WAVE5_PRI_AXI_ID<<4) |
  1676. (WAVE5_SEC_AXI_ID<<0));
  1677. vdi_fio_write_register(coreIdx, W5_BACKBONE_PROG_AXI_ID, regVal);
  1678. if (vdi_get_sram_memory(coreIdx, &vb) < 0) // get SRAM base/size
  1679. return RETCODE_INSUFFICIENT_RESOURCE;
  1680. VpuWriteReg(coreIdx, W5_ADDR_SEC_AXI, vb.phys_addr);
  1681. VpuWriteReg(coreIdx, W5_SEC_AXI_SIZE, vb.size);
  1682. VpuWriteReg(coreIdx, W5_VPU_BUSY_STATUS, 1);
  1683. VpuWriteReg(coreIdx, W5_COMMAND, (reset==TRUE ? W5_INIT_VPU : W5_WAKEUP_VPU));
  1684. VpuWriteReg(coreIdx, W5_VPU_REMAP_CORE_START, 1);
  1685. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  1686. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1687. }
  1688. regVal = VpuReadReg(coreIdx, W5_RET_SUCCESS);
  1689. if (regVal == 0) {
  1690. return RETCODE_FAILURE;
  1691. }
  1692. VpuWriteReg(coreIdx, W5_VPU_VINT_REASON_CLR, 0xffff);
  1693. VpuWriteReg(coreIdx, W5_VPU_VINT_REASON_USR, 0);
  1694. VpuWriteReg(coreIdx, W5_VPU_VINT_CLEAR, 0x1);
  1695. }
  1696. return RETCODE_SUCCESS;
  1697. }
  1698. RetCode Wave5VpuReset(Uint32 coreIdx, SWResetMode resetMode)
  1699. {
  1700. Uint32 val = 0;
  1701. RetCode ret = RETCODE_SUCCESS;
  1702. VpuAttr* pAttr = &g_VpuCoreAttributes[coreIdx];
  1703. // VPU doesn't send response. Force to set BUSY flag to 0.
  1704. VpuWriteReg(coreIdx, W5_VPU_BUSY_STATUS, 0);
  1705. val = VpuReadReg(coreIdx, W5_VPU_RET_VPU_CONFIG0);
  1706. if (((val>>16) & 0x1) == 0x01) {
  1707. pAttr->supportBackbone = TRUE;
  1708. }
  1709. if (((val>>22) & 0x1) == 0x01) {
  1710. pAttr->supportVcoreBackbone = TRUE;
  1711. }
  1712. val = VpuReadReg(coreIdx, W5_VPU_RET_VPU_CONFIG1);
  1713. if (((val>>26) & 0x1) == 0x01) {
  1714. pAttr->supportDualCore = TRUE;
  1715. }
  1716. // Waiting for completion of bus transaction
  1717. if (pAttr->supportBackbone == TRUE) {
  1718. if (pAttr->supportDualCore == TRUE) {
  1719. // check CORE0
  1720. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE0, 0x7);
  1721. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_BACKBONE_BUS_STATUS_VCORE0) == -1) {
  1722. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00);
  1723. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1724. }
  1725. // check CORE1
  1726. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE1, 0x7);
  1727. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_BACKBONE_BUS_STATUS_VCORE1) == -1) {
  1728. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE1, 0x00);
  1729. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1730. }
  1731. }
  1732. else {
  1733. if (pAttr->supportVcoreBackbone == TRUE) {
  1734. // Step1 : disable request
  1735. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE0, 0x7);
  1736. // Step2 : Waiting for completion of bus transaction
  1737. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_BACKBONE_BUS_STATUS_VCORE0) == -1) {
  1738. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00);
  1739. VLOG(ERR, "VpuReset Error = %d\n", pAttr->supportBackbone);
  1740. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1741. }
  1742. }
  1743. else {
  1744. // Step1 : disable request
  1745. vdi_fio_write_register(coreIdx, W5_COMBINED_BACKBONE_BUS_CTRL, 0x7);
  1746. // Step2 : Waiting for completion of bus transaction
  1747. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_COMBINED_BACKBONE_BUS_STATUS) == -1) {
  1748. vdi_fio_write_register(coreIdx, W5_COMBINED_BACKBONE_BUS_CTRL, 0x00);
  1749. VLOG(ERR, "VpuReset Error = %d\n", pAttr->supportBackbone);
  1750. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1751. }
  1752. }
  1753. }
  1754. }
  1755. else {
  1756. // Step1 : disable request
  1757. vdi_fio_write_register(coreIdx, W5_GDI_BUS_CTRL, 0x100);
  1758. // Step2 : Waiting for completion of bus transaction
  1759. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_GDI_BUS_STATUS) == -1) {
  1760. vdi_fio_write_register(coreIdx, W5_GDI_BUS_CTRL, 0x00);
  1761. VLOG(ERR, "VpuReset Error = %d\n", pAttr->supportBackbone);
  1762. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1763. }
  1764. }
  1765. if (resetMode == SW_RESET_SAFETY) {
  1766. if ((ret=Wave5VpuSleepWake(coreIdx, TRUE, NULL, 0, TRUE)) != RETCODE_SUCCESS) {
  1767. return ret;
  1768. }
  1769. }
  1770. switch (resetMode) {
  1771. case SW_RESET_ON_BOOT:
  1772. case SW_RESET_FORCE:
  1773. case SW_RESET_SAFETY:
  1774. val = W5_RST_BLOCK_ALL;
  1775. break;
  1776. default:
  1777. return RETCODE_INVALID_PARAM;
  1778. }
  1779. if (val) {
  1780. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, val);
  1781. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_RESET_STATUS) == -1) {
  1782. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, 0);
  1783. vdi_log(coreIdx, W5_RESET_VPU, 2);
  1784. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1785. }
  1786. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, 0);
  1787. }
  1788. // Step3 : must clear GDI_BUS_CTRL after done SW_RESET
  1789. if (pAttr->supportBackbone == TRUE) {
  1790. if (pAttr->supportDualCore == TRUE) {
  1791. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00);
  1792. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE1, 0x00);
  1793. }
  1794. else {
  1795. if (pAttr->supportVcoreBackbone == TRUE) {
  1796. vdi_fio_write_register(coreIdx, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00);
  1797. }
  1798. else {
  1799. vdi_fio_write_register(coreIdx, W5_COMBINED_BACKBONE_BUS_CTRL, 0x00);
  1800. }
  1801. }
  1802. }
  1803. else {
  1804. vdi_fio_write_register(coreIdx, W5_GDI_BUS_CTRL, 0x00);
  1805. }
  1806. if (resetMode == SW_RESET_SAFETY || resetMode == SW_RESET_FORCE ) {
  1807. ret = Wave5VpuSleepWake(coreIdx, FALSE, NULL, 0, TRUE);
  1808. }
  1809. return ret;
  1810. }
  1811. RetCode Wave5VpuDecFiniSeq(CodecInst* instance)
  1812. {
  1813. RetCode ret = RETCODE_SUCCESS;
  1814. Wave5BitIssueCommand(instance, W5_DESTROY_INSTANCE);
  1815. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1)
  1816. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1817. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE) {
  1818. Uint32 regVal;
  1819. regVal = VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON);
  1820. if (regVal != WAVE5_QUEUEING_FAIL && regVal != WAVE5_VPU_STILL_RUNNING)
  1821. VLOG(ERR, "FAIL_REASON = 0x%x\n", regVal);
  1822. if (regVal == WAVE5_VPU_STILL_RUNNING)
  1823. ret = RETCODE_VPU_STILL_RUNNING;
  1824. else if (regVal == WAVE5_SYSERR_ACCESS_VIOLATION_HW)
  1825. ret = RETCODE_MEMORY_ACCESS_VIOLATION;
  1826. else if (regVal == WAVE5_SYSERR_WATCHDOG_TIMEOUT)
  1827. ret = RETCODE_VPU_RESPONSE_TIMEOUT;
  1828. else if (regVal == WAVE5_SYSERR_DEC_VLC_BUF_FULL)
  1829. ret = RETCODE_VLC_BUF_FULL;
  1830. else if (regVal == WAVE5_ERROR_FW_FATAL)
  1831. ret = RETCODE_ERROR_FW_FATAL;
  1832. else
  1833. ret = RETCODE_FAILURE;
  1834. }
  1835. return ret;
  1836. }
  1837. RetCode Wave5VpuDecSetBitstreamFlag(CodecInst* instance, BOOL running, BOOL eos, BOOL explictEnd)
  1838. {
  1839. DecInfo* pDecInfo = &instance->CodecInfo->decInfo;
  1840. BitStreamMode bsMode = (BitStreamMode)pDecInfo->openParam.bitstreamMode;
  1841. pDecInfo->streamEndflag = (eos == 1) ? TRUE : FALSE;
  1842. if (bsMode == BS_MODE_INTERRUPT) {
  1843. if (pDecInfo->streamEndflag == TRUE) explictEnd = TRUE;
  1844. VpuWriteReg(instance->coreIdx, W5_BS_OPTION, (pDecInfo->streamEndflag<<1) | explictEnd);
  1845. VpuWriteReg(instance->coreIdx, W5_BS_WR_PTR, pDecInfo->streamWrPtr);
  1846. Wave5BitIssueCommand(instance, W5_UPDATE_BS);
  1847. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  1848. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1849. }
  1850. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == 0) {
  1851. return RETCODE_FAILURE;
  1852. }
  1853. }
  1854. return RETCODE_SUCCESS;
  1855. }
  1856. RetCode Wave5DecClrDispFlag(CodecInst* instance, Uint32 index)
  1857. {
  1858. RetCode ret = RETCODE_SUCCESS;
  1859. DecInfo * pDecInfo;
  1860. pDecInfo = &instance->CodecInfo->decInfo;
  1861. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_CLR_DISP_IDC, (1<<index));
  1862. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_SET_DISP_IDC, 0);
  1863. ret = SendQuery(instance, UPDATE_DISP_FLAG);
  1864. if (ret != RETCODE_SUCCESS) {
  1865. VLOG(ERR, "Wave5DecClrDispFlag QUERY FAILURE\n");
  1866. return RETCODE_QUERY_FAILURE;
  1867. }
  1868. pDecInfo->frameDisplayFlag = VpuReadReg(instance->coreIdx, pDecInfo->frameDisplayFlagRegAddr);
  1869. return RETCODE_SUCCESS;
  1870. }
  1871. RetCode Wave5DecSetDispFlag(CodecInst* instance, Uint32 index)
  1872. {
  1873. RetCode ret = RETCODE_SUCCESS;
  1874. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_CLR_DISP_IDC, 0);
  1875. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_SET_DISP_IDC, (1<<index));
  1876. ret = SendQuery(instance, UPDATE_DISP_FLAG);
  1877. return ret;
  1878. }
  1879. Int32 Wave5VpuWaitInterrupt(CodecInst* instance, Int32 timeout, BOOL pending)
  1880. {
  1881. Int32 reason = -1;
  1882. #ifdef SUPPORT_MULTI_INST_INTR
  1883. #else
  1884. Int32 orgReason = -1;
  1885. Int32 remain_intr = -1; // to set VPU_VINT_REASON for remain interrupt.
  1886. Int32 ownInt = 0;
  1887. Uint32 regVal;
  1888. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  1889. Uint32 IntrMask = ((1 << INT_WAVE5_BSBUF_EMPTY) | (1 << INT_WAVE5_DEC_PIC) | (1 << INT_WAVE5_INIT_SEQ) | (1 << INT_WAVE5_ENC_SET_PARAM) | (1 << INT_WAVE5_ENC_SRC_RELEASE));
  1890. #else
  1891. Uint32 IntrMask = ((1 << INT_WAVE5_BSBUF_EMPTY) | (1 << INT_WAVE5_DEC_PIC) | (1 << INT_WAVE5_INIT_SEQ) | (1 << INT_WAVE5_ENC_SET_PARAM));
  1892. #endif
  1893. #endif /* SUPPORT_MULTI_INST_INTR */
  1894. #ifdef SUPPORT_MULTI_INST_INTR
  1895. // check an interrupt for my instance during timeout
  1896. reason = vdi_wait_interrupt(instance->coreIdx, instance->instIndex, timeout);
  1897. #else
  1898. EnterLock(instance->coreIdx);
  1899. // check one interrupt for current instance even if the number of interrupt triggered more than one.
  1900. if ((reason = vdi_wait_interrupt(instance->coreIdx, timeout)) > 0) {
  1901. remain_intr = reason;
  1902. if (reason & (1 << INT_WAVE5_BSBUF_EMPTY)) {
  1903. regVal = VpuReadReg(instance->coreIdx, W5_RET_BS_EMPTY_INST);
  1904. regVal = (regVal & 0xffff);
  1905. if (regVal & (1 << instance->instIndex)) {
  1906. ownInt = 1;
  1907. reason = (1 << INT_WAVE5_BSBUF_EMPTY);
  1908. remain_intr &= ~(Uint32)reason;
  1909. regVal = regVal & ~(1UL << instance->instIndex);
  1910. VpuWriteReg(instance->coreIdx, W5_RET_BS_EMPTY_INST, regVal);
  1911. }
  1912. }
  1913. if (reason & (1 << INT_WAVE5_INIT_SEQ)) {
  1914. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_CMD_DONE_INST);
  1915. regVal = (regVal & 0xffff);
  1916. if (regVal & (1 << instance->instIndex)) {
  1917. ownInt = 1;
  1918. reason = (1 << INT_WAVE5_INIT_SEQ);
  1919. remain_intr &= ~(Uint32)reason;
  1920. regVal = regVal & ~(1UL << instance->instIndex);
  1921. VpuWriteReg(instance->coreIdx, W5_RET_QUEUE_CMD_DONE_INST, regVal);
  1922. }
  1923. }
  1924. if (reason & (1 << INT_WAVE5_DEC_PIC)) {
  1925. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_CMD_DONE_INST);
  1926. regVal = (regVal & 0xffff);
  1927. if (regVal & (1 << instance->instIndex)) {
  1928. ownInt = 1;
  1929. orgReason = reason;
  1930. reason = (1 << INT_WAVE5_DEC_PIC);
  1931. remain_intr &= ~(Uint32)reason;
  1932. /* Clear Low Latency Interrupt if two interrupts are occured */
  1933. if (orgReason & (1 << INT_WAVE5_ENC_LOW_LATENCY)) {
  1934. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_CMD_DONE_INST);
  1935. regVal = (regVal>>16);
  1936. if (regVal & (1 << instance->instIndex)) {
  1937. remain_intr &= ~(1<<INT_WAVE5_ENC_LOW_LATENCY);
  1938. Wave5VpuClearInterrupt(instance->coreIdx, 1<<INT_WAVE5_ENC_LOW_LATENCY);
  1939. }
  1940. }
  1941. regVal = regVal & ~(1UL << instance->instIndex);
  1942. VpuWriteReg(instance->coreIdx, W5_RET_QUEUE_CMD_DONE_INST, regVal);
  1943. }
  1944. }
  1945. if (reason & (1 << INT_WAVE5_ENC_SET_PARAM)) {
  1946. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_CMD_DONE_INST);
  1947. regVal = (regVal & 0xffff);
  1948. if (regVal & (1 << instance->instIndex)) {
  1949. ownInt = 1;
  1950. reason = (1 << INT_WAVE5_ENC_SET_PARAM);
  1951. remain_intr &= ~(Uint32)reason;
  1952. regVal = regVal & ~(1UL << instance->instIndex);
  1953. VpuWriteReg(instance->coreIdx, W5_RET_QUEUE_CMD_DONE_INST, regVal);
  1954. }
  1955. }
  1956. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  1957. if (reason & (1 << INT_WAVE5_ENC_SRC_RELEASE)) {
  1958. regVal = VpuReadReg(instance->coreIdx, W5_RET_RELEASED_SRC_INSTANCE);
  1959. regVal = (regVal & 0xffff);
  1960. if (regVal & (1 << instance->instIndex)) {
  1961. ownInt = 1;
  1962. reason = (1 << INT_WAVE5_ENC_SRC_RELEASE);
  1963. remain_intr &= ~(Uint32)reason;
  1964. regVal = regVal & ~(1UL << instance->instIndex);
  1965. VpuWriteReg(instance->coreIdx, W5_RET_RELEASED_SRC_INSTANCE, regVal);
  1966. }
  1967. }
  1968. #endif
  1969. if (reason & (1 << INT_WAVE5_ENC_LOW_LATENCY)) {
  1970. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_CMD_DONE_INST);
  1971. regVal = (regVal>>16);
  1972. if (regVal & (1 << instance->instIndex)) {
  1973. ownInt = 1;
  1974. reason = (1 << INT_WAVE5_ENC_LOW_LATENCY);
  1975. remain_intr &= ~(Uint32)reason;
  1976. regVal = regVal & ~(1UL << instance->instIndex);
  1977. regVal = (regVal << 16);
  1978. VpuWriteReg(instance->coreIdx, W5_RET_QUEUE_CMD_DONE_INST, regVal);
  1979. }
  1980. }
  1981. if (reason & ~IntrMask) { // when interrupt is not for empty, dec_pic, init_seq.
  1982. regVal = VpuReadReg(instance->coreIdx, W5_RET_SEQ_DONE_INSTANCE_INFO)&0xFF;
  1983. if (regVal == instance->instIndex) {
  1984. ownInt = 1;
  1985. reason = (reason & ~IntrMask);
  1986. remain_intr &= ~(Uint32)reason;
  1987. }
  1988. }
  1989. VpuWriteReg(instance->coreIdx, W5_VPU_VINT_REASON, remain_intr); // set remain interrupt flag to trigger interrupt next time.
  1990. if (!ownInt)
  1991. reason = -1; // if there was no interrupt for current instance id, reason should be -1;
  1992. }
  1993. LeaveLock(instance->coreIdx);
  1994. #endif
  1995. return reason;
  1996. }
  1997. RetCode Wave5VpuClearInterrupt(Uint32 coreIdx, Uint32 flags)
  1998. {
  1999. Uint32 interruptReason;
  2000. interruptReason = VpuReadReg(coreIdx, W5_VPU_VINT_REASON_USR);
  2001. interruptReason &= ~flags;
  2002. VpuWriteReg(coreIdx, W5_VPU_VINT_REASON_USR, interruptReason);
  2003. return RETCODE_SUCCESS;
  2004. }
  2005. RetCode Wave5VpuDecGetRdPtr(CodecInst* instance, PhysicalAddress *rdPtr)
  2006. {
  2007. RetCode ret = RETCODE_SUCCESS;
  2008. ret = SendQuery(instance, GET_BS_RD_PTR);
  2009. if (ret != RETCODE_SUCCESS)
  2010. return RETCODE_QUERY_FAILURE;
  2011. *rdPtr = VpuReadReg(instance->coreIdx, W5_RET_QUERY_DEC_BS_RD_PTR);
  2012. return RETCODE_SUCCESS;
  2013. }
  2014. RetCode Wave5VpuGetBwReport(CodecInst* instance, VPUBWData* bwMon)
  2015. {
  2016. RetCode ret = RETCODE_SUCCESS;
  2017. Int32 coreIdx;
  2018. coreIdx = instance->coreIdx;
  2019. ret = SendQuery(instance, GET_BW_REPORT);
  2020. if (ret != RETCODE_SUCCESS) {
  2021. if (VpuReadReg(coreIdx, W5_RET_FAIL_REASON) == WAVE5_RESULT_NOT_READY)
  2022. return RETCODE_REPORT_NOT_READY;
  2023. else
  2024. return RETCODE_QUERY_FAILURE;
  2025. }
  2026. bwMon->prpBwRead = VpuReadReg(coreIdx, RET_QUERY_BW_PRP_AXI_READ) * 16;
  2027. bwMon->prpBwWrite = VpuReadReg(coreIdx, RET_QUERY_BW_PRP_AXI_WRITE) * 16;
  2028. bwMon->fbdYRead = VpuReadReg(coreIdx, RET_QUERY_BW_FBD_Y_AXI_READ) * 16;
  2029. bwMon->fbcYWrite = VpuReadReg(coreIdx, RET_QUERY_BW_FBC_Y_AXI_WRITE) * 16;
  2030. bwMon->fbdCRead = VpuReadReg(coreIdx, RET_QUERY_BW_FBD_C_AXI_READ) * 16;
  2031. bwMon->fbcCWrite = VpuReadReg(coreIdx, RET_QUERY_BW_FBC_C_AXI_WRITE) * 16;
  2032. bwMon->priBwRead = VpuReadReg(coreIdx, RET_QUERY_BW_PRI_AXI_READ) * 16;
  2033. bwMon->priBwWrite = VpuReadReg(coreIdx, RET_QUERY_BW_PRI_AXI_WRITE) * 16;
  2034. bwMon->secBwRead = VpuReadReg(coreIdx, RET_QUERY_BW_SEC_AXI_READ) * 16;
  2035. bwMon->secBwWrite = VpuReadReg(coreIdx, RET_QUERY_BW_SEC_AXI_WRITE) * 16;
  2036. bwMon->procBwRead = VpuReadReg(coreIdx, RET_QUERY_BW_PROC_AXI_READ) * 16;
  2037. bwMon->procBwWrite = VpuReadReg(coreIdx, RET_QUERY_BW_PROC_AXI_WRITE) * 16;
  2038. return RETCODE_SUCCESS;
  2039. }
  2040. RetCode Wave5VpuGetDebugInfo(CodecInst* instance, VPUDebugInfo* info)
  2041. {
  2042. RetCode ret = RETCODE_SUCCESS;
  2043. Int32 coreIdx;
  2044. coreIdx = instance->coreIdx;
  2045. ret = SendQuery(instance, GET_DEBUG_INFO);
  2046. if (ret != RETCODE_SUCCESS) {
  2047. if (VpuReadReg(coreIdx, W5_RET_FAIL_REASON) == WAVE5_RESULT_NOT_READY)
  2048. return RETCODE_REPORT_NOT_READY;
  2049. else
  2050. return RETCODE_QUERY_FAILURE;
  2051. }
  2052. info->priReason = VpuReadReg(coreIdx, W5_RET_QUERY_DEBUG_PRI_REASON);
  2053. return RETCODE_SUCCESS;
  2054. }
  2055. /************************************************************************/
  2056. /* ENCODER functions */
  2057. /************************************************************************/
  2058. RetCode Wave5VpuEncUpdateBS(CodecInst* instance, BOOL updateNewBsbuf)
  2059. {
  2060. EncInfo* pEncInfo;
  2061. Int32 coreIdx;
  2062. Uint32 regVal = 0, bsEndian;
  2063. EncOpenParam* pOpenParam;
  2064. pEncInfo = VPU_HANDLE_TO_ENCINFO(instance);
  2065. pOpenParam = &pEncInfo->openParam;
  2066. coreIdx = instance->coreIdx;
  2067. regVal = vdi_convert_endian(coreIdx, pOpenParam->streamEndian);
  2068. bsEndian = (~regVal&VDI_128BIT_ENDIAN_MASK);
  2069. VpuWriteReg(coreIdx, W5_CMD_ENC_BS_START_ADDR, pEncInfo->streamRdPtr);
  2070. VpuWriteReg(coreIdx, W5_CMD_ENC_BS_SIZE, pEncInfo->streamBufSize);
  2071. VpuWriteReg(coreIdx, W5_BS_OPTION, (pEncInfo->lineBufIntEn<<6) | bsEndian);
  2072. Wave5BitIssueCommand(instance, W5_UPDATE_BS);
  2073. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  2074. return RETCODE_VPU_RESPONSE_TIMEOUT;
  2075. }
  2076. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == 0) {
  2077. return RETCODE_FAILURE;
  2078. }
  2079. return RETCODE_SUCCESS;
  2080. }
  2081. RetCode Wave5VpuEncGetRdWrPtr(CodecInst* instance, PhysicalAddress *rdPtr, PhysicalAddress *wrPtr)
  2082. {
  2083. EncInfo* pEncInfo = VPU_HANDLE_TO_ENCINFO(instance);
  2084. RetCode ret = RETCODE_SUCCESS;
  2085. VpuWriteReg(instance->coreIdx, W5_CMD_ENC_REASON_SEL, pEncInfo->encWrPtrSel);
  2086. ret = SendQuery(instance, GET_BS_WR_PTR);
  2087. if (ret != RETCODE_SUCCESS)
  2088. return RETCODE_QUERY_FAILURE;
  2089. *rdPtr = VpuReadReg(instance->coreIdx, W5_RET_ENC_RD_PTR);
  2090. *wrPtr = VpuReadReg(instance->coreIdx, W5_RET_ENC_WR_PTR);
  2091. return RETCODE_SUCCESS;
  2092. }
  2093. RetCode Wave5VpuBuildUpEncParam(CodecInst* instance, EncOpenParam* param)
  2094. {
  2095. RetCode ret = RETCODE_SUCCESS;
  2096. EncInfo* pEncInfo;
  2097. VpuAttr* pAttr = &g_VpuCoreAttributes[instance->coreIdx];
  2098. vpu_buffer_t vb;
  2099. Uint32 regVal = 0;
  2100. Uint32 bsEndian;
  2101. pEncInfo = VPU_HANDLE_TO_ENCINFO(instance);
  2102. pEncInfo->streamRdPtrRegAddr = W5_RET_ENC_RD_PTR;
  2103. pEncInfo->streamWrPtrRegAddr = W5_RET_ENC_WR_PTR;
  2104. pEncInfo->currentPC = W5_VCPU_CUR_PC;
  2105. pEncInfo->busyFlagAddr = W5_VPU_BUSY_STATUS;
  2106. if ((pAttr->supportEncoders&(1<<param->bitstreamFormat)) == 0)
  2107. return RETCODE_NOT_SUPPORTED_FEATURE;
  2108. if (param->bitstreamFormat == STD_HEVC)
  2109. instance->codecMode = W_HEVC_ENC;
  2110. else if (param->bitstreamFormat == STD_SVAC)
  2111. instance->codecMode = W_SVAC_ENC;
  2112. else if (param->bitstreamFormat == STD_AVC)
  2113. instance->codecMode = W_AVC_ENC;
  2114. vdi_get_common_memory(instance->coreIdx, &vb);
  2115. pEncInfo->vbTemp.base = vb.phys_addr + WAVE5_TEMPBUF_OFFSET;
  2116. pEncInfo->vbTemp.phys_addr = pEncInfo->vbTemp.base;
  2117. pEncInfo->vbTemp.virt_addr = pEncInfo->vbTemp.base;
  2118. pEncInfo->vbTemp.size = WAVE5_TEMPBUF_SIZE;
  2119. if (instance->productId == PRODUCT_ID_521)
  2120. pEncInfo->vbWork.size = WAVE521ENC_WORKBUF_SIZE;
  2121. if (vdi_allocate_dma_memory(instance->coreIdx, &pEncInfo->vbWork, ENC_WORK, instance->instIndex) < 0) {
  2122. pEncInfo->vbWork.base = 0;
  2123. pEncInfo->vbWork.phys_addr = 0;
  2124. pEncInfo->vbWork.size = 0;
  2125. pEncInfo->vbWork.virt_addr = 0;
  2126. return RETCODE_INSUFFICIENT_RESOURCE;
  2127. }
  2128. vdi_clear_memory(instance->coreIdx, pEncInfo->vbWork.phys_addr, pEncInfo->vbWork.size, 0);
  2129. VpuWriteReg(instance->coreIdx, W5_ADDR_WORK_BASE, pEncInfo->vbWork.phys_addr);
  2130. VpuWriteReg(instance->coreIdx, W5_WORK_SIZE, pEncInfo->vbWork.size);
  2131. regVal = vdi_convert_endian(instance->coreIdx, param->streamEndian);
  2132. bsEndian = (~regVal&VDI_128BIT_ENDIAN_MASK);
  2133. regVal = (param->lowLatencyMode<<7) | (param->lineBufIntEn<<6) | bsEndian;
  2134. VpuWriteReg(instance->coreIdx, W5_CMD_BS_PARAM, regVal);
  2135. VpuWriteReg(instance->coreIdx, W5_CMD_NUM_CQ_DEPTH_M1, COMMAND_QUEUE_DEPTH -1 );
  2136. regVal = 0;
  2137. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  2138. regVal |= (param->srcReleaseIntEnable<<2);
  2139. #endif
  2140. VpuWriteReg(instance->coreIdx, W5_CMD_ENC_SRC_OPTIONS, regVal);
  2141. VpuWriteReg(instance->coreIdx, W5_VPU_BUSY_STATUS, 1);
  2142. VpuWriteReg(instance->coreIdx, W5_RET_SUCCESS, 0); //for debug
  2143. VpuWriteReg(instance->coreIdx, W5_CMD_ENC_VCORE_INFO, 1);
  2144. Wave5BitIssueCommand(instance, W5_CREATE_INSTANCE);
  2145. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) { // Check QUEUE_DONE
  2146. if (instance->loggingEnable)
  2147. vdi_log(instance->coreIdx, W5_CREATE_INSTANCE, 2);
  2148. vdi_free_dma_memory(instance->coreIdx, &pEncInfo->vbWork, ENC_WORK, instance->instIndex);
  2149. return RETCODE_VPU_RESPONSE_TIMEOUT;
  2150. }
  2151. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE) { // FAILED for adding into VCPU QUEUE
  2152. vdi_free_dma_memory(instance->coreIdx, &pEncInfo->vbWork, ENC_WORK, instance->instIndex);
  2153. regVal = VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON);
  2154. if (regVal != WAVE5_QUEUEING_FAIL)
  2155. VLOG(ERR, "FAIL_REASON = 0x%x\n", regVal);
  2156. if (regVal == 2)
  2157. ret = RETCODE_INVALID_SFS_INSTANCE;
  2158. else if (regVal == WAVE5_SYSERR_WATCHDOG_TIMEOUT)
  2159. ret = RETCODE_VPU_RESPONSE_TIMEOUT;
  2160. else if (regVal == WAVE5_ERROR_FW_FATAL)
  2161. ret = RETCODE_ERROR_FW_FATAL;
  2162. else
  2163. ret = RETCODE_FAILURE;
  2164. }
  2165. pEncInfo->streamRdPtr = param->bitstreamBuffer;
  2166. pEncInfo->streamWrPtr = param->bitstreamBuffer;
  2167. pEncInfo->lineBufIntEn = param->lineBufIntEn;
  2168. pEncInfo->streamBufStartAddr = param->bitstreamBuffer;
  2169. pEncInfo->streamBufSize = param->bitstreamBufferSize;
  2170. pEncInfo->streamBufEndAddr = param->bitstreamBuffer + param->bitstreamBufferSize;
  2171. pEncInfo->streamBufTobeReadStartAddr = param->bitstreamBuffer;
  2172. pEncInfo->streamBufTobeReadSize = param->bitstreamBufferSize;
  2173. pEncInfo->streamBufTobeReadEndAddr = param->bitstreamBuffer + param->bitstreamBufferSize;
  2174. pEncInfo->stride = 0;
  2175. pEncInfo->vbFrame.size = 0;
  2176. pEncInfo->vbPPU.size = 0;
  2177. pEncInfo->frameAllocExt = 0;
  2178. pEncInfo->ppuAllocExt = 0;
  2179. pEncInfo->initialInfoObtained = 0;
  2180. pEncInfo->productCode = VpuReadReg(instance->coreIdx, W5_PRODUCT_NUMBER);
  2181. return ret;
  2182. }
  2183. RetCode Wave5VpuEncInitSeq(CodecInst* instance)
  2184. {
  2185. Int32 coreIdx, alignedWidth = 0, alignedHeight=0;
  2186. Uint32 regVal = 0, rotMirMode;
  2187. EncInfo* pEncInfo;
  2188. EncOpenParam* pOpenParam;
  2189. EncWaveParam* pParam;
  2190. coreIdx = instance->coreIdx;
  2191. pEncInfo = &instance->CodecInfo->encInfo;
  2192. pOpenParam = &pEncInfo->openParam;
  2193. pParam = &pOpenParam->EncStdParam.waveParam;
  2194. /*==============================================*/
  2195. /* OPT_CUSTOM_GOP */
  2196. /*==============================================*/
  2197. /*
  2198. * SET_PARAM + CUSTOM_GOP
  2199. * only when gopPresetIdx == custom_gop, custom_gop related registers should be set
  2200. */
  2201. if (pParam->gopPresetIdx == PRESET_IDX_CUSTOM_GOP) {
  2202. int i=0, j = 0;
  2203. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_SET_PARAM_OPTION, OPT_CUSTOM_GOP);
  2204. VpuWriteReg(coreIdx, W5_CMD_ENC_CUSTOM_GOP_PARAM, pParam->gopParam.customGopSize);
  2205. for (i=0 ; i<pParam->gopParam.customGopSize; i++) {
  2206. VpuWriteReg(coreIdx, W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_0 + (i*4), (pParam->gopParam.picParam[i].picType<<0) |
  2207. (pParam->gopParam.picParam[i].pocOffset<<2) |
  2208. (pParam->gopParam.picParam[i].picQp<<6) |
  2209. (pParam->gopParam.picParam[i].numRefPicL0<<12) |
  2210. ((pParam->gopParam.picParam[i].refPocL0&0x1F)<<14) |
  2211. ((pParam->gopParam.picParam[i].refPocL1&0x1F)<<19) |
  2212. (pParam->gopParam.picParam[i].temporalId<<24));
  2213. }
  2214. for (j = i; j < MAX_GOP_NUM; j++) {
  2215. VpuWriteReg(coreIdx, W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_0 + (j*4), 0);
  2216. }
  2217. Wave5BitIssueCommand(instance, W5_ENC_SET_PARAM);
  2218. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  2219. if (instance->loggingEnable)
  2220. vdi_log(coreIdx, W5_ENC_SET_PARAM, 2);
  2221. return RETCODE_VPU_RESPONSE_TIMEOUT;
  2222. }
  2223. }
  2224. /*======================================================================*/
  2225. /* OPT_COMMON */
  2226. /* : the last SET_PARAM command should be called with OPT_COMMON */
  2227. /*======================================================================*/
  2228. rotMirMode = 0;
  2229. /* CMD_ENC_ROT_MODE :
  2230. * | hor_mir | ver_mir | rot_angle | rot_en |
  2231. * [4] [3] [2:1] [0]
  2232. */
  2233. if (pEncInfo->rotationEnable == TRUE) {
  2234. switch (pEncInfo->rotationAngle) {
  2235. case 0:
  2236. rotMirMode |= 0x0;
  2237. break;
  2238. case 90:
  2239. rotMirMode |= 0x3;
  2240. break;
  2241. case 180:
  2242. rotMirMode |= 0x5;
  2243. break;
  2244. case 270:
  2245. rotMirMode |= 0x7;
  2246. break;
  2247. }
  2248. }
  2249. if (pEncInfo->mirrorEnable == TRUE) {
  2250. switch (pEncInfo->mirrorDirection) {
  2251. case MIRDIR_NONE :
  2252. rotMirMode |= 0x0;
  2253. break;
  2254. case MIRDIR_VER :
  2255. rotMirMode |= 0x9;
  2256. break;
  2257. case MIRDIR_HOR :
  2258. rotMirMode |= 0x11;
  2259. break;
  2260. case MIRDIR_HOR_VER :
  2261. rotMirMode |= 0x19;
  2262. break;
  2263. }
  2264. }
  2265. if (instance->codecMode == W_AVC_ENC) {
  2266. alignedWidth = (pOpenParam->picWidth + 15) & ~15;
  2267. alignedHeight= (pOpenParam->picHeight+ 15) & ~15;
  2268. }
  2269. else {
  2270. alignedWidth = (pOpenParam->picWidth + 31) & ~31;
  2271. alignedHeight= (pOpenParam->picHeight+ 31) & ~31;
  2272. }
  2273. if (((rotMirMode != 0) && !((pEncInfo->rotationAngle == 180) && (pEncInfo->mirrorDirection == MIRDIR_HOR_VER))) && ((pOpenParam->picWidth != alignedWidth) || (pOpenParam->picHeight != alignedHeight))) // if rot/mir enable && pic size is not 32(16)-aligned, set crop info.
  2274. CalcEncCropInfo(instance, pParam, rotMirMode, pOpenParam->picWidth, pOpenParam->picHeight);
  2275. /* SET_PARAM + COMMON */
  2276. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_SET_PARAM_OPTION, OPT_COMMON);
  2277. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_SRC_SIZE, pOpenParam->picHeight<<16 | pOpenParam->picWidth);
  2278. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MAP_ENDIAN, VDI_LITTLE_ENDIAN);
  2279. if (instance->codecMode == W_SVAC_ENC) {
  2280. regVal = (pParam->profile<<0) |
  2281. (pParam->level<<3) |
  2282. (pParam->internalBitDepth<<14) |
  2283. (pParam->useLongTerm<<21) |
  2284. (pParam->saoEnable<<24) |
  2285. (pParam->svcEnable<<28) |
  2286. (pParam->svcMode<<29);
  2287. }
  2288. else if (instance->codecMode == W_AVC_ENC) {
  2289. regVal = (pParam->profile<<0) |
  2290. (pParam->level<<3) |
  2291. (pParam->internalBitDepth<<14) |
  2292. (pParam->useLongTerm<<21) |
  2293. (pParam->scalingListEnable<<22) ;
  2294. }
  2295. else { // HEVC enc
  2296. regVal = (pParam->profile<<0) |
  2297. (pParam->level<<3) |
  2298. (pParam->tier<<12) |
  2299. (pParam->internalBitDepth<<14) |
  2300. (pParam->useLongTerm<<21) |
  2301. (pParam->scalingListEnable<<22) |
  2302. (pParam->tmvpEnable<<23) |
  2303. (pParam->saoEnable<<24) |
  2304. (pParam->skipIntraTrans<<25) |
  2305. (pParam->strongIntraSmoothEnable<<27) |
  2306. (pParam->enStillPicture<<30);
  2307. }
  2308. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_SPS_PARAM, regVal);
  2309. if (instance->codecMode == W_SVAC_ENC) {
  2310. regVal = (pParam->disableDeblk<<5) |
  2311. ((pParam->chromaDcQpOffset&0x1F)<<14) |
  2312. ((pParam->chromaAcQpOffset&0x1F)<<19) |
  2313. ((pParam->lumaDcQpOffset&0x1F)<<24);
  2314. }
  2315. else {
  2316. regVal = (pParam->losslessEnable) |
  2317. (pParam->constIntraPredFlag<<1) |
  2318. (pParam->lfCrossSliceBoundaryEnable<<2) |
  2319. ((pParam->weightPredEnable&1)<<3) |
  2320. (pParam->wppEnable<<4) |
  2321. (pParam->disableDeblk<<5) |
  2322. ((pParam->betaOffsetDiv2&0xF)<<6) |
  2323. ((pParam->tcOffsetDiv2&0xF)<<10) |
  2324. ((pParam->chromaCbQpOffset&0x1F)<<14) |
  2325. ((pParam->chromaCrQpOffset&0x1F)<<19) |
  2326. (pParam->transform8x8Enable<<29) |
  2327. (pParam->entropyCodingMode<<30);
  2328. }
  2329. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_PPS_PARAM, regVal);
  2330. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_GOP_PARAM, pParam->gopPresetIdx);
  2331. if (instance->codecMode == W_AVC_ENC) {
  2332. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_INTRA_PARAM, (pParam->intraQP<<0) | ((pParam->intraPeriod&0x7ff)<<6) | ((pParam->avcIdrPeriod&0x7ff)<<17) | ((pParam->forcedIdrHeaderEnable&3)<<28));
  2333. }
  2334. else {
  2335. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_INTRA_PARAM, (pParam->decodingRefreshType<<0) | (pParam->intraQP<<3) | (pParam->forcedIdrHeaderEnable<<9) | (pParam->intraPeriod<<16));
  2336. }
  2337. regVal = (pParam->useRecommendEncParam) |
  2338. (pParam->rdoSkip<<2) |
  2339. (pParam->lambdaScalingEnable<<3) |
  2340. (pParam->coefClearDisable<<4) |
  2341. (pParam->cuSizeMode<<5) |
  2342. (pParam->intraNxNEnable<<8) |
  2343. (pParam->maxNumMerge<<18) |
  2344. (pParam->customMDEnable<<20) |
  2345. (pParam->customLambdaEnable<<21) |
  2346. (pParam->monochromeEnable<<22);
  2347. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RDO_PARAM, regVal);
  2348. if (instance->codecMode == W_AVC_ENC) {
  2349. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_INTRA_REFRESH, pParam->intraMbRefreshArg<<16 | pParam->intraMbRefreshMode);
  2350. }
  2351. else {
  2352. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_INTRA_REFRESH, pParam->intraRefreshArg<<16 | pParam->intraRefreshMode);
  2353. }
  2354. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_FRAME_RATE, pOpenParam->frameRateInfo);
  2355. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_TARGET_RATE, pOpenParam->bitRate);
  2356. if (instance->codecMode == W_AVC_ENC) {
  2357. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_PARAM, (pOpenParam->rcEnable<<0) |
  2358. (pParam->mbLevelRcEnable<<1) |
  2359. (pParam->hvsQPEnable<<2) |
  2360. (pParam->hvsQpScale<<4) |
  2361. (pParam->bitAllocMode<<8) |
  2362. (pParam->roiEnable<<13) |
  2363. ((pParam->initialRcQp&0x3F)<<14) |
  2364. (pOpenParam->vbvBufferSize<<20));
  2365. }
  2366. else {
  2367. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_PARAM, (pOpenParam->rcEnable<<0) |
  2368. (pParam->cuLevelRCEnable<<1) |
  2369. (pParam->hvsQPEnable<<2) |
  2370. (pParam->hvsQpScale<<4) |
  2371. (pParam->bitAllocMode<<8) |
  2372. (pParam->roiEnable<<13) |
  2373. ((pParam->initialRcQp&0x3F)<<14) |
  2374. (pOpenParam->vbvBufferSize<<20));
  2375. }
  2376. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_WEIGHT_PARAM, pParam->rcWeightBuf<<8 | pParam->rcWeightParam);
  2377. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_MIN_MAX_QP, (pParam->minQpI<<0) |
  2378. (pParam->maxQpI<<6) |
  2379. (pParam->hvsMaxDeltaQp<<12));
  2380. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_INTER_MIN_MAX_QP, (pParam->minQpP << 0) |
  2381. (pParam->maxQpP << 6) |
  2382. (pParam->minQpB << 12) |
  2383. (pParam->maxQpB << 18));
  2384. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3, (pParam->fixedBitRatio[0]<<0) |
  2385. (pParam->fixedBitRatio[1]<<8) |
  2386. (pParam->fixedBitRatio[2]<<16) |
  2387. (pParam->fixedBitRatio[3]<<24));
  2388. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7, (pParam->fixedBitRatio[4]<<0) |
  2389. (pParam->fixedBitRatio[5]<<8) |
  2390. (pParam->fixedBitRatio[6]<<16) |
  2391. (pParam->fixedBitRatio[7]<<24));
  2392. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_ROT_PARAM, rotMirMode);
  2393. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_BG_PARAM, (pParam->bgDetectEnable) |
  2394. (pParam->bgThrDiff<<1) |
  2395. (pParam->bgThrMeanDiff<<10) |
  2396. (pParam->bgLambdaQp<<18) |
  2397. ((pParam->bgDeltaQp&0x1F)<<24) |
  2398. (instance->codecMode == W_AVC_ENC ? pParam->s2fmeDisable<<29 : 0));
  2399. if (instance->codecMode == W_HEVC_ENC || instance->codecMode == W_AVC_ENC) {
  2400. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR, pParam->customLambdaAddr);
  2401. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT, pParam->confWinBot<<16 | pParam->confWinTop);
  2402. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT, pParam->confWinRight<<16 | pParam->confWinLeft);
  2403. if (instance->codecMode == W_AVC_ENC) {
  2404. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, pParam->avcSliceArg<<16 | pParam->avcSliceMode);
  2405. }
  2406. else {
  2407. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, pParam->independSliceModeArg<<16 | pParam->independSliceMode);
  2408. }
  2409. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR, pParam->userScalingListAddr);
  2410. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK, pParam->numUnitsInTick);
  2411. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_TIME_SCALE, pParam->timeScale);
  2412. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE, pParam->numTicksPocDiffOne);
  2413. }
  2414. if (instance->codecMode == W_HEVC_ENC) {
  2415. // SVAC encoder can't configure below parameters
  2416. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_PU04, (pParam->pu04DeltaRate&0xFF) |
  2417. ((pParam->pu04IntraPlanarDeltaRate&0xFF)<<8) |
  2418. ((pParam->pu04IntraDcDeltaRate&0xFF)<<16) |
  2419. ((pParam->pu04IntraAngleDeltaRate&0xFF)<<24));
  2420. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_PU08, (pParam->pu08DeltaRate&0xFF) |
  2421. ((pParam->pu08IntraPlanarDeltaRate&0xFF)<<8) |
  2422. ((pParam->pu08IntraDcDeltaRate&0xFF)<<16) |
  2423. ((pParam->pu08IntraAngleDeltaRate&0xFF)<<24));
  2424. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_PU16, (pParam->pu16DeltaRate&0xFF) |
  2425. ((pParam->pu16IntraPlanarDeltaRate&0xFF)<<8) |
  2426. ((pParam->pu16IntraDcDeltaRate&0xFF)<<16) |
  2427. ((pParam->pu16IntraAngleDeltaRate&0xFF)<<24));
  2428. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_PU32, (pParam->pu32DeltaRate&0xFF) |
  2429. ((pParam->pu32IntraPlanarDeltaRate&0xFF)<<8) |
  2430. ((pParam->pu32IntraDcDeltaRate&0xFF)<<16) |
  2431. ((pParam->pu32IntraAngleDeltaRate&0xFF)<<24));
  2432. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_CU08, (pParam->cu08IntraDeltaRate&0xFF) |
  2433. ((pParam->cu08InterDeltaRate&0xFF)<<8) |
  2434. ((pParam->cu08MergeDeltaRate&0xFF)<<16));
  2435. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_CU16, (pParam->cu16IntraDeltaRate&0xFF) |
  2436. ((pParam->cu16InterDeltaRate&0xFF)<<8) |
  2437. ((pParam->cu16MergeDeltaRate&0xFF)<<16));
  2438. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_CU32, (pParam->cu32IntraDeltaRate&0xFF) |
  2439. ((pParam->cu32InterDeltaRate&0xFF)<<8) |
  2440. ((pParam->cu32MergeDeltaRate&0xFF)<<16));
  2441. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_DEPENDENT_SLICE, pParam->dependSliceModeArg<<16 | pParam->dependSliceMode);
  2442. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_NR_PARAM, (pParam->nrYEnable<<0) |
  2443. (pParam->nrCbEnable<<1) |
  2444. (pParam->nrCrEnable<<2) |
  2445. (pParam->nrNoiseEstEnable<<3)|
  2446. (pParam->nrNoiseSigmaY<<4) |
  2447. (pParam->nrNoiseSigmaCb<<12) |
  2448. (pParam->nrNoiseSigmaCr<<20));
  2449. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_NR_WEIGHT, (pParam->nrIntraWeightY<<0) |
  2450. (pParam->nrIntraWeightCb<<5) |
  2451. (pParam->nrIntraWeightCr<<10)|
  2452. (pParam->nrInterWeightY<<15) |
  2453. (pParam->nrInterWeightCb<<20)|
  2454. (pParam->nrInterWeightCr<<25));
  2455. }
  2456. #ifdef SUPPORT_LOOK_AHEAD_RC
  2457. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_LOOK_AHEAD_RC, (pParam->larcEnable<<0) |
  2458. ((pParam->larcPass-1)<<1) |
  2459. (pParam->larcSize<<2) |
  2460. (pParam->larcWeight<<9));
  2461. #endif
  2462. Wave5BitIssueCommand(instance, W5_ENC_SET_PARAM);
  2463. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  2464. if (instance->loggingEnable)
  2465. vdi_log(coreIdx, W5_ENC_SET_PARAM, 2);
  2466. return RETCODE_VPU_RESPONSE_TIMEOUT;
  2467. }
  2468. if (VpuReadReg(coreIdx, W5_RET_SUCCESS) == 0) {
  2469. regVal = VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON);
  2470. if (regVal != WAVE5_QUEUEING_FAIL)
  2471. VLOG(ERR, "FAIL_REASON = 0x%x\n", regVal);
  2472. if ( regVal == WAVE5_QUEUEING_FAIL)
  2473. return RETCODE_QUEUEING_FAILURE;
  2474. else if (regVal == WAVE5_SYSERR_ACCESS_VIOLATION_HW)
  2475. return RETCODE_MEMORY_ACCESS_VIOLATION;
  2476. else if (regVal == WAVE5_SYSERR_WATCHDOG_TIMEOUT)
  2477. return RETCODE_VPU_RESPONSE_TIMEOUT;
  2478. else if (regVal == WAVE5_ERROR_FW_FATAL)
  2479. return RETCODE_ERROR_FW_FATAL;
  2480. else
  2481. return RETCODE_FAILURE;
  2482. }
  2483. return RETCODE_SUCCESS;
  2484. }
  2485. #ifdef SUPPORT_LOOK_AHEAD_RC
  2486. #define LARC_DATA_REG_CNT 16
  2487. RetCode Wave5VpuEncSetLarcData(CodecInst* instance, EncLarcInfo larcInfo)
  2488. {
  2489. Int32 coreIdx;
  2490. EncInfo* pEncInfo;
  2491. EncOpenParam* pOpenParam;
  2492. EncWaveParam* pParam;
  2493. Uint32 regVal = 0;
  2494. Uint32 i, addr, k, remain;
  2495. Uint32 quotient;
  2496. Uint32 larcSizeMinus1;
  2497. coreIdx = instance->coreIdx;
  2498. pEncInfo = &instance->CodecInfo->encInfo;
  2499. pOpenParam = &pEncInfo->openParam;
  2500. pParam = &pOpenParam->EncStdParam.waveParam;
  2501. EnterLock(coreIdx);
  2502. larcSizeMinus1 = pParam->larcSize-1;
  2503. quotient = VPU_ALIGN16(larcSizeMinus1)/LARC_DATA_REG_CNT;//16 registers
  2504. if (pParam->larcEnable == TRUE) {
  2505. remain = larcSizeMinus1;
  2506. for ( k=0, i = 0 ; i < quotient ; i++ ) {
  2507. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_SET_PARAM_OPTION, OPT_LOOKAHEAD_PARAM_1+i);
  2508. for (addr = W5_CMD_ENC_SEQ_LOOK_AHEAD_RC_START ; addr < W5_CMD_ENC_SEQ_LOOK_AHEAD_RC_END ;addr+=12) {
  2509. if ( k < larcSizeMinus1) {
  2510. VpuWriteReg(coreIdx, addr, larcInfo.larcData[k][0]);
  2511. VpuWriteReg(coreIdx, addr+4, larcInfo.larcData[k][1]);
  2512. VpuWriteReg(coreIdx, addr+8, larcInfo.larcData[k][2]);
  2513. // VLOG(ERR, "PASS2 set (%d) = %x, %x, %x\n", k, larcInfo.larcData[k][0], larcInfo.larcData[k][1], larcInfo.larcData[k][2]);
  2514. }
  2515. else {
  2516. VpuWriteReg(coreIdx, addr, -1);
  2517. // VLOG(ERR, "PASS2 set (%d) = -1\n", k);
  2518. }
  2519. k++;
  2520. }
  2521. remain -= LARC_DATA_REG_CNT;
  2522. Wave5BitIssueCommand(instance, W5_ENC_SET_PARAM);
  2523. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  2524. if (instance->loggingEnable)
  2525. vdi_log(coreIdx, W5_ENC_SET_PARAM, 2);
  2526. return RETCODE_VPU_RESPONSE_TIMEOUT;
  2527. }
  2528. if (VpuReadReg(coreIdx, W5_RET_SUCCESS) == 0) {
  2529. regVal = VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON);
  2530. if ( regVal == WAVE5_QUEUEING_FAIL)
  2531. return RETCODE_QUEUEING_FAILURE;
  2532. else if (regVal == WAVE5_SYSERR_ACCESS_VIOLATION_HW)
  2533. return RETCODE_MEMORY_ACCESS_VIOLATION;
  2534. else if (regVal == WAVE5_SYSERR_WATCHDOG_TIMEOUT)
  2535. return RETCODE_VPU_RESPONSE_TIMEOUT;
  2536. else
  2537. return RETCODE_FAILURE;
  2538. }
  2539. }
  2540. }
  2541. LeaveLock(coreIdx);
  2542. return RETCODE_SUCCESS;
  2543. }
  2544. #endif
  2545. RetCode Wave5VpuEncGetSeqInfo(CodecInst* instance, EncInitialInfo* info)
  2546. {
  2547. RetCode ret = RETCODE_SUCCESS;
  2548. Uint32 regVal;
  2549. EncInfo* pEncInfo;
  2550. pEncInfo = VPU_HANDLE_TO_ENCINFO(instance);
  2551. // Send QUERY cmd
  2552. ret = SendQuery(instance, GET_RESULT);
  2553. if (ret != RETCODE_SUCCESS) {
  2554. regVal = VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON);
  2555. if (regVal != WAVE5_QUEUEING_FAIL)
  2556. VLOG(ERR, "FAIL_REASON = 0x%x\n", regVal);
  2557. if (regVal == WAVE5_RESULT_NOT_READY)
  2558. return RETCODE_REPORT_NOT_READY;
  2559. else if(regVal == WAVE5_SYSERR_ACCESS_VIOLATION_HW)
  2560. return RETCODE_MEMORY_ACCESS_VIOLATION;
  2561. else if (regVal == WAVE5_SYSERR_WATCHDOG_TIMEOUT)
  2562. return RETCODE_VPU_RESPONSE_TIMEOUT;
  2563. else if (regVal == WAVE5_ERROR_FW_FATAL)
  2564. return RETCODE_ERROR_FW_FATAL;
  2565. else
  2566. return RETCODE_QUERY_FAILURE;
  2567. }
  2568. if (instance->loggingEnable)
  2569. vdi_log(instance->coreIdx, W5_INIT_SEQ, 0);
  2570. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_STATUS);
  2571. pEncInfo->instanceQueueCount = (regVal>>16)&0xff;
  2572. pEncInfo->reportQueueCount = (regVal & 0xffff);
  2573. if (VpuReadReg(instance->coreIdx, W5_RET_ENC_ENCODING_SUCCESS) != 1) {
  2574. info->seqInitErrReason = VpuReadReg(instance->coreIdx, W5_RET_ENC_ERR_INFO);
  2575. ret = RETCODE_FAILURE;
  2576. }
  2577. else {
  2578. info->warnInfo = VpuReadReg(instance->coreIdx, W5_RET_ENC_WARN_INFO);
  2579. }
  2580. info->minFrameBufferCount = VpuReadReg(instance->coreIdx, W5_RET_ENC_NUM_REQUIRED_FB);
  2581. info->minSrcFrameCount = VpuReadReg(instance->coreIdx, W5_RET_ENC_MIN_SRC_BUF_NUM);
  2582. info->maxLatencyPictures = VpuReadReg(instance->coreIdx, W5_RET_ENC_PIC_MAX_LATENCY_PICTURES);
  2583. info->vlcBufSize = VpuReadReg(instance->coreIdx, W5_RET_VLC_BUF_SIZE);
  2584. info->paramBufSize = VpuReadReg(instance->coreIdx, W5_RET_PARAM_BUF_SIZE);
  2585. pEncInfo->vlcBufSize = info->vlcBufSize;
  2586. pEncInfo->paramBufSize = info->paramBufSize;
  2587. return ret;
  2588. }
  2589. RetCode Wave5VpuEncRegisterFramebuffer(CodecInst* inst, FrameBuffer* fbArr, TiledMapType mapType, Uint32 count)
  2590. {
  2591. RetCode ret = RETCODE_SUCCESS;
  2592. Int32 q, j, i, remain, idx, coreIdx, startNo, endNo, stride;
  2593. Uint32 regVal=0, picSize=0, mvColSize, fbcYTblSize, fbcCTblSize, subSampledSize=0;
  2594. Uint32 endian, nv21=0, cbcrInterleave = 0, lumaStride, chromaStride, bufHeight = 0, bufWidth = 0;
  2595. Uint32 addrY, addrCb, addrCr;
  2596. Uint32 svacMvColSize0 = 0, svacMvColSize1 = 0;
  2597. vpu_buffer_t vbMV = {0,};
  2598. vpu_buffer_t vbFbcYTbl = {0,};
  2599. vpu_buffer_t vbFbcCTbl = {0,};
  2600. vpu_buffer_t vbSubSamBuf = {0,};
  2601. vpu_buffer_t vbTask = {0,};
  2602. EncOpenParam* pOpenParam;
  2603. EncInfo* pEncInfo = &inst->CodecInfo->encInfo;
  2604. pOpenParam = &pEncInfo->openParam;
  2605. coreIdx = inst->coreIdx;
  2606. mvColSize = fbcYTblSize = fbcCTblSize = 0;
  2607. stride = pEncInfo->stride;
  2608. bufWidth = VPU_ALIGN8(pOpenParam->picWidth);
  2609. bufHeight = VPU_ALIGN8(pOpenParam->picHeight);
  2610. if (mapType == COMPRESSED_FRAME_MAP_SVAC_SVC_BL) {
  2611. bufWidth = pOpenParam->picWidthBL;
  2612. bufHeight = pOpenParam->picHeightBL;
  2613. }
  2614. if ((pEncInfo->rotationAngle != 0 || pEncInfo->mirrorDirection != 0) && !(pEncInfo->rotationAngle == 180 && pEncInfo->mirrorDirection == MIRDIR_HOR_VER)) {
  2615. bufWidth = VPU_ALIGN32(pOpenParam->picWidth);
  2616. bufHeight = VPU_ALIGN32(pOpenParam->picHeight);
  2617. }
  2618. if (pEncInfo->rotationAngle == 90 || pEncInfo->rotationAngle == 270) {
  2619. bufWidth = VPU_ALIGN32(pOpenParam->picHeight);
  2620. bufHeight = VPU_ALIGN32(pOpenParam->picWidth);
  2621. }
  2622. svacMvColSize0 = WAVE5_ENC_SVAC_MVCOL_0_BUF_SIZE(bufWidth, bufHeight);
  2623. svacMvColSize1 = WAVE5_ENC_SVAC_MVCOL_1_BUF_SIZE(bufWidth, bufHeight);
  2624. picSize = (bufWidth<<16) | bufHeight;
  2625. if (mapType >= COMPRESSED_FRAME_MAP) {
  2626. nv21 = 0;
  2627. cbcrInterleave = 0;
  2628. if (inst->codecMode == W_SVAC_ENC) {
  2629. mvColSize = svacMvColSize0 + svacMvColSize1;
  2630. vbMV.phys_addr = 0;
  2631. vbMV.size = ((mvColSize+4095)&~4095)+4096; /* 4096 is a margin */
  2632. }
  2633. else if (inst->codecMode == W_HEVC_ENC) {
  2634. mvColSize = WAVE5_ENC_HEVC_MVCOL_BUF_SIZE(bufWidth, bufHeight);
  2635. mvColSize = VPU_ALIGN16(mvColSize);
  2636. vbMV.phys_addr = 0;
  2637. vbMV.size = ((mvColSize*count+4095)&~4095)+4096; /* 4096 is a margin */
  2638. }
  2639. else if (inst->codecMode == W_AVC_ENC) {
  2640. mvColSize = WAVE5_ENC_AVC_MVCOL_BUF_SIZE(bufWidth, bufHeight);
  2641. vbMV.phys_addr = 0;
  2642. vbMV.size = ((mvColSize*count+4095)&~4095)+4096; /* 4096 is a margin */
  2643. }
  2644. if (vdi_allocate_dma_memory(inst->coreIdx, &vbMV, ENC_MV, inst->instIndex) < 0)
  2645. return RETCODE_INSUFFICIENT_RESOURCE;
  2646. if (mapType == COMPRESSED_FRAME_MAP_SVAC_SVC_BL)
  2647. pEncInfo->vbMVBL = vbMV;
  2648. else
  2649. pEncInfo->vbMV = vbMV;
  2650. if (pEncInfo->productCode == WAVE521C_DUAL_CODE) {
  2651. Uint32 bgs_width, ot_bg_width, comp_frm_width, ot_frm_width, ot_bg_height, bgs_height, comp_frm_height, ot_frm_height;
  2652. Uint32 frm_width, frm_height;
  2653. bgs_width = (pOpenParam->EncStdParam.waveParam.internalBitDepth >8 ? 256 : 512);
  2654. ot_bg_width = 1024;
  2655. frm_width = VPU_CEIL(bufWidth, 16);
  2656. frm_height = VPU_CEIL(bufHeight, 16);
  2657. comp_frm_width = VPU_CEIL(VPU_CEIL(frm_width , 16) + 16, 16); // valid_width = align(width, 16), comp_frm_width = align(valid_width+pad_x, 16)
  2658. ot_frm_width = VPU_CEIL(comp_frm_width, ot_bg_width); // 1024 = offset table BG width
  2659. // sizeof_offset_table()
  2660. ot_bg_height = 32;
  2661. bgs_height = (1<<14) / bgs_width / (pOpenParam->EncStdParam.waveParam.internalBitDepth>8 ? 2 : 1);
  2662. comp_frm_height = VPU_CEIL(VPU_CEIL(frm_height, 4) + 4, bgs_height);
  2663. ot_frm_height = VPU_CEIL(comp_frm_height, ot_bg_height);
  2664. fbcYTblSize = (ot_frm_width/16) * (ot_frm_height/4) *2;
  2665. }
  2666. else {
  2667. fbcYTblSize = WAVE5_FBC_LUMA_TABLE_SIZE(bufWidth, bufHeight);
  2668. fbcYTblSize = VPU_ALIGN16(fbcYTblSize);
  2669. }
  2670. vbFbcYTbl.phys_addr = 0;
  2671. vbFbcYTbl.size = ((fbcYTblSize*count+4095)&~4095)+4096;
  2672. if (vdi_allocate_dma_memory(inst->coreIdx, &vbFbcYTbl, ENC_FBCY_TBL, inst->instIndex) < 0)
  2673. return RETCODE_INSUFFICIENT_RESOURCE;
  2674. if (mapType == COMPRESSED_FRAME_MAP_SVAC_SVC_BL)
  2675. pEncInfo->vbFbcYTblBL = vbFbcYTbl;
  2676. else
  2677. pEncInfo->vbFbcYTbl = vbFbcYTbl;
  2678. if (pEncInfo->productCode == WAVE521C_DUAL_CODE) {
  2679. Uint32 bgs_width, ot_bg_width, comp_frm_width, ot_frm_width, ot_bg_height, bgs_height, comp_frm_height, ot_frm_height;
  2680. Uint32 frm_width, frm_height;
  2681. bgs_width = (pOpenParam->EncStdParam.waveParam.internalBitDepth >8 ? 256 : 512);
  2682. ot_bg_width = 1024;
  2683. frm_width = VPU_CEIL(bufWidth, 16);
  2684. frm_height = VPU_CEIL(bufHeight, 16);
  2685. comp_frm_width = VPU_CEIL(VPU_CEIL(frm_width/2 , 16) + 16, 16); // valid_width = align(width, 16), comp_frm_width = align(valid_width+pad_x, 16)
  2686. ot_frm_width = VPU_CEIL(comp_frm_width, ot_bg_width); // 1024 = offset table BG width
  2687. // sizeof_offset_table()
  2688. ot_bg_height = 32;
  2689. bgs_height = (1<<14) / bgs_width / (pOpenParam->EncStdParam.waveParam.internalBitDepth>8 ? 2 : 1);
  2690. comp_frm_height = VPU_CEIL(VPU_CEIL(frm_height, 4) + 4, bgs_height);
  2691. ot_frm_height = VPU_CEIL(comp_frm_height, ot_bg_height);
  2692. fbcCTblSize = (ot_frm_width/16) * (ot_frm_height/4) *2;
  2693. }
  2694. else {
  2695. fbcCTblSize = WAVE5_FBC_CHROMA_TABLE_SIZE(bufWidth, bufHeight);
  2696. fbcCTblSize = VPU_ALIGN16(fbcCTblSize);
  2697. }
  2698. vbFbcCTbl.phys_addr = 0;
  2699. vbFbcCTbl.size = ((fbcCTblSize*count+4095)&~4095)+4096;
  2700. if (vdi_allocate_dma_memory(inst->coreIdx, &vbFbcCTbl, ENC_FBCC_TBL, inst->instIndex) < 0)
  2701. return RETCODE_INSUFFICIENT_RESOURCE;
  2702. if (mapType == COMPRESSED_FRAME_MAP_SVAC_SVC_BL)
  2703. pEncInfo->vbFbcCTblBL = vbFbcCTbl;
  2704. else
  2705. pEncInfo->vbFbcCTbl = vbFbcCTbl;
  2706. if (pOpenParam->bitstreamFormat == STD_AVC) {
  2707. subSampledSize = WAVE5_AVC_SUBSAMPLED_ONE_SIZE(bufWidth, bufHeight);
  2708. }
  2709. else {
  2710. subSampledSize = WAVE5_SUBSAMPLED_ONE_SIZE(bufWidth, bufHeight);
  2711. }
  2712. vbSubSamBuf.size = ((subSampledSize*count+4095)&~4095)+4096;
  2713. vbSubSamBuf.phys_addr = 0;
  2714. if (vdi_allocate_dma_memory(coreIdx, &vbSubSamBuf, ENC_SUBSAMBUF, inst->instIndex) < 0)
  2715. return RETCODE_INSUFFICIENT_RESOURCE;
  2716. if (mapType == COMPRESSED_FRAME_MAP_SVAC_SVC_BL)
  2717. pEncInfo->vbSubSamBufBL = vbSubSamBuf;
  2718. else
  2719. pEncInfo->vbSubSamBuf = vbSubSamBuf;
  2720. vbTask.size = (Uint32)((pEncInfo->vlcBufSize * VLC_BUF_NUM) + (pEncInfo->paramBufSize * COMMAND_QUEUE_DEPTH));
  2721. vbTask.phys_addr = 0;
  2722. if (pEncInfo->vbTask.size == 0) {
  2723. if (vdi_allocate_dma_memory(coreIdx, &vbTask, ENC_TASK, inst->instIndex) < 0)
  2724. return RETCODE_INSUFFICIENT_RESOURCE;
  2725. pEncInfo->vbTask = vbTask;
  2726. VpuWriteReg(coreIdx, W5_CMD_SET_FB_ADDR_TASK_BUF, pEncInfo->vbTask.phys_addr);
  2727. VpuWriteReg(coreIdx, W5_CMD_SET_FB_TASK_BUF_SIZE, vbTask.size);
  2728. }
  2729. }
  2730. VpuWriteReg(coreIdx, W5_ADDR_SUB_SAMPLED_FB_BASE, vbSubSamBuf.phys_addr); // set sub-sampled buffer base addr
  2731. VpuWriteReg(coreIdx, W5_SUB_SAMPLED_ONE_FB_SIZE, subSampledSize); // set sub-sampled buffer size for one frame
  2732. endian = vdi_convert_endian(coreIdx, fbArr[0].endian);
  2733. VpuWriteReg(coreIdx, W5_PIC_SIZE, picSize);
  2734. // set stride of Luma/Chroma for compressed buffer
  2735. if ((pEncInfo->rotationAngle != 0 || pEncInfo->mirrorDirection != 0) && !(pEncInfo->rotationAngle == 180 && pEncInfo->mirrorDirection == MIRDIR_HOR_VER)){
  2736. lumaStride = VPU_ALIGN32(bufWidth)*(pOpenParam->EncStdParam.waveParam.internalBitDepth >8 ? 5 : 4);
  2737. lumaStride = VPU_ALIGN32(lumaStride);
  2738. chromaStride = VPU_ALIGN16(bufWidth/2)*(pOpenParam->EncStdParam.waveParam.internalBitDepth >8 ? 5 : 4);
  2739. chromaStride = VPU_ALIGN32(chromaStride);
  2740. }
  2741. else {
  2742. if (mapType == COMPRESSED_FRAME_MAP_SVAC_SVC_BL) {
  2743. lumaStride = VPU_ALIGN16(pOpenParam->picWidthBL)*(pOpenParam->EncStdParam.waveParam.internalBitDepth >8 ? 5 : 4);
  2744. lumaStride = VPU_ALIGN32(lumaStride);
  2745. chromaStride = VPU_ALIGN16(pOpenParam->picWidthBL/2)*(pOpenParam->EncStdParam.waveParam.internalBitDepth >8 ? 5 : 4);
  2746. chromaStride = VPU_ALIGN32(chromaStride);
  2747. }
  2748. else {
  2749. lumaStride = VPU_ALIGN16(pOpenParam->picWidth)*(pOpenParam->EncStdParam.waveParam.internalBitDepth >8 ? 5 : 4);
  2750. lumaStride = VPU_ALIGN32(lumaStride);
  2751. chromaStride = VPU_ALIGN16(pOpenParam->picWidth/2)*(pOpenParam->EncStdParam.waveParam.internalBitDepth >8 ? 5 : 4);
  2752. chromaStride = VPU_ALIGN32(chromaStride);
  2753. }
  2754. }
  2755. VpuWriteReg(coreIdx, W5_FBC_STRIDE, lumaStride<<16 | chromaStride);
  2756. cbcrInterleave = pOpenParam->cbcrInterleave;
  2757. stride = pEncInfo->stride;
  2758. if (mapType == COMPRESSED_FRAME_MAP_SVAC_SVC_BL) {
  2759. stride = VPU_ALIGN32(VPU_ALIGN32(VPU_ALIGN16(pOpenParam->picWidthBL)*5)/4);
  2760. }
  2761. regVal =(nv21 << 29) |
  2762. (cbcrInterleave << 16) |
  2763. (stride);
  2764. VpuWriteReg(coreIdx, W5_COMMON_PIC_INFO, regVal);
  2765. remain = count;
  2766. q = (remain+7)/8;
  2767. idx = 0;
  2768. for (j=0; j<q; j++) {
  2769. regVal = (endian<<16) | (j==q-1)<<4 | ((j==0)<<3);//lint !e514
  2770. regVal |= (pOpenParam->EncStdParam.waveParam.svcEnable == TRUE) ? (mapType == COMPRESSED_FRAME_MAP_SVAC_SVC_BL ? 0 : 1 << 27) : 0; // 0 = BL, 1 = EL
  2771. regVal |= (pOpenParam->enableNonRefFbcWrite<< 26);
  2772. VpuWriteReg(coreIdx, W5_SFB_OPTION, regVal);
  2773. startNo = j*8;
  2774. endNo = startNo + (remain>=8 ? 8 : remain) - 1;
  2775. VpuWriteReg(coreIdx, W5_SET_FB_NUM, (startNo<<8)|endNo);
  2776. for (i=0; i<8 && i<remain; i++) {
  2777. if (mapType == LINEAR_FRAME_MAP && pEncInfo->openParam.cbcrOrder == CBCR_ORDER_REVERSED) {
  2778. addrY = fbArr[i+startNo].bufY;
  2779. addrCb = fbArr[i+startNo].bufCr;
  2780. addrCr = fbArr[i+startNo].bufCb;
  2781. }
  2782. else {
  2783. addrY = fbArr[i+startNo].bufY;
  2784. addrCb = fbArr[i+startNo].bufCb;
  2785. addrCr = fbArr[i+startNo].bufCr;
  2786. }
  2787. VpuWriteReg(coreIdx, W5_ADDR_LUMA_BASE0 + (i<<4), addrY);
  2788. VpuWriteReg(coreIdx, W5_ADDR_CB_BASE0 + (i<<4), addrCb);
  2789. APIDPRINT("REGISTER FB[%02d] Y(0x%08x), Cb(0x%08x) ", i, addrY, addrCb);
  2790. if (mapType >= COMPRESSED_FRAME_MAP) {
  2791. VpuWriteReg(coreIdx, W5_ADDR_FBC_Y_OFFSET0 + (i<<4), vbFbcYTbl.phys_addr+idx*fbcYTblSize); /* Luma FBC offset table */
  2792. VpuWriteReg(coreIdx, W5_ADDR_FBC_C_OFFSET0 + (i<<4), vbFbcCTbl.phys_addr+idx*fbcCTblSize); /* Chroma FBC offset table */
  2793. if (inst->codecMode == W_SVAC_ENC) {
  2794. if (idx == 0) { // SVAC encoder needs only 2 mv-col buffers. (COL0 = for RDO, COL1 = for MVP)
  2795. VpuWriteReg(coreIdx, W5_ADDR_MV_COL0, vbMV.phys_addr);
  2796. VpuWriteReg(coreIdx, W5_ADDR_MV_COL1, vbMV.phys_addr + svacMvColSize0);
  2797. APIDPRINT("Yo(0x%08x) Co(0x%08x), Mv(0x%08x), Mv1(0x%8x)\n",
  2798. vbFbcYTbl.phys_addr, vbFbcCTbl.phys_addr,
  2799. vbMV.phys_addr, vbMV.phys_addr + svacMvColSize0);
  2800. }
  2801. else {
  2802. APIDPRINT("Yo(0x%08x) Co(0x%08x)\n", vbFbcYTbl.phys_addr+idx*fbcYTblSize, vbFbcCTbl.phys_addr+idx*fbcCTblSize);
  2803. }
  2804. }
  2805. else {
  2806. VpuWriteReg(coreIdx, W5_ADDR_MV_COL0 + (i<<2), vbMV.phys_addr+idx*mvColSize);
  2807. APIDPRINT("Yo(0x%08x) Co(0x%08x), Mv(0x%08x)\n",
  2808. vbFbcYTbl.phys_addr+idx*fbcYTblSize,
  2809. vbFbcCTbl.phys_addr+idx*fbcCTblSize,
  2810. vbMV.phys_addr+idx*mvColSize);
  2811. }
  2812. }
  2813. else {
  2814. VpuWriteReg(coreIdx, W5_ADDR_CR_BASE0 + (i<<4), addrCr);
  2815. VpuWriteReg(coreIdx, W5_ADDR_FBC_C_OFFSET0 + (i<<4), 0);
  2816. VpuWriteReg(coreIdx, W5_ADDR_MV_COL0 + (i<<2), 0);
  2817. APIDPRINT("Cr(0x%08x)\n", addrCr);
  2818. }
  2819. idx++;
  2820. }
  2821. remain -= i;
  2822. Wave5BitIssueCommand(inst, W5_SET_FB);
  2823. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  2824. return RETCODE_VPU_RESPONSE_TIMEOUT;
  2825. }
  2826. }
  2827. regVal = VpuReadReg(coreIdx, W5_RET_SUCCESS);
  2828. if (regVal == 0) {
  2829. return RETCODE_FAILURE;
  2830. }
  2831. if (ConfigSecAXIWave(coreIdx, inst->codecMode,
  2832. &pEncInfo->secAxiInfo, pOpenParam->picWidth, pOpenParam->picHeight,
  2833. pOpenParam->EncStdParam.waveParam.profile, pOpenParam->EncStdParam.waveParam.level) == 0) {
  2834. return RETCODE_INSUFFICIENT_RESOURCE;
  2835. }
  2836. return ret;
  2837. }
  2838. RetCode Wave5VpuEncode(CodecInst* instance, EncParam* option)
  2839. {
  2840. Int32 coreIdx, srcFrameFormat, srcPixelFormat, packedFormat;
  2841. Uint32 regVal = 0, bsEndian;
  2842. Uint32 srcStrideC = 0;
  2843. EncInfo* pEncInfo;
  2844. FrameBuffer* pSrcFrame;
  2845. EncOpenParam* pOpenParam;
  2846. BOOL justified = WTL_RIGHT_JUSTIFIED;
  2847. Uint32 formatNo = WTL_PIXEL_8BIT;
  2848. coreIdx = instance->coreIdx;
  2849. pEncInfo = VPU_HANDLE_TO_ENCINFO(instance);
  2850. pOpenParam = &pEncInfo->openParam;
  2851. pSrcFrame = option->sourceFrame;
  2852. switch (pOpenParam->srcFormat) {
  2853. case FORMAT_420_P10_16BIT_MSB:
  2854. case FORMAT_YUYV_P10_16BIT_MSB:
  2855. case FORMAT_YVYU_P10_16BIT_MSB:
  2856. case FORMAT_UYVY_P10_16BIT_MSB:
  2857. case FORMAT_VYUY_P10_16BIT_MSB:
  2858. justified = WTL_RIGHT_JUSTIFIED;
  2859. formatNo = WTL_PIXEL_16BIT;
  2860. break;
  2861. case FORMAT_420_P10_16BIT_LSB:
  2862. case FORMAT_YUYV_P10_16BIT_LSB:
  2863. case FORMAT_YVYU_P10_16BIT_LSB:
  2864. case FORMAT_UYVY_P10_16BIT_LSB:
  2865. case FORMAT_VYUY_P10_16BIT_LSB:
  2866. justified = WTL_LEFT_JUSTIFIED;
  2867. formatNo = WTL_PIXEL_16BIT;
  2868. break;
  2869. case FORMAT_420_P10_32BIT_MSB:
  2870. case FORMAT_YUYV_P10_32BIT_MSB:
  2871. case FORMAT_YVYU_P10_32BIT_MSB:
  2872. case FORMAT_UYVY_P10_32BIT_MSB:
  2873. case FORMAT_VYUY_P10_32BIT_MSB:
  2874. justified = WTL_RIGHT_JUSTIFIED;
  2875. formatNo = WTL_PIXEL_32BIT;
  2876. break;
  2877. case FORMAT_420_P10_32BIT_LSB:
  2878. case FORMAT_YUYV_P10_32BIT_LSB:
  2879. case FORMAT_YVYU_P10_32BIT_LSB:
  2880. case FORMAT_UYVY_P10_32BIT_LSB:
  2881. case FORMAT_VYUY_P10_32BIT_LSB:
  2882. justified = WTL_LEFT_JUSTIFIED;
  2883. formatNo = WTL_PIXEL_32BIT;
  2884. break;
  2885. case FORMAT_420:
  2886. case FORMAT_YUYV:
  2887. case FORMAT_YVYU:
  2888. case FORMAT_UYVY:
  2889. case FORMAT_VYUY:
  2890. justified = WTL_LEFT_JUSTIFIED;
  2891. formatNo = WTL_PIXEL_8BIT;
  2892. break;
  2893. default:
  2894. return RETCODE_FAILURE;
  2895. }
  2896. packedFormat = (pOpenParam->packedFormat >= 1) ? 1 : 0;
  2897. srcFrameFormat = packedFormat<<2 |
  2898. pOpenParam->cbcrInterleave<<1 |
  2899. pOpenParam->nv21;
  2900. switch (pOpenParam->packedFormat) { // additional packed format (interleave & nv21 bit are used to present these modes)
  2901. case PACKED_YVYU:
  2902. srcFrameFormat = 0x5;
  2903. break;
  2904. case PACKED_UYVY:
  2905. srcFrameFormat = 0x6;
  2906. break;
  2907. case PACKED_VYUY:
  2908. srcFrameFormat = 0x7;
  2909. break;
  2910. default:
  2911. break;
  2912. }
  2913. srcPixelFormat = justified<<2 | formatNo;
  2914. VpuWriteReg(coreIdx, W5_CMD_ENC_BS_START_ADDR, option->picStreamBufferAddr);
  2915. VpuWriteReg(coreIdx, W5_CMD_ENC_BS_SIZE, option->picStreamBufferSize);
  2916. pEncInfo->streamBufStartAddr = option->picStreamBufferAddr;
  2917. pEncInfo->streamBufSize = option->picStreamBufferSize;
  2918. pEncInfo->streamBufEndAddr = option->picStreamBufferAddr + option->picStreamBufferSize;
  2919. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_AXI_SEL, DEFAULT_SRC_AXI);
  2920. /* Secondary AXI */
  2921. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_USE_SEC_AXI, (pEncInfo->secAxiInfo.u.wave.useEncRdoEnable<<11) | (pEncInfo->secAxiInfo.u.wave.useEncLfEnable<<15));
  2922. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_REPORT_ENDIAN, VDI_128BIT_LITTLE_ENDIAN);
  2923. if (option->codeOption.implicitHeaderEncode == 1) {
  2924. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_CODE_OPTION, CODEOPT_ENC_HEADER_IMPLICIT | CODEOPT_ENC_VCL | // implicitly encode a header(headers) for generating bitstream. (to encode a header only, use ENC_PUT_VIDEO_HEADER for GiveCommand)
  2925. (option->codeOption.encodeAUD<<5) |
  2926. (option->codeOption.encodeEOS<<6) |
  2927. (option->codeOption.encodeEOB<<7));
  2928. }
  2929. else {
  2930. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_CODE_OPTION, (option->codeOption.implicitHeaderEncode<<0) |
  2931. (option->codeOption.encodeVCL<<1) |
  2932. (option->codeOption.encodeVPS<<2) |
  2933. (option->codeOption.encodeSPS<<3) |
  2934. (option->codeOption.encodePPS<<4) |
  2935. (option->codeOption.encodeAUD<<5) |
  2936. (option->codeOption.encodeEOS<<6) |
  2937. (option->codeOption.encodeEOB<<7) |
  2938. (option->codeOption.encodeFiller<<8));
  2939. }
  2940. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_PIC_PARAM, (option->skipPicture<<0) |
  2941. (option->forcePicQpEnable<<1) |
  2942. (option->forcePicQpI<<2) |
  2943. (option->forcePicQpP<<8) |
  2944. (option->forcePicQpB<<14) |
  2945. (option->forcePicTypeEnable<<20) |
  2946. (option->forcePicType<<21) |
  2947. (option->forceAllCtuCoefDropEnable<<24) |
  2948. (option->svcLayerFlag<<25));
  2949. if (option->srcEndFlag == 1)
  2950. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_PIC_IDX, 0xFFFFFFFF); // no more source image.
  2951. else
  2952. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_PIC_IDX, option->srcIdx);
  2953. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_ADDR_Y, pSrcFrame->bufY);
  2954. if (pOpenParam->cbcrOrder == CBCR_ORDER_NORMAL) {
  2955. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_ADDR_U, pSrcFrame->bufCb);
  2956. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_ADDR_V, pSrcFrame->bufCr);
  2957. }
  2958. else {
  2959. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_ADDR_U, pSrcFrame->bufCr);
  2960. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_ADDR_V, pSrcFrame->bufCb);
  2961. }
  2962. if (formatNo == WTL_PIXEL_32BIT) {
  2963. srcStrideC = VPU_ALIGN16(pSrcFrame->stride/2)*(1<<pSrcFrame->cbcrInterleave);
  2964. if ( pSrcFrame->cbcrInterleave == 1)
  2965. srcStrideC = pSrcFrame->stride;
  2966. }
  2967. else {
  2968. srcStrideC = (pSrcFrame->cbcrInterleave == 1) ? pSrcFrame->stride : (pSrcFrame->stride>>1);
  2969. }
  2970. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_STRIDE, (pSrcFrame->stride<<16) | srcStrideC );
  2971. regVal = vdi_convert_endian(coreIdx, pOpenParam->sourceEndian);
  2972. bsEndian = (~regVal&VDI_128BIT_ENDIAN_MASK);
  2973. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_FORMAT, (srcFrameFormat<<0) |
  2974. (srcPixelFormat<<3) |
  2975. (bsEndian<<6));
  2976. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR, option->customMapOpt.addrCustomMap);
  2977. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM, (option->customMapOpt.customRoiMapEnable << 0) |
  2978. (option->customMapOpt.roiAvgQp << 1) |
  2979. (option->customMapOpt.customLambdaMapEnable<< 8) |
  2980. (option->customMapOpt.customModeMapEnable<< 9) |
  2981. (option->customMapOpt.customCoefDropEnable<< 10));
  2982. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_LONGTERM_PIC, (option->useCurSrcAsLongtermPic<<0) | (option->useLongtermRef<<1));
  2983. if (instance->codecMode == W_HEVC_ENC || instance->codecMode == W_AVC_ENC) {
  2984. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_Y, option->wpPixSigmaY);
  2985. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_C, (option->wpPixSigmaCr<<16) | option->wpPixSigmaCb);
  2986. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_Y, option->wpPixMeanY);
  2987. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_C, (option->wpPixMeanCr<<16) | (option->wpPixMeanCb));
  2988. }
  2989. else if (instance->codecMode == W_SVAC_ENC) {
  2990. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_LF_PARAM_0, ((option->lfRefDeltaIntra&0x7f)<<0) |
  2991. ((option->lfRefDeltaRef0&0x7f)<<7) |
  2992. ((option->lfRefDeltaRef1&0x7f)<<14) |
  2993. ((option->lfModeDelta&0x7f)<<21) |
  2994. (option->sharpLevel<<28));
  2995. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_LF_PARAM_1, (option->userFilterLevelEnable<<0) | ((option->lfFilterLevel&0x3f)<<1));
  2996. }
  2997. #ifdef SUPPORT_LOOK_AHEAD_RC
  2998. if (TRUE == pOpenParam->EncStdParam.waveParam.larcEnable && pOpenParam->EncStdParam.waveParam.larcPass == 2) {
  2999. VpuWriteReg(coreIdx, W5_CMD_ENC_LARC_RC_B, option->larcData[0]);
  3000. VpuWriteReg(coreIdx, W5_CMD_ENC_LARC_RC_BPP, option->larcData[1]);
  3001. VpuWriteReg(coreIdx, W5_CMD_ENC_LARC_RC_ENC_ORDER, option->larcData[2]);
  3002. }
  3003. #endif
  3004. Wave5BitIssueCommand(instance, W5_ENC_PIC);
  3005. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) { // Check QUEUE_DONE
  3006. if (instance->loggingEnable)
  3007. vdi_log(instance->coreIdx, W5_ENC_PIC, 2);
  3008. return RETCODE_VPU_RESPONSE_TIMEOUT;
  3009. }
  3010. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_STATUS);
  3011. pEncInfo->instanceQueueCount = (regVal>>16)&0xff;
  3012. pEncInfo->reportQueueCount = (regVal & 0xffff);
  3013. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE) { // FAILED for adding a command into VCPU QUEUE
  3014. regVal = VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON);
  3015. if (regVal != WAVE5_QUEUEING_FAIL)
  3016. VLOG(ERR, "FAIL_REASON = 0x%x\n", regVal);
  3017. if (regVal == WAVE5_QUEUEING_FAIL)
  3018. return RETCODE_QUEUEING_FAILURE;
  3019. else if (regVal == WAVE5_SYSERR_WATCHDOG_TIMEOUT)
  3020. return RETCODE_VPU_RESPONSE_TIMEOUT;
  3021. else if (regVal == WAVE5_ERROR_FW_FATAL)
  3022. return RETCODE_ERROR_FW_FATAL;
  3023. else
  3024. return RETCODE_FAILURE;
  3025. }
  3026. return RETCODE_SUCCESS;
  3027. }
  3028. RetCode Wave5VpuEncGetResult(CodecInst* instance, EncOutputInfo* result)
  3029. {
  3030. RetCode ret = RETCODE_SUCCESS;
  3031. Uint32 encodingSuccess;
  3032. Uint32 regVal;
  3033. Int32 coreIdx;
  3034. EncInfo* pEncInfo = VPU_HANDLE_TO_ENCINFO(instance);
  3035. vpu_instance_pool_t* instancePool = NULL;
  3036. coreIdx = instance->coreIdx;
  3037. ret = SendQuery(instance, GET_RESULT);
  3038. if (ret != RETCODE_SUCCESS) {
  3039. regVal = VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON);
  3040. if (regVal != WAVE5_QUEUEING_FAIL)
  3041. VLOG(ERR, "FAIL_REASON = 0x%x\n", regVal);
  3042. if (regVal == WAVE5_RESULT_NOT_READY)
  3043. return RETCODE_REPORT_NOT_READY;
  3044. else if(regVal == WAVE5_SYSERR_ACCESS_VIOLATION_HW)
  3045. return RETCODE_MEMORY_ACCESS_VIOLATION;
  3046. else if (regVal == WAVE5_SYSERR_WATCHDOG_TIMEOUT)
  3047. return RETCODE_VPU_RESPONSE_TIMEOUT;
  3048. else if (regVal == WAVE5_ERROR_FW_FATAL)
  3049. return RETCODE_ERROR_FW_FATAL;
  3050. else
  3051. return RETCODE_QUERY_FAILURE;
  3052. }
  3053. if (instance->loggingEnable)
  3054. vdi_log(coreIdx, W5_ENC_PIC, 0);
  3055. regVal = VpuReadReg(coreIdx, W5_RET_QUEUE_STATUS);
  3056. pEncInfo->instanceQueueCount = (regVal>>16)&0xff;
  3057. pEncInfo->reportQueueCount = (regVal & 0xffff);
  3058. encodingSuccess = VpuReadReg(coreIdx, W5_RET_ENC_ENCODING_SUCCESS);
  3059. if (encodingSuccess == FALSE) {
  3060. result->errorReason = VpuReadReg(coreIdx, W5_RET_ENC_ERR_INFO);
  3061. if (result->errorReason == WAVE5_SYSERR_ENC_VLC_BUF_FULL) {
  3062. return RETCODE_VLC_BUF_FULL;
  3063. }
  3064. return RETCODE_FAILURE;
  3065. } else {
  3066. result->warnInfo = VpuReadReg(instance->coreIdx, W5_RET_ENC_WARN_INFO);
  3067. }
  3068. result->encPicCnt = VpuReadReg(coreIdx, W5_RET_ENC_PIC_NUM);
  3069. regVal= VpuReadReg(coreIdx, W5_RET_ENC_PIC_TYPE);
  3070. result->picType = regVal & 0xFFFF;
  3071. result->encVclNut = VpuReadReg(coreIdx, W5_RET_ENC_VCL_NUT);
  3072. result->reconFrameIndex = VpuReadReg(coreIdx, W5_RET_ENC_PIC_IDX);
  3073. if (result->reconFrameIndex >= 0)
  3074. result->reconFrame = pEncInfo->frameBufPool[result->reconFrameIndex];
  3075. result->isSvcLayerEL = VpuReadReg(coreIdx, W5_RET_ENC_SVC_LAYER);
  3076. if (pEncInfo->openParam.EncStdParam.waveParam.svcEnable == 1 && result->isSvcLayerEL == FALSE) {
  3077. if (result->reconFrameIndex >= 0)
  3078. result->reconFrame = pEncInfo->frameBufPool[result->reconFrameIndex+pEncInfo->numFrameBuffers];
  3079. }
  3080. result->numOfSlices = VpuReadReg(coreIdx, W5_RET_ENC_PIC_SLICE_NUM);
  3081. result->picSkipped = VpuReadReg(coreIdx, W5_RET_ENC_PIC_SKIP);
  3082. result->numOfIntra = VpuReadReg(coreIdx, W5_RET_ENC_PIC_NUM_INTRA);
  3083. result->numOfMerge = VpuReadReg(coreIdx, W5_RET_ENC_PIC_NUM_MERGE);
  3084. result->numOfSkipBlock = VpuReadReg(coreIdx, W5_RET_ENC_PIC_NUM_SKIP);
  3085. result->bitstreamWrapAround = 0; // wave520 only support line-buffer mode.
  3086. result->avgCtuQp = VpuReadReg(coreIdx, W5_RET_ENC_PIC_AVG_CTU_QP);
  3087. result->encPicByte = VpuReadReg(coreIdx, W5_RET_ENC_PIC_BYTE);
  3088. result->encGopPicIdx = VpuReadReg(coreIdx, W5_RET_ENC_GOP_PIC_IDX);
  3089. result->encPicPoc = VpuReadReg(coreIdx, W5_RET_ENC_PIC_POC);
  3090. result->encSrcIdx = VpuReadReg(coreIdx, W5_RET_ENC_USED_SRC_IDX);
  3091. result->releaseSrcFlag = VpuReadReg(coreIdx, W5_RET_ENC_SRC_BUF_FLAG);
  3092. pEncInfo->streamWrPtr = VpuReadReg(coreIdx, pEncInfo->streamWrPtrRegAddr);
  3093. pEncInfo->streamRdPtr = VpuReadReg(coreIdx, pEncInfo->streamRdPtrRegAddr);
  3094. result->picDistortionLow = VpuReadReg(coreIdx, W5_RET_ENC_PIC_DIST_LOW);
  3095. result->picDistortionHigh = VpuReadReg(coreIdx, W5_RET_ENC_PIC_DIST_HIGH);
  3096. result->bitstreamBuffer = VpuReadReg(coreIdx, pEncInfo->streamRdPtrRegAddr);
  3097. result->rdPtr = pEncInfo->streamRdPtr;
  3098. result->wrPtr = pEncInfo->streamWrPtr;
  3099. if (result->reconFrameIndex == RECON_IDX_FLAG_HEADER_ONLY) //result for header only(no vcl) encoding
  3100. result->bitstreamSize = result->encPicByte;
  3101. else if (result->reconFrameIndex < 0)
  3102. result->bitstreamSize = 0;
  3103. else
  3104. result->bitstreamSize = result->encPicByte;
  3105. result->encHostCmdTick = VpuReadReg(coreIdx, W5_RET_ENC_HOST_CMD_TICK);
  3106. result->encPrepareStartTick = VpuReadReg(coreIdx, W5_RET_ENC_PREPARE_START_TICK);
  3107. result->encPrepareEndTick = VpuReadReg(coreIdx, W5_RET_ENC_PREPARE_END_TICK);
  3108. result->encProcessingStartTick = VpuReadReg(coreIdx, W5_RET_ENC_PROCESSING_START_TICK);
  3109. result->encProcessingEndTick = VpuReadReg(coreIdx, W5_RET_ENC_PROCESSING_END_TICK);
  3110. result->encEncodeStartTick = VpuReadReg(coreIdx, W5_RET_ENC_ENCODING_START_TICK);
  3111. result->encEncodeEndTick = VpuReadReg(coreIdx, W5_RET_ENC_ENCODING_END_TICK);
  3112. instancePool = vdi_get_instance_pool(instance->coreIdx);
  3113. if ( pEncInfo->firstCycleCheck == FALSE ) {
  3114. result->frameCycle = (result->encEncodeEndTick - result->encHostCmdTick) * pEncInfo->cyclePerTick;
  3115. pEncInfo->firstCycleCheck = TRUE;
  3116. }
  3117. else {
  3118. result->frameCycle = (result->encEncodeEndTick - instancePool->lastPerformanceCycles) * pEncInfo->cyclePerTick;
  3119. if (instancePool->lastPerformanceCycles < result->encHostCmdTick)
  3120. result->frameCycle = (result->encEncodeEndTick - result->encHostCmdTick) * pEncInfo->cyclePerTick;
  3121. }
  3122. instancePool->lastPerformanceCycles = result->encEncodeEndTick;
  3123. result->prepareCycle = (result->encPrepareEndTick - result->encPrepareStartTick) * pEncInfo->cyclePerTick;
  3124. result->processing = (result->encProcessingEndTick - result->encProcessingStartTick) * pEncInfo->cyclePerTick;
  3125. result->EncodedCycle = (result->encEncodeEndTick - result->encEncodeStartTick) * pEncInfo->cyclePerTick;
  3126. #ifdef SUPPORT_LOOK_AHEAD_RC
  3127. result->larcData[0] = VpuReadReg(coreIdx, W5_RET_ENC_LARC_RC_B);
  3128. result->larcData[1] = VpuReadReg(coreIdx, W5_RET_ENC_LARC_RC_BPP);
  3129. result->larcData[2] = VpuReadReg(coreIdx, W5_RET_ENC_LARC_RC_ENC_ORDER);
  3130. #endif
  3131. return RETCODE_SUCCESS;
  3132. }
  3133. RetCode Wave5VpuEncGetHeader(EncHandle instance, EncHeaderParam * encHeaderParam)
  3134. {
  3135. Int32 coreIdx;
  3136. Uint32 regVal = 0;
  3137. EncInfo* pEncInfo = VPU_HANDLE_TO_ENCINFO(instance);
  3138. coreIdx = instance->coreIdx;
  3139. EnterLock(coreIdx);
  3140. VpuWriteReg(coreIdx, W5_CMD_ENC_BS_START_ADDR, encHeaderParam->buf);
  3141. VpuWriteReg(coreIdx, W5_CMD_ENC_BS_SIZE, encHeaderParam->size);
  3142. pEncInfo->streamRdPtr = encHeaderParam->buf;
  3143. pEncInfo->streamWrPtr = encHeaderParam->buf;
  3144. pEncInfo->streamBufStartAddr = encHeaderParam->buf;
  3145. pEncInfo->streamBufSize = encHeaderParam->size;
  3146. pEncInfo->streamBufEndAddr = encHeaderParam->buf + encHeaderParam->size;
  3147. /* Secondary AXI */
  3148. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_USE_SEC_AXI, (pEncInfo->secAxiInfo.u.wave.useEncImdEnable<<9) |
  3149. (pEncInfo->secAxiInfo.u.wave.useEncRdoEnable<<11) |
  3150. (pEncInfo->secAxiInfo.u.wave.useEncLfEnable<<15));
  3151. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_CODE_OPTION, encHeaderParam->headerType);
  3152. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_PIC_IDX, 0);
  3153. Wave5BitIssueCommand(instance, W5_ENC_PIC);
  3154. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) { // Check QUEUE_DONE
  3155. if (instance->loggingEnable)
  3156. vdi_log(instance->coreIdx, W5_ENC_PIC, 2);
  3157. LeaveLock(coreIdx);
  3158. return RETCODE_VPU_RESPONSE_TIMEOUT;
  3159. }
  3160. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_STATUS);
  3161. pEncInfo->instanceQueueCount = (regVal>>16)&0xff;
  3162. pEncInfo->reportQueueCount = (regVal & 0xffff);
  3163. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE) { // FAILED for adding a command into VCPU QUEUE
  3164. regVal = VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON);
  3165. if (regVal != WAVE5_QUEUEING_FAIL)
  3166. VLOG(ERR, "FAIL_REASON = 0x%x\n", regVal);
  3167. LeaveLock(coreIdx);
  3168. if ( regVal == WAVE5_QUEUEING_FAIL)
  3169. return RETCODE_QUEUEING_FAILURE;
  3170. else if (regVal == WAVE5_SYSERR_ACCESS_VIOLATION_HW)
  3171. return RETCODE_MEMORY_ACCESS_VIOLATION;
  3172. else if (regVal == WAVE5_SYSERR_WATCHDOG_TIMEOUT)
  3173. return RETCODE_VPU_RESPONSE_TIMEOUT;
  3174. else if (regVal == WAVE5_ERROR_FW_FATAL)
  3175. return RETCODE_ERROR_FW_FATAL;
  3176. else
  3177. return RETCODE_FAILURE;
  3178. }
  3179. LeaveLock(coreIdx);
  3180. return RETCODE_SUCCESS;
  3181. }
  3182. RetCode Wave5VpuEncFiniSeq(CodecInst* instance )
  3183. {
  3184. RetCode ret = RETCODE_SUCCESS;
  3185. Wave5BitIssueCommand(instance, W5_DESTROY_INSTANCE);
  3186. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1)
  3187. return RETCODE_VPU_RESPONSE_TIMEOUT;
  3188. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE) {
  3189. if (VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON) == WAVE5_VPU_STILL_RUNNING)
  3190. ret = RETCODE_VPU_STILL_RUNNING;
  3191. else
  3192. ret = RETCODE_FAILURE;
  3193. }
  3194. return ret;
  3195. }
  3196. RetCode Wave5VpuEncParaChange(EncHandle instance, EncChangeParam* param)
  3197. {
  3198. Int32 coreIdx;
  3199. Uint32 regVal = 0;
  3200. EncInfo* pEncInfo;
  3201. coreIdx = instance->coreIdx;
  3202. pEncInfo = &instance->CodecInfo->encInfo;
  3203. EnterLock(coreIdx);
  3204. /* SET_PARAM + COMMON */
  3205. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_SET_PARAM_OPTION, OPT_CHANGE_PARAM);
  3206. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_SET_PARAM_ENABLE, param->enable_option);
  3207. if (param->enable_option & ENC_SET_CHANGE_PARAM_PPS) {
  3208. if (instance->codecMode == W_SVAC_ENC) {
  3209. regVal = (param->disableDeblk<<5) |
  3210. ((param->chromaDcQpOffset&0x1F)<<14) |
  3211. ((param->chromaAcQpOffset&0x1F)<<19) |
  3212. ((param->lumaDcQpOffset&0x1F)<<24);
  3213. }
  3214. else {
  3215. regVal = (param->constIntraPredFlag<<1) |
  3216. (param->lfCrossSliceBoundaryEnable<<2) |
  3217. ((param->weightPredEnable&1)<<3) |
  3218. (param->disableDeblk<<5) |
  3219. ((param->betaOffsetDiv2&0xF)<<6) |
  3220. ((param->tcOffsetDiv2&0xF)<<10) |
  3221. ((param->chromaCbQpOffset&0x1F)<<14) |
  3222. ((param->chromaCrQpOffset&0x1F)<<19) |
  3223. (param->transform8x8Enable<<29) |
  3224. (param->entropyCodingMode<<30);
  3225. }
  3226. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_PPS_PARAM, regVal);
  3227. }
  3228. if (param->enable_option & ENC_SET_CHANGE_PARAM_INTRA_PARAM) {
  3229. if (instance->codecMode == W_AVC_ENC) {
  3230. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_INTRA_PARAM, (param->intraQP<<0) | ( (param->intraPeriod&0x7ff)<<6) | ( (param->avcIdrPeriod&0x7ff)<<17) | ( (param->forcedIdrHeaderEnable&3)<<28));
  3231. }
  3232. else {
  3233. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_INTRA_PARAM, (param->intraQP<<3) | (param->forcedIdrHeaderEnable<<9) | (param->intraPeriod<<16));
  3234. }
  3235. }
  3236. if (param->enable_option & ENC_SET_CHANGE_PARAM_RC_TARGET_RATE) {
  3237. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_TARGET_RATE, param->bitRate);
  3238. }
  3239. if (param->enable_option & ENC_SET_CHANGE_PARAM_RC) {
  3240. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_PARAM, (param->hvsQPEnable<<2) |
  3241. (param->hvsQpScale<<4) |
  3242. (param->vbvBufferSize<<20));
  3243. }
  3244. if (param->enable_option & ENC_SET_CHANGE_PARAM_RC_MIN_MAX_QP) {
  3245. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_MIN_MAX_QP, (param->minQpI<<0) |
  3246. (param->maxQpI<<6) |
  3247. (param->hvsMaxDeltaQp<<12));
  3248. }
  3249. if (param->enable_option & ENC_SET_CHANGE_PARAM_RC_INTER_MIN_MAX_QP) {
  3250. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_INTER_MIN_MAX_QP, (param->minQpP<<0) |
  3251. (param->maxQpP<<6) |
  3252. (param->minQpB<<12) |
  3253. (param->maxQpB<<18));
  3254. }
  3255. if (param->enable_option & ENC_SET_CHANGE_PARAM_RC_BIT_RATIO_LAYER) {
  3256. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3, (param->fixedBitRatio[0]<<0) |
  3257. (param->fixedBitRatio[1]<<8) |
  3258. (param->fixedBitRatio[2]<<16) |
  3259. (param->fixedBitRatio[3]<<24));
  3260. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7, (param->fixedBitRatio[4]<<0) |
  3261. (param->fixedBitRatio[5]<<8) |
  3262. (param->fixedBitRatio[6]<<16) |
  3263. (param->fixedBitRatio[7]<<24));
  3264. }
  3265. if (param->enable_option & ENC_SET_CHANGE_PARAM_RC_WEIGHT) {
  3266. regVal = (param->rcWeightBuf<<8 | param->rcWeightParam);
  3267. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_WEIGHT_PARAM, regVal);
  3268. }
  3269. if (param->enable_option & ENC_SET_CHANGE_PARAM_RDO) {
  3270. regVal = (param->rdoSkip<<2) |
  3271. (param->lambdaScalingEnable<<3) |
  3272. (param->coefClearDisable<<4) |
  3273. (param->intraNxNEnable<<8) |
  3274. (param->maxNumMerge<<18) |
  3275. (param->customMDEnable<<20) |
  3276. (param->customLambdaEnable<<21);
  3277. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RDO_PARAM, regVal);
  3278. }
  3279. if (param->enable_option & ENC_SET_CHANGE_PARAM_INDEPEND_SLICE) {
  3280. if (instance->codecMode == W_HEVC_ENC ) {
  3281. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, param->independSliceModeArg<<16 | param->independSliceMode);
  3282. }
  3283. else if (instance->codecMode == W_AVC_ENC) {
  3284. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, param->avcSliceArg<<16 | param->avcSliceMode);
  3285. }
  3286. }
  3287. if (instance->codecMode == W_HEVC_ENC && param->enable_option & ENC_SET_CHANGE_PARAM_DEPEND_SLICE) {
  3288. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_DEPENDENT_SLICE, param->dependSliceModeArg<<16 | param->dependSliceMode);
  3289. }
  3290. if (instance->codecMode == W_HEVC_ENC && param->enable_option & ENC_SET_CHANGE_PARAM_NR) {
  3291. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_NR_PARAM, (param->nrYEnable<<0) |
  3292. (param->nrCbEnable<<1) |
  3293. (param->nrCrEnable<<2) |
  3294. (param->nrNoiseEstEnable<<3)|
  3295. (param->nrNoiseSigmaY<<4) |
  3296. (param->nrNoiseSigmaCb<<12) |
  3297. (param->nrNoiseSigmaCr<<20));
  3298. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_NR_WEIGHT, (param->nrIntraWeightY<<0) |
  3299. (param->nrIntraWeightCb<<5) |
  3300. (param->nrIntraWeightCr<<10)|
  3301. (param->nrInterWeightY<<15) |
  3302. (param->nrInterWeightCb<<20)|
  3303. (param->nrInterWeightCr<<25));
  3304. }
  3305. if (param->enable_option & ENC_SET_CHANGE_PARAM_BG) {
  3306. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_BG_PARAM, (param->bgThrDiff<<1) |
  3307. (param->bgThrMeanDiff<<10) |
  3308. (param->bgLambdaQp<<18) |
  3309. ((param->bgDeltaQp&0x1F)<<24) |
  3310. (instance->codecMode == W_AVC_ENC ? param->s2fmeDisable<<29 : 0));
  3311. }
  3312. if (instance->codecMode == W_HEVC_ENC && param->enable_option & ENC_SET_CHANGE_PARAM_CUSTOM_MD) {
  3313. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_PU04, (param->pu04DeltaRate&0xFF) |
  3314. ((param->pu04IntraPlanarDeltaRate&0xFF)<<8) |
  3315. ((param->pu04IntraDcDeltaRate&0xFF)<<16) |
  3316. ((param->pu04IntraAngleDeltaRate&0xFF)<<24));
  3317. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_PU08, (param->pu08DeltaRate&0xFF) |
  3318. ((param->pu08IntraPlanarDeltaRate&0xFF)<<8) |
  3319. ((param->pu08IntraDcDeltaRate&0xFF)<<16) |
  3320. ((param->pu08IntraAngleDeltaRate&0xFF)<<24));
  3321. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_PU16, (param->pu16DeltaRate&0xFF) |
  3322. ((param->pu16IntraPlanarDeltaRate&0xFF)<<8) |
  3323. ((param->pu16IntraDcDeltaRate&0xFF)<<16) |
  3324. ((param->pu16IntraAngleDeltaRate&0xFF)<<24));
  3325. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_PU32, (param->pu32DeltaRate&0xFF) |
  3326. ((param->pu32IntraPlanarDeltaRate&0xFF)<<8) |
  3327. ((param->pu32IntraDcDeltaRate&0xFF)<<16) |
  3328. ((param->pu32IntraAngleDeltaRate&0xFF)<<24));
  3329. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_CU08, (param->cu08IntraDeltaRate&0xFF) |
  3330. ((param->cu08InterDeltaRate&0xFF)<<8) |
  3331. ((param->cu08MergeDeltaRate&0xFF)<<16));
  3332. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_CU16, (param->cu16IntraDeltaRate&0xFF) |
  3333. ((param->cu16InterDeltaRate&0xFF)<<8) |
  3334. ((param->cu16MergeDeltaRate&0xFF)<<16));
  3335. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_CU32, (param->cu32IntraDeltaRate&0xFF) |
  3336. ((param->cu32InterDeltaRate&0xFF)<<8) |
  3337. ((param->cu32MergeDeltaRate&0xFF)<<16));
  3338. }
  3339. if (instance->codecMode == W_HEVC_ENC && param->enable_option & ENC_SET_CHANGE_PARAM_CUSTOM_LAMBDA) {
  3340. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR, param->customLambdaAddr);
  3341. }
  3342. Wave5BitIssueCommand(instance, W5_ENC_SET_PARAM);
  3343. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  3344. if (instance->loggingEnable)
  3345. vdi_log(coreIdx, W5_ENC_SET_PARAM, 2);
  3346. return RETCODE_VPU_RESPONSE_TIMEOUT;
  3347. }
  3348. regVal = VpuReadReg(coreIdx, W5_RET_QUEUE_STATUS);
  3349. pEncInfo->instanceQueueCount = (regVal>>16) & 0xFF;
  3350. pEncInfo->reportQueueCount = (regVal & 0xFFFF);
  3351. if (VpuReadReg(coreIdx, W5_RET_SUCCESS) == 0) {
  3352. regVal = VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON);
  3353. if (regVal != WAVE5_QUEUEING_FAIL)
  3354. VLOG(ERR, "FAIL_REASON = 0x%x\n", regVal);
  3355. LeaveLock(coreIdx);
  3356. if ( regVal == WAVE5_QUEUEING_FAIL)
  3357. return RETCODE_QUEUEING_FAILURE;
  3358. else if (regVal == WAVE5_SYSERR_ACCESS_VIOLATION_HW)
  3359. return RETCODE_MEMORY_ACCESS_VIOLATION;
  3360. else if (regVal == WAVE5_SYSERR_WATCHDOG_TIMEOUT)
  3361. return RETCODE_VPU_RESPONSE_TIMEOUT;
  3362. else if (regVal == WAVE5_ERROR_FW_FATAL)
  3363. return RETCODE_ERROR_FW_FATAL;
  3364. else
  3365. return RETCODE_FAILURE;
  3366. }
  3367. LeaveLock(coreIdx);
  3368. return RETCODE_SUCCESS;
  3369. }
  3370. RetCode Wave5VpuGetSrcBufFlag(CodecInst* instance, Uint32* flag) {
  3371. RetCode ret = RETCODE_SUCCESS;
  3372. ret = SendQuery(instance, GET_SRC_BUF_FLAG);
  3373. if (ret != RETCODE_SUCCESS)
  3374. return RETCODE_QUERY_FAILURE;
  3375. *flag = VpuReadReg(instance->coreIdx, W5_RET_ENC_SRC_BUF_FLAG);
  3376. return RETCODE_SUCCESS;
  3377. }
  3378. //static RetCode CalcEncCropInfo(EncWaveParam* param, int rotMode, int srcWidth, int srcHeight);
  3379. static Uint32 presetGopSize[] = {
  3380. 1, /* Custom GOP, Not used */
  3381. 1, /* All Intra */
  3382. 1, /* IPP Cyclic GOP size 1 */
  3383. 1, /* IBB Cyclic GOP size 1 */
  3384. 2, /* IBP Cyclic GOP size 2 */
  3385. 4, /* IBBBP */
  3386. 4,
  3387. 4,
  3388. 8,
  3389. };
  3390. RetCode CheckEncCommonParamValid(EncOpenParam* pop)
  3391. {
  3392. RetCode ret = RETCODE_SUCCESS;
  3393. Int32 low_delay = 0;
  3394. Int32 intra_period_gop_step_size;
  3395. Int32 i;
  3396. EncWaveParam* param = &pop->EncStdParam.waveParam;
  3397. // check low-delay gop structure
  3398. if(param->gopPresetIdx == PRESET_IDX_CUSTOM_GOP) // common gop
  3399. {
  3400. Int32 minVal = 0;
  3401. if(param->gopParam.customGopSize > 1)
  3402. {
  3403. minVal = param->gopParam.picParam[0].pocOffset;
  3404. low_delay = 1;
  3405. for(i = 1; i < param->gopParam.customGopSize; i++)
  3406. {
  3407. if(minVal > param->gopParam.picParam[i].pocOffset)
  3408. {
  3409. low_delay = 0;
  3410. break;
  3411. }
  3412. else
  3413. minVal = param->gopParam.picParam[i].pocOffset;
  3414. }
  3415. }
  3416. }
  3417. else if(param->gopPresetIdx == PRESET_IDX_ALL_I ||
  3418. param->gopPresetIdx == PRESET_IDX_IPP ||
  3419. param->gopPresetIdx == PRESET_IDX_IBBB ||
  3420. param->gopPresetIdx == PRESET_IDX_IPPPP ||
  3421. param->gopPresetIdx == PRESET_IDX_IBBBB) // low-delay case (IPPP, IBBB)
  3422. low_delay = 1;
  3423. if(low_delay) {
  3424. intra_period_gop_step_size = 1;
  3425. }
  3426. else {
  3427. if (param->gopPresetIdx == PRESET_IDX_CUSTOM_GOP) {
  3428. intra_period_gop_step_size = param->gopParam.customGopSize;
  3429. }
  3430. else {
  3431. intra_period_gop_step_size = presetGopSize[param->gopPresetIdx];
  3432. }
  3433. }
  3434. if (pop->bitstreamFormat == STD_HEVC) {
  3435. if( !low_delay && (param->intraPeriod != 0) && (param->decodingRefreshType != 0) && (intra_period_gop_step_size != 0) &&
  3436. (param->intraPeriod < intra_period_gop_step_size * 2)) {
  3437. VLOG(ERR,"CFG FAIL : Not support intra period[%d] for the gop structure\n", param->intraPeriod);
  3438. VLOG(ERR,"RECOMMEND CONFIG PARAMETER : Intra period >= %d\n", intra_period_gop_step_size * 2);
  3439. ret = RETCODE_FAILURE;
  3440. }
  3441. }
  3442. else if (pop->bitstreamFormat == STD_SVAC) {
  3443. if( !low_delay && (param->intraPeriod != 0) && (intra_period_gop_step_size != 0) &&
  3444. (param->intraPeriod % intra_period_gop_step_size) != 1) {
  3445. VLOG(ERR,"CFG FAIL : Not support intra period[%d] for the gop structure\n", param->intraPeriod);
  3446. VLOG(ERR,"RECOMMEND CONFIG PARAMETER : Intra period = %d\n", intra_period_gop_step_size * (param->intraPeriod / intra_period_gop_step_size));
  3447. ret = RETCODE_FAILURE;
  3448. }
  3449. }
  3450. if( !low_delay && (param->intraPeriod != 0) && (intra_period_gop_step_size != 0) && ((param->intraPeriod % intra_period_gop_step_size) == 1) && param->decodingRefreshType == 0)
  3451. {
  3452. VLOG(ERR,"CFG FAIL : Not support decoding refresh type[%d] for closed gop structure\n", param->decodingRefreshType );
  3453. VLOG(ERR,"RECOMMEND CONFIG PARAMETER : Decoding refresh type = IDR\n");
  3454. ret = RETCODE_FAILURE;
  3455. }
  3456. if (param->gopPresetIdx == PRESET_IDX_CUSTOM_GOP) {
  3457. for(i = 0; i < param->gopParam.customGopSize; i++)
  3458. {
  3459. if (param->gopParam.picParam[i].temporalId >= MAX_NUM_TEMPORAL_LAYER )
  3460. {
  3461. VLOG(ERR,"CFG FAIL : temporalId %d exceeds MAX_NUM_TEMPORAL_LAYER\n", param->gopParam.picParam[i].temporalId);
  3462. VLOG(ERR,"RECOMMEND CONFIG PARAMETER : Adjust temporal ID under MAX_NUM_TEMPORAL_LAYER(7) in GOP structure\n");
  3463. ret = RETCODE_FAILURE;
  3464. }
  3465. if (param->gopParam.picParam[i].temporalId < 0)
  3466. {
  3467. VLOG(ERR,"CFG FAIL : Must be %d-th temporal_id >= 0\n",param->gopParam.picParam[i].temporalId);
  3468. VLOG(ERR,"RECOMMEND CONFIG PARAMETER : Adjust temporal layer above '0' in GOP structure\n");
  3469. ret = RETCODE_FAILURE;
  3470. }
  3471. }
  3472. }
  3473. if (param->useRecommendEncParam == 0)
  3474. {
  3475. // RDO
  3476. {
  3477. int align_32_width_flag = pop->picWidth % 32;
  3478. int align_16_width_flag = pop->picWidth % 16;
  3479. int align_8_width_flag = pop->picWidth % 8;
  3480. int align_32_height_flag = pop->picHeight % 32;
  3481. int align_16_height_flag = pop->picHeight % 16;
  3482. int align_8_height_flag = pop->picHeight % 8;
  3483. if( ((param->cuSizeMode&0x1) == 0) && ((align_8_width_flag != 0) || (align_8_height_flag != 0)) )
  3484. {
  3485. VLOG(ERR,"CFG FAIL : Picture width and height must be aligned with 8 pixels when enable CU8x8 of cuSizeMode \n");
  3486. VLOG(ERR,"RECOMMEND CONFIG PARAMETER : cuSizeMode |= 0x1 (CU8x8)\n");
  3487. ret = RETCODE_FAILURE;
  3488. }
  3489. else if(((param->cuSizeMode&0x1) == 0) && ((param->cuSizeMode&0x2) == 0) && ((align_16_width_flag != 0) || (align_16_height_flag != 0)) )
  3490. {
  3491. VLOG(ERR,"CFG FAIL : Picture width and height must be aligned with 16 pixels when enable CU16x16 of cuSizeMode\n");
  3492. VLOG(ERR,"RECOMMEND CONFIG PARAMETER : cuSizeMode |= 0x2 (CU16x16)\n");
  3493. ret = RETCODE_FAILURE;
  3494. }
  3495. else if(((param->cuSizeMode&0x1) == 0) && ((param->cuSizeMode&0x2) == 0) && ((param->cuSizeMode&0x4) == 0) && ((align_32_width_flag != 0) || (align_32_height_flag != 0)) )
  3496. {
  3497. VLOG(ERR,"CFG FAIL : Picture width and height must be aligned with 32 pixels when enable CU32x32 of cuSizeMode\n");
  3498. VLOG(ERR,"RECOMMEND CONFIG PARAMETER : cuSizeMode |= 0x4 (CU32x32)\n");
  3499. ret = RETCODE_FAILURE;
  3500. }
  3501. }
  3502. }
  3503. // Slice
  3504. {
  3505. if ( param->wppEnable == 1 && param->independSliceMode == 1) {
  3506. int num_ctb_in_width = VPU_ALIGN64(pop->picWidth)>>6;
  3507. if (param->independSliceModeArg % num_ctb_in_width) {
  3508. printf("CFG FAIL : If WaveFrontSynchro(WPP) '1', the number of IndeSliceArg(ctb_num) must be multiple of num_ctb_in_width\n");
  3509. printf("RECOMMEND CONFIG PARAMETER : IndeSliceArg = num_ctb_in_width * a\n");
  3510. ret = RETCODE_FAILURE;
  3511. }
  3512. }
  3513. // multi-slice & wpp
  3514. if(param->wppEnable == 1 && param->dependSliceMode != 0) {
  3515. VLOG(ERR,"CFG FAIL : If WaveFrontSynchro(WPP) '1', the option of multi-slice must be '0'\n");
  3516. VLOG(ERR,"RECOMMEND CONFIG PARAMETER : independSliceMode = 0, dependSliceMode = 0\n");
  3517. ret = RETCODE_FAILURE;
  3518. }
  3519. if(param->independSliceMode == 0 && param->dependSliceMode != 0)
  3520. {
  3521. VLOG(ERR,"CFG FAIL : If independSliceMode is '0', dependSliceMode must be '0'\n");
  3522. VLOG(ERR,"RECOMMEND CONFIG PARAMETER : independSliceMode = 1, independSliceModeArg = TotalCtuNum\n");
  3523. ret = RETCODE_FAILURE;
  3524. }
  3525. else if((param->independSliceMode == 1) && (param->dependSliceMode == 1) )
  3526. {
  3527. if(param->independSliceModeArg < param->dependSliceModeArg)
  3528. {
  3529. VLOG(ERR,"CFG FAIL : If independSliceMode & dependSliceMode is both '1' (multi-slice with ctu count), must be independSliceModeArg >= dependSliceModeArg\n");
  3530. VLOG(ERR,"RECOMMEND CONFIG PARAMETER : dependSliceMode = 0\n");
  3531. ret = RETCODE_FAILURE;
  3532. }
  3533. }
  3534. if (param->independSliceMode != 0)
  3535. {
  3536. if (param->independSliceModeArg > 65535)
  3537. {
  3538. VLOG(ERR,"CFG FAIL : If independSliceMode is not 0, must be independSliceModeArg <= 0xFFFF\n");
  3539. ret = RETCODE_FAILURE;
  3540. }
  3541. }
  3542. if (param->dependSliceMode != 0)
  3543. {
  3544. if (param->dependSliceModeArg > 65535)
  3545. {
  3546. VLOG(ERR,"CFG FAIL : If dependSliceMode is not 0, must be dependSliceModeArg <= 0xFFFF\n");
  3547. ret = RETCODE_FAILURE;
  3548. }
  3549. }
  3550. }
  3551. if (param->confWinTop % 2) {
  3552. VLOG(ERR, "CFG FAIL : conf_win_top : %d value is not available. The value should be equal to multiple of 2.\n", param->confWinTop);
  3553. ret = RETCODE_FAILURE;
  3554. }
  3555. if (param->confWinBot % 2) {
  3556. VLOG(ERR, "CFG FAIL : conf_win_bot : %d value is not available. The value should be equal to multiple of 2.\n", param->confWinBot);
  3557. ret = RETCODE_FAILURE;
  3558. }
  3559. if (param->confWinLeft % 2) {
  3560. VLOG(ERR, "CFG FAIL : conf_win_left : %d value is not available. The value should be equal to multiple of 2.\n", param->confWinLeft);
  3561. ret = RETCODE_FAILURE;
  3562. }
  3563. if (param->confWinRight % 2) {
  3564. VLOG(ERR, "CFG FAIL : conf_win_right : %d value is not available. The value should be equal to multiple of 2.\n", param->confWinRight);
  3565. ret = RETCODE_FAILURE;
  3566. }
  3567. // RDO
  3568. if (param->cuSizeMode == 0) {
  3569. VLOG(ERR, "CFG FAIL : EnCu8x8, EnCu16x16, and EnCu32x32 must be equal to 1 respectively.\n");
  3570. ret = RETCODE_FAILURE;
  3571. }
  3572. if (param->losslessEnable && (param->nrYEnable || param->nrCbEnable || param->nrCrEnable)) {
  3573. VLOG(ERR, "CFG FAIL : LosslessCoding and NoiseReduction (EnNrY, EnNrCb, and EnNrCr) cannot be used simultaneously.\n");
  3574. ret = RETCODE_FAILURE;
  3575. }
  3576. if (param->losslessEnable && param->bgDetectEnable) {
  3577. VLOG(ERR, "CFG FAIL : LosslessCoding and BgDetect cannot be used simultaneously.\n");
  3578. ret = RETCODE_FAILURE;
  3579. }
  3580. if (param->losslessEnable && pop->rcEnable) {
  3581. VLOG(ERR, "CFG FAIL : osslessCoding and RateControl cannot be used simultaneously.\n");
  3582. ret = RETCODE_FAILURE;
  3583. }
  3584. if (param->losslessEnable && param->roiEnable) {
  3585. VLOG(ERR, "CFG FAIL : LosslessCoding and Roi cannot be used simultaneously.\n");
  3586. ret = RETCODE_FAILURE;
  3587. }
  3588. if (param->losslessEnable && !param->skipIntraTrans) {
  3589. VLOG(ERR, "CFG FAIL : IntraTransSkip must be enabled when LosslessCoding is enabled.\n");
  3590. ret = RETCODE_FAILURE;
  3591. }
  3592. // Intra refresh
  3593. {
  3594. Int32 num_ctu_row = (pop->picHeight + 64 - 1) / 64;
  3595. Int32 num_ctu_col = (pop->picWidth + 64 - 1) / 64;
  3596. if(param->intraRefreshMode && param->intraRefreshArg <= 0)
  3597. {
  3598. VLOG(ERR, "CFG FAIL : IntraCtuRefreshArg must be greater then 0 when IntraCtuRefreshMode is enabled.\n");
  3599. ret = RETCODE_FAILURE;
  3600. }
  3601. if(param->intraRefreshMode == 1 && param->intraRefreshArg > num_ctu_row)
  3602. {
  3603. VLOG(ERR, "CFG FAIL : IntraCtuRefreshArg must be less then the number of CTUs in a row when IntraCtuRefreshMode is equal to 1.\n");
  3604. ret = RETCODE_FAILURE;
  3605. }
  3606. if(param->intraRefreshMode == 2 && param->intraRefreshArg > num_ctu_col)
  3607. {
  3608. VLOG(ERR, "CFG FAIL : IntraCtuRefreshArg must be less then the number of CTUs in a column when IntraCtuRefreshMode is equal to 2.\n");
  3609. ret = RETCODE_FAILURE;
  3610. }
  3611. if(param->intraRefreshMode == 3 && param->intraRefreshArg > num_ctu_row*num_ctu_col)
  3612. {
  3613. VLOG(ERR, "CFG FAIL : IntraCtuRefreshArg must be less then the number of CTUs in a picture when IntraCtuRefreshMode is equal to 3.\n");
  3614. ret = RETCODE_FAILURE;
  3615. }
  3616. if(param->intraRefreshMode == 4 && param->intraRefreshArg > num_ctu_row*num_ctu_col)
  3617. {
  3618. VLOG(ERR, "CFG FAIL : IntraCtuRefreshArg must be less then the number of CTUs in a picture when IntraCtuRefreshMode is equal to 4.\n");
  3619. ret = RETCODE_FAILURE;
  3620. }
  3621. if(param->intraRefreshMode == 4 && param->losslessEnable)
  3622. {
  3623. VLOG(ERR, "CFG FAIL : LosslessCoding and IntraCtuRefreshMode (4) cannot be used simultaneously.\n");
  3624. ret = RETCODE_FAILURE;
  3625. }
  3626. if(param->intraRefreshMode == 4 && param->roiEnable)
  3627. {
  3628. VLOG(ERR, "CFG FAIL : Roi and IntraCtuRefreshMode (4) cannot be used simultaneously.\n");
  3629. ret = RETCODE_FAILURE;
  3630. }
  3631. }
  3632. return ret;
  3633. }
  3634. RetCode CheckEncRcParamValid(EncOpenParam* pop)
  3635. {
  3636. RetCode ret = RETCODE_SUCCESS;
  3637. EncWaveParam* param = &pop->EncStdParam.waveParam;
  3638. if(pop->rcEnable == 1)
  3639. {
  3640. if((param->minQpI > param->maxQpI) || (param->minQpP > param->maxQpP) || (param->minQpB > param->maxQpB))
  3641. {
  3642. VLOG(ERR,"CFG FAIL : Not allowed MinQP > MaxQP\n");
  3643. VLOG(ERR,"RECOMMEND CONFIG PARAMETER : MinQP = MaxQP\n");
  3644. ret = RETCODE_FAILURE;
  3645. }
  3646. if(pop->bitRate <= (int) pop->frameRateInfo)
  3647. {
  3648. VLOG(ERR,"CFG FAIL : Not allowed EncBitRate <= FrameRate\n");
  3649. VLOG(ERR,"RECOMMEND CONFIG PARAMETER : EncBitRate = FrameRate * 10000\n");
  3650. ret = RETCODE_FAILURE;
  3651. }
  3652. }
  3653. return ret;
  3654. }
  3655. RetCode CheckEncCustomGopParamValid(EncOpenParam* pop)
  3656. {
  3657. RetCode ret = RETCODE_SUCCESS;
  3658. CustomGopParam* gopParam;
  3659. CustomGopPicParam* gopPicParam;
  3660. CustomGopPicParam new_gop[MAX_GOP_NUM*2 +1];
  3661. Int32 curr_poc, i, ei, gi, gop_size;
  3662. Int32 enc_tid[MAX_GOP_NUM*2 +1];
  3663. gopParam = &(pop->EncStdParam.waveParam.gopParam);
  3664. gop_size = gopParam->customGopSize;
  3665. new_gop[0].pocOffset = 0;
  3666. new_gop[0].temporalId = 0;
  3667. new_gop[0].picType = PIC_TYPE_I;
  3668. new_gop[0].numRefPicL0 = 0;
  3669. enc_tid[0] = 0;
  3670. for(i = 0; i < gop_size * 2; i++)
  3671. {
  3672. ei = i % gop_size;
  3673. gi = i / gop_size;
  3674. gopPicParam = &gopParam->picParam[ei];
  3675. curr_poc = gi * gop_size + gopPicParam->pocOffset;
  3676. new_gop[i + 1].pocOffset = curr_poc;
  3677. new_gop[i + 1].temporalId = gopPicParam->temporalId;
  3678. new_gop[i + 1].picType = gopPicParam->picType;
  3679. new_gop[i + 1].refPocL0 = gopPicParam->refPocL0 + gi * gop_size;
  3680. new_gop[i + 1].refPocL1 = gopPicParam->refPocL1 + gi * gop_size;
  3681. new_gop[i + 1].numRefPicL0 = gopPicParam->numRefPicL0;
  3682. enc_tid[i + 1] = -1;
  3683. }
  3684. for(i = 0; i < gop_size; i++)
  3685. {
  3686. gopPicParam = &gopParam->picParam[ei];
  3687. if(gopPicParam->pocOffset <= 0)
  3688. {
  3689. VLOG(ERR, "CFG FAIL : the POC of the %d-th picture must be greater then -1\n", i+1);
  3690. ret = RETCODE_FAILURE;
  3691. }
  3692. if(gopPicParam->pocOffset > gop_size)
  3693. {
  3694. VLOG(ERR, "CFG FAIL : the POC of the %d-th picture must be less then GopSize + 1\n", i+1);
  3695. ret = RETCODE_FAILURE;
  3696. }
  3697. if(gopPicParam->temporalId < 0)
  3698. {
  3699. VLOG(ERR, "CFG FAIL : the temporal_id of the %d-th picture must be greater than -1\n", i+1);
  3700. ret = RETCODE_FAILURE;
  3701. }
  3702. }
  3703. for(ei = 1; ei < gop_size * 2 + 1; ei++)
  3704. {
  3705. CustomGopPicParam* cur_pic = &new_gop[ei];
  3706. if(ei <= gop_size)
  3707. {
  3708. enc_tid[cur_pic->pocOffset] = cur_pic->temporalId;
  3709. continue;
  3710. }
  3711. if(new_gop[ei].picType != PIC_TYPE_I)
  3712. {
  3713. Int32 ref_poc = cur_pic->refPocL0;
  3714. if(enc_tid[ref_poc] < 0) // reference picture is not encoded yet
  3715. {
  3716. VLOG(ERR, "CFG FAIL : the 1st reference picture cannot be used as the reference of the picture (POC %d) in encoding order\n", cur_pic->pocOffset - gop_size);
  3717. ret = RETCODE_FAILURE;
  3718. }
  3719. if(enc_tid[ref_poc] > cur_pic->temporalId)
  3720. {
  3721. VLOG(ERR, "CFG FAIL : the temporal_id of the picture (POC %d) is wrong\n", cur_pic->pocOffset - gop_size);
  3722. ret = RETCODE_FAILURE;
  3723. }
  3724. if(ref_poc >= cur_pic->pocOffset)
  3725. {
  3726. VLOG(ERR, "CFG FAIL : the POC of the 1st reference picture of %d-th picture is wrong\n", cur_pic->pocOffset - gop_size);
  3727. ret = RETCODE_FAILURE;
  3728. }
  3729. }
  3730. if(new_gop[ei].picType != PIC_TYPE_P)
  3731. {
  3732. Int32 ref_poc = cur_pic->refPocL1;
  3733. if(enc_tid[ref_poc] < 0) // reference picture is not encoded yet
  3734. {
  3735. VLOG(ERR, "CFG FAIL : the 2nd reference picture cannot be used as the reference of the picture (POC %d) in encoding order\n", cur_pic->pocOffset - gop_size);
  3736. ret = RETCODE_FAILURE;
  3737. }
  3738. if(enc_tid[ref_poc] > cur_pic->temporalId)
  3739. {
  3740. VLOG(ERR, "CFG FAIL : the temporal_id of %d-th picture is wrong\n", cur_pic->pocOffset - gop_size);
  3741. ret = RETCODE_FAILURE;
  3742. }
  3743. if(new_gop[ei].picType == PIC_TYPE_P && new_gop[ei].numRefPicL0>1)
  3744. {
  3745. if(ref_poc >= cur_pic->pocOffset)
  3746. {
  3747. VLOG(ERR, "CFG FAIL : the POC of the 2nd reference picture of %d-th picture is wrong\n", cur_pic->pocOffset - gop_size);
  3748. ret = RETCODE_FAILURE;
  3749. }
  3750. }
  3751. else // HOST_PIC_TYPE_B
  3752. {
  3753. if(ref_poc == cur_pic->pocOffset)
  3754. {
  3755. VLOG(ERR, "CFG FAIL : the POC of the 2nd reference picture of %d-th picture is wrong\n", cur_pic->pocOffset - gop_size);
  3756. ret = RETCODE_FAILURE;
  3757. }
  3758. }
  3759. }
  3760. curr_poc = cur_pic->pocOffset;
  3761. enc_tid[curr_poc] = cur_pic->temporalId;
  3762. }
  3763. return ret;
  3764. }