coda9.c 105 KB

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  1. /*
  2. * Copyright (c) 2019, Chips&Media
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions are met:
  7. *
  8. * 1. Redistributions of source code must retain the above copyright notice, this
  9. * list of conditions and the following disclaimer.
  10. * 2. Redistributions in binary form must reproduce the above copyright notice,
  11. * this list of conditions and the following disclaimer in the documentation
  12. * and/or other materials provided with the distribution.
  13. *
  14. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  15. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  16. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  17. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
  18. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  19. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  20. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  21. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  23. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24. */
  25. #include "coda9_vpuconfig.h"
  26. #include "product.h"
  27. #include "coda9_regdefine.h"
  28. #include "misc/debug.h"
  29. static void LoadBitCode(Uint32 coreIdx, PhysicalAddress codeBase, const Uint16 *codeWord, int codeSize)
  30. {
  31. int i;
  32. BYTE code[8];
  33. for (i=0; i<codeSize; i+=4) {
  34. // 2byte little endian variable to 1byte big endian buffer
  35. code[0] = (BYTE)(codeWord[i+0]>>8);
  36. code[1] = (BYTE)codeWord[i+0];
  37. code[2] = (BYTE)(codeWord[i+1]>>8);
  38. code[3] = (BYTE)codeWord[i+1];
  39. code[4] = (BYTE)(codeWord[i+2]>>8);
  40. code[5] = (BYTE)codeWord[i+2];
  41. code[6] = (BYTE)(codeWord[i+3]>>8);
  42. code[7] = (BYTE)codeWord[i+3];
  43. VpuWriteMem(coreIdx, codeBase+i*2, (BYTE *)code, 8, VDI_BIG_ENDIAN);
  44. }
  45. vdi_set_bit_firmware_to_pm(coreIdx, codeWord);
  46. }
  47. static RetCode BitLoadFirmware(Uint32 coreIdx, PhysicalAddress codeBase, const Uint16 *codeWord, int codeSize)
  48. {
  49. int i;
  50. Uint32 data;
  51. LoadBitCode(coreIdx, codeBase, codeWord, codeSize);
  52. VpuWriteReg(coreIdx, BIT_INT_ENABLE, 0);
  53. VpuWriteReg(coreIdx, BIT_CODE_RUN, 0);
  54. for (i=0; i<2048; ++i) {
  55. data = codeWord[i];
  56. VpuWriteReg(coreIdx, BIT_CODE_DOWN, (i << 16) | data);
  57. }
  58. return RETCODE_SUCCESS;
  59. }
  60. static void SetEncFrameMemInfo(CodecInst* pCodecInst)
  61. {
  62. Uint32 val;
  63. EncInfo* pEncInfo = &pCodecInst->CodecInfo->encInfo;
  64. switch (pCodecInst->productId) {
  65. case PRODUCT_ID_960:
  66. val = 0;
  67. if (pEncInfo->mapType) {
  68. if (pEncInfo->mapType == TILED_FRAME_MB_RASTER_MAP || pEncInfo->mapType == TILED_FIELD_MB_RASTER_MAP)
  69. val |= (pEncInfo->linear2TiledEnable<<11)|(0x03<<9)|(FORMAT_420<<6);
  70. else
  71. val |= (pEncInfo->linear2TiledEnable<<11)|(0x02<<9)|(FORMAT_420<<6);
  72. }
  73. val |= ((pEncInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  74. #if defined(SUPPORT_NV21) || defined(SUPPORT_ENC_NV21)
  75. val |= (pEncInfo->openParam.cbcrInterleave&pEncInfo->openParam.nv21) << 3;
  76. #endif
  77. val |= (pEncInfo->openParam.bwbEnable<<12);
  78. val |= pEncInfo->openParam.frameEndian;
  79. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  80. break;
  81. }
  82. return;
  83. }
  84. void Coda9BitIssueCommand(Uint32 coreIdx, CodecInst *inst, int cmd)
  85. {
  86. int instIdx = 0;
  87. int cdcMode = 0;
  88. int auxMode = 0;
  89. if (inst != NULL) // command is specific to instance
  90. {
  91. instIdx = inst->instIndex;
  92. cdcMode = inst->codecMode;
  93. auxMode = inst->codecModeAux;
  94. }
  95. if (inst) {
  96. if (inst->codecMode < AVC_ENC) {
  97. VpuWriteReg(coreIdx, BIT_WORK_BUF_ADDR, inst->CodecInfo->decInfo.vbWork.phys_addr);
  98. }
  99. else {
  100. VpuWriteReg(coreIdx, BIT_WORK_BUF_ADDR, inst->CodecInfo->encInfo.vbWork.phys_addr);
  101. }
  102. }
  103. VpuWriteReg(coreIdx, BIT_BUSY_FLAG, 1);
  104. VpuWriteReg(coreIdx, BIT_RUN_INDEX, instIdx);
  105. VpuWriteReg(coreIdx, BIT_RUN_COD_STD, cdcMode);
  106. VpuWriteReg(coreIdx, BIT_RUN_AUX_STD, auxMode);
  107. if (inst && inst->loggingEnable)
  108. vdi_log(coreIdx, cmd, 1);
  109. VpuWriteReg(coreIdx, BIT_RUN_COMMAND, cmd);
  110. }
  111. static void SetupCoda9Properties(Uint32 coreIdx, Uint32 productId)
  112. {
  113. VpuAttr* pAttr = &g_VpuCoreAttributes[coreIdx];
  114. Int32 val;
  115. char* pstr;
  116. /* Setup Attributes */
  117. pAttr = &g_VpuCoreAttributes[coreIdx];
  118. // Hardware version information
  119. val = VpuReadReg(coreIdx, VPU_PRODUCT_CODE_REGISTER);
  120. if ((val&0xff00) == 0x3200) val = 0x3200;
  121. val = VpuReadReg(coreIdx, DBG_CONFIG_REPORT_0);
  122. pstr = (char*)&val;
  123. pAttr->productName[0] = pstr[3];
  124. pAttr->productName[1] = pstr[2];
  125. pAttr->productName[2] = pstr[1];
  126. pAttr->productName[3] = pstr[0];
  127. pAttr->productName[4] = 0;
  128. pAttr->supportDecoders = (1<<STD_AVC) |
  129. (1<<STD_VC1) |
  130. (1<<STD_MPEG2) |
  131. (1<<STD_MPEG4) |
  132. (1<<STD_H263) |
  133. (1<<STD_AVS) |
  134. (1<<STD_DIV3) |
  135. (1<<STD_RV) |
  136. (1<<STD_THO) |
  137. (1<<STD_VP8);
  138. /* Encoder */
  139. pAttr->supportEncoders = (1<<STD_AVC) | (1<<STD_MPEG4) | (1<<STD_H263);
  140. /* WTL */
  141. if (productId == PRODUCT_ID_960 || productId == PRODUCT_ID_980) {
  142. pAttr->supportWTL = 1;
  143. }
  144. /* Tiled2Linear */
  145. pAttr->supportTiled2Linear = 1;
  146. /* Maptypes */
  147. pAttr->supportMapTypes = (1<<LINEAR_FRAME_MAP) |
  148. (1<<TILED_FRAME_V_MAP) |
  149. (1<<TILED_FRAME_H_MAP) |
  150. (1<<TILED_FIELD_V_MAP) |
  151. (1<<TILED_MIXED_V_MAP) |
  152. (1<<TILED_FRAME_MB_RASTER_MAP) |
  153. (1<<TILED_FIELD_MB_RASTER_MAP);
  154. if (productId == PRODUCT_ID_980) {
  155. pAttr->supportMapTypes |= (1<<TILED_FRAME_NO_BANK_MAP) |
  156. (1<<TILED_FIELD_NO_BANK_MAP);
  157. }
  158. /* Linear2Tiled */
  159. if (productId == PRODUCT_ID_960 || productId == PRODUCT_ID_980) {
  160. pAttr->supportLinear2Tiled = 1;
  161. }
  162. /* Framebuffer Cache */
  163. if (productId == PRODUCT_ID_960)
  164. pAttr->framebufferCacheType = FramebufCacheMaverickI;
  165. else if (productId == PRODUCT_ID_980)
  166. pAttr->framebufferCacheType = FramebufCacheMaverickII;
  167. else
  168. pAttr->framebufferCacheType = FramebufCacheNone;
  169. /* AXI 128bit Bus */
  170. pAttr->support128bitBus = FALSE;
  171. pAttr->supportEndianMask = (1<<VDI_LITTLE_ENDIAN) | (1<<VDI_BIG_ENDIAN) | (1<<VDI_32BIT_LITTLE_ENDIAN) | (1<<VDI_32BIT_BIG_ENDIAN);
  172. pAttr->supportBitstreamMode = (1<<BS_MODE_INTERRUPT) | (1<<BS_MODE_PIC_END);
  173. pAttr->bitstreamBufferMargin = VPU_GBU_SIZE;
  174. pAttr->numberOfMemProtectRgns = 6;
  175. }
  176. Uint32 Coda9VpuGetProductId(Uint32 coreIdx)
  177. {
  178. Uint32 productId;
  179. Uint32 val;
  180. val = VpuReadReg(coreIdx, VPU_PRODUCT_CODE_REGISTER);
  181. if (val == BODA950_CODE)
  182. productId = PRODUCT_ID_950;
  183. else if (val == CODA960_CODE)
  184. productId = PRODUCT_ID_960;
  185. else if (val == CODA980_CODE)
  186. productId = PRODUCT_ID_980;
  187. else
  188. productId = PRODUCT_ID_NONE;
  189. if (productId != PRODUCT_ID_NONE)
  190. SetupCoda9Properties(coreIdx, productId);
  191. return productId;
  192. }
  193. RetCode Coda9VpuGetVersion(Uint32 coreIdx, Uint32* versionInfo, Uint32* revision)
  194. {
  195. /* Get Firmware version */
  196. VpuWriteReg(coreIdx, RET_FW_VER_NUM , 0);
  197. Coda9BitIssueCommand(coreIdx, NULL, FIRMWARE_GET);
  198. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1)
  199. return RETCODE_VPU_RESPONSE_TIMEOUT;
  200. if (versionInfo != NULL) {
  201. *versionInfo = VpuReadReg(coreIdx, RET_FW_VER_NUM);
  202. }
  203. if (revision != NULL) {
  204. *revision = VpuReadReg(coreIdx, RET_FW_CODE_REV);
  205. }
  206. return RETCODE_SUCCESS;
  207. }
  208. RetCode Coda9VpuInit(Uint32 coreIdx, void* firmware, Uint32 size)
  209. {
  210. Uint32 data;
  211. vpu_buffer_t vb;
  212. PhysicalAddress tempBuffer;
  213. PhysicalAddress paraBuffer;
  214. PhysicalAddress codeBuffer;
  215. vdi_get_common_memory((unsigned long)coreIdx, &vb);
  216. codeBuffer = vb.phys_addr;
  217. tempBuffer = codeBuffer + CODE_BUF_SIZE;
  218. paraBuffer = tempBuffer + TEMP_BUF_SIZE;
  219. BitLoadFirmware(coreIdx, codeBuffer, (const Uint16 *)firmware, size);
  220. /* Clear registers */
  221. if (vdi_read_register(coreIdx, BIT_CUR_PC) == 0) {
  222. Uint32 i;
  223. for (i=0; i<64; i++) {
  224. vdi_write_register(coreIdx, (i*4) + 0x100, 0x0);
  225. }
  226. }
  227. VpuWriteReg(coreIdx, BIT_PARA_BUF_ADDR, paraBuffer);
  228. VpuWriteReg(coreIdx, BIT_CODE_BUF_ADDR, codeBuffer);
  229. VpuWriteReg(coreIdx, BIT_TEMP_BUF_ADDR, tempBuffer);
  230. VpuWriteReg(coreIdx, BIT_BIT_STREAM_CTRL, VPU_STREAM_ENDIAN);
  231. VpuWriteReg(coreIdx, BIT_FRAME_MEM_CTRL, CBCR_INTERLEAVE<<2|VPU_FRAME_ENDIAN); // Interleave bit position is modified
  232. VpuWriteReg(coreIdx, BIT_BIT_STREAM_PARAM, 0);
  233. VpuWriteReg(coreIdx, BIT_AXI_SRAM_USE, 0);
  234. VpuWriteReg(coreIdx, BIT_INT_ENABLE, 0);
  235. VpuWriteReg(coreIdx, BIT_ROLLBACK_STATUS, 0);
  236. data = (1<<INT_BIT_BIT_BUF_FULL);
  237. data |= (1<<INT_BIT_BIT_BUF_EMPTY);
  238. data |= (1<<INT_BIT_DEC_MB_ROWS);
  239. data |= (1<<INT_BIT_SEQ_INIT);
  240. data |= (1<<INT_BIT_DEC_FIELD);
  241. data |= (1<<INT_BIT_PIC_RUN);
  242. VpuWriteReg(coreIdx, BIT_INT_ENABLE, data);
  243. VpuWriteReg(coreIdx, BIT_INT_CLEAR, 0x1);
  244. VpuWriteReg(coreIdx, BIT_BUSY_FLAG, 0x1);
  245. VpuWriteReg(coreIdx, BIT_CODE_RESET, 1);
  246. VpuWriteReg(coreIdx, BIT_CODE_RUN, 1);
  247. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1)
  248. return RETCODE_VPU_RESPONSE_TIMEOUT;
  249. return RETCODE_SUCCESS;
  250. }
  251. RetCode Coda9VpuReInit(Uint32 coreIdx, void* firmware, Uint32 size)
  252. {
  253. vpu_buffer_t vb;
  254. PhysicalAddress tempBuffer;
  255. PhysicalAddress paraBuffer;
  256. PhysicalAddress codeBuffer;
  257. PhysicalAddress oldCodeBuffer;
  258. vdi_get_common_memory((unsigned long)coreIdx, &vb);
  259. codeBuffer = vb.phys_addr;
  260. tempBuffer = codeBuffer + CODE_BUF_SIZE;
  261. paraBuffer = tempBuffer + TEMP_BUF_SIZE;
  262. oldCodeBuffer = VpuReadReg(coreIdx, BIT_CODE_BUF_ADDR);
  263. VpuWriteReg(coreIdx, BIT_PARA_BUF_ADDR, paraBuffer);
  264. VpuWriteReg(coreIdx, BIT_CODE_BUF_ADDR, codeBuffer);
  265. VpuWriteReg(coreIdx, BIT_TEMP_BUF_ADDR, tempBuffer);
  266. if (oldCodeBuffer != codeBuffer) {
  267. LoadBitCode(coreIdx, codeBuffer, (const Uint16 *)firmware, size);
  268. }
  269. return RETCODE_SUCCESS;
  270. }
  271. Uint32 Coda9VpuIsInit(Uint32 coreIdx)
  272. {
  273. Uint32 pc;
  274. pc = VpuReadReg(coreIdx, BIT_CUR_PC);
  275. return pc;
  276. }
  277. Int32 Coda9VpuIsBusy(Uint32 coreIdx)
  278. {
  279. return VpuReadReg(coreIdx, BIT_BUSY_FLAG);
  280. }
  281. Int32 Coda9VpuWaitInterrupt(CodecInst* handle, Int32 timeout)
  282. {
  283. Int32 reason = 0;
  284. #ifdef SUPPORT_MULTI_INST_INTR
  285. reason = vdi_wait_interrupt(handle->coreIdx, 0, timeout);
  286. #else
  287. reason = vdi_wait_interrupt(handle->coreIdx, timeout);
  288. #endif
  289. if (reason != INTERRUPT_TIMEOUT_VALUE) {
  290. VpuWriteReg(handle->coreIdx, BIT_INT_CLEAR, 1); // clear HW signal
  291. }
  292. return reason;
  293. }
  294. RetCode Coda9VpuClearInterrupt(Uint32 coreIdx)
  295. {
  296. VpuWriteReg(coreIdx, BIT_INT_REASON, 0); // tell to F/W that HOST received an interrupt.
  297. return RETCODE_SUCCESS;
  298. }
  299. RetCode Coda9VpuReset(Uint32 coreIdx, SWResetMode resetMode)
  300. {
  301. Uint32 cmd;
  302. Int32 productId = Coda9VpuGetProductId(coreIdx);
  303. if (productId == PRODUCT_ID_960 || productId == PRODUCT_ID_980) {
  304. if (resetMode != SW_RESET_ON_BOOT) {
  305. cmd = VpuReadReg(coreIdx, BIT_RUN_COMMAND);
  306. if (cmd == DEC_SEQ_INIT || cmd == PIC_RUN) {
  307. if (VpuReadReg(coreIdx, BIT_BUSY_FLAG) || VpuReadReg(coreIdx, BIT_INT_REASON)) {
  308. #define MBC_SET_SUBBLK_EN (MBC_BASE+0xA0) // subblk_man_mode[20] cr_subblk_man_en[19:0]
  309. // stop all of pipeline
  310. VpuWriteReg(coreIdx, MBC_SET_SUBBLK_EN, ((1<<20) | 0));
  311. // force to set the end of Bitstream to be decoded.
  312. cmd = VpuReadReg(coreIdx, BIT_BIT_STREAM_PARAM);
  313. cmd |= 1 << 2;
  314. VpuWriteReg(coreIdx, BIT_BIT_STREAM_PARAM, cmd);
  315. cmd = VpuReadReg(coreIdx, BIT_RD_PTR);
  316. VpuWriteReg(coreIdx, BIT_WR_PTR, cmd);
  317. #ifdef SUPPORT_MULTI_INST_INTR
  318. cmd = vdi_wait_interrupt(coreIdx, 0, __VPU_BUSY_TIMEOUT);
  319. #else
  320. cmd = vdi_wait_interrupt(coreIdx, __VPU_BUSY_TIMEOUT);
  321. #endif
  322. if ((Int32)cmd != INTERRUPT_TIMEOUT_VALUE) {
  323. VpuWriteReg(coreIdx, BIT_INT_REASON, 0);
  324. VpuWriteReg(coreIdx, BIT_INT_CLEAR, 1); // clear HW signal
  325. }
  326. // now all of hardwares would be stop.
  327. }
  328. }
  329. }
  330. // Waiting for completion of BWB transaction first
  331. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, GDI_BWB_STATUS) == -1) {
  332. vdi_log(coreIdx, 0x10, 2);
  333. return RETCODE_VPU_RESPONSE_TIMEOUT;
  334. }
  335. // Waiting for completion of bus transaction
  336. // Step1 : No more request
  337. VpuWriteReg(coreIdx, GDI_BUS_CTRL, 0x11); // no more request {3'b0,no_more_req_sec,3'b0,no_more_req}
  338. // Step2 : Waiting for completion of bus transaction
  339. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, GDI_BUS_STATUS) == -1) {
  340. VpuWriteReg(coreIdx, GDI_BUS_CTRL, 0x00);
  341. vdi_log(coreIdx, 0x10, 2);
  342. return RETCODE_VPU_RESPONSE_TIMEOUT;
  343. }
  344. cmd = 0;
  345. // Software Reset Trigger
  346. if (resetMode != SW_RESET_ON_BOOT)
  347. cmd = VPU_SW_RESET_BPU_CORE | VPU_SW_RESET_BPU_BUS;
  348. cmd |= VPU_SW_RESET_VCE_CORE | VPU_SW_RESET_VCE_BUS;
  349. if (resetMode == SW_RESET_ON_BOOT)
  350. cmd |= VPU_SW_RESET_GDI_CORE | VPU_SW_RESET_GDI_BUS;// If you reset GDI, tiled map should be reconfigured
  351. VpuWriteReg(coreIdx, BIT_SW_RESET, cmd);
  352. // wait until reset is done
  353. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_SW_RESET_STATUS) == -1) {
  354. VpuWriteReg(coreIdx, BIT_SW_RESET, 0x00);
  355. VpuWriteReg(coreIdx, GDI_BUS_CTRL, 0x00);
  356. vdi_log(coreIdx, 0x10, 2);
  357. return RETCODE_VPU_RESPONSE_TIMEOUT;
  358. }
  359. VpuWriteReg(coreIdx, BIT_SW_RESET, 0);
  360. // Step3 : must clear GDI_BUS_CTRL after done SW_RESET
  361. VpuWriteReg(coreIdx, GDI_BUS_CTRL, 0x00);
  362. }
  363. else {
  364. vdi_log(coreIdx, 0x10, 0);
  365. return RETCODE_NOT_FOUND_VPU_DEVICE;
  366. }
  367. return RETCODE_SUCCESS;
  368. }
  369. RetCode Coda9VpuSleepWake(Uint32 coreIdx, int iSleepWake, const Uint16* code, Uint32 size)
  370. {
  371. static unsigned int regBk[64];
  372. int i=0;
  373. const Uint16* bit_code = NULL;
  374. if (code && size > 0)
  375. bit_code = code;
  376. if (!bit_code)
  377. return RETCODE_INVALID_PARAM;
  378. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  379. return RETCODE_VPU_RESPONSE_TIMEOUT;
  380. }
  381. if(iSleepWake==1)
  382. {
  383. for ( i = 0 ; i < 64 ; i++)
  384. regBk[i] = VpuReadReg(coreIdx, BIT_BASE + 0x100 + (i * 4));
  385. }
  386. else
  387. {
  388. VpuWriteReg(coreIdx, BIT_CODE_RUN, 0);
  389. for ( i = 0 ; i < 64 ; i++)
  390. VpuWriteReg(coreIdx, BIT_BASE + 0x100 + (i * 4), regBk[i]);
  391. VpuWriteReg(coreIdx, BIT_BUSY_FLAG, 1);
  392. VpuWriteReg(coreIdx, BIT_CODE_RESET, 1);
  393. VpuWriteReg(coreIdx, BIT_CODE_RUN, 1);
  394. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  395. return RETCODE_VPU_RESPONSE_TIMEOUT;
  396. }
  397. }
  398. return RETCODE_SUCCESS;
  399. }
  400. static RetCode SetupDecCodecInstance(Int32 productId, CodecInst* pCodec)
  401. {
  402. DecInfo* pDecInfo = &pCodec->CodecInfo->decInfo;
  403. pDecInfo->streamRdPtrRegAddr = BIT_RD_PTR;
  404. pDecInfo->streamWrPtrRegAddr = BIT_WR_PTR;
  405. pDecInfo->frameDisplayFlagRegAddr = BIT_FRM_DIS_FLG;
  406. pDecInfo->currentPC = BIT_CUR_PC;
  407. pDecInfo->busyFlagAddr = BIT_BUSY_FLAG;
  408. if (productId == PRODUCT_ID_960) {
  409. pDecInfo->dramCfg.rasBit = EM_RAS;
  410. pDecInfo->dramCfg.casBit = EM_CAS;
  411. pDecInfo->dramCfg.bankBit = EM_BANK;
  412. pDecInfo->dramCfg.busBit = EM_WIDTH;
  413. }
  414. return RETCODE_SUCCESS;
  415. }
  416. static RetCode SetupEncCodecInstance(Int32 productId, CodecInst* pCodec)
  417. {
  418. EncInfo* pEncInfo = &pCodec->CodecInfo->encInfo;
  419. pEncInfo->streamRdPtrRegAddr = BIT_RD_PTR;
  420. pEncInfo->streamWrPtrRegAddr = BIT_WR_PTR;
  421. pEncInfo->currentPC = BIT_CUR_PC;
  422. pEncInfo->busyFlagAddr = BIT_BUSY_FLAG;
  423. if (productId == PRODUCT_ID_960) {
  424. pEncInfo->dramCfg.rasBit = EM_RAS;
  425. pEncInfo->dramCfg.casBit = EM_CAS;
  426. pEncInfo->dramCfg.bankBit = EM_BANK;
  427. pEncInfo->dramCfg.busBit = EM_WIDTH;
  428. }
  429. return RETCODE_SUCCESS;
  430. }
  431. RetCode Coda9VpuBuildUpDecParam(CodecInst* pCodec, DecOpenParam* param)
  432. {
  433. RetCode ret = RETCODE_SUCCESS;
  434. Uint32 coreIdx;
  435. Uint32 productId;
  436. DecInfo* pDecInfo = &pCodec->CodecInfo->decInfo;
  437. coreIdx = pCodec->coreIdx;
  438. productId = Coda9VpuGetProductId(coreIdx);
  439. if ((ret=SetupDecCodecInstance(productId, pCodec)) != RETCODE_SUCCESS)
  440. return ret;
  441. if (param->vbWork.size) {
  442. pDecInfo->vbWork = param->vbWork;
  443. pDecInfo->workBufferAllocExt = 1;
  444. }
  445. else {
  446. pDecInfo->vbWork.size = WORK_BUF_SIZE;
  447. if (pCodec->codecMode == AVC_DEC)
  448. pDecInfo->vbWork.size += PS_SAVE_SIZE;
  449. if (vdi_allocate_dma_memory(pCodec->coreIdx, &pDecInfo->vbWork, DEC_WORK, pCodec->instIndex) < 0)
  450. return RETCODE_INSUFFICIENT_RESOURCE;
  451. param->vbWork = pDecInfo->vbWork;
  452. pDecInfo->workBufferAllocExt = 0;
  453. }
  454. if (productId == PRODUCT_ID_960) {
  455. pDecInfo->dramCfg.bankBit = EM_BANK;
  456. pDecInfo->dramCfg.casBit = EM_CAS;
  457. pDecInfo->dramCfg.rasBit = EM_RAS;
  458. pDecInfo->dramCfg.busBit = EM_WIDTH;
  459. }
  460. return ret;
  461. }
  462. RetCode Coda9VpuDecInitSeq(DecHandle handle)
  463. {
  464. CodecInst* pCodecInst = (CodecInst*)handle;
  465. DecInfo* pDecInfo = &pCodecInst->CodecInfo->decInfo;
  466. Uint32 val = 0;
  467. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_BB_START, pDecInfo->streamBufStartAddr);
  468. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_BB_SIZE, pDecInfo->streamBufSize / 1024); // size in KBytes
  469. if(pDecInfo->userDataEnable == TRUE) {
  470. val = 0;
  471. val |= (pDecInfo->userDataReportMode << 10);
  472. val |= (pDecInfo->userDataEnable << 5);
  473. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_OPTION, val);
  474. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_BASE_ADDR, pDecInfo->userDataBufAddr);
  475. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_BUF_SIZE, pDecInfo->userDataBufSize);
  476. }
  477. else {
  478. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_OPTION, 0);
  479. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_BASE_ADDR, 0);
  480. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_BUF_SIZE, 0);
  481. }
  482. val = 0;
  483. val |= (pDecInfo->reorderEnable<<1) & 0x2;
  484. val |= (pDecInfo->openParam.mp4DeblkEnable & 0x1);
  485. val |= (pDecInfo->avcErrorConcealMode << 2);
  486. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_OPTION, val);
  487. switch(pCodecInst->codecMode) {
  488. case VC1_DEC:
  489. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_VC1_STREAM_FMT, (0 << 3) & 0x08);
  490. break;
  491. case MP4_DEC:
  492. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_MP4_ASP_CLASS, (VPU_GMC_PROCESS_METHOD<<3)|pDecInfo->openParam.mp4Class);
  493. break;
  494. case AVC_DEC:
  495. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_X264_MV_EN, VPU_AVC_X264_SUPPORT);
  496. break;
  497. }
  498. if( pCodecInst->codecMode == AVC_DEC )
  499. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_SPP_CHUNK_SIZE, VPU_GBU_SIZE);
  500. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->streamWrPtrRegAddr, pDecInfo->streamWrPtr);
  501. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->streamRdPtrRegAddr, pDecInfo->streamRdPtr);
  502. if (pCodecInst->productId == PRODUCT_ID_980 || pCodecInst->productId == PRODUCT_ID_960) {
  503. pDecInfo->streamEndflag &= ~(3<<3);
  504. if (pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END)
  505. pDecInfo->streamEndflag |= (2<<3);
  506. else { // Interrupt Mode
  507. if (pDecInfo->seqInitEscape) {
  508. pDecInfo->streamEndflag |= (2<<3);
  509. }
  510. }
  511. }
  512. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM, pDecInfo->streamEndflag);
  513. val = pDecInfo->openParam.streamEndian;
  514. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_CTRL, val);
  515. if (pCodecInst->productId == PRODUCT_ID_980) {
  516. val = 0;
  517. val |= (pDecInfo->openParam.bwbEnable<<15);
  518. val |= (pDecInfo->wtlMode<<17)|(pDecInfo->tiled2LinearMode<<13)|(FORMAT_420<<6);
  519. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  520. val |= pDecInfo->openParam.frameEndian;
  521. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  522. }
  523. else if (pCodecInst->productId == PRODUCT_ID_960) {
  524. val = 0;
  525. val |= (pDecInfo->wtlEnable<<17);
  526. val |= (pDecInfo->openParam.bwbEnable<<12);
  527. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  528. val |= pDecInfo->openParam.frameEndian;
  529. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  530. }
  531. else {
  532. return RETCODE_NOT_FOUND_VPU_DEVICE;
  533. }
  534. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->frameDisplayFlagRegAddr, 0);
  535. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, DEC_SEQ_INIT);
  536. return RETCODE_SUCCESS;
  537. }
  538. RetCode Coda9VpuFiniSeq(CodecInst* instance)
  539. {
  540. Coda9BitIssueCommand(instance->coreIdx, instance, DEC_SEQ_END);
  541. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  542. return RETCODE_VPU_RESPONSE_TIMEOUT;
  543. }
  544. return RETCODE_SUCCESS;
  545. }
  546. RetCode Coda9VpuDecode(CodecInst* instance, DecParam* param)
  547. {
  548. CodecInst* pCodecInst;
  549. DecInfo* pDecInfo;
  550. Uint32 rotMir;
  551. Int32 val;
  552. vpu_instance_pool_t *vip;
  553. pCodecInst = instance;
  554. pDecInfo = &pCodecInst->CodecInfo->decInfo;
  555. vip = (vpu_instance_pool_t *)vdi_get_instance_pool(pCodecInst->coreIdx);
  556. if (!vip) {
  557. return RETCODE_INVALID_HANDLE;
  558. }
  559. rotMir = 0;
  560. if (pDecInfo->rotationEnable) {
  561. rotMir |= 0x10; // Enable rotator
  562. switch (pDecInfo->rotationAngle) {
  563. case 0:
  564. rotMir |= 0x0;
  565. break;
  566. case 90:
  567. rotMir |= 0x1;
  568. break;
  569. case 180:
  570. rotMir |= 0x2;
  571. break;
  572. case 270:
  573. rotMir |= 0x3;
  574. break;
  575. }
  576. }
  577. if (pDecInfo->mirrorEnable) {
  578. rotMir |= 0x10; // Enable rotator
  579. switch (pDecInfo->mirrorDirection) {
  580. case MIRDIR_NONE :
  581. rotMir |= 0x0;
  582. break;
  583. case MIRDIR_VER :
  584. rotMir |= 0x4;
  585. break;
  586. case MIRDIR_HOR :
  587. rotMir |= 0x8;
  588. break;
  589. case MIRDIR_HOR_VER :
  590. rotMir |= 0xc;
  591. break;
  592. }
  593. }
  594. if (pDecInfo->tiled2LinearEnable) {
  595. rotMir |= 0x10;
  596. }
  597. if (pDecInfo->deringEnable) {
  598. rotMir |= 0x20; // Enable Dering Filter
  599. }
  600. if (rotMir && !pDecInfo->rotatorOutputValid) {
  601. return RETCODE_ROTATOR_OUTPUT_NOT_SET;
  602. }
  603. VpuWriteReg(pCodecInst->coreIdx, RET_DEC_PIC_CROP_LEFT_RIGHT, 0); // frame crop information(left, right)
  604. VpuWriteReg(pCodecInst->coreIdx, RET_DEC_PIC_CROP_TOP_BOTTOM, 0); // frame crop information(top, bottom)
  605. if (pCodecInst->productId == PRODUCT_ID_960) {
  606. if (pDecInfo->mapType>LINEAR_FRAME_MAP && pDecInfo->mapType<=TILED_MIXED_V_MAP) {
  607. SetTiledFrameBase(pCodecInst->coreIdx, pDecInfo->mapCfg.tiledBaseAddr);
  608. }
  609. else {
  610. SetTiledFrameBase(pCodecInst->coreIdx, 0);
  611. }
  612. }
  613. if (pDecInfo->mapType != LINEAR_FRAME_MAP && pDecInfo->mapType != LINEAR_FIELD_MAP) {
  614. val = SetTiledMapType(pCodecInst->coreIdx, &pDecInfo->mapCfg, pDecInfo->mapType,
  615. (pDecInfo->stride > pDecInfo->frameBufferHeight)?pDecInfo->stride: pDecInfo->frameBufferHeight,
  616. pDecInfo->openParam.cbcrInterleave, &pDecInfo->dramCfg);
  617. } else {
  618. val = SetTiledMapType(pCodecInst->coreIdx, &pDecInfo->mapCfg, pDecInfo->mapType,
  619. pDecInfo->stride, pDecInfo->openParam.cbcrInterleave, &pDecInfo->dramCfg);
  620. }
  621. if (val == 0) {
  622. return RETCODE_INVALID_PARAM;
  623. }
  624. if (rotMir & 0x30) { // rotator or dering or tiled2linear enabled
  625. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_MODE, rotMir);
  626. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_INDEX, pDecInfo->rotatorOutput.myIndex);
  627. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_ADDR_Y, pDecInfo->rotatorOutput.bufY);
  628. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_ADDR_CB, pDecInfo->rotatorOutput.bufCb);
  629. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_ADDR_CR, pDecInfo->rotatorOutput.bufCr);
  630. if (pCodecInst->productId == PRODUCT_ID_980) {
  631. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_BOTTOM_Y, pDecInfo->rotatorOutput.bufYBot);
  632. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_BOTTOM_CB, pDecInfo->rotatorOutput.bufCbBot);
  633. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_BOTTOM_CR, pDecInfo->rotatorOutput.bufCrBot);
  634. }
  635. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_STRIDE, pDecInfo->rotatorStride);
  636. }
  637. else {
  638. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_MODE, rotMir);
  639. }
  640. if(pDecInfo->userDataEnable) {
  641. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_USER_DATA_BASE_ADDR, pDecInfo->userDataBufAddr);
  642. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_USER_DATA_BUF_SIZE, pDecInfo->userDataBufSize);
  643. }
  644. else {
  645. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_USER_DATA_BASE_ADDR, 0);
  646. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_USER_DATA_BUF_SIZE, 0);
  647. }
  648. val = 0;
  649. if (param->iframeSearchEnable == TRUE) { // if iframeSearch is Enable, other bit is ignore;
  650. val |= (pDecInfo->userDataReportMode <<10);
  651. if (pCodecInst->codecMode == AVC_DEC || pCodecInst->codecMode == VC1_DEC) {
  652. if (param->iframeSearchEnable==1)
  653. val |= (1<< 11) | (1<<2);
  654. else if (param->iframeSearchEnable==2)
  655. val |= (1<<2);
  656. }
  657. else {
  658. val |= (( param->iframeSearchEnable &0x1) << 2 );
  659. }
  660. }
  661. else {
  662. val |= (pDecInfo->userDataReportMode <<10);
  663. val |= (pDecInfo->userDataEnable << 5);
  664. val |= (param->skipframeMode << 3);
  665. }
  666. if (pCodecInst->productId == PRODUCT_ID_980) {
  667. if (pCodecInst->codecMode == AVC_DEC && pDecInfo->lowDelayInfo.lowDelayEn) {
  668. val |= (pDecInfo->lowDelayInfo.lowDelayEn <<18 );
  669. }
  670. }
  671. if (pCodecInst->codecMode == MP2_DEC) {
  672. val |= ((param->DecStdParam.mp2PicFlush&1)<<15);
  673. }
  674. if (pCodecInst->codecMode == RV_DEC) {
  675. val |= ((param->DecStdParam.rvDbkMode&0x0f)<<16);
  676. }
  677. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_OPTION, val);
  678. if (pCodecInst->productId == PRODUCT_ID_980) {
  679. if (pDecInfo->lowDelayInfo.lowDelayEn == TRUE) {
  680. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_NUM_ROWS, pDecInfo->lowDelayInfo.numRows);
  681. }
  682. else {
  683. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_NUM_ROWS, 0);
  684. }
  685. }
  686. val = 0;
  687. val = (
  688. (pDecInfo->secAxiInfo.u.coda9.useBitEnable&0x01)<<0 |
  689. (pDecInfo->secAxiInfo.u.coda9.useIpEnable&0x01)<<1 |
  690. (pDecInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01)<<2 |
  691. (pDecInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01)<<3 |
  692. (pDecInfo->secAxiInfo.u.coda9.useOvlEnable&0x01)<<4 |
  693. (pDecInfo->secAxiInfo.u.coda9.useBtpEnable&0x01)<<5 |
  694. (pDecInfo->secAxiInfo.u.coda9.useBitEnable&0x01)<<8 |
  695. (pDecInfo->secAxiInfo.u.coda9.useIpEnable&0x01)<<9 |
  696. (pDecInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01)<<10 |
  697. (pDecInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01)<<11 |
  698. (pDecInfo->secAxiInfo.u.coda9.useOvlEnable&0x01)<<12 |
  699. (pDecInfo->secAxiInfo.u.coda9.useBtpEnable&0x01)<<13 );
  700. VpuWriteReg(pCodecInst->coreIdx, BIT_AXI_SRAM_USE, val);
  701. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->streamWrPtrRegAddr, pDecInfo->streamWrPtr);
  702. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->streamRdPtrRegAddr, pDecInfo->streamRdPtr);
  703. pDecInfo->streamEndflag &= ~(3<<3);
  704. if (pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END)
  705. pDecInfo->streamEndflag |= (2<<3);
  706. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM, pDecInfo->streamEndflag);
  707. if (pCodecInst->productId == PRODUCT_ID_980) {
  708. val = 0;
  709. val |= (pDecInfo->openParam.bwbEnable<<15);
  710. val |= (pDecInfo->wtlMode<<17)|(pDecInfo->tiled2LinearMode<<13)|(pDecInfo->mapType<<9)|(FORMAT_420<<6);
  711. }
  712. else if (pCodecInst->productId == PRODUCT_ID_960) {
  713. val = 0;
  714. val |= (pDecInfo->wtlEnable<<17);
  715. val |= (pDecInfo->openParam.bwbEnable<<12);
  716. if (pDecInfo->mapType) {
  717. if (pDecInfo->mapType == TILED_FRAME_MB_RASTER_MAP || pDecInfo->mapType == TILED_FIELD_MB_RASTER_MAP)
  718. val |= (pDecInfo->tiled2LinearEnable<<11)|(0x03<<9)|(FORMAT_420<<6);
  719. else
  720. val |= (pDecInfo->tiled2LinearEnable<<11)|(0x02<<9)|(FORMAT_420<<6);
  721. }
  722. }
  723. else {
  724. return RETCODE_NOT_FOUND_VPU_DEVICE;
  725. }
  726. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  727. val |= pDecInfo->openParam.frameEndian;
  728. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  729. val = pDecInfo->openParam.streamEndian;
  730. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_CTRL, val);
  731. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, PIC_RUN);
  732. return RETCODE_SUCCESS;
  733. }
  734. RetCode Coda9VpuDecGetResult(CodecInst* instance, DecOutputInfo* result)
  735. {
  736. CodecInst* pCodecInst;
  737. DecInfo* pDecInfo;
  738. Uint32 val = 0;
  739. pCodecInst = instance;
  740. pDecInfo = &pCodecInst->CodecInfo->decInfo;
  741. if (pCodecInst->loggingEnable)
  742. vdi_log(pCodecInst->coreIdx, PIC_RUN, 0);
  743. result->warnInfo = 0;
  744. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_SUCCESS);
  745. result->decodingSuccess = val;
  746. if (result->decodingSuccess & (1UL<<31)) {
  747. return RETCODE_MEMORY_ACCESS_VIOLATION;
  748. }
  749. if( pCodecInst->codecMode == AVC_DEC ) {
  750. result->notSufficientPsBuffer = (val >> 3) & 0x1;
  751. result->notSufficientSliceBuffer = (val >> 2) & 0x1;
  752. result->refMissingFrameFlag = (val>>21) & 0x1;
  753. }
  754. result->chunkReuseRequired = 0;
  755. if (pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END) {
  756. switch (pCodecInst->codecMode) {
  757. case AVC_DEC:
  758. result->chunkReuseRequired = ((val >> 16) & 0x01); // in case of NPF frame
  759. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_DECODED_IDX);
  760. if (val == (Uint32)-1) {
  761. result->chunkReuseRequired = TRUE;
  762. }
  763. break;
  764. case MP2_DEC:
  765. case MP4_DEC:
  766. result->chunkReuseRequired = ((val >> 16) & 0x01);
  767. break;
  768. default:
  769. break;
  770. }
  771. }
  772. result->indexFrameDecoded = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_DECODED_IDX);
  773. result->indexFrameDisplay = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_DISPLAY_IDX);
  774. if (pDecInfo->mapType == LINEAR_FRAME_MAP) {
  775. result->indexFrameDecodedForTiled = -1;
  776. result->indexFrameDisplayForTiled = -1;
  777. }
  778. else {
  779. result->indexFrameDecodedForTiled = result->indexFrameDecoded;
  780. result->indexFrameDisplayForTiled = result->indexFrameDisplay;
  781. }
  782. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_SIZE); // decoding picture size
  783. result->decPicWidth = (val>>16) & 0xFFFF;
  784. result->decPicHeight = (val) & 0xFFFF;
  785. if (result->indexFrameDecoded >= 0 && result->indexFrameDecoded < MAX_GDI_IDX) {
  786. switch (pCodecInst->codecMode) {
  787. case VPX_DEC:
  788. if ( pCodecInst->codecModeAux == VPX_AUX_VP8 ) {
  789. // VP8 specific header information
  790. // h_scale[31:30] v_scale[29:28] pic_width[27:14] pic_height[13:0]
  791. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VP8_SCALE_INFO);
  792. result->vp8ScaleInfo.hScaleFactor = (val >> 30) & 0x03;
  793. result->vp8ScaleInfo.vScaleFactor = (val >> 28) & 0x03;
  794. result->vp8ScaleInfo.picWidth = (val >> 14) & 0x3FFF;
  795. result->vp8ScaleInfo.picHeight = (val >> 0) & 0x3FFF;
  796. // ref_idx_gold[31:24], ref_idx_altr[23:16], ref_idx_last[15: 8],
  797. // version_number[3:1], show_frame[0]
  798. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VP8_PIC_REPORT);
  799. result->vp8PicInfo.refIdxGold = (val >> 24) & 0x0FF;
  800. result->vp8PicInfo.refIdxAltr = (val >> 16) & 0x0FF;
  801. result->vp8PicInfo.refIdxLast = (val >> 8) & 0x0FF;
  802. result->vp8PicInfo.versionNumber = (val >> 1) & 0x07;
  803. result->vp8PicInfo.showFrame = (val >> 0) & 0x01;
  804. }
  805. break;
  806. case AVC_DEC:
  807. case AVS_DEC:
  808. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_CROP_LEFT_RIGHT); // frame crop information(left, right)
  809. pDecInfo->initialInfo.picCropRect.left = (val>>16) & 0xffff;
  810. pDecInfo->initialInfo.picCropRect.right = pDecInfo->initialInfo.picWidth - (val&0xffff);
  811. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_CROP_TOP_BOTTOM); // frame crop information(top, bottom)
  812. pDecInfo->initialInfo.picCropRect.top = (val>>16) & 0xffff;
  813. pDecInfo->initialInfo.picCropRect.bottom = pDecInfo->initialInfo.picHeight - (val&0xffff);
  814. break;
  815. case MP2_DEC:
  816. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_MP2_BAR_LEFT_RIGHT);
  817. pDecInfo->initialInfo.mp2BardataInfo.barLeft = ((val>>16) & 0xFFFF);
  818. pDecInfo->initialInfo.mp2BardataInfo.barRight = (val&0xFFFF);
  819. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_MP2_BAR_TOP_BOTTOM);
  820. pDecInfo->initialInfo.mp2BardataInfo.barTop = ((val>>16) & 0xFFFF);
  821. pDecInfo->initialInfo.mp2BardataInfo.barBottom = (val&0xFFFF);
  822. result->mp2BardataInfo = pDecInfo->initialInfo.mp2BardataInfo;
  823. result->mp2PicDispExtInfo.offsetNum = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MP2_OFFSET_NUM);
  824. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MP2_OFFSET1);
  825. result->mp2PicDispExtInfo.horizontalOffset1 = (Int16) (val >> 16) & 0xFFFF;
  826. result->mp2PicDispExtInfo.verticalOffset1 = (Int16) (val & 0xFFFF);
  827. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MP2_OFFSET2);
  828. result->mp2PicDispExtInfo.horizontalOffset2 = (Int16) (val >> 16) & 0xFFFF;
  829. result->mp2PicDispExtInfo.verticalOffset2 = (Int16) (val & 0xFFFF);
  830. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MP2_OFFSET3);
  831. result->mp2PicDispExtInfo.horizontalOffset3 = (Int16) (val >> 16) & 0xFFFF;
  832. result->mp2PicDispExtInfo.verticalOffset3 = (Int16) (val & 0xFFFF);
  833. break;
  834. }
  835. }
  836. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_TYPE);
  837. result->interlacedFrame = (val >> 18) & 0x1;
  838. result->topFieldFirst = (val >> 21) & 0x0001; // TopFieldFirst[21]
  839. if (result->interlacedFrame) {
  840. result->picTypeFirst = (val & 0x38) >> 3; // pic_type of 1st field
  841. result->picType = val & 7; // pic_type of 2nd field
  842. }
  843. else {
  844. result->picTypeFirst = PIC_TYPE_MAX; // no meaning
  845. result->picType = val & 7;
  846. }
  847. result->pictureStructure = (val >> 19) & 0x0003; // MbAffFlag[17], FieldPicFlag[16]
  848. result->repeatFirstField = (val >> 22) & 0x0001;
  849. result->progressiveFrame = (val >> 23) & 0x0003;
  850. if( pCodecInst->codecMode == AVC_DEC)
  851. {
  852. result->decFrameInfo = (val >> 15) & 0x0001;
  853. result->picStrPresent = (val >> 27) & 0x0001;
  854. result->picTimingStruct = (val >> 28) & 0x000f;
  855. //update picture type when IDR frame
  856. if (val & 0x40) { // 6th bit
  857. if (result->interlacedFrame)
  858. result->picTypeFirst = PIC_TYPE_IDR;
  859. else
  860. result->picType = PIC_TYPE_IDR;
  861. }
  862. result->decFrameInfo = (val >> 16) & 0x0003;
  863. if (result->indexFrameDisplay >= 0) {
  864. if (result->indexFrameDisplay == result->indexFrameDecoded)
  865. result->avcNpfFieldInfo = result->decFrameInfo;
  866. else
  867. result->avcNpfFieldInfo = pDecInfo->decOutInfo[result->indexFrameDisplay].decFrameInfo;
  868. }
  869. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_HRD_INFO);
  870. result->avcHrdInfo.cpbMinus1 = val>>2;
  871. result->avcHrdInfo.vclHrdParamFlag = (val>>1)&1;
  872. result->avcHrdInfo.nalHrdParamFlag = val&1;
  873. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VUI_INFO);
  874. result->avcVuiInfo.fixedFrameRateFlag = val &1;
  875. result->avcVuiInfo.timingInfoPresent = (val>>1) & 0x01;
  876. result->avcVuiInfo.chromaLocBotField = (val>>2) & 0x07;
  877. result->avcVuiInfo.chromaLocTopField = (val>>5) & 0x07;
  878. result->avcVuiInfo.chromaLocInfoPresent = (val>>8) & 0x01;
  879. result->avcVuiInfo.colorPrimaries = (val>>16) & 0xff;
  880. result->avcVuiInfo.colorDescPresent = (val>>24) & 0x01;
  881. result->avcVuiInfo.isExtSAR = (val>>25) & 0x01;
  882. result->avcVuiInfo.vidFullRange = (val>>26) & 0x01;
  883. result->avcVuiInfo.vidFormat = (val>>27) & 0x07;
  884. result->avcVuiInfo.vidSigTypePresent = (val>>30) & 0x01;
  885. result->avcVuiInfo.vuiParamPresent = (val>>31) & 0x01;
  886. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VUI_PIC_STRUCT);
  887. result->avcVuiInfo.vuiPicStructPresent = (val & 0x1);
  888. result->avcVuiInfo.vuiPicStruct = (val>>1);
  889. }
  890. if( pCodecInst->codecMode == MP2_DEC)
  891. {
  892. result->fieldSequence = (val >> 25) & 0x0007;
  893. result->frameDct = (val >> 28) & 0x0001;
  894. result->progressiveSequence = (val >> 29) & 0x0001;
  895. }
  896. result->fRateNumerator = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_FRATE_NR); //Frame rate, Aspect ratio can be changed frame by frame.
  897. result->fRateDenominator = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_FRATE_DR);
  898. if (pCodecInst->codecMode == AVC_DEC && result->fRateDenominator > 0)
  899. result->fRateDenominator *= 2;
  900. if (pCodecInst->codecMode == MP4_DEC)
  901. {
  902. result->mp4ModuloTimeBase = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MODULO_TIME_BASE);
  903. result->mp4TimeIncrement = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VOP_TIME_INCREMENT);
  904. }
  905. if (pCodecInst->codecMode == RV_DEC) {
  906. result->rvTr = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_RV_TR);
  907. result->rvTrB = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_RV_TR_BFRAME);
  908. }
  909. if (pCodecInst->codecMode == VPX_DEC) {
  910. result->aspectRateInfo = 0;
  911. }
  912. else {
  913. result->aspectRateInfo = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_ASPECT);
  914. }
  915. // User Data
  916. if (pDecInfo->userDataEnable) {
  917. int userDataNum;
  918. int userDataSize;
  919. BYTE tempBuf[8] = {0,};
  920. VpuReadMem(pCodecInst->coreIdx, pDecInfo->userDataBufAddr + 0, tempBuf, 8, VPU_USER_DATA_ENDIAN);
  921. val = ((tempBuf[0]<<24) & 0xFF000000) |
  922. ((tempBuf[1]<<16) & 0x00FF0000) |
  923. ((tempBuf[2]<< 8) & 0x0000FF00) |
  924. ((tempBuf[3]<< 0) & 0x000000FF);
  925. userDataNum = (val >> 16) & 0xFFFF;
  926. userDataSize = (val >> 0) & 0xFFFF;
  927. if (userDataNum == 0)
  928. userDataSize = 0;
  929. result->decOutputExtData.userDataNum = userDataNum;
  930. result->decOutputExtData.userDataSize = userDataSize;
  931. val = ((tempBuf[4]<<24) & 0xFF000000) |
  932. ((tempBuf[5]<<16) & 0x00FF0000) |
  933. ((tempBuf[6]<< 8) & 0x0000FF00) |
  934. ((tempBuf[7]<< 0) & 0x000000FF);
  935. if (userDataNum == 0)
  936. result->decOutputExtData.userDataBufFull = 0;
  937. else
  938. result->decOutputExtData.userDataBufFull = (val >> 16) & 0xFFFF;
  939. result->decOutputExtData.activeFormat = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_ATSC_USER_DATA_INFO)&0xf;
  940. }
  941. result->numOfErrMBs = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_ERR_MB);
  942. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_SUCCESS);
  943. result->sequenceChanged = ((val>>20) & 0x1);
  944. result->streamEndFlag = ((pDecInfo->streamEndflag>>2) & 0x01);
  945. if (pCodecInst->codecMode == VC1_DEC && result->indexFrameDisplay != -3) {
  946. if (pDecInfo->vc1BframeDisplayValid == 0) {
  947. if (result->picType == 2) {
  948. result->indexFrameDisplay = -3;
  949. } else {
  950. pDecInfo->vc1BframeDisplayValid = 1;
  951. }
  952. }
  953. }
  954. if (pCodecInst->codecMode == AVC_DEC && pCodecInst->codecModeAux == AVC_AUX_MVC)
  955. {
  956. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MVC_REPORT);
  957. result->mvcPicInfo.viewIdxDisplay = (val>>0) & 1;
  958. result->mvcPicInfo.viewIdxDecoded = (val>>1) & 1;
  959. }
  960. if (pCodecInst->codecMode == AVC_DEC)
  961. {
  962. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_AVC_FPA_SEI0);
  963. if ((int)val < 0) {
  964. result->avcFpaSei.exist = 0;
  965. }
  966. else {
  967. result->avcFpaSei.exist = 1;
  968. result->avcFpaSei.framePackingArrangementId = val;
  969. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_AVC_FPA_SEI1);
  970. result->avcFpaSei.contentInterpretationType = val&0x3F; // [5:0]
  971. result->avcFpaSei.framePackingArrangementType = (val >> 6)&0x7F; // [12:6]
  972. result->avcFpaSei.framePackingArrangementExtensionFlag = (val >> 13)&0x01; // [13]
  973. result->avcFpaSei.frame1SelfContainedFlag = (val >> 14)&0x01; // [14]
  974. result->avcFpaSei.frame0SelfContainedFlag = (val >> 15)&0x01; // [15]
  975. result->avcFpaSei.currentFrameIsFrame0Flag = (val >> 16)&0x01; // [16]
  976. result->avcFpaSei.fieldViewsFlag = (val >> 17)&0x01; // [17]
  977. result->avcFpaSei.frame0FlippedFlag = (val >> 18)&0x01; // [18]
  978. result->avcFpaSei.spatialFlippingFlag = (val >> 19)&0x01; // [19]
  979. result->avcFpaSei.quincunxSamplingFlag = (val >> 20)&0x01; // [20]
  980. result->avcFpaSei.framePackingArrangementCancelFlag = (val >> 21)&0x01; // [21]
  981. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_AVC_FPA_SEI2);
  982. result->avcFpaSei.framePackingArrangementRepetitionPeriod = val&0x7FFF; // [14:0]
  983. result->avcFpaSei.frame1GridPositionY = (val >> 16)&0x0F; // [19:16]
  984. result->avcFpaSei.frame1GridPositionX = (val >> 20)&0x0F; // [23:20]
  985. result->avcFpaSei.frame0GridPositionY = (val >> 24)&0x0F; // [27:24]
  986. result->avcFpaSei.frame0GridPositionX = (val >> 28)&0x0F; // [31:28]
  987. }
  988. result->avcPocTop = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_POC_TOP);
  989. result->avcPocBot = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_POC_BOT);
  990. if (result->interlacedFrame)
  991. {
  992. if (result->avcPocTop > result->avcPocBot) {
  993. result->avcPocPic = result->avcPocBot;
  994. } else {
  995. result->avcPocPic = result->avcPocTop;
  996. }
  997. }
  998. else
  999. result->avcPocPic = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_POC);
  1000. }
  1001. if (pCodecInst->codecMode == AVC_DEC)
  1002. {
  1003. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_AVC_SEI_RP_INFO);
  1004. if ((int)val < 0) {
  1005. result->avcRpSei.exist = 0;
  1006. }
  1007. else {
  1008. result->avcRpSei.exist = 1;
  1009. result->avcRpSei.changingSliceGroupIdc = val & 0x3; // [1:0]
  1010. result->avcRpSei.brokenLinkFlag = (val >> 2)&0x01; // [2]
  1011. result->avcRpSei.exactMatchFlag = (val >> 3)&0x01; // [3]
  1012. result->avcRpSei.recoveryFrameCnt = (val >> 4)&0x3F; // [9:4]
  1013. }
  1014. }
  1015. result->bytePosFrameStart = VpuReadReg(pCodecInst->coreIdx, BIT_BYTE_POS_FRAME_START);
  1016. result->bytePosFrameEnd = VpuReadReg(pCodecInst->coreIdx, BIT_BYTE_POS_FRAME_END);
  1017. if (result->indexFrameDecoded >= 0 && result->indexFrameDecoded < MAX_GDI_IDX)
  1018. pDecInfo->decOutInfo[result->indexFrameDecoded] = *result;
  1019. result->frameDisplayFlag = pDecInfo->frameDisplayFlag;
  1020. result->frameCycle = VpuReadReg(pCodecInst->coreIdx, BIT_FRAME_CYCLE);
  1021. return RETCODE_SUCCESS;
  1022. }
  1023. RetCode Coda9VpuDecSetBitstreamFlag(CodecInst* instance, BOOL running, BOOL eos)
  1024. {
  1025. Uint32 val;
  1026. DecInfo* pDecInfo;
  1027. pDecInfo = &instance->CodecInfo->decInfo;
  1028. if (eos&0x01) {
  1029. val = VpuReadReg(instance->coreIdx, BIT_BIT_STREAM_PARAM);
  1030. val |= 1 << 2;
  1031. pDecInfo->streamEndflag = val;
  1032. if (running == TRUE)
  1033. VpuWriteReg(instance->coreIdx, BIT_BIT_STREAM_PARAM, val);
  1034. return RETCODE_SUCCESS;
  1035. }
  1036. else {
  1037. val = VpuReadReg(instance->coreIdx, BIT_BIT_STREAM_PARAM);
  1038. val &= ~(1 << 2);
  1039. pDecInfo->streamEndflag = val;
  1040. if (running == TRUE)
  1041. VpuWriteReg(instance->coreIdx, BIT_BIT_STREAM_PARAM, val);
  1042. return RETCODE_SUCCESS;
  1043. }
  1044. }
  1045. RetCode Coda9VpuDecGetSeqInfo(CodecInst* instance, DecInitialInfo* info)
  1046. {
  1047. CodecInst* pCodecInst = NULL;
  1048. DecInfo* pDecInfo = NULL;
  1049. Uint32 val, val2;
  1050. pCodecInst = instance;
  1051. pDecInfo = &pCodecInst->CodecInfo->decInfo;
  1052. if (pCodecInst->loggingEnable) {
  1053. vdi_log(pCodecInst->coreIdx, DEC_SEQ_INIT, 0);
  1054. }
  1055. info->warnInfo = 0;
  1056. if (pDecInfo->openParam.bitstreamMode == BS_MODE_INTERRUPT && pDecInfo->seqInitEscape) {
  1057. pDecInfo->streamEndflag &= ~(3<<3);
  1058. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM, pDecInfo->streamEndflag);
  1059. pDecInfo->seqInitEscape = 0;
  1060. }
  1061. pDecInfo->streamRdPtr = VpuReadReg(instance->coreIdx, pDecInfo->streamRdPtrRegAddr);
  1062. pDecInfo->frameDisplayFlag = VpuReadReg(pCodecInst->coreIdx, pDecInfo->frameDisplayFlagRegAddr);
  1063. pDecInfo->streamEndflag = VpuReadReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM);
  1064. info->seqInitErrReason = 0;
  1065. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_SUCCESS);
  1066. if (val & (1UL<<31)) {
  1067. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1068. }
  1069. if ( pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END) {
  1070. if (val & (1<<4)) {
  1071. info->seqInitErrReason = (VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_SEQ_ERR_REASON));
  1072. return RETCODE_FAILURE;
  1073. }
  1074. }
  1075. if (val == 0) {
  1076. info->seqInitErrReason = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_SEQ_ERR_REASON);
  1077. return RETCODE_FAILURE;
  1078. }
  1079. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_SRC_SIZE);
  1080. info->picWidth = ( (val >> 16) & 0xffff );
  1081. info->picHeight = ( val & 0xffff );
  1082. info->lumaBitdepth = 8;
  1083. info->chromaBitdepth = 8;
  1084. info->fRateNumerator = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_FRATE_NR);
  1085. info->fRateDenominator = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_FRATE_DR);
  1086. if (pCodecInst->codecMode == AVC_DEC && info->fRateDenominator > 0) {
  1087. info->fRateDenominator *= 2;
  1088. }
  1089. if (pCodecInst->codecMode == MP4_DEC) {
  1090. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_INFO);
  1091. info->mp4ShortVideoHeader = (val >> 2) & 1;
  1092. info->mp4DataPartitionEnable = val & 1;
  1093. info->mp4ReversibleVlcEnable = info->mp4DataPartitionEnable ? ((val >> 1) & 1) : 0;
  1094. info->h263AnnexJEnable = (val >> 3) & 1;
  1095. }
  1096. else if (pCodecInst->codecMode == VPX_DEC && pCodecInst->codecModeAux == VPX_AUX_VP8) {
  1097. // h_scale[31:30] v_scale[29:28] pic_width[27:14] pic_height[13:0]
  1098. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_VP8_SCALE_INFO);
  1099. info->vp8ScaleInfo.hScaleFactor = (val >> 30) & 0x03;
  1100. info->vp8ScaleInfo.vScaleFactor = (val >> 28) & 0x03;
  1101. info->vp8ScaleInfo.picWidth = (val >> 14) & 0x3FFF;
  1102. info->vp8ScaleInfo.picHeight = (val >> 0) & 0x3FFF;
  1103. }
  1104. info->minFrameBufferCount = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_FRAME_NEED);
  1105. info->frameBufDelay = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_FRAME_DELAY);
  1106. if (pCodecInst->codecMode == AVC_DEC || pCodecInst->codecMode == MP2_DEC || pCodecInst->codecMode == AVS_DEC) {
  1107. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_CROP_LEFT_RIGHT);
  1108. val2 = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_CROP_TOP_BOTTOM);
  1109. info->picCropRect.left = ((val>>16) & 0xFFFF);
  1110. info->picCropRect.right = info->picWidth - (val & 0xFFFF);;
  1111. info->picCropRect.top = ((val2>>16) & 0xFFFF);
  1112. info->picCropRect.bottom = info->picHeight - (val2 & 0xFFFF);
  1113. val = (info->picWidth * info->picHeight * 3 / 2) / 1024;
  1114. info->normalSliceSize = val / 4;
  1115. info->worstSliceSize = val / 2;
  1116. }
  1117. else {
  1118. info->picCropRect.left = 0;
  1119. info->picCropRect.right = info->picWidth;
  1120. info->picCropRect.top = 0;
  1121. info->picCropRect.bottom = info->picHeight;
  1122. }
  1123. if (pCodecInst->codecMode == MP2_DEC) {
  1124. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_MP2_BAR_LEFT_RIGHT);
  1125. val2 = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_MP2_BAR_TOP_BOTTOM);
  1126. info->mp2BardataInfo.barLeft = ((val>>16) & 0xFFFF);
  1127. info->mp2BardataInfo.barRight = (val&0xFFFF);
  1128. info->mp2BardataInfo.barTop = ((val2>>16) & 0xFFFF);
  1129. info->mp2BardataInfo.barBottom = (val2&0xFFFF);
  1130. }
  1131. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_HEADER_REPORT);
  1132. info->profile = (val >> 0) & 0xFF;
  1133. info->level = (val >> 8) & 0xFF;
  1134. info->interlace = (val >> 16) & 0x01;
  1135. info->direct8x8Flag = (val >> 17) & 0x01;
  1136. info->vc1Psf = (val >> 18) & 0x01;
  1137. info->constraint_set_flag[0] = (val >> 19) & 0x01;
  1138. info->constraint_set_flag[1] = (val >> 20) & 0x01;
  1139. info->constraint_set_flag[2] = (val >> 21) & 0x01;
  1140. info->constraint_set_flag[3] = (val >> 22) & 0x01;
  1141. info->chromaFormatIDC = (val >> 23) & 0x03;
  1142. info->isExtSAR = (val >> 25) & 0x01;
  1143. info->maxNumRefFrm = (val >> 27) & 0x0f;
  1144. info->maxNumRefFrmFlag = (val >> 31) & 0x01;
  1145. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_ASPECT);
  1146. info->aspectRateInfo = val;
  1147. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_BIT_RATE);
  1148. info->bitRate = val;
  1149. if (pCodecInst->codecMode == AVC_DEC) {
  1150. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_VUI_INFO);
  1151. info->avcVuiInfo.fixedFrameRateFlag = val &1;
  1152. info->avcVuiInfo.timingInfoPresent = (val>>1) & 0x01;
  1153. info->avcVuiInfo.chromaLocBotField = (val>>2) & 0x07;
  1154. info->avcVuiInfo.chromaLocTopField = (val>>5) & 0x07;
  1155. info->avcVuiInfo.chromaLocInfoPresent = (val>>8) & 0x01;
  1156. info->avcVuiInfo.colorPrimaries = (val>>16) & 0xff;
  1157. info->avcVuiInfo.colorDescPresent = (val>>24) & 0x01;
  1158. info->avcVuiInfo.isExtSAR = (val>>25) & 0x01;
  1159. info->avcVuiInfo.vidFullRange = (val>>26) & 0x01;
  1160. info->avcVuiInfo.vidFormat = (val>>27) & 0x07;
  1161. info->avcVuiInfo.vidSigTypePresent = (val>>30) & 0x01;
  1162. info->avcVuiInfo.vuiParamPresent = (val>>31) & 0x01;
  1163. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_VUI_PIC_STRUCT);
  1164. info->avcVuiInfo.vuiPicStructPresent = (val & 0x1);
  1165. info->avcVuiInfo.vuiPicStruct = (val>>1);
  1166. }
  1167. if (pCodecInst->codecMode == MP2_DEC) {
  1168. // seq_ext info
  1169. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_EXT_INFO);
  1170. info->mp2LowDelay = val & 1;
  1171. info->mp2DispVerSize = (val>>1) & 0x3fff;
  1172. info->mp2DispHorSize = (val>>15) & 0x3fff;
  1173. if (pDecInfo->userDataEnable) {
  1174. Uint32 userDataNum = 0;
  1175. Uint32 userDataSize = 0;
  1176. BYTE tempBuf[8] = {0,};
  1177. // user data
  1178. VpuReadMem(pCodecInst->coreIdx, pDecInfo->userDataBufAddr, tempBuf, 8, VPU_USER_DATA_ENDIAN);
  1179. val = ((tempBuf[0]<<24) & 0xFF000000) |
  1180. ((tempBuf[1]<<16) & 0x00FF0000) |
  1181. ((tempBuf[2]<< 8) & 0x0000FF00) |
  1182. ((tempBuf[3]<< 0) & 0x000000FF);
  1183. userDataNum = (val >> 16) & 0xFFFF;
  1184. userDataSize = (val >> 0) & 0xFFFF;
  1185. if (userDataNum == 0) {
  1186. userDataSize = 0;
  1187. }
  1188. info->userDataNum = userDataNum;
  1189. info->userDataSize = userDataSize;
  1190. val = ((tempBuf[4]<<24) & 0xFF000000) |
  1191. ((tempBuf[5]<<16) & 0x00FF0000) |
  1192. ((tempBuf[6]<< 8) & 0x0000FF00) |
  1193. ((tempBuf[7]<< 0) & 0x000000FF);
  1194. if (userDataNum == 0) {
  1195. info->userDataBufFull = 0;
  1196. }
  1197. else {
  1198. info->userDataBufFull = (val >> 16) & 0xFFFF;
  1199. }
  1200. }
  1201. }
  1202. return RETCODE_SUCCESS;
  1203. }
  1204. RetCode Coda9VpuDecRegisterFramebuffer(CodecInst* instance)
  1205. {
  1206. CodecInst* pCodecInst;
  1207. DecInfo* pDecInfo;
  1208. PhysicalAddress paraBuffer;
  1209. vpu_buffer_t vb;
  1210. Uint32 val;
  1211. int i;
  1212. BYTE frameAddr[MAX_GDI_IDX][3][4];
  1213. BYTE colMvAddr[MAX_GDI_IDX][4];
  1214. pCodecInst = instance;
  1215. pDecInfo = &pCodecInst->CodecInfo->decInfo;
  1216. vdi_get_common_memory(pCodecInst->coreIdx, &vb);
  1217. paraBuffer = vb.phys_addr + CODE_BUF_SIZE + TEMP_BUF_SIZE;
  1218. pDecInfo->mapCfg.productId = pCodecInst->productId;
  1219. if (pDecInfo->mapType != LINEAR_FRAME_MAP && pDecInfo->mapType != LINEAR_FIELD_MAP) {
  1220. val = SetTiledMapType(pCodecInst->coreIdx, &pDecInfo->mapCfg, pDecInfo->mapType, (pDecInfo->stride > pDecInfo->frameBufferHeight)?pDecInfo->stride:pDecInfo->frameBufferHeight,
  1221. pDecInfo->openParam.cbcrInterleave, &pDecInfo->dramCfg);
  1222. }
  1223. else {
  1224. val = SetTiledMapType(pCodecInst->coreIdx, &pDecInfo->mapCfg, pDecInfo->mapType,pDecInfo->stride, pDecInfo->openParam.cbcrInterleave, &pDecInfo->dramCfg);
  1225. }
  1226. if (val == 0) {
  1227. return RETCODE_INVALID_PARAM;
  1228. }
  1229. //Allocate frame buffer
  1230. for (i=0; i<pDecInfo->numFbsForDecoding; i++) {
  1231. frameAddr[i][0][0] = (pDecInfo->frameBufPool[i].bufY >> 24) & 0xFF;
  1232. frameAddr[i][0][1] = (pDecInfo->frameBufPool[i].bufY >> 16) & 0xFF;
  1233. frameAddr[i][0][2] = (pDecInfo->frameBufPool[i].bufY >> 8) & 0xFF;
  1234. frameAddr[i][0][3] = (pDecInfo->frameBufPool[i].bufY >> 0) & 0xFF;
  1235. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1236. frameAddr[i][1][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1237. frameAddr[i][1][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1238. frameAddr[i][1][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1239. frameAddr[i][1][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1240. frameAddr[i][2][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1241. frameAddr[i][2][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1242. frameAddr[i][2][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1243. frameAddr[i][2][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1244. }
  1245. else {
  1246. frameAddr[i][2][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1247. frameAddr[i][2][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1248. frameAddr[i][2][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1249. frameAddr[i][2][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1250. frameAddr[i][1][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1251. frameAddr[i][1][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1252. frameAddr[i][1][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1253. frameAddr[i][1][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1254. }
  1255. }
  1256. VpuWriteMem(pCodecInst->coreIdx, paraBuffer, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1257. // MV allocation and register
  1258. if (pCodecInst->codecMode == AVC_DEC || pCodecInst->codecMode == VC1_DEC || pCodecInst->codecMode == MP4_DEC ||
  1259. pCodecInst->codecMode == RV_DEC || pCodecInst->codecMode == AVS_DEC)
  1260. {
  1261. int size_mvcolbuf;
  1262. vpu_buffer_t vbBuffer;
  1263. size_mvcolbuf = ((pDecInfo->initialInfo.picWidth+31)&~31)*((pDecInfo->initialInfo.picHeight+31)&~31);
  1264. size_mvcolbuf = (size_mvcolbuf*3)/2;
  1265. size_mvcolbuf = (size_mvcolbuf+4)/5;
  1266. size_mvcolbuf = ((size_mvcolbuf+7)/8)*8;
  1267. vbBuffer.size = size_mvcolbuf;
  1268. vbBuffer.phys_addr = 0;
  1269. for (i=0 ; i<pDecInfo->numFbsForDecoding ; i++) {
  1270. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, &vbBuffer, DEC_MV, pCodecInst->instIndex)<0){
  1271. return RETCODE_FAILURE;
  1272. }
  1273. pDecInfo->vbMV[i] = vbBuffer;
  1274. }
  1275. if (pCodecInst->codecMode == AVC_DEC) {
  1276. for (i=0; i<pDecInfo->numFbsForDecoding; i++) {
  1277. colMvAddr[i][0] = (pDecInfo->vbMV[i].phys_addr >> 24) & 0xFF;
  1278. colMvAddr[i][1] = (pDecInfo->vbMV[i].phys_addr >> 16) & 0xFF;
  1279. colMvAddr[i][2] = (pDecInfo->vbMV[i].phys_addr >> 8) & 0xFF;
  1280. colMvAddr[i][3] = (pDecInfo->vbMV[i].phys_addr >> 0) & 0xFF;
  1281. }
  1282. }
  1283. else {
  1284. colMvAddr[0][0] = (pDecInfo->vbMV[0].phys_addr >> 24) & 0xFF;
  1285. colMvAddr[0][1] = (pDecInfo->vbMV[0].phys_addr >> 16) & 0xFF;
  1286. colMvAddr[0][2] = (pDecInfo->vbMV[0].phys_addr >> 8) & 0xFF;
  1287. colMvAddr[0][3] = (pDecInfo->vbMV[0].phys_addr >> 0) & 0xFF;
  1288. }
  1289. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384, (BYTE*)colMvAddr, sizeof(colMvAddr), VDI_BIG_ENDIAN);
  1290. }
  1291. if (pCodecInst->productId == PRODUCT_ID_980) {
  1292. for (i=0; i<pDecInfo->numFbsForDecoding; i++) {
  1293. frameAddr[i][0][0] = (pDecInfo->frameBufPool[i].bufYBot >> 24) & 0xFF;
  1294. frameAddr[i][0][1] = (pDecInfo->frameBufPool[i].bufYBot >> 16) & 0xFF;
  1295. frameAddr[i][0][2] = (pDecInfo->frameBufPool[i].bufYBot >> 8) & 0xFF;
  1296. frameAddr[i][0][3] = (pDecInfo->frameBufPool[i].bufYBot >> 0) & 0xFF;
  1297. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1298. frameAddr[i][1][0] = (pDecInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1299. frameAddr[i][1][1] = (pDecInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1300. frameAddr[i][1][2] = (pDecInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1301. frameAddr[i][1][3] = (pDecInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1302. frameAddr[i][2][0] = (pDecInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1303. frameAddr[i][2][1] = (pDecInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1304. frameAddr[i][2][2] = (pDecInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1305. frameAddr[i][2][3] = (pDecInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1306. }
  1307. else {
  1308. frameAddr[i][2][0] = (pDecInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1309. frameAddr[i][2][1] = (pDecInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1310. frameAddr[i][2][2] = (pDecInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1311. frameAddr[i][2][3] = (pDecInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1312. frameAddr[i][1][0] = (pDecInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1313. frameAddr[i][1][1] = (pDecInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1314. frameAddr[i][1][2] = (pDecInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1315. frameAddr[i][1][3] = (pDecInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1316. }
  1317. }
  1318. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1319. if (pDecInfo->wtlEnable) {
  1320. int num = pDecInfo->numFbsForDecoding; /* start index of WTL fb array */
  1321. int end = pDecInfo->numFrameBuffers;
  1322. for (i=num; i<end; i++) {
  1323. frameAddr[i-num][0][0] = (pDecInfo->frameBufPool[i].bufY >> 24) & 0xFF;
  1324. frameAddr[i-num][0][1] = (pDecInfo->frameBufPool[i].bufY >> 16) & 0xFF;
  1325. frameAddr[i-num][0][2] = (pDecInfo->frameBufPool[i].bufY >> 8) & 0xFF;
  1326. frameAddr[i-num][0][3] = (pDecInfo->frameBufPool[i].bufY >> 0) & 0xFF;
  1327. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1328. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1329. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1330. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1331. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1332. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1333. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1334. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1335. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1336. }
  1337. else {
  1338. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1339. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1340. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1341. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1342. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1343. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1344. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1345. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1346. }
  1347. }
  1348. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128+384, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1349. if (pDecInfo->wtlMode == FF_FIELD ) {
  1350. for (i=num; i<num*2; i++) {
  1351. frameAddr[i-num][0][0] = (pDecInfo->frameBufPool[i].bufYBot >> 24) & 0xFF;
  1352. frameAddr[i-num][0][1] = (pDecInfo->frameBufPool[i].bufYBot >> 16) & 0xFF;
  1353. frameAddr[i-num][0][2] = (pDecInfo->frameBufPool[i].bufYBot >> 8) & 0xFF;
  1354. frameAddr[i-num][0][3] = (pDecInfo->frameBufPool[i].bufYBot >> 0) & 0xFF;
  1355. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1356. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1357. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1358. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1359. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1360. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1361. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1362. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1363. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1364. }
  1365. else {
  1366. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1367. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1368. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1369. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1370. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1371. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1372. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1373. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1374. }
  1375. }
  1376. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128+384+384, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1377. }
  1378. }
  1379. }
  1380. else {
  1381. if (pDecInfo->wtlEnable) {
  1382. int num = pDecInfo->numFbsForDecoding; /* start index of WTL fb array */
  1383. int end = pDecInfo->numFrameBuffers;
  1384. for (i=num; i<end; i++) {
  1385. frameAddr[i-num][0][0] = (pDecInfo->frameBufPool[i].bufY >> 24) & 0xFF;
  1386. frameAddr[i-num][0][1] = (pDecInfo->frameBufPool[i].bufY >> 16) & 0xFF;
  1387. frameAddr[i-num][0][2] = (pDecInfo->frameBufPool[i].bufY >> 8) & 0xFF;
  1388. frameAddr[i-num][0][3] = (pDecInfo->frameBufPool[i].bufY >> 0) & 0xFF;
  1389. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1390. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1391. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1392. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1393. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1394. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1395. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1396. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1397. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1398. }
  1399. else {
  1400. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1401. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1402. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1403. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1404. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1405. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1406. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1407. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1408. }
  1409. }
  1410. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128+384, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1411. }
  1412. }
  1413. if (!ConfigSecAXICoda9(pCodecInst->coreIdx, pCodecInst->codecMode, &pDecInfo->secAxiInfo, pDecInfo->initialInfo.picWidth,
  1414. pDecInfo->frameBufferHeight, pDecInfo->initialInfo.profile&0xff)) {
  1415. return RETCODE_INSUFFICIENT_RESOURCE;
  1416. }
  1417. // Tell the decoder how much frame buffers were allocated.
  1418. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_BUF_NUM, pDecInfo->numFrameBuffers);
  1419. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_BUF_STRIDE, pDecInfo->stride);
  1420. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_BIT_ADDR, pDecInfo->secAxiInfo.u.coda9.bufBitUse);
  1421. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_IPACDC_ADDR, pDecInfo->secAxiInfo.u.coda9.bufIpAcDcUse);
  1422. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_DBKY_ADDR, pDecInfo->secAxiInfo.u.coda9.bufDbkYUse);
  1423. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_DBKC_ADDR, pDecInfo->secAxiInfo.u.coda9.bufDbkCUse);
  1424. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_OVL_ADDR, pDecInfo->secAxiInfo.u.coda9.bufOvlUse);
  1425. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_BTP_ADDR, pDecInfo->secAxiInfo.u.coda9.bufBtpUse);
  1426. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_DELAY, pDecInfo->frameDelay);
  1427. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_CACHE_CONFIG, pDecInfo->cacheConfig.type2.CacheMode);
  1428. if (pCodecInst->codecMode == VPX_DEC) {
  1429. vpu_buffer_t *pvbSlice = &pDecInfo->vbSlice;
  1430. if (pvbSlice->size == 0) {
  1431. pvbSlice->size = VP8_MB_SAVE_SIZE;
  1432. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, pvbSlice, DEC_ETC, pCodecInst->instIndex) < 0) {
  1433. return RETCODE_INSUFFICIENT_RESOURCE;
  1434. }
  1435. }
  1436. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_MB_BUF_BASE, pvbSlice->phys_addr);
  1437. }
  1438. if (pCodecInst->codecMode == AVC_DEC) {
  1439. vpu_buffer_t *pvbSlice = &pDecInfo->vbSlice;
  1440. if (pvbSlice->size == 0) {
  1441. pvbSlice->size = SLICE_SAVE_SIZE;
  1442. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, pvbSlice, DEC_ETC, pCodecInst->instIndex) < 0) {
  1443. return RETCODE_INSUFFICIENT_RESOURCE;
  1444. }
  1445. }
  1446. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SLICE_BB_START, pvbSlice->phys_addr);
  1447. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SLICE_BB_SIZE, (pvbSlice->size/1024));
  1448. }
  1449. if (pCodecInst->productId == PRODUCT_ID_980) {
  1450. val = 0;
  1451. val |= (pDecInfo->openParam.bwbEnable<<15);
  1452. val |= (pDecInfo->wtlMode<<17)|(pDecInfo->tiled2LinearMode<<13)|(pDecInfo->mapType<<9)|(FORMAT_420<<6);
  1453. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  1454. val |= pDecInfo->openParam.frameEndian;
  1455. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  1456. }
  1457. else if (pCodecInst->productId == PRODUCT_ID_960) {
  1458. val = 0;
  1459. val |= (pDecInfo->wtlEnable<<17);
  1460. val |= (pDecInfo->openParam.bwbEnable<<12);
  1461. if (pDecInfo->mapType) {
  1462. if (pDecInfo->mapType == TILED_FRAME_MB_RASTER_MAP || pDecInfo->mapType == TILED_FIELD_MB_RASTER_MAP)
  1463. val |= (pDecInfo->tiled2LinearEnable<<11)|(0x03<<9)|(FORMAT_420<<6);
  1464. else
  1465. val |= (pDecInfo->tiled2LinearEnable<<11)|(0x02<<9)|(FORMAT_420<<6);
  1466. }
  1467. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  1468. val |= pDecInfo->openParam.frameEndian;
  1469. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  1470. }
  1471. else {
  1472. return RETCODE_NOT_FOUND_VPU_DEVICE;
  1473. }
  1474. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_MAX_DEC_SIZE, 0);
  1475. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, SET_FRAME_BUF);
  1476. if (vdi_wait_vpu_busy(pCodecInst->coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  1477. if (pCodecInst->loggingEnable)
  1478. vdi_log(pCodecInst->coreIdx, SET_FRAME_BUF, 2);
  1479. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1480. }
  1481. if (pCodecInst->loggingEnable)
  1482. vdi_log(pCodecInst->coreIdx, SET_FRAME_BUF, 0);
  1483. if (VpuReadReg(pCodecInst->coreIdx, RET_SET_FRAME_SUCCESS) & (1UL<<31)) {
  1484. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1485. }
  1486. return RETCODE_SUCCESS;
  1487. }
  1488. RetCode Coda9VpuDecFlush(CodecInst* instance, FramebufferIndex* framebufferIndexes, Uint32 size)
  1489. {
  1490. Uint32 i;
  1491. DecInfo* pDecInfo = &instance->CodecInfo->decInfo;
  1492. Coda9BitIssueCommand(instance->coreIdx, instance, DEC_BUF_FLUSH);
  1493. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  1494. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1495. }
  1496. pDecInfo->frameDisplayFlag = 0;
  1497. if (framebufferIndexes != NULL) {
  1498. for (i=0; i<size; i++) {
  1499. framebufferIndexes[i].linearIndex = -2;
  1500. framebufferIndexes[i].tiledIndex = -2;
  1501. }
  1502. }
  1503. return RETCODE_SUCCESS;
  1504. }
  1505. /************************************************************************/
  1506. /* Encoder */
  1507. /************************************************************************/
  1508. RetCode Coda9VpuBuildUpEncParam(CodecInst* pCodec, EncOpenParam* param)
  1509. {
  1510. RetCode ret = RETCODE_SUCCESS;
  1511. Uint32 coreIdx;
  1512. Int32 productId;
  1513. EncInfo* pEncInfo = &pCodec->CodecInfo->encInfo;
  1514. coreIdx = pCodec->coreIdx;
  1515. productId = Coda9VpuGetProductId(coreIdx);
  1516. if ((ret=SetupEncCodecInstance(productId, pCodec)) != RETCODE_SUCCESS)
  1517. return ret;
  1518. if (param->bitstreamFormat == STD_MPEG4 || param->bitstreamFormat == STD_H263)
  1519. pCodec->codecMode = MP4_ENC;
  1520. else if (param->bitstreamFormat == STD_AVC)
  1521. pCodec->codecMode = AVC_ENC;
  1522. pCodec->codecModeAux = 0;
  1523. if (productId == PRODUCT_ID_980) {
  1524. pEncInfo->ActivePPSIdx = 0;
  1525. pEncInfo->frameIdx = 0;
  1526. pEncInfo->fieldDone = 0;
  1527. }
  1528. pEncInfo->vbWork.size = WORK_BUF_SIZE;
  1529. if (vdi_allocate_dma_memory(pCodec->coreIdx, &pEncInfo->vbWork, ENC_WORK, pCodec->instIndex) < 0)
  1530. return RETCODE_INSUFFICIENT_RESOURCE;
  1531. pEncInfo->streamRdPtr = param->bitstreamBuffer;
  1532. pEncInfo->streamWrPtr = param->bitstreamBuffer;
  1533. pEncInfo->lineBufIntEn = param->lineBufIntEn;
  1534. pEncInfo->streamBufStartAddr = param->bitstreamBuffer;
  1535. pEncInfo->streamBufSize = param->bitstreamBufferSize;
  1536. pEncInfo->streamBufEndAddr = param->bitstreamBuffer + param->bitstreamBufferSize;
  1537. pEncInfo->stride = 0;
  1538. pEncInfo->vbFrame.size = 0;
  1539. pEncInfo->vbPPU.size = 0;
  1540. pEncInfo->frameAllocExt = 0;
  1541. pEncInfo->ppuAllocExt = 0;
  1542. pEncInfo->secAxiInfo.u.coda9.useBitEnable = 0;
  1543. pEncInfo->secAxiInfo.u.coda9.useIpEnable = 0;
  1544. pEncInfo->secAxiInfo.u.coda9.useDbkYEnable = 0;
  1545. pEncInfo->secAxiInfo.u.coda9.useDbkCEnable = 0;
  1546. pEncInfo->secAxiInfo.u.coda9.useOvlEnable = 0;
  1547. pEncInfo->rotationEnable = 0;
  1548. pEncInfo->mirrorEnable = 0;
  1549. pEncInfo->mirrorDirection = MIRDIR_NONE;
  1550. pEncInfo->rotationAngle = 0;
  1551. pEncInfo->initialInfoObtained = 0;
  1552. pEncInfo->ringBufferEnable = param->ringBufferEnable;
  1553. pEncInfo->linear2TiledEnable = param->linear2TiledEnable;
  1554. pEncInfo->linear2TiledMode = param->linear2TiledMode; // coda980 only
  1555. if (!pEncInfo->linear2TiledEnable)
  1556. pEncInfo->linear2TiledMode = 0;
  1557. /* Maverick Cache I */
  1558. osal_memset((void*)&pEncInfo->cacheConfig, 0x00, sizeof(MaverickCacheConfig));
  1559. if (productId == PRODUCT_ID_960) {
  1560. pEncInfo->dramCfg.bankBit = EM_BANK;
  1561. pEncInfo->dramCfg.casBit = EM_CAS;
  1562. pEncInfo->dramCfg.rasBit = EM_RAS;
  1563. pEncInfo->dramCfg.busBit = EM_WIDTH;
  1564. }
  1565. return ret;
  1566. }
  1567. RetCode Coda9VpuEncSetup(CodecInst* pCodecInst)
  1568. {
  1569. Int32 picWidth, picHeight;
  1570. Int32 data, val;
  1571. Int32 productId, rcEnable;
  1572. EncInfo* pEncInfo = &pCodecInst->CodecInfo->encInfo;
  1573. rcEnable = pEncInfo->openParam.rcEnable&0xf;
  1574. productId = pCodecInst->productId;
  1575. picWidth = pEncInfo->openParam.picWidth;
  1576. picHeight = pEncInfo->openParam.picHeight;
  1577. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_BB_START, pEncInfo->streamBufStartAddr);
  1578. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_BB_SIZE, pEncInfo->streamBufSize / 1024); // size in KB
  1579. // Rotation Left 90 or 270 case : Swap XY resolution for VPU internal usage
  1580. if (pEncInfo->rotationAngle == 90 || pEncInfo->rotationAngle == 270)
  1581. data = (picHeight<< 16) | picWidth;
  1582. else
  1583. data = (picWidth << 16) | picHeight;
  1584. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_SRC_SIZE, data);
  1585. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_SRC_F_RATE, pEncInfo->openParam.frameRateInfo);
  1586. if (pEncInfo->openParam.bitstreamFormat == STD_MPEG4) {
  1587. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_COD_STD, 3);
  1588. data = pEncInfo->openParam.EncStdParam.mp4Param.mp4IntraDcVlcThr << 2 |
  1589. pEncInfo->openParam.EncStdParam.mp4Param.mp4ReversibleVlcEnable << 1 |
  1590. pEncInfo->openParam.EncStdParam.mp4Param.mp4DataPartitionEnable;
  1591. data |= ((pEncInfo->openParam.EncStdParam.mp4Param.mp4HecEnable >0)? 1:0)<<5;
  1592. data |= ((pEncInfo->openParam.EncStdParam.mp4Param.mp4Verid == 2)? 0:1) << 6;
  1593. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_MP4_PARA, data);
  1594. if (productId == PRODUCT_ID_980)
  1595. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (VPU_ME_LINEBUFFER_MODE << 9) |
  1596. (pEncInfo->openParam.meBlkMode << 5) |
  1597. (pEncInfo->openParam.MEUseZeroPmv << 4) |
  1598. (pEncInfo->openParam.MESearchRangeY<<2) |
  1599. pEncInfo->openParam.MESearchRangeX);
  1600. else
  1601. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (pEncInfo->openParam.meBlkMode << 3) |
  1602. (pEncInfo->openParam.MEUseZeroPmv << 2) |
  1603. pEncInfo->openParam.MESearchRange);
  1604. }
  1605. else if (pEncInfo->openParam.bitstreamFormat == STD_H263) {
  1606. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_COD_STD, 11);
  1607. data = pEncInfo->openParam.EncStdParam.h263Param.h263AnnexIEnable << 3 |
  1608. pEncInfo->openParam.EncStdParam.h263Param.h263AnnexJEnable << 2 |
  1609. pEncInfo->openParam.EncStdParam.h263Param.h263AnnexKEnable << 1|
  1610. pEncInfo->openParam.EncStdParam.h263Param.h263AnnexTEnable;
  1611. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_263_PARA, data);
  1612. if (productId == PRODUCT_ID_980)
  1613. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (VPU_ME_LINEBUFFER_MODE << 9) |
  1614. (pEncInfo->openParam.meBlkMode << 5) |
  1615. (pEncInfo->openParam.MEUseZeroPmv << 4) |
  1616. (pEncInfo->openParam.MESearchRangeY<<2) |
  1617. pEncInfo->openParam.MESearchRangeX);
  1618. else
  1619. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (pEncInfo->openParam.meBlkMode << 3) |
  1620. (pEncInfo->openParam.MEUseZeroPmv << 2) |
  1621. pEncInfo->openParam.MESearchRange);
  1622. }
  1623. else if (pEncInfo->openParam.bitstreamFormat == STD_AVC) {
  1624. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_COD_STD, 0x0);
  1625. data = (pEncInfo->openParam.EncStdParam.avcParam.deblkFilterOffsetBeta & 15) << 12 |
  1626. (pEncInfo->openParam.EncStdParam.avcParam.deblkFilterOffsetAlpha & 15) << 8 |
  1627. pEncInfo->openParam.EncStdParam.avcParam.disableDeblk << 6 |
  1628. pEncInfo->openParam.EncStdParam.avcParam.constrainedIntraPredFlag << 5 |
  1629. (pEncInfo->openParam.EncStdParam.avcParam.chromaQpOffset & 31);
  1630. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_264_PARA, data);
  1631. if (productId == PRODUCT_ID_980) {
  1632. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (VPU_ME_LINEBUFFER_MODE << 9) |
  1633. (pEncInfo->openParam.meBlkMode << 5) |
  1634. (pEncInfo->openParam.MEUseZeroPmv << 4) |
  1635. (pEncInfo->openParam.MESearchRangeY<<2) |
  1636. pEncInfo->openParam.MESearchRangeX);
  1637. }
  1638. else {
  1639. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (pEncInfo->openParam.meBlkMode << 3) | (pEncInfo->openParam.MEUseZeroPmv << 2) | pEncInfo->openParam.MESearchRange);
  1640. }
  1641. }
  1642. if (productId == PRODUCT_ID_980) {
  1643. data = 0;
  1644. if (pEncInfo->openParam.sliceMode.sliceMode!=0) {
  1645. data = pEncInfo->openParam.sliceMode.sliceSize << 2 |
  1646. (pEncInfo->openParam.sliceMode.sliceSizeMode+1); // encoding mode 0,1,2
  1647. }
  1648. }
  1649. else {
  1650. data = pEncInfo->openParam.sliceMode.sliceSize << 2 |
  1651. pEncInfo->openParam.sliceMode.sliceSizeMode << 1 |
  1652. pEncInfo->openParam.sliceMode.sliceMode;
  1653. }
  1654. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_SLICE_MODE, data);
  1655. if (rcEnable) { // rate control enabled
  1656. if (productId == PRODUCT_ID_980) {
  1657. if (pEncInfo->openParam.bitstreamFormat == STD_AVC) {
  1658. int MinDeltaQp, MaxDeltaQp, QpMin, QpMax;
  1659. data = (pEncInfo->openParam.idrInterval << 21) | (pEncInfo->openParam.rcGopIQpOffsetEn<<20) | ((pEncInfo->openParam.rcGopIQpOffset & 0xF)<<16) | pEncInfo->openParam.gopSize ;
  1660. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, data);
  1661. data = (pEncInfo->openParam.frameSkipDisable) << 31 |
  1662. pEncInfo->openParam.rcInitDelay << 16 | 0;
  1663. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, data);
  1664. data = (pEncInfo->openParam.bitRate<<4)|(rcEnable);
  1665. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA2, data);
  1666. data = 0;
  1667. if (pEncInfo->openParam.maxIntraSize>0)
  1668. data = (1<<16) | (pEncInfo->openParam.maxIntraSize & 0xFFFF);
  1669. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_MAX_INTRA_SIZE, data);
  1670. if (pEncInfo->openParam.userMinDeltaQp<0)
  1671. MinDeltaQp = 0;
  1672. else
  1673. MinDeltaQp = (1<<6)|pEncInfo->openParam.userMinDeltaQp;
  1674. if (pEncInfo->openParam.userMaxDeltaQp<0)
  1675. MaxDeltaQp = 0;
  1676. else
  1677. MaxDeltaQp = (1<<6)|pEncInfo->openParam.userMaxDeltaQp;
  1678. if (pEncInfo->openParam.userQpMin<0)
  1679. QpMin = 0;
  1680. else
  1681. QpMin = (1<<6)|pEncInfo->openParam.userQpMin;
  1682. if (pEncInfo->openParam.userQpMax<0)
  1683. QpMax = 0;
  1684. else
  1685. QpMax = (1<<6)|pEncInfo->openParam.userQpMax;
  1686. data = MinDeltaQp<<24 | MaxDeltaQp<<16 | QpMin<<8 | QpMax;
  1687. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_QP_RANGE_SET, data);
  1688. }
  1689. else { // MP4
  1690. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, pEncInfo->openParam.gopSize);
  1691. data = (pEncInfo->openParam.frameSkipDisable) << 31 |
  1692. pEncInfo->openParam.rcInitDelay << 16 |
  1693. pEncInfo->openParam.bitRate<<1 | 1;
  1694. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, data);
  1695. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_QP_RANGE_SET, 0);
  1696. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA2, 0);
  1697. }
  1698. }
  1699. else {
  1700. /* coda960 ENCODER */
  1701. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, pEncInfo->openParam.gopSize);
  1702. data = (pEncInfo->openParam.frameSkipDisable) << 31 |
  1703. pEncInfo->openParam.rcInitDelay << 16 |
  1704. pEncInfo->openParam.bitRate<<1 | 1;
  1705. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, data);
  1706. }
  1707. }
  1708. else {
  1709. if (pEncInfo->openParam.bitstreamFormat == STD_AVC)
  1710. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, (pEncInfo->openParam.idrInterval << 21) | pEncInfo->openParam.gopSize);
  1711. else
  1712. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, pEncInfo->openParam.gopSize);
  1713. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, 0);
  1714. if (productId == PRODUCT_ID_980) {
  1715. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_QP_RANGE_SET, 0);
  1716. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA2, 0);
  1717. }
  1718. }
  1719. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_BUF_SIZE, pEncInfo->openParam.vbvBufferSize);
  1720. data = pEncInfo->openParam.intraRefreshNum | pEncInfo->openParam.ConscIntraRefreshEnable<<16;
  1721. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_INTRA_REFRESH, data);
  1722. data = 0;
  1723. if(pEncInfo->openParam.rcIntraQp>=0) {
  1724. data = (1 << 5);
  1725. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_INTRA_QP, pEncInfo->openParam.rcIntraQp);
  1726. }
  1727. else {
  1728. data = 0;
  1729. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_INTRA_QP, (Uint32)-1);
  1730. }
  1731. if (pCodecInst->codecMode == AVC_ENC) {
  1732. data |= (pEncInfo->openParam.EncStdParam.avcParam.audEnable << 2);
  1733. }
  1734. if(pEncInfo->openParam.userQpMax>=0) {
  1735. data |= (1<<6);
  1736. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_QP_MAX, pEncInfo->openParam.userQpMax);
  1737. }
  1738. else {
  1739. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_QP_MAX, 0);
  1740. }
  1741. if(pEncInfo->openParam.userGamma >= 0) {
  1742. data |= (1<<7);
  1743. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_GAMMA, pEncInfo->openParam.userGamma);
  1744. }
  1745. else {
  1746. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_GAMMA, 0);
  1747. }
  1748. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_OPTION, data);
  1749. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_INTERVAL_MODE, (pEncInfo->openParam.mbInterval<<2) | pEncInfo->openParam.rcIntervalMode);
  1750. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_INTRA_WEIGHT, pEncInfo->openParam.intraCostWeight);
  1751. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr, pEncInfo->streamWrPtr);
  1752. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamRdPtrRegAddr, pEncInfo->streamRdPtr);
  1753. SetEncFrameMemInfo(pCodecInst);
  1754. val = 0;
  1755. if (pEncInfo->ringBufferEnable == 0) {
  1756. if (pEncInfo->lineBufIntEn)
  1757. val |= (0x1<<6);
  1758. val |= (0x1<<5);
  1759. val |= (0x1<<4);
  1760. }
  1761. else {
  1762. val |= (0x1<<3);
  1763. }
  1764. val |= pEncInfo->openParam.streamEndian;
  1765. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_CTRL, val);
  1766. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, ENC_SEQ_INIT);
  1767. #ifdef SUPPORT_MULTI_INST_INTR
  1768. if (vdi_wait_interrupt(pCodecInst->coreIdx, 0, __VPU_BUSY_TIMEOUT) == -1) {
  1769. #else
  1770. if (vdi_wait_interrupt(pCodecInst->coreIdx, __VPU_BUSY_TIMEOUT) == -1) {
  1771. #endif
  1772. if (pCodecInst->loggingEnable)
  1773. vdi_log(pCodecInst->coreIdx, ENC_SEQ_INIT, 2);
  1774. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1775. }
  1776. VpuWriteReg(pCodecInst->coreIdx, BIT_INT_CLEAR, 1); // that is OK. HW signal already is clear by device driver
  1777. VpuWriteReg(pCodecInst->coreIdx, BIT_INT_REASON, 0);
  1778. if (pCodecInst->loggingEnable)
  1779. vdi_log(pCodecInst->coreIdx, ENC_SEQ_INIT, 0);
  1780. if (VpuReadReg(pCodecInst->coreIdx, RET_ENC_SEQ_END_SUCCESS) & (1UL<<31))
  1781. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1782. if (VpuReadReg(pCodecInst->coreIdx, RET_ENC_SEQ_END_SUCCESS) == 0)
  1783. return RETCODE_FAILURE;
  1784. pEncInfo->streamWrPtr = VpuReadReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr);
  1785. pEncInfo->streamEndflag = VpuReadReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM);
  1786. return RETCODE_SUCCESS;
  1787. }
  1788. RetCode Coda9VpuEncRegisterFramebuffer(CodecInst* instance)
  1789. {
  1790. CodecInst* pCodecInst = instance;
  1791. EncInfo* pEncInfo;
  1792. Int32 i, val;
  1793. RetCode ret;
  1794. PhysicalAddress paraBuffer;
  1795. BYTE frameAddr[MAX_FRAMEBUFFER_COUNT][3][4];
  1796. Int32 stride, height, mapType, num;
  1797. VpuAttr* pAttr = &g_VpuCoreAttributes[instance->coreIdx];
  1798. pEncInfo = &instance->CodecInfo->encInfo;
  1799. stride = pEncInfo->stride;
  1800. height = pEncInfo->frameBufferHeight;
  1801. mapType = pEncInfo->mapType;
  1802. if (pCodecInst->productId == PRODUCT_ID_960) {
  1803. pEncInfo->mapCfg.tiledBaseAddr = pEncInfo->vbFrame.phys_addr;
  1804. }
  1805. if (!ConfigSecAXICoda9(pCodecInst->coreIdx, instance->codecMode, &pEncInfo->secAxiInfo, stride, height, 0))
  1806. return RETCODE_INSUFFICIENT_RESOURCE;
  1807. if (pCodecInst->productId == PRODUCT_ID_960) {
  1808. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, mapType,stride, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  1809. }
  1810. else {
  1811. if (mapType != LINEAR_FRAME_MAP && mapType != LINEAR_FIELD_MAP)
  1812. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, mapType, (stride > height)?stride:height, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  1813. else
  1814. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, mapType,stride, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  1815. }
  1816. if (val == 0)
  1817. return RETCODE_INVALID_PARAM;
  1818. SetEncFrameMemInfo(pCodecInst);
  1819. paraBuffer = VpuReadReg(pCodecInst->coreIdx, BIT_PARA_BUF_ADDR);
  1820. // Let the decoder know the addresses of the frame buffers.
  1821. for (i=0; i<pEncInfo->numFrameBuffers; i++)
  1822. {
  1823. frameAddr[i][0][0] = (pEncInfo->frameBufPool[i].bufY >> 24) & 0xFF;
  1824. frameAddr[i][0][1] = (pEncInfo->frameBufPool[i].bufY >> 16) & 0xFF;
  1825. frameAddr[i][0][2] = (pEncInfo->frameBufPool[i].bufY >> 8) & 0xFF;
  1826. frameAddr[i][0][3] = (pEncInfo->frameBufPool[i].bufY >> 0) & 0xFF;
  1827. frameAddr[i][1][0] = (pEncInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1828. frameAddr[i][1][1] = (pEncInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1829. frameAddr[i][1][2] = (pEncInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1830. frameAddr[i][1][3] = (pEncInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1831. frameAddr[i][2][0] = (pEncInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1832. frameAddr[i][2][1] = (pEncInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1833. frameAddr[i][2][2] = (pEncInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1834. frameAddr[i][2][3] = (pEncInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1835. }
  1836. VpuWriteMem(pCodecInst->coreIdx, paraBuffer, (BYTE *)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1837. if (pCodecInst->productId == PRODUCT_ID_980) {
  1838. for (i=0; i<pEncInfo->numFrameBuffers; i++) {
  1839. frameAddr[i][0][0] = (pEncInfo->frameBufPool[i].bufYBot >> 24) & 0xFF;
  1840. frameAddr[i][0][1] = (pEncInfo->frameBufPool[i].bufYBot >> 16) & 0xFF;
  1841. frameAddr[i][0][2] = (pEncInfo->frameBufPool[i].bufYBot >> 8) & 0xFF;
  1842. frameAddr[i][0][3] = (pEncInfo->frameBufPool[i].bufYBot >> 0) & 0xFF;
  1843. frameAddr[i][1][0] = (pEncInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1844. frameAddr[i][1][1] = (pEncInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1845. frameAddr[i][1][2] = (pEncInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1846. frameAddr[i][1][3] = (pEncInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1847. frameAddr[i][2][0] = (pEncInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1848. frameAddr[i][2][1] = (pEncInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1849. frameAddr[i][2][2] = (pEncInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1850. frameAddr[i][2][3] = (pEncInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1851. }
  1852. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128, (BYTE *)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1853. }
  1854. // Tell the codec how much frame buffers were allocated.
  1855. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_BUF_NUM, pEncInfo->numFrameBuffers);
  1856. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_BUF_STRIDE, stride);
  1857. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_BIT_ADDR, pEncInfo->secAxiInfo.u.coda9.bufBitUse);
  1858. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_IPACDC_ADDR, pEncInfo->secAxiInfo.u.coda9.bufIpAcDcUse);
  1859. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_DBKY_ADDR, pEncInfo->secAxiInfo.u.coda9.bufDbkYUse);
  1860. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_DBKC_ADDR, pEncInfo->secAxiInfo.u.coda9.bufDbkCUse);
  1861. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_OVL_ADDR, pEncInfo->secAxiInfo.u.coda9.bufOvlUse);
  1862. if (pAttr->framebufferCacheType == FramebufCacheMaverickII) {
  1863. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_CACHE_CONFIG, pEncInfo->cacheConfig.type2.CacheMode);
  1864. }
  1865. else if (pAttr->framebufferCacheType == FramebufCacheMaverickI) {
  1866. // Maverick Cache Configuration
  1867. val = (pEncInfo->cacheConfig.type1.luma.cfg.PageSizeX << 28) |
  1868. (pEncInfo->cacheConfig.type1.luma.cfg.PageSizeY << 24) |
  1869. (pEncInfo->cacheConfig.type1.luma.cfg.CacheSizeX << 20) |
  1870. (pEncInfo->cacheConfig.type1.luma.cfg.CacheSizeY << 16) |
  1871. (pEncInfo->cacheConfig.type1.chroma.cfg.PageSizeX << 12) |
  1872. (pEncInfo->cacheConfig.type1.chroma.cfg.PageSizeY << 8) |
  1873. (pEncInfo->cacheConfig.type1.chroma.cfg.CacheSizeX << 4) |
  1874. (pEncInfo->cacheConfig.type1.chroma.cfg.CacheSizeY << 0);
  1875. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_CACHE_SIZE, val);
  1876. val = (pEncInfo->cacheConfig.type1.Bypass << 4) |
  1877. (pEncInfo->cacheConfig.type1.DualConf << 2) |
  1878. (pEncInfo->cacheConfig.type1.PageMerge << 0);
  1879. val = val << 24;
  1880. val |= (pEncInfo->cacheConfig.type1.luma.cfg.BufferSize << 16) |
  1881. (pEncInfo->cacheConfig.type1.chroma.cfg.BufferSize << 8) |
  1882. (pEncInfo->cacheConfig.type1.chroma.cfg.BufferSize << 8);
  1883. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_CACHE_CONFIG, val);
  1884. }
  1885. num = pEncInfo->numFrameBuffers;
  1886. if (pCodecInst->productId == PRODUCT_ID_960) {
  1887. Uint32 subsampleLumaSize = stride*height;
  1888. Uint32 subsampleChromaSize = stride*height/4; // FORMAT_420
  1889. vpu_buffer_t vbBuf;
  1890. FrameBuffer* pFb;
  1891. vbBuf.size = subsampleLumaSize + 2*subsampleChromaSize;
  1892. vbBuf.phys_addr = (PhysicalAddress)0;
  1893. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, &vbBuf, ENC_ETC, pCodecInst->instIndex) < 0) {
  1894. pEncInfo->vbSubSampFrame.size = 0;
  1895. pEncInfo->vbSubSampFrame.phys_addr = 0;
  1896. return RETCODE_INSUFFICIENT_RESOURCE;
  1897. }
  1898. pFb = &pEncInfo->frameBufPool[num];
  1899. pFb->bufY = vbBuf.phys_addr;
  1900. pFb->bufCb = (PhysicalAddress)-1;
  1901. pFb->bufCr = (PhysicalAddress)-1;
  1902. pFb->updateFbInfo = TRUE;
  1903. ret = UpdateFrameBufferAddr(LINEAR_FRAME_MAP, pFb, 1, subsampleLumaSize, subsampleChromaSize);
  1904. if (ret != RETCODE_SUCCESS) {
  1905. pEncInfo->vbSubSampFrame.size = 0;
  1906. pEncInfo->vbSubSampFrame.phys_addr = 0;
  1907. return RETCODE_INSUFFICIENT_RESOURCE;
  1908. }
  1909. pEncInfo->vbSubSampFrame = vbBuf;
  1910. num++;
  1911. // Set Sub-Sampling buffer for ME-Reference and DBK-Reconstruction
  1912. // BPU will swap below two buffer internally every pic by pic
  1913. val = GetXY2AXIAddr(&pEncInfo->mapCfg, 0, 0, 0, stride, pFb);
  1914. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SUBSAMP_A, val);
  1915. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SUBSAMP_B, val+(stride*height/2));
  1916. if (pCodecInst->codecMode == AVC_ENC && pCodecInst->codecModeAux == AVC_AUX_MVC) {
  1917. vbBuf.size = subsampleLumaSize + 2*subsampleChromaSize;
  1918. vbBuf.phys_addr = (PhysicalAddress)0;
  1919. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, &vbBuf, ENC_ETC, pCodecInst->instIndex) < 0) {
  1920. pEncInfo->vbSubSampFrame.size = 0;
  1921. pEncInfo->vbSubSampFrame.phys_addr = 0;
  1922. return RETCODE_INSUFFICIENT_RESOURCE;
  1923. }
  1924. pFb = &pEncInfo->frameBufPool[num];
  1925. pFb->bufY = vbBuf.phys_addr;
  1926. pFb->bufCb = (PhysicalAddress)-1;
  1927. pFb->bufCr = (PhysicalAddress)-1;
  1928. pFb->updateFbInfo = TRUE;
  1929. ret = UpdateFrameBufferAddr(LINEAR_FRAME_MAP, pFb, 1, subsampleLumaSize, subsampleChromaSize);
  1930. if (ret != RETCODE_SUCCESS) {
  1931. pEncInfo->vbMvcSubSampFrame.size = 0;
  1932. pEncInfo->vbMvcSubSampFrame.phys_addr = 0;
  1933. return RETCODE_INSUFFICIENT_RESOURCE;
  1934. }
  1935. pEncInfo->vbMvcSubSampFrame = vbBuf;
  1936. val = GetXY2AXIAddr(&pEncInfo->mapCfg, 0, 0, 0, stride, pFb);
  1937. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SUBSAMP_A_MVC, val);
  1938. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SUBSAMP_B_MVC, val+(stride*height/2));
  1939. }
  1940. }
  1941. if (pCodecInst->codecMode == MP4_ENC) {
  1942. // MPEG4 Encoder Data-Partitioned bitstream temporal buffer
  1943. pEncInfo->vbScratch.size = SIZE_MP4ENC_DATA_PARTITION;
  1944. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, &pEncInfo->vbScratch, ENC_ETC, pCodecInst->instIndex)<0)
  1945. return RETCODE_INSUFFICIENT_RESOURCE;
  1946. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_DP_BUF_BASE, pEncInfo->vbScratch.phys_addr);
  1947. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_DP_BUF_SIZE, pEncInfo->vbScratch.size>>10);
  1948. }
  1949. SetPendingInst(pCodecInst->coreIdx, pCodecInst);
  1950. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, SET_FRAME_BUF);
  1951. if (vdi_wait_vpu_busy(pCodecInst->coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  1952. if (pCodecInst->loggingEnable)
  1953. vdi_log(pCodecInst->coreIdx, SET_FRAME_BUF, 2);
  1954. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1955. }
  1956. if (pCodecInst->loggingEnable)
  1957. vdi_log(pCodecInst->coreIdx, SET_FRAME_BUF, 0);
  1958. if (VpuReadReg(pCodecInst->coreIdx, RET_SET_FRAME_SUCCESS) & (1UL<<31)) {
  1959. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1960. }
  1961. return RETCODE_SUCCESS;
  1962. }
  1963. RetCode Coda9VpuEncode(CodecInst* pCodecInst, EncParam* param)
  1964. {
  1965. EncInfo* pEncInfo;
  1966. FrameBuffer* pSrcFrame;
  1967. Uint32 rotMirMode;
  1968. Uint32 val;
  1969. vpu_instance_pool_t *vip;
  1970. #ifdef CLIP_PIC_DELTA_QP
  1971. int row_max_dqp_minus = 0;
  1972. int row_max_dqp_plus = 0;
  1973. #endif
  1974. pEncInfo = &pCodecInst->CodecInfo->encInfo;
  1975. vip = (vpu_instance_pool_t *)vdi_get_instance_pool(pCodecInst->coreIdx);
  1976. if (!vip) {
  1977. return RETCODE_INVALID_HANDLE;
  1978. }
  1979. pSrcFrame = param->sourceFrame;
  1980. rotMirMode = 0;
  1981. if (pEncInfo->rotationEnable == TRUE) {
  1982. switch (pEncInfo->rotationAngle) {
  1983. case 0:
  1984. rotMirMode |= 0x0;
  1985. break;
  1986. case 90:
  1987. rotMirMode |= 0x1;
  1988. break;
  1989. case 180:
  1990. rotMirMode |= 0x2;
  1991. break;
  1992. case 270:
  1993. rotMirMode |= 0x3;
  1994. break;
  1995. }
  1996. }
  1997. if (pEncInfo->mirrorEnable == TRUE) {
  1998. switch (pEncInfo->mirrorDirection) {
  1999. case MIRDIR_NONE :
  2000. rotMirMode |= 0x0;
  2001. break;
  2002. case MIRDIR_VER :
  2003. rotMirMode |= 0x4;
  2004. break;
  2005. case MIRDIR_HOR :
  2006. rotMirMode |= 0x8;
  2007. break;
  2008. case MIRDIR_HOR_VER :
  2009. rotMirMode |= 0xc;
  2010. break;
  2011. }
  2012. }
  2013. if (pCodecInst->productId == PRODUCT_ID_980) {
  2014. rotMirMode |= ((pSrcFrame->endian&0x03)<<16);
  2015. rotMirMode |= ((pSrcFrame->cbcrInterleave&0x01)<<18);
  2016. rotMirMode |= ((pSrcFrame->sourceLBurstEn&0x01)<<4);
  2017. }
  2018. else {
  2019. rotMirMode |= ((pSrcFrame->sourceLBurstEn&0x01)<<4);
  2020. #if defined(SUPPORT_NV21) || defined(SUPPORT_ENC_NV21)
  2021. rotMirMode |= ((pSrcFrame->cbcrInterleave&0x01)<<18);
  2022. rotMirMode |= pEncInfo->openParam.nv21 << 21;
  2023. #endif
  2024. }
  2025. if (pCodecInst->productId == PRODUCT_ID_980 && pCodecInst->codecMode == AVC_ENC)
  2026. {
  2027. }
  2028. if (pCodecInst->productId == PRODUCT_ID_960) {
  2029. if (pEncInfo->mapType > LINEAR_FRAME_MAP && pEncInfo->mapType <= TILED_MIXED_V_MAP) {
  2030. SetTiledFrameBase(pCodecInst->coreIdx, pEncInfo->vbFrame.phys_addr);
  2031. }
  2032. else {
  2033. SetTiledFrameBase(pCodecInst->coreIdx, 0);
  2034. }
  2035. }
  2036. if (pEncInfo->mapType != LINEAR_FRAME_MAP && pEncInfo->mapType != LINEAR_FIELD_MAP) {
  2037. if (pEncInfo->stride > pEncInfo->frameBufferHeight)
  2038. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, pEncInfo->mapType, pEncInfo->stride, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  2039. else
  2040. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, pEncInfo->mapType, pEncInfo->frameBufferHeight, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  2041. } else {
  2042. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, pEncInfo->mapType, pEncInfo->stride, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  2043. }
  2044. if (val == 0) {
  2045. return RETCODE_INVALID_PARAM;
  2046. }
  2047. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_ROT_MODE, rotMirMode);
  2048. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_QS, param->quantParam);
  2049. if (param->skipPicture) {
  2050. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_OPTION, 1);
  2051. }
  2052. else {
  2053. // Registering Source Frame Buffer information
  2054. // Hide GDI IF under FW level
  2055. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_INDEX, pSrcFrame->myIndex);
  2056. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_STRIDE, pSrcFrame->stride);
  2057. if (pEncInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  2058. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_Y, pSrcFrame->bufY);
  2059. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_CB, pSrcFrame->bufCb);
  2060. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_CR, pSrcFrame->bufCr);
  2061. }
  2062. else { // CBCR_ORDER_REVERSED (YV12)
  2063. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_Y, pSrcFrame->bufY);
  2064. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_CB, pSrcFrame->bufCr);
  2065. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_CR, pSrcFrame->bufCb);
  2066. }
  2067. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_OPTION, (param->forceIPicture << 1 & 0x2));
  2068. }
  2069. if (pEncInfo->ringBufferEnable == 0) {
  2070. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_BB_START, param->picStreamBufferAddr);
  2071. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_BB_SIZE, param->picStreamBufferSize/1024); // size in KB
  2072. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamRdPtrRegAddr, param->picStreamBufferAddr);
  2073. pEncInfo->streamRdPtr = param->picStreamBufferAddr;
  2074. }
  2075. val = 0;
  2076. val = (
  2077. (pEncInfo->secAxiInfo.u.coda9.useBitEnable&0x01)<<0 |
  2078. (pEncInfo->secAxiInfo.u.coda9.useIpEnable&0x01)<<1 |
  2079. (pEncInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01)<<2 |
  2080. (pEncInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01)<<3 |
  2081. (pEncInfo->secAxiInfo.u.coda9.useOvlEnable&0x01)<<4 |
  2082. (pEncInfo->secAxiInfo.u.coda9.useBtpEnable&0x01)<<5 |
  2083. (pEncInfo->secAxiInfo.u.coda9.useBitEnable&0x01)<<8 |
  2084. (pEncInfo->secAxiInfo.u.coda9.useIpEnable&0x01)<<9 |
  2085. (pEncInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01)<<10 |
  2086. (pEncInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01)<<11 |
  2087. (pEncInfo->secAxiInfo.u.coda9.useOvlEnable&0x01)<<12 |
  2088. (pEncInfo->secAxiInfo.u.coda9.useBtpEnable&0x01)<<13 );
  2089. VpuWriteReg(pCodecInst->coreIdx, BIT_AXI_SRAM_USE, val);
  2090. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr, pEncInfo->streamWrPtr);
  2091. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamRdPtrRegAddr, pEncInfo->streamRdPtr);
  2092. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM, pEncInfo->streamEndflag);
  2093. SetEncFrameMemInfo(pCodecInst);
  2094. val = 0;
  2095. if (pEncInfo->ringBufferEnable == 0) {
  2096. if (pEncInfo->lineBufIntEn)
  2097. val |= (0x1<<6);
  2098. val |= (0x1<<5);
  2099. val |= (0x1<<4);
  2100. }
  2101. else {
  2102. val |= (0x1<<3);
  2103. }
  2104. val |= pEncInfo->openParam.streamEndian;
  2105. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_CTRL, val);
  2106. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, PIC_RUN);
  2107. return RETCODE_SUCCESS;
  2108. }
  2109. RetCode Coda9VpuEncGetResult(CodecInst* pCodecInst, EncOutputInfo* info)
  2110. {
  2111. EncInfo* pEncInfo;
  2112. PhysicalAddress rdPtr;
  2113. PhysicalAddress wrPtr;
  2114. Uint32 pic_enc_result;
  2115. pEncInfo = &pCodecInst->CodecInfo->encInfo;
  2116. if (pCodecInst->loggingEnable)
  2117. vdi_log(pCodecInst->coreIdx, PIC_RUN, 0);
  2118. pic_enc_result = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_SUCCESS);
  2119. if (pic_enc_result & (1UL<<31)) {
  2120. return RETCODE_MEMORY_ACCESS_VIOLATION;
  2121. }
  2122. if (pCodecInst->productId == PRODUCT_ID_980) {
  2123. if (pic_enc_result & 2) { //top field coding done
  2124. if (!pEncInfo->fieldDone)
  2125. pEncInfo->fieldDone = 1;
  2126. }
  2127. else
  2128. {
  2129. pEncInfo->frameIdx = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_FRAME_NUM);
  2130. pEncInfo->fieldDone = 0;
  2131. }
  2132. }
  2133. info->picType = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_TYPE);
  2134. if (pEncInfo->ringBufferEnable == 0) {
  2135. rdPtr = VpuReadReg(pCodecInst->coreIdx, pEncInfo->streamRdPtrRegAddr);
  2136. wrPtr = VpuReadReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr);
  2137. info->bitstreamBuffer = rdPtr;
  2138. info->bitstreamSize = wrPtr - rdPtr;
  2139. }
  2140. info->numOfSlices = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_SLICE_NUM);
  2141. info->bitstreamWrapAround = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_FLAG);
  2142. info->reconFrameIndex = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_FRAME_IDX);
  2143. if (info->reconFrameIndex < MAX_REG_FRAME) {
  2144. info->reconFrame = pEncInfo->frameBufPool[info->reconFrameIndex];
  2145. }
  2146. info->encSrcIdx = info->reconFrameIndex;
  2147. pEncInfo->streamWrPtr = VpuReadReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr);
  2148. pEncInfo->streamEndflag = VpuReadReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM);
  2149. info->frameCycle = VpuReadReg(pCodecInst->coreIdx, BIT_FRAME_CYCLE);
  2150. info->rdPtr = pEncInfo->streamRdPtr;
  2151. info->wrPtr = pEncInfo->streamWrPtr;
  2152. return RETCODE_SUCCESS;
  2153. }
  2154. RetCode Coda9VpuEncGiveCommand(CodecInst* pCodecInst, CodecCommand cmd, void* param)
  2155. {
  2156. RetCode ret = RETCODE_SUCCESS;
  2157. UNREFERENCED_PARAMETER(cmd);
  2158. UNREFERENCED_PARAMETER(param);
  2159. switch (cmd) {
  2160. default:
  2161. ret = RETCODE_NOT_SUPPORTED_FEATURE;
  2162. }
  2163. return ret;
  2164. }