vdec.c 68 KB

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  1. #include <linux/kernel.h>
  2. #include <linux/mm.h>
  3. #include <linux/interrupt.h>
  4. #include <linux/ioport.h>
  5. #include <linux/module.h>
  6. #include <linux/platform_device.h>
  7. #include <linux/dma-mapping.h>
  8. #include <linux/of.h>
  9. #include <linux/wait.h>
  10. #include <linux/list.h>
  11. #include <linux/clk.h>
  12. #include <linux/delay.h>
  13. #include <linux/uaccess.h>
  14. #include <linux/cdev.h>
  15. #include <linux/slab.h>
  16. #include <linux/of_address.h>
  17. #include <linux/sched.h>
  18. #include <linux/sched/signal.h>
  19. #include <linux/version.h>
  20. #include <linux/kfifo.h>
  21. #include <linux/kthread.h>
  22. #include <asm/io.h>
  23. #include <soc/sifive/sifive_l2_cache.h>
  24. #include "../../../vpuapi/vpuconfig.h"
  25. #include "vpu.h"
  26. #include "vdec-starfive.h"
  27. #define starfive_flush_dcache(start, len) \
  28. sifive_l2_flush64_range(start, len)
  29. //#define ENABLE_DEBUG_MSG
  30. #ifdef ENABLE_DEBUG_MSG
  31. #define DPRINTK(args...) printk(KERN_INFO args);
  32. #else
  33. #define DPRINTK(args...)
  34. #endif
  35. /* definitions to be changed as customer configuration */
  36. /* if linux version is 5.15 or later, then can use clock and reset framework */
  37. #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)
  38. #define VPU_SUPPORT_CLOCK_CONTROL
  39. #endif
  40. /* if the driver want to use interrupt service from kernel ISR */
  41. #define VPU_SUPPORT_ISR
  42. #ifdef VPU_SUPPORT_ISR
  43. /* if the driver want to disable and enable IRQ whenever interrupt asserted. */
  44. //#define VPU_IRQ_CONTROL
  45. #endif
  46. /* if the platform driver knows the name of this driver */
  47. /* VPU_PLATFORM_DEVICE_NAME */
  48. #define VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  49. /* if this driver knows the dedicated video memory address */
  50. //#define VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  51. #define VPU_PLATFORM_DEVICE_NAME "vdec"
  52. #define VPU_CLK_NAME "vcodec"
  53. #define VPU_DEV_NAME "vdec"
  54. /* if the platform driver knows this driver */
  55. /* the definition of VPU_REG_BASE_ADDR and VPU_REG_SIZE are not meaningful */
  56. #define VPU_REG_BASE_ADDR 0x118F0000
  57. #define VPU_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
  58. #ifdef VPU_SUPPORT_ISR
  59. #define VPU_IRQ_NUM (23)
  60. #endif
  61. /* this definition is only for chipsnmedia FPGA board env */
  62. /* so for SOC env of customers can be ignored */
  63. #ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/
  64. #define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
  65. #endif
  66. struct device *vpu_dev;
  67. typedef struct vpu_drv_context_t {
  68. struct fasync_struct *async_queue;
  69. #ifdef SUPPORT_MULTI_INST_INTR
  70. unsigned long interrupt_reason[MAX_NUM_INSTANCE];
  71. #else
  72. unsigned long interrupt_reason;
  73. #endif
  74. u32 open_count; /*!<< device reference count. Not instance count */
  75. } vpu_drv_context_t;
  76. /* To track the allocated memory buffer */
  77. typedef struct vpudrv_buffer_pool_t {
  78. struct list_head list;
  79. struct vpudrv_buffer_t vb;
  80. struct file *filp;
  81. } vpudrv_buffer_pool_t;
  82. /* To track the instance index and buffer in instance pool */
  83. typedef struct vpudrv_instanace_list_t {
  84. struct list_head list;
  85. unsigned long inst_idx;
  86. unsigned long core_idx;
  87. struct file *filp;
  88. } vpudrv_instanace_list_t;
  89. typedef struct vpudrv_instance_pool_t {
  90. unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
  91. } vpudrv_instance_pool_t;
  92. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  93. #include "vmm.h"
  94. static video_mm_t s_vmem;
  95. static vpudrv_buffer_t s_video_memory = {0};
  96. #endif /*VPU_SUPPORT_RESERVED_VIDEO_MEMORY*/
  97. static int vpu_hw_reset(void);
  98. static void vpu_clk_disable(struct clk *clk);
  99. static int vpu_clk_enable(struct clk *clk);
  100. static struct clk *vpu_clk_get(struct device *dev);
  101. static void vpu_clk_put(struct clk *clk);
  102. /* end customer definition */
  103. static vpudrv_buffer_t s_instance_pool = {0};
  104. static vpudrv_buffer_t s_common_memory = {0};
  105. static vpu_drv_context_t s_vpu_drv_context;
  106. static int s_vpu_major;
  107. static struct cdev s_vpu_cdev;
  108. #ifndef VPU_SUPPORT_CLOCK_CONTROL
  109. static struct clk *s_vpu_clk = NULL;
  110. #endif
  111. static int s_vpu_open_ref_count;
  112. #ifdef VPU_SUPPORT_ISR
  113. static int s_vpu_irq = VPU_IRQ_NUM;
  114. #endif
  115. static vpudrv_buffer_t s_vpu_register = {0};
  116. #ifdef SUPPORT_MULTI_INST_INTR
  117. static int s_interrupt_flag[MAX_NUM_INSTANCE];
  118. static wait_queue_head_t s_interrupt_wait_q[MAX_NUM_INSTANCE];
  119. typedef struct kfifo kfifo_t;
  120. static kfifo_t s_interrupt_pending_q[MAX_NUM_INSTANCE];
  121. static spinlock_t s_kfifo_lock = __SPIN_LOCK_UNLOCKED(s_kfifo_lock);
  122. #else
  123. static int s_interrupt_flag;
  124. static wait_queue_head_t s_interrupt_wait_q;
  125. #endif
  126. static spinlock_t s_vpu_lock = __SPIN_LOCK_UNLOCKED(s_vpu_lock);
  127. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
  128. static DECLARE_MUTEX(s_vpu_sem);
  129. #else
  130. static DEFINE_SEMAPHORE(s_vpu_sem);
  131. #endif
  132. static struct list_head s_vbp_head = LIST_HEAD_INIT(s_vbp_head);
  133. static struct list_head s_inst_list_head = LIST_HEAD_INIT(s_inst_list_head);
  134. static vpu_bit_firmware_info_t s_bit_firmware_info[MAX_NUM_VPU_CORE];
  135. //#ifdef CONFIG_PM
  136. /* implement to power management functions */
  137. #define BIT_BASE 0x0000
  138. #define BIT_CODE_RUN (BIT_BASE + 0x000)
  139. #define BIT_CODE_DOWN (BIT_BASE + 0x004)
  140. #define BIT_INT_CLEAR (BIT_BASE + 0x00C)
  141. #define BIT_INT_STS (BIT_BASE + 0x010)
  142. #define BIT_CODE_RESET (BIT_BASE + 0x014)
  143. #define BIT_INT_REASON (BIT_BASE + 0x174)
  144. #define BIT_BUSY_FLAG (BIT_BASE + 0x160)
  145. #define BIT_RUN_COMMAND (BIT_BASE + 0x164)
  146. #define BIT_RUN_INDEX (BIT_BASE + 0x168)
  147. #define BIT_RUN_COD_STD (BIT_BASE + 0x16C)
  148. /* WAVE5 registers */
  149. #define W5_REG_BASE 0x0000
  150. #define W5_VPU_BUSY_STATUS (W5_REG_BASE + 0x0070)
  151. #define W5_VPU_INT_REASON_CLEAR (W5_REG_BASE + 0x0034)
  152. #define W5_VPU_VINT_CLEAR (W5_REG_BASE + 0x003C)
  153. #define W5_VPU_VPU_INT_STS (W5_REG_BASE + 0x0044)
  154. #define W5_VPU_INT_REASON (W5_REG_BASE + 0x004c)
  155. #define W5_RET_FAIL_REASON (W5_REG_BASE + 0x010C)
  156. #ifdef SUPPORT_MULTI_INST_INTR
  157. #define W5_RET_BS_EMPTY_INST (W5_REG_BASE + 0x01E4)
  158. #define W5_RET_QUEUE_CMD_DONE_INST (W5_REG_BASE + 0x01E8)
  159. #define W5_RET_SEQ_DONE_INSTANCE_INFO (W5_REG_BASE + 0x01FC)
  160. typedef enum {
  161. INT_WAVE5_INIT_VPU = 0,
  162. INT_WAVE5_WAKEUP_VPU = 1,
  163. INT_WAVE5_SLEEP_VPU = 2,
  164. INT_WAVE5_CREATE_INSTANCE = 3,
  165. INT_WAVE5_FLUSH_INSTANCE = 4,
  166. INT_WAVE5_DESTORY_INSTANCE = 5,
  167. INT_WAVE5_INIT_SEQ = 6,
  168. INT_WAVE5_SET_FRAMEBUF = 7,
  169. INT_WAVE5_DEC_PIC = 8,
  170. INT_WAVE5_ENC_PIC = 8,
  171. INT_WAVE5_ENC_SET_PARAM = 9,
  172. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  173. INT_WAVE5_ENC_SRC_RELEASE = 10,
  174. #endif
  175. INT_WAVE5_ENC_LOW_LATENCY = 13,
  176. INT_WAVE5_DEC_QUERY = 14,
  177. INT_WAVE5_BSBUF_EMPTY = 15,
  178. INT_WAVE5_BSBUF_FULL = 15,
  179. } Wave5InterruptBit;
  180. #endif
  181. /* WAVE5 INIT, WAKEUP */
  182. #define W5_PO_CONF (W5_REG_BASE + 0x0000)
  183. #define W5_VPU_VINT_ENABLE (W5_REG_BASE + 0x0048)
  184. #define W5_VPU_RESET_REQ (W5_REG_BASE + 0x0050)
  185. #define W5_VPU_RESET_STATUS (W5_REG_BASE + 0x0054)
  186. #define W5_VPU_REMAP_CTRL (W5_REG_BASE + 0x0060)
  187. #define W5_VPU_REMAP_VADDR (W5_REG_BASE + 0x0064)
  188. #define W5_VPU_REMAP_PADDR (W5_REG_BASE + 0x0068)
  189. #define W5_VPU_REMAP_CORE_START (W5_REG_BASE + 0x006C)
  190. #define W5_REMAP_CODE_INDEX 0
  191. /* WAVE5 registers */
  192. #define W5_ADDR_CODE_BASE (W5_REG_BASE + 0x0110)
  193. #define W5_CODE_SIZE (W5_REG_BASE + 0x0114)
  194. #define W5_CODE_PARAM (W5_REG_BASE + 0x0118)
  195. #define W5_INIT_VPU_TIME_OUT_CNT (W5_REG_BASE + 0x0130)
  196. #define W5_HW_OPTION (W5_REG_BASE + 0x012C)
  197. #define W5_RET_SUCCESS (W5_REG_BASE + 0x0108)
  198. #define W5_COMMAND (W5_REG_BASE + 0x0100)
  199. #define W5_VPU_HOST_INT_REQ (W5_REG_BASE + 0x0038)
  200. /* Product register */
  201. #define VPU_PRODUCT_CODE_REGISTER (BIT_BASE + 0x1044)
  202. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  203. static u32 s_vpu_reg_store[MAX_NUM_VPU_CORE][64];
  204. #endif
  205. //#endif //CONFIG_PM
  206. #define ReadVpuRegister(addr) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr)
  207. #define WriteVpuRegister(addr, val) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr) = (unsigned int)val
  208. #define WriteVpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
  209. #define vic_readl(addr) readl((void __iomem *)addr)
  210. #define vic_writel(val,addr) writel(val,(void __iomem *)addr)
  211. #define rstgen_Software_RESET_BASE_REG_ADDR 0x11840000
  212. #define rstgen_Software_RESET_assert0_OFFSET (0x0)
  213. #define rstgen_Software_RESET_status0_OFFSET (0x10)
  214. #define NBIT_RSTN_VDEC_BRG_MAIN 13
  215. #define NBIT_RSTN_VDEC_AXI 14
  216. #define NBIT_RSTN_VDEC_BCLK 15
  217. #define NBIT_RSTN_VDEC_CCLK 16
  218. #define NBIT_RSTN_VDEC_APB 17
  219. #define clk_BASE_REG_ADDR 0x11800000
  220. #define clk_vdec_axi_ctrl_REG_OFFSET (0xac)
  221. #define clk_vdecbrg_mainclk_ctrl_REG_OFFSET (0xb0)
  222. #define clk_vdec_bclk_ctrl_REG_OFFSET (0xb4)
  223. #define clk_vdec_cclk_ctrl_REG_OFFSET (0xb8)
  224. #define clk_vdec_apb_ctrl_REG_OFFSET (0xbc)
  225. static int vpu_alloc_dma_buffer(vpudrv_buffer_t *vb)
  226. {
  227. if (!vb)
  228. return -1;
  229. DPRINTK("[VPUDRV] vpu_alloc_dma_buffer \n");
  230. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  231. vb->phys_addr = (unsigned long)vmem_alloc(&s_vmem, vb->size, 0);
  232. if ((unsigned long)vb->phys_addr == (unsigned long)-1) {
  233. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  234. return -1;
  235. }
  236. vb->base = (unsigned long)(s_video_memory.base + (vb->phys_addr - s_video_memory.phys_addr));
  237. #else
  238. vb->base = (unsigned long)dma_alloc_coherent(vpu_dev, PAGE_ALIGN(vb->size), (dma_addr_t *) (&vb->phys_addr), GFP_DMA | GFP_KERNEL);
  239. if ((void *)(vb->base) == NULL) {
  240. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  241. return -1;
  242. }
  243. starfive_flush_dcache(vb->phys_addr,PAGE_ALIGN(vb->size));
  244. #endif
  245. return 0;
  246. }
  247. static void vpu_free_dma_buffer(vpudrv_buffer_t *vb)
  248. {
  249. if (!vb)
  250. return;
  251. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  252. if (vb->base)
  253. vmem_free(&s_vmem, vb->phys_addr, 0);
  254. #else
  255. if (vb->base)
  256. dma_free_coherent(vpu_dev, PAGE_ALIGN(vb->size), (void *)vb->base, vb->phys_addr);
  257. #endif
  258. }
  259. static int vpu_free_instances(struct file *filp)
  260. {
  261. vpudrv_instanace_list_t *vil, *n;
  262. vpudrv_instance_pool_t *vip;
  263. void *vip_base;
  264. int instance_pool_size_per_core;
  265. void *vdi_mutexes_base;
  266. const int PTHREAD_MUTEX_T_DESTROY_VALUE = 0xdead10cc;
  267. DPRINTK("[VPUDRV] vpu_free_instances\n");
  268. instance_pool_size_per_core = (s_instance_pool.size/MAX_NUM_VPU_CORE); /* s_instance_pool.size assigned to the size of all core once call VDI_IOCTL_GET_INSTANCE_POOL by user. */
  269. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  270. {
  271. if (vil->filp == filp) {
  272. vip_base = (void *)(s_instance_pool.base + (instance_pool_size_per_core*vil->core_idx));
  273. DPRINTK("[VPUDRV] vpu_free_instances detect instance crash instIdx=%d, coreIdx=%d, vip_base=%p, instance_pool_size_per_core=%d\n", (int)vil->inst_idx, (int)vil->core_idx, vip_base, (int)instance_pool_size_per_core);
  274. vip = (vpudrv_instance_pool_t *)vip_base;
  275. if (vip) {
  276. memset(&vip->codecInstPool[vil->inst_idx], 0x00, 4); /* only first 4 byte is key point(inUse of CodecInst in vpuapi) to free the corresponding instance. */
  277. #define PTHREAD_MUTEX_T_HANDLE_SIZE 4
  278. vdi_mutexes_base = (vip_base + (instance_pool_size_per_core - PTHREAD_MUTEX_T_HANDLE_SIZE*4));
  279. DPRINTK("[VPUDRV] vpu_free_instances : force to destroy vdi_mutexes_base=%p in userspace \n", vdi_mutexes_base);
  280. if (vdi_mutexes_base) {
  281. int i;
  282. for (i = 0; i < 4; i++) {
  283. memcpy(vdi_mutexes_base, &PTHREAD_MUTEX_T_DESTROY_VALUE, PTHREAD_MUTEX_T_HANDLE_SIZE);
  284. vdi_mutexes_base += PTHREAD_MUTEX_T_HANDLE_SIZE;
  285. }
  286. }
  287. }
  288. s_vpu_open_ref_count--;
  289. list_del(&vil->list);
  290. kfree(vil);
  291. }
  292. }
  293. return 1;
  294. }
  295. static int vpu_free_buffers(struct file *filp)
  296. {
  297. vpudrv_buffer_pool_t *pool, *n;
  298. vpudrv_buffer_t vb;
  299. DPRINTK("[VPUDRV] vpu_free_buffers\n");
  300. list_for_each_entry_safe(pool, n, &s_vbp_head, list)
  301. {
  302. if (pool->filp == filp) {
  303. vb = pool->vb;
  304. if (vb.base) {
  305. vpu_free_dma_buffer(&vb);
  306. list_del(&pool->list);
  307. kfree(pool);
  308. }
  309. }
  310. }
  311. return 0;
  312. }
  313. #ifdef SUPPORT_MULTI_INST_INTR
  314. static inline u32 get_inst_idx(u32 reg_val)
  315. {
  316. u32 inst_idx;
  317. int i;
  318. for (i=0; i < MAX_NUM_INSTANCE; i++)
  319. {
  320. if(((reg_val >> i)&0x01) == 1)
  321. break;
  322. }
  323. inst_idx = i;
  324. return inst_idx;
  325. }
  326. static s32 get_vpu_inst_idx(vpu_drv_context_t *dev, u32 *reason, u32 empty_inst, u32 done_inst, u32 seq_inst)
  327. {
  328. s32 inst_idx;
  329. u32 reg_val;
  330. u32 int_reason;
  331. int_reason = *reason;
  332. DPRINTK("[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  333. //printk(KERN_ERR "[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  334. if (int_reason & (1 << INT_WAVE5_BSBUF_EMPTY))
  335. {
  336. reg_val = (empty_inst & 0xffff);
  337. inst_idx = get_inst_idx(reg_val);
  338. *reason = (1 << INT_WAVE5_BSBUF_EMPTY);
  339. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  340. goto GET_VPU_INST_IDX_HANDLED;
  341. }
  342. if (int_reason & (1 << INT_WAVE5_INIT_SEQ))
  343. {
  344. reg_val = (seq_inst & 0xffff);
  345. inst_idx = get_inst_idx(reg_val);
  346. *reason = (1 << INT_WAVE5_INIT_SEQ);
  347. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO INIT_SEQ reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  348. goto GET_VPU_INST_IDX_HANDLED;
  349. }
  350. if (int_reason & (1 << INT_WAVE5_DEC_PIC))
  351. {
  352. reg_val = (done_inst & 0xffff);
  353. inst_idx = get_inst_idx(reg_val);
  354. *reason = (1 << INT_WAVE5_DEC_PIC);
  355. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  356. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  357. {
  358. u32 ll_inst_idx;
  359. reg_val = (done_inst >> 16);
  360. ll_inst_idx = get_inst_idx(reg_val);
  361. if (ll_inst_idx == inst_idx)
  362. *reason = ((1 << INT_WAVE5_DEC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY));
  363. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC and ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d, ll_inst_idx=%d\n", __func__, reg_val, inst_idx, ll_inst_idx);
  364. }
  365. goto GET_VPU_INST_IDX_HANDLED;
  366. }
  367. if (int_reason & (1 << INT_WAVE5_ENC_SET_PARAM))
  368. {
  369. reg_val = (seq_inst & 0xffff);
  370. inst_idx = get_inst_idx(reg_val);
  371. *reason = (1 << INT_WAVE5_ENC_SET_PARAM);
  372. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  373. goto GET_VPU_INST_IDX_HANDLED;
  374. }
  375. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  376. if (int_reason & (1 << INT_WAVE5_ENC_SRC_RELEASE))
  377. {
  378. reg_val = (done_inst & 0xffff);
  379. inst_idx = get_inst_idx(reg_val);
  380. *reason = (1 << INT_WAVE5_ENC_SRC_RELEASE);
  381. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  382. goto GET_VPU_INST_IDX_HANDLED;
  383. }
  384. #endif
  385. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  386. {
  387. reg_val = (done_inst >> 16);
  388. inst_idx = get_inst_idx(reg_val);
  389. *reason = (1 << INT_WAVE5_ENC_LOW_LATENCY);
  390. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  391. goto GET_VPU_INST_IDX_HANDLED;
  392. }
  393. inst_idx = -1;
  394. *reason = 0;
  395. DPRINTK("[VPUDRV] %s, UNKNOWN INTERRUPT REASON: %08x\n", __func__, int_reason);
  396. GET_VPU_INST_IDX_HANDLED:
  397. DPRINTK("[VPUDRV][-]%s, inst_idx=%d. *reason=0x%x\n", __func__, inst_idx, *reason);
  398. return inst_idx;
  399. }
  400. #endif
  401. static irqreturn_t vpu_irq_handler(int irq, void *dev_id)
  402. {
  403. vpu_drv_context_t *dev = (vpu_drv_context_t *)dev_id;
  404. /* this can be removed. it also work in VPU_WaitInterrupt of API function */
  405. int core;
  406. int product_code;
  407. #ifdef SUPPORT_MULTI_INST_INTR
  408. u32 intr_reason;
  409. s32 intr_inst_index;
  410. #endif
  411. DPRINTK("[VPUDRV][+]%s\n", __func__);
  412. #ifdef VPU_IRQ_CONTROL
  413. disable_irq_nosync(s_vpu_irq);
  414. #endif
  415. #ifdef SUPPORT_MULTI_INST_INTR
  416. intr_inst_index = 0;
  417. intr_reason = 0;
  418. #endif
  419. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  420. if (s_bit_firmware_info[core].size == 0) {/* it means that we didn't get an information the current core from API layer. No core activated.*/
  421. printk(KERN_ERR "[VPUDRV] : s_bit_firmware_info[core].size is zero\n");
  422. continue;
  423. }
  424. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  425. if (PRODUCT_CODE_W_SERIES(product_code)) {
  426. if (ReadVpuRegister(W5_VPU_VPU_INT_STS)) {
  427. #ifdef SUPPORT_MULTI_INST_INTR
  428. u32 empty_inst;
  429. u32 done_inst;
  430. u32 seq_inst;
  431. u32 i, reason, reason_clr;
  432. reason = ReadVpuRegister(W5_VPU_INT_REASON);
  433. empty_inst = ReadVpuRegister(W5_RET_BS_EMPTY_INST);
  434. done_inst = ReadVpuRegister(W5_RET_QUEUE_CMD_DONE_INST);
  435. seq_inst = ReadVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO);
  436. reason_clr = reason;
  437. DPRINTK("[VPUDRV] vpu_irq_handler reason=0x%x, empty_inst=0x%x, done_inst=0x%x, seq_inst=0x%x \n", reason, empty_inst, done_inst, seq_inst);
  438. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  439. if (0 == empty_inst && 0 == done_inst && 0 == seq_inst) break;
  440. intr_reason = reason;
  441. intr_inst_index = get_vpu_inst_idx(dev, &intr_reason, empty_inst, done_inst, seq_inst);
  442. DPRINTK("[VPUDRV] > instance_index: %d, intr_reason: %08x empty_inst: %08x done_inst: %08x seq_inst: %08x\n", intr_inst_index, intr_reason, empty_inst, done_inst, seq_inst);
  443. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  444. if (intr_reason == (1 << INT_WAVE5_BSBUF_EMPTY)) {
  445. empty_inst = empty_inst & ~(1 << intr_inst_index);
  446. WriteVpuRegister(W5_RET_BS_EMPTY_INST, empty_inst);
  447. if (0 == empty_inst) {
  448. reason &= ~(1<<INT_WAVE5_BSBUF_EMPTY);
  449. }
  450. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST Clear empty_inst=0x%x, intr_inst_index=%d\n", __func__, empty_inst, intr_inst_index);
  451. }
  452. if (intr_reason == (1 << INT_WAVE5_DEC_PIC))
  453. {
  454. done_inst = done_inst & ~(1 << intr_inst_index);
  455. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  456. if (0 == done_inst) {
  457. reason &= ~(1<<INT_WAVE5_DEC_PIC);
  458. }
  459. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  460. }
  461. if ((intr_reason == (1 << INT_WAVE5_INIT_SEQ)) || (intr_reason == (1 << INT_WAVE5_ENC_SET_PARAM)))
  462. {
  463. seq_inst = seq_inst & ~(1 << intr_inst_index);
  464. WriteVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO, seq_inst);
  465. if (0 == seq_inst) {
  466. reason &= ~(1<<INT_WAVE5_INIT_SEQ | 1<<INT_WAVE5_ENC_SET_PARAM);
  467. }
  468. DPRINTK("[VPUDRV] %s, W5_RET_SEQ_DONE_INSTANCE_INFO Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  469. }
  470. if ((intr_reason == (1 << INT_WAVE5_ENC_LOW_LATENCY)))
  471. {
  472. done_inst = (done_inst >> 16);
  473. done_inst = done_inst & ~(1 << intr_inst_index);
  474. done_inst = (done_inst << 16);
  475. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  476. if (0 == done_inst) {
  477. reason &= ~(1 << INT_WAVE5_ENC_LOW_LATENCY);
  478. }
  479. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST INT_WAVE5_ENC_LOW_LATENCY Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  480. }
  481. if (!kfifo_is_full(&s_interrupt_pending_q[intr_inst_index])) {
  482. if (intr_reason == ((1 << INT_WAVE5_ENC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY))) {
  483. u32 ll_intr_reason = (1 << INT_WAVE5_ENC_PIC);
  484. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &ll_intr_reason, sizeof(u32), &s_kfifo_lock);
  485. }
  486. else
  487. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  488. }
  489. else {
  490. printk(KERN_ERR "[VPUDRV] : kfifo_is_full kfifo_count=%d \n", kfifo_len(&s_interrupt_pending_q[intr_inst_index]));
  491. }
  492. }
  493. else {
  494. printk(KERN_ERR "[VPUDRV] : intr_inst_index is wrong intr_inst_index=%d \n", intr_inst_index);
  495. }
  496. }
  497. if (0 != reason)
  498. printk(KERN_ERR "INTERRUPT REASON REMAINED: %08x\n", reason);
  499. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, reason_clr);
  500. #else
  501. dev->interrupt_reason = ReadVpuRegister(W5_VPU_INT_REASON);
  502. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, dev->interrupt_reason);
  503. #endif
  504. WriteVpuRegister(W5_VPU_VINT_CLEAR, 0x1);
  505. }
  506. }
  507. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  508. if (ReadVpuRegister(BIT_INT_STS)) {
  509. #ifdef SUPPORT_MULTI_INST_INTR
  510. intr_reason = ReadVpuRegister(BIT_INT_REASON);
  511. intr_inst_index = 0; // in case of coda seriese. treats intr_inst_index is already 0
  512. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  513. #else
  514. dev->interrupt_reason = ReadVpuRegister(BIT_INT_REASON);
  515. #endif
  516. WriteVpuRegister(BIT_INT_CLEAR, 0x1);
  517. }
  518. }
  519. else {
  520. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  521. continue;
  522. }
  523. #ifdef SUPPORT_MULTI_INST_INTR
  524. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n\n", product_code, intr_reason);
  525. #else
  526. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n", product_code, dev->interrupt_reason);
  527. #endif
  528. }
  529. if (dev->async_queue)
  530. kill_fasync(&dev->async_queue, SIGIO, POLL_IN); /* notify the interrupt to user space */
  531. #ifdef SUPPORT_MULTI_INST_INTR
  532. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  533. s_interrupt_flag[intr_inst_index]= 1;
  534. wake_up_interruptible(&s_interrupt_wait_q[intr_inst_index]);
  535. }
  536. #else
  537. s_interrupt_flag = 1;
  538. wake_up_interruptible(&s_interrupt_wait_q);
  539. #endif
  540. DPRINTK("[VPUDRV][-]%s\n", __func__);
  541. return IRQ_HANDLED;
  542. }
  543. static int vpu_open(struct inode *inode, struct file *filp)
  544. {
  545. DPRINTK("[VPUDRV][+] %s\n", __func__);
  546. spin_lock(&s_vpu_lock);
  547. s_vpu_drv_context.open_count++;
  548. filp->private_data = (void *)(&s_vpu_drv_context);
  549. spin_unlock(&s_vpu_lock);
  550. DPRINTK("[VPUDRV][-] %s\n", __func__);
  551. return 0;
  552. }
  553. /*static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, u_long arg) // for kernel 2.6.9 of C&M*/
  554. static long vpu_ioctl(struct file *filp, u_int cmd, u_long arg)
  555. {
  556. int ret = 0;
  557. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  558. switch (cmd) {
  559. case VDI_IOCTL_GET_PHYSICAL_MEMORY:
  560. {
  561. vpudrv_buffer_pool_t *vbp = NULL;
  562. void *user_address = NULL;
  563. struct task_struct *my_struct = NULL;
  564. struct mm_struct *mm = NULL;
  565. unsigned long address = 0;
  566. pgd_t *pgd = NULL;
  567. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  568. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  569. if (!vbp) {
  570. up(&s_vpu_sem);
  571. return -ENOMEM;
  572. }
  573. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  574. if (ret) {
  575. kfree(vbp);
  576. up(&s_vpu_sem);
  577. return -EFAULT;
  578. }
  579. user_address = (void *)vbp->vb.virt_addr;
  580. my_struct = get_current();
  581. mm = my_struct->mm;
  582. address = (unsigned long)user_address;
  583. pgd = pgd_offset(mm, address);
  584. if (!pgd_none(*pgd) && !pgd_bad(*pgd)) {
  585. p4d_t *p4d = p4d_offset(pgd, address);
  586. pud_t *pud = pud_offset(p4d, address);
  587. if (!pud_none(*pud) && !pud_bad(*pud)) {
  588. pmd_t *pmd = pmd_offset(pud, address);
  589. if (!pmd_none(*pmd) && !pmd_bad(*pmd)) {
  590. pte_t *pte = pte_offset_map(pmd, address);
  591. if (!pte_none(*pte)) {
  592. struct page *pg = pte_page(*pte);
  593. unsigned long phys = page_to_phys(pg);
  594. unsigned long virt = (unsigned long)phys_to_virt(phys);
  595. printk("phy address = %lx, virt = %lx\r\n", phys, virt);
  596. vbp->vb.phys_addr = phys;
  597. vbp->vb.base = virt;
  598. }
  599. pte_unmap(pte);
  600. }
  601. }
  602. }
  603. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  604. if (ret) {
  605. kfree(vbp);
  606. ret = -EFAULT;
  607. up(&s_vpu_sem);
  608. break;
  609. }
  610. vbp->filp = filp;
  611. spin_lock(&s_vpu_lock);
  612. list_add(&vbp->list, &s_vbp_head);
  613. spin_unlock(&s_vpu_lock);
  614. up(&s_vpu_sem);
  615. }
  616. }
  617. break;
  618. case VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY:
  619. {
  620. vpudrv_buffer_pool_t *vbp;
  621. DPRINTK("[VPUDRV][+]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  622. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  623. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  624. if (!vbp) {
  625. up(&s_vpu_sem);
  626. return -ENOMEM;
  627. }
  628. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  629. if (ret) {
  630. kfree(vbp);
  631. up(&s_vpu_sem);
  632. return -EFAULT;
  633. }
  634. ret = vpu_alloc_dma_buffer(&(vbp->vb));
  635. if (ret == -1) {
  636. ret = -ENOMEM;
  637. kfree(vbp);
  638. up(&s_vpu_sem);
  639. break;
  640. }
  641. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  642. if (ret) {
  643. kfree(vbp);
  644. ret = -EFAULT;
  645. up(&s_vpu_sem);
  646. break;
  647. }
  648. vbp->filp = filp;
  649. spin_lock(&s_vpu_lock);
  650. list_add(&vbp->list, &s_vbp_head);
  651. spin_unlock(&s_vpu_lock);
  652. up(&s_vpu_sem);
  653. }
  654. DPRINTK("[VPUDRV][-]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  655. }
  656. break;
  657. case VDI_IOCTL_FREE_PHYSICALMEMORY:
  658. {
  659. vpudrv_buffer_pool_t *vbp, *n;
  660. vpudrv_buffer_t vb;
  661. DPRINTK("[VPUDRV][+]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  662. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  663. ret = copy_from_user(&vb, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  664. if (ret) {
  665. up(&s_vpu_sem);
  666. return -EACCES;
  667. }
  668. if (vb.base)
  669. vpu_free_dma_buffer(&vb);
  670. spin_lock(&s_vpu_lock);
  671. list_for_each_entry_safe(vbp, n, &s_vbp_head, list)
  672. {
  673. if (vbp->vb.base == vb.base) {
  674. list_del(&vbp->list);
  675. kfree(vbp);
  676. break;
  677. }
  678. }
  679. spin_unlock(&s_vpu_lock);
  680. up(&s_vpu_sem);
  681. }
  682. DPRINTK("[VPUDRV][-]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  683. }
  684. break;
  685. case VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO:
  686. {
  687. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  688. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  689. if (s_video_memory.base != 0) {
  690. ret = copy_to_user((void __user *)arg, &s_video_memory, sizeof(vpudrv_buffer_t));
  691. if (ret != 0)
  692. ret = -EFAULT;
  693. } else {
  694. ret = -EFAULT;
  695. }
  696. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  697. #endif
  698. }
  699. break;
  700. case VDI_IOCTL_WAIT_INTERRUPT:
  701. {
  702. vpudrv_intr_info_t info;
  703. #ifdef SUPPORT_MULTI_INST_INTR
  704. u32 intr_inst_index;
  705. u32 intr_reason_in_q;
  706. u32 interrupt_flag_in_q;
  707. #endif
  708. DPRINTK("[VPUDRV][+]VDI_IOCTL_WAIT_INTERRUPT\n");
  709. ret = copy_from_user(&info, (vpudrv_intr_info_t *)arg, sizeof(vpudrv_intr_info_t));
  710. if (ret != 0)
  711. {
  712. return -EFAULT;
  713. }
  714. #ifdef SUPPORT_MULTI_INST_INTR
  715. intr_inst_index = info.intr_inst_index;
  716. intr_reason_in_q = 0;
  717. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  718. if (interrupt_flag_in_q > 0)
  719. {
  720. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  721. DPRINTK("[VPUDRV] Interrupt Remain : intr_inst_index=%d, intr_reason_in_q=0x%x, interrupt_flag_in_q=%d\n", intr_inst_index, intr_reason_in_q, interrupt_flag_in_q);
  722. goto INTERRUPT_REMAIN_IN_QUEUE;
  723. }
  724. #endif
  725. #ifdef SUPPORT_MULTI_INST_INTR
  726. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  727. kt = ktime_set(0, info.timeout*1000*1000);
  728. ret = wait_event_interruptible_hrtimeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, kt);
  729. #else
  730. ret = wait_event_interruptible_timeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, msecs_to_jiffies(info.timeout));
  731. #endif
  732. #else
  733. ret = wait_event_interruptible_timeout(s_interrupt_wait_q, s_interrupt_flag != 0, msecs_to_jiffies(info.timeout));
  734. #endif
  735. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  736. if (ret == -ETIME) {
  737. //DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT timeout = %d \n", info.timeout);
  738. break;
  739. }
  740. #endif
  741. if (!ret) {
  742. ret = -ETIME;
  743. break;
  744. }
  745. if (signal_pending(current)) {
  746. ret = -ERESTARTSYS;
  747. break;
  748. }
  749. #ifdef SUPPORT_MULTI_INST_INTR
  750. intr_reason_in_q = 0;
  751. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  752. if (interrupt_flag_in_q > 0) {
  753. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  754. }
  755. else {
  756. dev->interrupt_reason[intr_inst_index] = 0;
  757. }
  758. #endif
  759. #ifdef SUPPORT_MULTI_INST_INTR
  760. DPRINTK("[VPUDRV] inst_index(%d), s_interrupt_flag(%d), reason(0x%08lx)\n", intr_inst_index, s_interrupt_flag[intr_inst_index], dev->interrupt_reason[intr_inst_index]);
  761. #else
  762. DPRINTK("[VPUDRV] s_interrupt_flag(%d), reason(0x%08lx)\n", s_interrupt_flag, dev->interrupt_reason);
  763. #endif
  764. #ifdef SUPPORT_MULTI_INST_INTR
  765. INTERRUPT_REMAIN_IN_QUEUE:
  766. info.intr_reason = dev->interrupt_reason[intr_inst_index];
  767. s_interrupt_flag[intr_inst_index] = 0;
  768. dev->interrupt_reason[intr_inst_index] = 0;
  769. #else
  770. info.intr_reason = dev->interrupt_reason;
  771. s_interrupt_flag = 0;
  772. dev->interrupt_reason = 0;
  773. #endif
  774. #ifdef VPU_IRQ_CONTROL
  775. enable_irq(s_vpu_irq);
  776. #endif
  777. ret = copy_to_user((void __user *)arg, &info, sizeof(vpudrv_intr_info_t));
  778. DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT\n");
  779. if (ret != 0)
  780. {
  781. return -EFAULT;
  782. }
  783. }
  784. break;
  785. case VDI_IOCTL_SET_CLOCK_GATE:
  786. {
  787. #ifndef VPU_SUPPORT_CLOCK_CONTROL
  788. u32 clkgate;
  789. DPRINTK("[VPUDRV][+]VDI_IOCTL_SET_CLOCK_GATE\n");
  790. if (get_user(clkgate, (u32 __user *) arg))
  791. return -EFAULT;
  792. if (clkgate)
  793. vpu_clk_enable(s_vpu_clk);
  794. else
  795. vpu_clk_disable(s_vpu_clk);
  796. DPRINTK("[VPUDRV][-]VDI_IOCTL_SET_CLOCK_GATE\n");
  797. #endif
  798. }
  799. break;
  800. case VDI_IOCTL_GET_INSTANCE_POOL:
  801. {
  802. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_POOL\n");
  803. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  804. if (s_instance_pool.base != 0) {
  805. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  806. if (ret != 0)
  807. ret = -EFAULT;
  808. } else {
  809. ret = copy_from_user(&s_instance_pool, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  810. if (ret == 0) {
  811. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  812. s_instance_pool.size = PAGE_ALIGN(s_instance_pool.size);
  813. s_instance_pool.base = (unsigned long)vmalloc(s_instance_pool.size);
  814. s_instance_pool.phys_addr = s_instance_pool.base;
  815. if (s_instance_pool.base != 0)
  816. #else
  817. if (vpu_alloc_dma_buffer(&s_instance_pool) != -1)
  818. #endif
  819. {
  820. memset((void *)s_instance_pool.base, 0x0, s_instance_pool.size); /*clearing memory*/
  821. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  822. if (ret == 0) {
  823. /* success to get memory for instance pool */
  824. up(&s_vpu_sem);
  825. break;
  826. }
  827. }
  828. }
  829. ret = -EFAULT;
  830. }
  831. up(&s_vpu_sem);
  832. }
  833. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_INSTANCE_POOL\n");
  834. }
  835. break;
  836. case VDI_IOCTL_GET_COMMON_MEMORY:
  837. {
  838. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_COMMON_MEMORY\n");
  839. if (s_common_memory.base != 0) {
  840. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  841. if (ret != 0)
  842. ret = -EFAULT;
  843. } else {
  844. ret = copy_from_user(&s_common_memory, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  845. if (ret == 0) {
  846. if (vpu_alloc_dma_buffer(&s_common_memory) != -1) {
  847. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  848. if (ret == 0) {
  849. /* success to get memory for common memory */
  850. break;
  851. }
  852. }
  853. }
  854. ret = -EFAULT;
  855. }
  856. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_COMMON_MEMORY\n");
  857. }
  858. break;
  859. case VDI_IOCTL_OPEN_INSTANCE:
  860. {
  861. vpudrv_inst_info_t inst_info;
  862. vpudrv_instanace_list_t *vil, *n;
  863. vil = kzalloc(sizeof(*vil), GFP_KERNEL);
  864. if (!vil)
  865. return -ENOMEM;
  866. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  867. return -EFAULT;
  868. vil->inst_idx = inst_info.inst_idx;
  869. vil->core_idx = inst_info.core_idx;
  870. vil->filp = filp;
  871. spin_lock(&s_vpu_lock);
  872. list_add(&vil->list, &s_inst_list_head);
  873. inst_info.inst_open_count = 0; /* counting the current open instance number */
  874. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  875. {
  876. if (vil->core_idx == inst_info.core_idx)
  877. inst_info.inst_open_count++;
  878. }
  879. #ifdef SUPPORT_MULTI_INST_INTR
  880. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  881. #endif
  882. spin_unlock(&s_vpu_lock);
  883. s_vpu_open_ref_count++; /* flag just for that vpu is in opened or closed */
  884. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t))) {
  885. kfree(vil);
  886. return -EFAULT;
  887. }
  888. DPRINTK("[VPUDRV] VDI_IOCTL_OPEN_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  889. }
  890. break;
  891. case VDI_IOCTL_CLOSE_INSTANCE:
  892. {
  893. vpudrv_inst_info_t inst_info;
  894. vpudrv_instanace_list_t *vil, *n;
  895. u32 found = 0;
  896. DPRINTK("[VPUDRV][+]VDI_IOCTL_CLOSE_INSTANCE\n");
  897. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  898. return -EFAULT;
  899. spin_lock(&s_vpu_lock);
  900. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  901. {
  902. if (vil->inst_idx == inst_info.inst_idx && vil->core_idx == inst_info.core_idx) {
  903. list_del(&vil->list);
  904. kfree(vil);
  905. found = 1;
  906. break;
  907. }
  908. }
  909. if (0 == found) {
  910. spin_unlock(&s_vpu_lock);
  911. return -EINVAL;
  912. }
  913. inst_info.inst_open_count = 0; /* counting the current open instance number */
  914. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  915. {
  916. if (vil->core_idx == inst_info.core_idx)
  917. inst_info.inst_open_count++;
  918. }
  919. #ifdef SUPPORT_MULTI_INST_INTR
  920. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  921. #endif
  922. spin_unlock(&s_vpu_lock);
  923. s_vpu_open_ref_count--; /* flag just for that vpu is in opened or closed */
  924. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t)))
  925. return -EFAULT;
  926. DPRINTK("[VPUDRV] VDI_IOCTL_CLOSE_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  927. }
  928. break;
  929. case VDI_IOCTL_GET_INSTANCE_NUM:
  930. {
  931. vpudrv_inst_info_t inst_info;
  932. vpudrv_instanace_list_t *vil, *n;
  933. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_NUM\n");
  934. ret = copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t));
  935. if (ret != 0)
  936. break;
  937. spin_lock(&s_vpu_lock);
  938. inst_info.inst_open_count = 0;
  939. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  940. {
  941. if (vil->core_idx == inst_info.core_idx)
  942. inst_info.inst_open_count++;
  943. }
  944. spin_unlock(&s_vpu_lock);
  945. ret = copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t));
  946. DPRINTK("[VPUDRV] VDI_IOCTL_GET_INSTANCE_NUM core_idx=%d, inst_idx=%d, open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, inst_info.inst_open_count);
  947. }
  948. break;
  949. case VDI_IOCTL_RESET:
  950. {
  951. #ifndef VPU_SUPPORT_CLOCK_CONTROL
  952. vpu_hw_reset();
  953. #endif
  954. }
  955. break;
  956. case VDI_IOCTL_GET_REGISTER_INFO:
  957. {
  958. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_REGISTER_INFO\n");
  959. ret = copy_to_user((void __user *)arg, &s_vpu_register, sizeof(vpudrv_buffer_t));
  960. if (ret != 0)
  961. ret = -EFAULT;
  962. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_REGISTER_INFO s_vpu_register.phys_addr==0x%lx, s_vpu_register.virt_addr=0x%lx, s_vpu_register.size=%d\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr, s_vpu_register.size);
  963. }
  964. break;
  965. case VDI_IOCTL_FLUSH_DCACHE:
  966. {
  967. vpudrv_flush_cache_t cache_info;
  968. ret = copy_from_user(&cache_info, (vpudrv_flush_cache_t *)arg, sizeof(vpudrv_flush_cache_t));
  969. if (ret != 0)
  970. ret = -EFAULT;
  971. if(cache_info.flag)
  972. starfive_flush_dcache(cache_info.start,cache_info.size);
  973. break;
  974. }
  975. default:
  976. {
  977. printk(KERN_ERR "[VPUDRV] No such IOCTL, cmd is %d\n", cmd);
  978. }
  979. break;
  980. }
  981. return ret;
  982. }
  983. static ssize_t vpu_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos)
  984. {
  985. return -1;
  986. }
  987. static ssize_t vpu_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos)
  988. {
  989. /* DPRINTK("[VPUDRV] vpu_write len=%d\n", (int)len); */
  990. if (!buf) {
  991. printk(KERN_ERR "[VPUDRV] vpu_write buf = NULL error \n");
  992. return -EFAULT;
  993. }
  994. if (len == sizeof(vpu_bit_firmware_info_t)) {
  995. vpu_bit_firmware_info_t *bit_firmware_info;
  996. bit_firmware_info = kmalloc(sizeof(vpu_bit_firmware_info_t), GFP_KERNEL);
  997. if (!bit_firmware_info) {
  998. printk(KERN_ERR "[VPUDRV] vpu_write bit_firmware_info allocation error \n");
  999. return -EFAULT;
  1000. }
  1001. if (copy_from_user(bit_firmware_info, buf, len)) {
  1002. printk(KERN_ERR "[VPUDRV] vpu_write copy_from_user error for bit_firmware_info\n");
  1003. return -EFAULT;
  1004. }
  1005. if (bit_firmware_info->size == sizeof(vpu_bit_firmware_info_t)) {
  1006. DPRINTK("[VPUDRV] vpu_write set bit_firmware_info coreIdx=0x%x, reg_base_offset=0x%x size=0x%x, bit_code[0]=0x%x\n",
  1007. bit_firmware_info->core_idx, (int)bit_firmware_info->reg_base_offset, bit_firmware_info->size, bit_firmware_info->bit_code[0]);
  1008. if (bit_firmware_info->core_idx > MAX_NUM_VPU_CORE) {
  1009. printk(KERN_ERR "[VPUDRV] vpu_write coreIdx[%d] is exceeded than MAX_NUM_VPU_CORE[%d]\n", bit_firmware_info->core_idx, MAX_NUM_VPU_CORE);
  1010. return -ENODEV;
  1011. }
  1012. memcpy((void *)&s_bit_firmware_info[bit_firmware_info->core_idx], bit_firmware_info, sizeof(vpu_bit_firmware_info_t));
  1013. kfree(bit_firmware_info);
  1014. return len;
  1015. }
  1016. kfree(bit_firmware_info);
  1017. }
  1018. return -1;
  1019. }
  1020. static int vpu_release(struct inode *inode, struct file *filp)
  1021. {
  1022. int ret = 0;
  1023. u32 open_count;
  1024. #ifdef SUPPORT_MULTI_INST_INTR
  1025. int i;
  1026. #endif
  1027. DPRINTK("[VPUDRV] vpu_release\n");
  1028. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  1029. /* found and free the not handled buffer by user applications */
  1030. vpu_free_buffers(filp);
  1031. /* found and free the not closed instance by user applications */
  1032. vpu_free_instances(filp);
  1033. spin_lock(&s_vpu_lock);
  1034. s_vpu_drv_context.open_count--;
  1035. open_count = s_vpu_drv_context.open_count;
  1036. spin_unlock(&s_vpu_lock);
  1037. if (open_count == 0) {
  1038. #ifdef SUPPORT_MULTI_INST_INTR
  1039. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1040. kfifo_reset(&s_interrupt_pending_q[i]);
  1041. }
  1042. #endif
  1043. if (s_instance_pool.base) {
  1044. DPRINTK("[VPUDRV] free instance pool\n");
  1045. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1046. vfree((const void *)s_instance_pool.base);
  1047. #else
  1048. vpu_free_dma_buffer(&s_instance_pool);
  1049. #endif
  1050. s_instance_pool.base = 0;
  1051. }
  1052. }
  1053. }
  1054. up(&s_vpu_sem);
  1055. return 0;
  1056. }
  1057. static int vpu_fasync(int fd, struct file *filp, int mode)
  1058. {
  1059. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  1060. return fasync_helper(fd, filp, mode, &dev->async_queue);
  1061. }
  1062. static int vpu_map_to_register(struct file *fp, struct vm_area_struct *vm)
  1063. {
  1064. unsigned long pfn;
  1065. vm->vm_flags |= VM_IO | VM_RESERVED;
  1066. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1067. pfn = s_vpu_register.phys_addr >> PAGE_SHIFT;
  1068. return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1069. }
  1070. static int vpu_map_to_physical_memory(struct file *fp, struct vm_area_struct *vm)
  1071. {
  1072. vm->vm_flags |= VM_IO | VM_RESERVED;
  1073. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1074. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1075. }
  1076. static int vpu_map_to_instance_pool_memory(struct file *fp, struct vm_area_struct *vm)
  1077. {
  1078. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1079. int ret;
  1080. long length = vm->vm_end - vm->vm_start;
  1081. unsigned long start = vm->vm_start;
  1082. char *vmalloc_area_ptr = (char *)s_instance_pool.base;
  1083. unsigned long pfn;
  1084. vm->vm_flags |= VM_RESERVED;
  1085. /* loop over all pages, map it page individually */
  1086. while (length > 0)
  1087. {
  1088. pfn = vmalloc_to_pfn(vmalloc_area_ptr);
  1089. if ((ret = remap_pfn_range(vm, start, pfn, PAGE_SIZE, PAGE_SHARED)) < 0) {
  1090. return ret;
  1091. }
  1092. start += PAGE_SIZE;
  1093. vmalloc_area_ptr += PAGE_SIZE;
  1094. length -= PAGE_SIZE;
  1095. }
  1096. return 0;
  1097. #else
  1098. vm->vm_flags |= VM_RESERVED;
  1099. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1100. #endif
  1101. }
  1102. /*!
  1103. * @brief memory map interface for vpu file operation
  1104. * @return 0 on success or negative error code on error
  1105. */
  1106. static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
  1107. {
  1108. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1109. if (vm->vm_pgoff == 0)
  1110. return vpu_map_to_instance_pool_memory(fp, vm);
  1111. if (vm->vm_pgoff == (s_vpu_register.phys_addr>>PAGE_SHIFT))
  1112. return vpu_map_to_register(fp, vm);
  1113. return vpu_map_to_physical_memory(fp, vm);
  1114. #else
  1115. if (vm->vm_pgoff) {
  1116. if (vm->vm_pgoff == (s_instance_pool.phys_addr>>PAGE_SHIFT))
  1117. return vpu_map_to_instance_pool_memory(fp, vm);
  1118. return vpu_map_to_physical_memory(fp, vm);
  1119. } else {
  1120. return vpu_map_to_register(fp, vm);
  1121. }
  1122. #endif
  1123. }
  1124. struct file_operations vpu_fops = {
  1125. .owner = THIS_MODULE,
  1126. .open = vpu_open,
  1127. .read = vpu_read,
  1128. .write = vpu_write,
  1129. /*.ioctl = vpu_ioctl, // for kernel 2.6.9 of C&M*/
  1130. .unlocked_ioctl = vpu_ioctl,
  1131. .release = vpu_release,
  1132. .fasync = vpu_fasync,
  1133. .mmap = vpu_mmap,
  1134. };
  1135. static int vpu_probe(struct platform_device *pdev)
  1136. {
  1137. int err = 0;
  1138. struct resource *res = NULL;
  1139. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1140. struct resource res_cma;
  1141. struct device_node *node;
  1142. #endif
  1143. DPRINTK("[VPUDRV] vpu_probe\n");
  1144. if(pdev){
  1145. vpu_dev = &pdev->dev;
  1146. vpu_dev->coherent_dma_mask = 0xffffffff;;
  1147. //vpu_dev->dma_ops = NULL;
  1148. dev_info(vpu_dev,"device init.\n");
  1149. }
  1150. if (pdev)
  1151. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1152. if (res) {/* if platform driver is implemented */
  1153. s_vpu_register.phys_addr = res->start;
  1154. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(res->start, res->end - res->start);
  1155. s_vpu_register.size = res->end - res->start;
  1156. DPRINTK("[VPUDRV] : vpu base address get from platform driver physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr);
  1157. } else {
  1158. s_vpu_register.phys_addr = VPU_REG_BASE_ADDR;
  1159. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(s_vpu_register.phys_addr, VPU_REG_SIZE);
  1160. s_vpu_register.size = VPU_REG_SIZE;
  1161. DPRINTK("[VPUDRV] : vpu base address get from defined value physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr, s_vpu_register.virt_addr);
  1162. }
  1163. /* get the major number of the character device */
  1164. if ((alloc_chrdev_region(&s_vpu_major, 0, 1, VPU_DEV_NAME)) < 0) {
  1165. err = -EBUSY;
  1166. printk(KERN_ERR "could not allocate major number\n");
  1167. goto ERROR_PROVE_DEVICE;
  1168. }
  1169. printk(KERN_INFO "SUCCESS alloc_chrdev_region\n");
  1170. /* initialize the device structure and register the device with the kernel */
  1171. cdev_init(&s_vpu_cdev, &vpu_fops);
  1172. if ((cdev_add(&s_vpu_cdev, s_vpu_major, 1)) < 0) {
  1173. err = -EBUSY;
  1174. printk(KERN_ERR "could not allocate chrdev\n");
  1175. goto ERROR_PROVE_DEVICE;
  1176. }
  1177. #ifndef VPU_SUPPORT_CLOCK_CONTROL
  1178. if (pdev)
  1179. s_vpu_clk = vpu_clk_get(&pdev->dev);
  1180. else
  1181. s_vpu_clk = vpu_clk_get(NULL);
  1182. if (!s_vpu_clk)
  1183. printk(KERN_ERR "[VPUDRV] : not support clock controller.\n");
  1184. else
  1185. DPRINTK("[VPUDRV] : get clock controller s_vpu_clk=%p\n", s_vpu_clk);
  1186. #endif
  1187. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1188. err = starfive_vdec_clk_rst_init(pdev);
  1189. if (err){
  1190. goto ERROR_PROVE_DEVICE;
  1191. }
  1192. #else
  1193. vpu_clk_enable(s_vpu_clk);
  1194. vpu_hw_reset();
  1195. #endif
  1196. #ifdef VPU_SUPPORT_ISR
  1197. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1198. if (pdev)
  1199. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1200. if (res) {/* if platform driver is implemented */
  1201. s_vpu_irq = res->start;
  1202. DPRINTK("[VPUDRV] : vpu irq number get from platform driver irq=0x%x\n", s_vpu_irq);
  1203. } else {
  1204. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1205. }
  1206. #else
  1207. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1208. #endif
  1209. err = request_irq(s_vpu_irq, vpu_irq_handler, 0, pdev->name, (void *)(&s_vpu_drv_context));
  1210. if (err) {
  1211. printk(KERN_ERR "[VPUDRV] : fail to register interrupt handler\n");
  1212. goto ERROR_PROVE_DEVICE;
  1213. }
  1214. #endif
  1215. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1216. node = of_parse_phandle(vpu_dev->of_node, "memory-region", 0);
  1217. if(node){
  1218. dev_info(vpu_dev, "Get mem form memory-region\n");
  1219. of_address_to_resource(node, 0, &res_cma);
  1220. s_video_memory.size = resource_size(&res_cma);
  1221. s_video_memory.phys_addr = res_cma.start;
  1222. }else{
  1223. dev_info(vpu_dev, "Get mem form memory-region fiiled.please check the dts file.\n");
  1224. return 0;
  1225. }
  1226. s_video_memory.base = (unsigned long)ioremap_nocache(DRAM_MEM2SYS(s_video_memory.phys_addr), PAGE_ALIGN(s_video_memory.size));
  1227. if (!s_video_memory.base) {
  1228. printk(KERN_ERR "[VPUDRV] : fail to remap video memory physical phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base, (int)s_video_memory.size);
  1229. goto ERROR_PROVE_DEVICE;
  1230. }
  1231. if (vmem_init(&s_vmem, s_video_memory.phys_addr, s_video_memory.size) < 0) {
  1232. printk(KERN_ERR "[VPUDRV] : fail to init vmem system\n");
  1233. goto ERROR_PROVE_DEVICE;
  1234. }
  1235. DPRINTK("[VPUDRV] success to probe vpu device with reserved video memory phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base,s_video_memory.size);
  1236. #else
  1237. DPRINTK("[VPUDRV] success to probe vpu device with non reserved video memory\n");
  1238. #endif
  1239. return 0;
  1240. ERROR_PROVE_DEVICE:
  1241. if (s_vpu_major)
  1242. unregister_chrdev_region(s_vpu_major, 1);
  1243. if (s_vpu_register.virt_addr)
  1244. iounmap((void *)s_vpu_register.virt_addr);
  1245. return err;
  1246. }
  1247. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1248. static int vpu_remove(struct platform_device *pdev)
  1249. {
  1250. DPRINTK("[VPUDRV] vpu_remove\n");
  1251. if (s_instance_pool.base) {
  1252. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1253. vfree((const void *)s_instance_pool.base);
  1254. #else
  1255. vpu_free_dma_buffer(&s_instance_pool);
  1256. #endif
  1257. s_instance_pool.base = 0;
  1258. }
  1259. if (s_common_memory.base) {
  1260. vpu_free_dma_buffer(&s_common_memory);
  1261. s_common_memory.base = 0;
  1262. }
  1263. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1264. if (s_video_memory.base) {
  1265. iounmap((void *)s_video_memory.base);
  1266. s_video_memory.base = 0;
  1267. vmem_exit(&s_vmem);
  1268. }
  1269. #endif
  1270. if (s_vpu_major > 0) {
  1271. cdev_del(&s_vpu_cdev);
  1272. unregister_chrdev_region(s_vpu_major, 1);
  1273. s_vpu_major = 0;
  1274. }
  1275. #ifdef VPU_SUPPORT_ISR
  1276. if (s_vpu_irq)
  1277. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1278. #endif
  1279. if (s_vpu_register.virt_addr)
  1280. iounmap((void *)s_vpu_register.virt_addr);
  1281. #ifndef VPU_SUPPORT_CLOCK_CONTROL
  1282. vpu_clk_put(s_vpu_clk);
  1283. #endif
  1284. return 0;
  1285. }
  1286. #endif /*VPU_SUPPORT_PLATFORM_DRIVER_REGISTER*/
  1287. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  1288. #define W5_MAX_CODE_BUF_SIZE (512*1024)
  1289. #define W5_CMD_INIT_VPU (0x0001)
  1290. #define W5_CMD_SLEEP_VPU (0x0004)
  1291. #define W5_CMD_WAKEUP_VPU (0x0002)
  1292. static void Wave5BitIssueCommand(int core, u32 cmd)
  1293. {
  1294. WriteVpuRegister(W5_VPU_BUSY_STATUS, 1);
  1295. WriteVpuRegister(W5_COMMAND, cmd);
  1296. WriteVpuRegister(W5_VPU_HOST_INT_REQ, 1);
  1297. return;
  1298. }
  1299. static int vpu_suspend(struct platform_device *pdev, pm_message_t state)
  1300. {
  1301. int i;
  1302. int core;
  1303. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1304. int product_code;
  1305. DPRINTK("[VPUDRV] vpu_suspend\n");
  1306. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1307. starfive_vdec_clk_enable(&pdev->dev);
  1308. #else
  1309. vpu_clk_enable(s_vpu_clk);
  1310. #endif
  1311. if (s_vpu_open_ref_count > 0) {
  1312. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1313. if (s_bit_firmware_info[core].size == 0)
  1314. continue;
  1315. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1316. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1317. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1318. if (time_after(jiffies, timeout)) {
  1319. DPRINTK("SLEEP_VPU BUSY timeout");
  1320. goto DONE_SUSPEND;
  1321. }
  1322. }
  1323. Wave5BitIssueCommand(core, W5_CMD_SLEEP_VPU);
  1324. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1325. if (time_after(jiffies, timeout)) {
  1326. DPRINTK("SLEEP_VPU BUSY timeout");
  1327. goto DONE_SUSPEND;
  1328. }
  1329. }
  1330. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1331. DPRINTK("SLEEP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1332. goto DONE_SUSPEND;
  1333. }
  1334. }
  1335. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1336. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1337. if (time_after(jiffies, timeout))
  1338. goto DONE_SUSPEND;
  1339. }
  1340. for (i = 0; i < 64; i++)
  1341. s_vpu_reg_store[core][i] = ReadVpuRegister(BIT_BASE+(0x100+(i * 4)));
  1342. }
  1343. else {
  1344. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1345. goto DONE_SUSPEND;
  1346. }
  1347. }
  1348. }
  1349. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1350. starfive_vdec_clk_disable(&pdev->dev);
  1351. #else
  1352. vpu_clk_disable(s_vpu_clk);
  1353. #endif
  1354. return 0;
  1355. DONE_SUSPEND:
  1356. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1357. starfive_vdec_clk_disable(&pdev->dev);
  1358. #else
  1359. vpu_clk_disable(s_vpu_clk);
  1360. #endif
  1361. return -EAGAIN;
  1362. }
  1363. static int vpu_resume(struct platform_device *pdev)
  1364. {
  1365. int i;
  1366. int core;
  1367. u32 val;
  1368. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1369. int product_code;
  1370. unsigned long code_base;
  1371. u32 code_size;
  1372. u32 remap_size;
  1373. int regVal;
  1374. u32 hwOption = 0;
  1375. DPRINTK("[VPUDRV] vpu_resume\n");
  1376. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1377. starfive_vdec_clk_enable(&pdev->dev);
  1378. #else
  1379. vpu_clk_enable(s_vpu_clk);
  1380. #endif
  1381. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1382. if (s_bit_firmware_info[core].size == 0) {
  1383. continue;
  1384. }
  1385. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1386. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1387. code_base = s_common_memory.phys_addr;
  1388. /* ALIGN TO 4KB */
  1389. code_size = (W5_MAX_CODE_BUF_SIZE&~0xfff);
  1390. if (code_size < s_bit_firmware_info[core].size*2) {
  1391. goto DONE_WAKEUP;
  1392. }
  1393. regVal = 0;
  1394. WriteVpuRegister(W5_PO_CONF, regVal);
  1395. /* Reset All blocks */
  1396. regVal = 0x7ffffff;
  1397. WriteVpuRegister(W5_VPU_RESET_REQ, regVal); /*Reset All blocks*/
  1398. /* Waiting reset done */
  1399. while (ReadVpuRegister(W5_VPU_RESET_STATUS)) {
  1400. if (time_after(jiffies, timeout))
  1401. goto DONE_WAKEUP;
  1402. }
  1403. WriteVpuRegister(W5_VPU_RESET_REQ, 0);
  1404. /* remap page size */
  1405. remap_size = (code_size >> 12) & 0x1ff;
  1406. regVal = 0x80000000 | (W5_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remap_size;
  1407. WriteVpuRegister(W5_VPU_REMAP_CTRL, regVal);
  1408. WriteVpuRegister(W5_VPU_REMAP_VADDR,0x00000000); /* DO NOT CHANGE! */
  1409. WriteVpuRegister(W5_VPU_REMAP_PADDR,code_base);
  1410. WriteVpuRegister(W5_ADDR_CODE_BASE, code_base);
  1411. WriteVpuRegister(W5_CODE_SIZE, code_size);
  1412. WriteVpuRegister(W5_CODE_PARAM, 0);
  1413. WriteVpuRegister(W5_INIT_VPU_TIME_OUT_CNT, timeout);
  1414. WriteVpuRegister(W5_HW_OPTION, hwOption);
  1415. /* Interrupt */
  1416. if (product_code == WAVE521_CODE || product_code == WAVE521C_CODE ) {
  1417. regVal = (1<<INT_WAVE5_ENC_SET_PARAM);
  1418. regVal |= (1<<INT_WAVE5_ENC_PIC);
  1419. regVal |= (1<<INT_WAVE5_INIT_SEQ);
  1420. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1421. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1422. }
  1423. else {
  1424. // decoder
  1425. regVal = (1<<INT_WAVE5_INIT_SEQ);
  1426. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1427. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1428. }
  1429. WriteVpuRegister(W5_VPU_VINT_ENABLE, regVal);
  1430. Wave5BitIssueCommand(core, W5_CMD_INIT_VPU);
  1431. WriteVpuRegister(W5_VPU_REMAP_CORE_START, 1);
  1432. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1433. if (time_after(jiffies, timeout))
  1434. goto DONE_WAKEUP;
  1435. }
  1436. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1437. DPRINTK("WAKEUP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1438. goto DONE_WAKEUP;
  1439. }
  1440. }
  1441. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1442. WriteVpuRegister(BIT_CODE_RUN, 0);
  1443. /*---- LOAD BOOT CODE*/
  1444. for (i = 0; i < 512; i++) {
  1445. val = s_bit_firmware_info[core].bit_code[i];
  1446. WriteVpuRegister(BIT_CODE_DOWN, ((i << 16) | val));
  1447. }
  1448. for (i = 0 ; i < 64 ; i++)
  1449. WriteVpuRegister(BIT_BASE+(0x100+(i * 4)), s_vpu_reg_store[core][i]);
  1450. WriteVpuRegister(BIT_BUSY_FLAG, 1);
  1451. WriteVpuRegister(BIT_CODE_RESET, 1);
  1452. WriteVpuRegister(BIT_CODE_RUN, 1);
  1453. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1454. if (time_after(jiffies, timeout))
  1455. goto DONE_WAKEUP;
  1456. }
  1457. }
  1458. else {
  1459. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1460. goto DONE_WAKEUP;
  1461. }
  1462. }
  1463. if (s_vpu_open_ref_count == 0){
  1464. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1465. starfive_vdec_clk_disable(&pdev->dev);
  1466. #else
  1467. vpu_clk_disable(s_vpu_clk);
  1468. #endif
  1469. }
  1470. DONE_WAKEUP:
  1471. if (s_vpu_open_ref_count > 0){
  1472. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1473. starfive_vdec_clk_enable(&pdev->dev);
  1474. #else
  1475. vpu_clk_enable(s_vpu_clk);
  1476. #endif
  1477. }
  1478. return 0;
  1479. }
  1480. #else
  1481. #define vpu_suspend NULL
  1482. #define vpu_resume NULL
  1483. #endif /* !CONFIG_PM */
  1484. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1485. static const struct of_device_id cm_vpu_match[] = {
  1486. {
  1487. .compatible = "c&m,cm511-vpu",
  1488. },
  1489. {
  1490. },
  1491. };
  1492. MODULE_DEVICE_TABLE(of, cm_vpu_match);
  1493. static struct platform_driver vpu_driver = {
  1494. .driver = {
  1495. .name = VPU_PLATFORM_DEVICE_NAME,
  1496. .of_match_table = cm_vpu_match,
  1497. },
  1498. .probe = vpu_probe,
  1499. .remove = vpu_remove,
  1500. .suspend = vpu_suspend,
  1501. .resume = vpu_resume,
  1502. };
  1503. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1504. static int __init vpu_init(void)
  1505. {
  1506. int res;
  1507. #ifdef SUPPORT_MULTI_INST_INTR
  1508. int i;
  1509. #endif
  1510. DPRINTK("[VPUDRV] begin vpu_init\n");
  1511. #ifdef SUPPORT_MULTI_INST_INTR
  1512. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1513. init_waitqueue_head(&s_interrupt_wait_q[i]);
  1514. }
  1515. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1516. #define MAX_INTERRUPT_QUEUE (16*MAX_NUM_INSTANCE)
  1517. res = kfifo_alloc(&s_interrupt_pending_q[i], MAX_INTERRUPT_QUEUE*sizeof(u32), GFP_KERNEL);
  1518. if (res) {
  1519. DPRINTK("[VPUDRV] kfifo_alloc failed 0x%x\n", res);
  1520. }
  1521. }
  1522. #else
  1523. init_waitqueue_head(&s_interrupt_wait_q);
  1524. #endif
  1525. s_common_memory.base = 0;
  1526. s_instance_pool.base = 0;
  1527. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1528. res = platform_driver_register(&vpu_driver);
  1529. #else
  1530. res = vpu_probe(NULL);
  1531. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1532. DPRINTK("[VPUDRV] end vpu_init result=0x%x\n", res);
  1533. return res;
  1534. }
  1535. static void __exit vpu_exit(void)
  1536. {
  1537. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1538. starfive_vdec_clk_disable(vpu_dev);
  1539. starfive_vdec_rst_assert(vpu_dev);
  1540. #endif
  1541. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1542. DPRINTK("[VPUDRV] vpu_exit\n");
  1543. platform_driver_unregister(&vpu_driver);
  1544. #else /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1545. #ifndef VPU_SUPPORT_CLOCK_CONTROL
  1546. vpu_clk_disable(s_vpu_clk);
  1547. vpu_clk_put(s_vpu_clk);
  1548. #endif
  1549. if (s_instance_pool.base) {
  1550. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1551. vfree((const void *)s_instance_pool.base);
  1552. #else
  1553. vpu_free_dma_buffer(&s_instance_pool);
  1554. #endif
  1555. s_instance_pool.base = 0;
  1556. }
  1557. if (s_common_memory.base) {
  1558. vpu_free_dma_buffer(&s_common_memory);
  1559. s_common_memory.base = 0;
  1560. }
  1561. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1562. if (s_video_memory.base) {
  1563. iounmap((void *)s_video_memory.base);
  1564. s_video_memory.base = 0;
  1565. vmem_exit(&s_vmem);
  1566. }
  1567. #endif
  1568. if (s_vpu_major > 0) {
  1569. cdev_del(&s_vpu_cdev);
  1570. unregister_chrdev_region(s_vpu_major, 1);
  1571. s_vpu_major = 0;
  1572. }
  1573. #ifdef VPU_SUPPORT_ISR
  1574. if (s_vpu_irq)
  1575. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1576. #endif
  1577. #ifdef SUPPORT_MULTI_INST_INTR
  1578. {
  1579. int i;
  1580. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1581. kfifo_free(&s_interrupt_pending_q[i]);
  1582. }
  1583. }
  1584. #endif
  1585. if (s_vpu_register.virt_addr) {
  1586. iounmap((void *)s_vpu_register.virt_addr);
  1587. s_vpu_register.virt_addr = 0x00;
  1588. }
  1589. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1590. return;
  1591. }
  1592. MODULE_AUTHOR("A customer using C&M VPU, Inc.");
  1593. MODULE_DESCRIPTION("VPU linux driver");
  1594. MODULE_LICENSE("GPL");
  1595. module_init(vpu_init);
  1596. module_exit(vpu_exit);
  1597. static void _set_reset(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg,int ibit)
  1598. {
  1599. unsigned int read_value;
  1600. read_value = vic_readl(p_assert_reg);
  1601. read_value &= ~(0x1<<ibit);
  1602. read_value |= (0x1&0x1)<<ibit;
  1603. vic_writel(read_value,p_assert_reg);
  1604. do {
  1605. read_value = (vic_readl(p_status_reg))>>ibit;
  1606. read_value &= 0x1;
  1607. } while(read_value!=0x0);
  1608. }
  1609. static void _clr_reset(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg,int ibit)
  1610. {
  1611. unsigned int read_value;
  1612. read_value = vic_readl(p_assert_reg);
  1613. read_value &= ~(0x1<<ibit);
  1614. read_value |= (0x0&0x1)<<ibit;
  1615. vic_writel(read_value,p_assert_reg);
  1616. do {
  1617. read_value = (vic_readl(p_status_reg))>>ibit;
  1618. read_value &= 0x1;
  1619. } while(read_value!=0x1);
  1620. }
  1621. static void _enable_clk(volatile unsigned long p_reg,int ibit)
  1622. {
  1623. unsigned int read_value;
  1624. read_value = vic_readl(p_reg);
  1625. read_value &= ~(0x1<<ibit);
  1626. read_value |= (0x1&0x1)<<ibit;
  1627. vic_writel(read_value,p_reg);
  1628. }
  1629. static void _disable_clk(volatile unsigned long p_reg,int ibit)
  1630. {
  1631. unsigned int read_value;
  1632. read_value = vic_readl(p_reg);
  1633. read_value &= ~(0x1<<ibit);
  1634. read_value |= (0x0&0x1)<<ibit;
  1635. vic_writel(read_value,p_reg);
  1636. }
  1637. static void _reset_assert(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg)
  1638. {
  1639. //_set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_BRG_MAIN);
  1640. _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_APB);
  1641. _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_AXI);
  1642. _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_BCLK);
  1643. _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_CCLK);
  1644. }
  1645. static void _reset_clear(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg)
  1646. {
  1647. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_BRG_MAIN);
  1648. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_AXI);
  1649. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_BCLK);
  1650. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_CCLK);
  1651. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_APB);
  1652. }
  1653. static int _reset(void)
  1654. {
  1655. volatile unsigned long p_breg = (unsigned long)ioremap_nocache(rstgen_Software_RESET_BASE_REG_ADDR,0x20);
  1656. if(!p_breg){
  1657. return -1;
  1658. }
  1659. _reset_assert(p_breg+rstgen_Software_RESET_assert0_OFFSET,p_breg+rstgen_Software_RESET_status0_OFFSET);
  1660. mdelay(1);
  1661. _reset_clear(p_breg+rstgen_Software_RESET_assert0_OFFSET,p_breg+rstgen_Software_RESET_status0_OFFSET);
  1662. iounmap((void *)p_breg);
  1663. return 0;
  1664. }
  1665. static int _clk_control(int enable)
  1666. {
  1667. volatile unsigned long p_breg = (unsigned long)ioremap_nocache(clk_BASE_REG_ADDR,0x100);
  1668. if(!p_breg){
  1669. return -1;
  1670. }
  1671. if(enable){
  1672. _enable_clk(p_breg+clk_vdec_axi_ctrl_REG_OFFSET,31);
  1673. _enable_clk(p_breg+clk_vdecbrg_mainclk_ctrl_REG_OFFSET,31);
  1674. _enable_clk(p_breg+clk_vdec_bclk_ctrl_REG_OFFSET,31);
  1675. _enable_clk(p_breg+clk_vdec_cclk_ctrl_REG_OFFSET,31);
  1676. _enable_clk(p_breg+clk_vdec_apb_ctrl_REG_OFFSET,31);
  1677. }
  1678. else
  1679. {
  1680. _disable_clk(p_breg+clk_vdec_axi_ctrl_REG_OFFSET,31);
  1681. // _disable_clk(p_breg+clk_vdecbrg_mainclk_ctrl_REG_OFFSET,31);
  1682. _disable_clk(p_breg+clk_vdec_bclk_ctrl_REG_OFFSET,31);
  1683. _disable_clk(p_breg+clk_vdec_cclk_ctrl_REG_OFFSET,31);
  1684. _disable_clk(p_breg+clk_vdec_apb_ctrl_REG_OFFSET,31);
  1685. }
  1686. iounmap((void *)p_breg);
  1687. return 0;
  1688. }
  1689. int vpu_hw_reset(void)
  1690. {
  1691. _reset();
  1692. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1693. return 0;
  1694. }
  1695. struct clk *vpu_clk_get(struct device *dev)
  1696. {
  1697. return clk_get(dev, VPU_CLK_NAME);
  1698. }
  1699. void vpu_clk_put(struct clk *clk)
  1700. {
  1701. if (!(clk == NULL || IS_ERR(clk)))
  1702. clk_put(clk);
  1703. }
  1704. int vpu_clk_enable(struct clk *clk)
  1705. {
  1706. if (!(clk == NULL || IS_ERR(clk))) {
  1707. /* the bellow is for C&M EVB.*/
  1708. /*
  1709. {
  1710. struct clk *s_vpuext_clk = NULL;
  1711. s_vpuext_clk = clk_get(NULL, "vcore");
  1712. if (s_vpuext_clk)
  1713. {
  1714. DPRINTK("[VPUDRV] vcore clk=%p\n", s_vpuext_clk);
  1715. clk_enable(s_vpuext_clk);
  1716. }
  1717. DPRINTK("[VPUDRV] vbus clk=%p\n", s_vpuext_clk);
  1718. if (s_vpuext_clk)
  1719. {
  1720. s_vpuext_clk = clk_get(NULL, "vbus");
  1721. clk_enable(s_vpuext_clk);
  1722. }
  1723. }
  1724. */
  1725. /* for C&M EVB. */
  1726. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1727. //customers needs implementation to turn on clock like clk_enable(clk)
  1728. return 1;
  1729. }
  1730. _clk_control(1);
  1731. return 0;
  1732. }
  1733. void vpu_clk_disable(struct clk *clk)
  1734. {
  1735. if (!(clk == NULL || IS_ERR(clk))) {
  1736. DPRINTK("[VPUDRV] vpu_clk_disable\n");
  1737. //customers needs implementation to turn off clock like clk_disable(clk)
  1738. }
  1739. _clk_control(0);
  1740. }