venc.c 58 KB

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  1. #include <linux/kernel.h>
  2. #include <linux/mm.h>
  3. #include <linux/interrupt.h>
  4. #include <linux/ioport.h>
  5. #include <linux/module.h>
  6. #include <linux/platform_device.h>
  7. #include <linux/dma-mapping.h>
  8. #include <linux/of.h>
  9. #include <linux/of_address.h>
  10. #include <linux/wait.h>
  11. #include <linux/list.h>
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/uaccess.h>
  15. #include <linux/cdev.h>
  16. #include <linux/slab.h>
  17. #include <linux/sched.h>
  18. #include <linux/version.h>
  19. #include <linux/kfifo.h>
  20. #include <linux/kthread.h>
  21. #include <linux/sched/signal.h>
  22. #include <soc/sifive/sifive_l2_cache.h>
  23. #include "../../../vpuapi/vpuconfig.h"
  24. #include "vpu.h"
  25. #include "venc-starfive.h"
  26. #include <linux/of_device.h>
  27. #define starfive_flush_dcache(start, len) \
  28. sifive_l2_flush64_range(start, len)
  29. //#define ENABLE_DEBUG_MSG
  30. #ifdef ENABLE_DEBUG_MSG
  31. #define DPRINTK(args...) printk(KERN_INFO args);
  32. #else
  33. #define DPRINTK(args...)
  34. #endif
  35. /* definitions to be changed as customer configuration */
  36. /* if linux version is 5.15 or later, then can use clock and reset framework */
  37. #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)
  38. #define VPU_SUPPORT_CLOCK_CONTROL
  39. #endif
  40. /* if the driver want to use interrupt service from kernel ISR */
  41. #define VPU_SUPPORT_ISR
  42. #ifdef VPU_SUPPORT_ISR
  43. /* if the driver want to disable and enable IRQ whenever interrupt asserted. */
  44. //#define VPU_IRQ_CONTROL
  45. #endif
  46. /* if the platform driver knows the name of this driver */
  47. /* VPU_PLATFORM_DEVICE_NAME */
  48. #define VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  49. /* if this driver knows the dedicated video memory address */
  50. //#define VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  51. #define VPU_PLATFORM_DEVICE_NAME "venc"
  52. #define VPU_DEV_NAME "venc"
  53. /* if the platform driver knows this driver */
  54. /* the definition of VPU_REG_BASE_ADDR and VPU_REG_SIZE are not meaningful */
  55. #define VPU_REG_BASE_ADDR 0x118E0000
  56. #define VPU_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
  57. #define VENC_IRQ_ADDR 0x18
  58. #ifdef VPU_SUPPORT_ISR
  59. #define VPU_IRQ_NUM (26)
  60. #endif
  61. /* this definition is only for chipsnmedia FPGA board env */
  62. /* so for SOC env of customers can be ignored */
  63. #ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/
  64. # define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
  65. #endif
  66. struct device *vpu_dev;
  67. typedef struct vpu_drv_context_t {
  68. struct fasync_struct *async_queue;
  69. #ifdef SUPPORT_MULTI_INST_INTR
  70. unsigned long interrupt_reason[MAX_NUM_INSTANCE];
  71. #else
  72. unsigned long interrupt_reason;
  73. #endif
  74. u32 open_count; /*!<< device reference count. Not instance count */
  75. } vpu_drv_context_t;
  76. /* To track the allocated memory buffer */
  77. typedef struct vpudrv_buffer_pool_t {
  78. struct list_head list;
  79. struct vpudrv_buffer_t vb;
  80. struct file *filp;
  81. } vpudrv_buffer_pool_t;
  82. /* To track the instance index and buffer in instance pool */
  83. typedef struct vpudrv_instanace_list_t {
  84. struct list_head list;
  85. unsigned long inst_idx;
  86. unsigned long core_idx;
  87. struct file *filp;
  88. } vpudrv_instanace_list_t;
  89. typedef struct vpudrv_instance_pool_t {
  90. unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
  91. } vpudrv_instance_pool_t;
  92. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  93. #include "vmm.h"
  94. static video_mm_t s_vmem;
  95. static vpudrv_buffer_t s_video_memory = {0};
  96. #endif /*VPU_SUPPORT_RESERVED_VIDEO_MEMORY*/
  97. static int vpu_hw_reset(void);
  98. static void vpu_clk_disable(void);
  99. static int vpu_clk_enable(void);
  100. /* end customer definition */
  101. static vpudrv_buffer_t s_instance_pool = {0};
  102. static vpudrv_buffer_t s_common_memory = {0};
  103. static vpu_drv_context_t s_vpu_drv_context;
  104. static int s_vpu_major;
  105. static struct cdev s_vpu_cdev;
  106. static int s_vpu_open_ref_count;
  107. #ifdef VPU_SUPPORT_ISR
  108. static int s_vpu_irq = VPU_IRQ_NUM;
  109. #endif
  110. static vpudrv_buffer_t s_vpu_register = {0};
  111. #ifdef SUPPORT_MULTI_INST_INTR
  112. static int s_interrupt_flag[MAX_NUM_INSTANCE];
  113. static wait_queue_head_t s_interrupt_wait_q[MAX_NUM_INSTANCE];
  114. typedef struct kfifo kfifo_t;
  115. static kfifo_t s_interrupt_pending_q[MAX_NUM_INSTANCE];
  116. static spinlock_t s_kfifo_lock = __SPIN_LOCK_UNLOCKED(s_kfifo_lock);
  117. #else
  118. static int s_interrupt_flag;
  119. static wait_queue_head_t s_interrupt_wait_q;
  120. #endif
  121. static spinlock_t s_vpu_lock = __SPIN_LOCK_UNLOCKED(s_vpu_lock);
  122. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
  123. static DECLARE_MUTEX(s_vpu_sem);
  124. #else
  125. static DEFINE_SEMAPHORE(s_vpu_sem);
  126. #endif
  127. static struct list_head s_vbp_head = LIST_HEAD_INIT(s_vbp_head);
  128. static struct list_head s_inst_list_head = LIST_HEAD_INIT(s_inst_list_head);
  129. static vpu_bit_firmware_info_t s_bit_firmware_info[MAX_NUM_VPU_CORE];
  130. #ifdef CONFIG_PM
  131. /* implement to power management functions */
  132. #define BIT_BASE 0x0000
  133. #define BIT_CODE_RUN (BIT_BASE + 0x000)
  134. #define BIT_CODE_DOWN (BIT_BASE + 0x004)
  135. #define BIT_INT_CLEAR (BIT_BASE + 0x00C)
  136. #define BIT_INT_STS (BIT_BASE + 0x010)
  137. #define BIT_CODE_RESET (BIT_BASE + 0x014)
  138. #define BIT_INT_REASON (BIT_BASE + 0x174)
  139. #define BIT_BUSY_FLAG (BIT_BASE + 0x160)
  140. #define BIT_RUN_COMMAND (BIT_BASE + 0x164)
  141. #define BIT_RUN_INDEX (BIT_BASE + 0x168)
  142. #define BIT_RUN_COD_STD (BIT_BASE + 0x16C)
  143. /* WAVE5 registers */
  144. #define W5_REG_BASE 0x0000
  145. #define W5_VPU_BUSY_STATUS (W5_REG_BASE + 0x0070)
  146. #define W5_VPU_INT_REASON_CLEAR (W5_REG_BASE + 0x0034)
  147. #define W5_VPU_VINT_CLEAR (W5_REG_BASE + 0x003C)
  148. #define W5_VPU_VPU_INT_STS (W5_REG_BASE + 0x0044)
  149. #define W5_VPU_INT_REASON (W5_REG_BASE + 0x004c)
  150. #define W5_RET_FAIL_REASON (W5_REG_BASE + 0x010C)
  151. #ifdef SUPPORT_MULTI_INST_INTR
  152. #define W5_RET_BS_EMPTY_INST (W5_REG_BASE + 0x01E4)
  153. #define W5_RET_QUEUE_CMD_DONE_INST (W5_REG_BASE + 0x01E8)
  154. #define W5_RET_SEQ_DONE_INSTANCE_INFO (W5_REG_BASE + 0x01FC)
  155. typedef enum {
  156. INT_WAVE5_INIT_VPU = 0,
  157. INT_WAVE5_WAKEUP_VPU = 1,
  158. INT_WAVE5_SLEEP_VPU = 2,
  159. INT_WAVE5_CREATE_INSTANCE = 3,
  160. INT_WAVE5_FLUSH_INSTANCE = 4,
  161. INT_WAVE5_DESTORY_INSTANCE = 5,
  162. INT_WAVE5_INIT_SEQ = 6,
  163. INT_WAVE5_SET_FRAMEBUF = 7,
  164. INT_WAVE5_DEC_PIC = 8,
  165. INT_WAVE5_ENC_PIC = 8,
  166. INT_WAVE5_ENC_SET_PARAM = 9,
  167. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  168. INT_WAVE5_ENC_SRC_RELEASE = 10,
  169. #endif
  170. INT_WAVE5_ENC_LOW_LATENCY = 13,
  171. INT_WAVE5_DEC_QUERY = 14,
  172. INT_WAVE5_BSBUF_EMPTY = 15,
  173. INT_WAVE5_BSBUF_FULL = 15,
  174. } Wave5InterruptBit;
  175. #endif
  176. /* WAVE5 INIT, WAKEUP */
  177. #define W5_PO_CONF (W5_REG_BASE + 0x0000)
  178. #define W5_VPU_VINT_ENABLE (W5_REG_BASE + 0x0048)
  179. #define W5_VPU_RESET_REQ (W5_REG_BASE + 0x0050)
  180. #define W5_VPU_RESET_STATUS (W5_REG_BASE + 0x0054)
  181. #define W5_VPU_REMAP_CTRL (W5_REG_BASE + 0x0060)
  182. #define W5_VPU_REMAP_VADDR (W5_REG_BASE + 0x0064)
  183. #define W5_VPU_REMAP_PADDR (W5_REG_BASE + 0x0068)
  184. #define W5_VPU_REMAP_CORE_START (W5_REG_BASE + 0x006C)
  185. #define W5_REMAP_CODE_INDEX 0
  186. /* WAVE5 registers */
  187. #define W5_ADDR_CODE_BASE (W5_REG_BASE + 0x0110)
  188. #define W5_CODE_SIZE (W5_REG_BASE + 0x0114)
  189. #define W5_CODE_PARAM (W5_REG_BASE + 0x0118)
  190. #define W5_INIT_VPU_TIME_OUT_CNT (W5_REG_BASE + 0x0130)
  191. #define W5_HW_OPTION (W5_REG_BASE + 0x012C)
  192. #define W5_RET_SUCCESS (W5_REG_BASE + 0x0108)
  193. #define W5_COMMAND (W5_REG_BASE + 0x0100)
  194. #define W5_VPU_HOST_INT_REQ (W5_REG_BASE + 0x0038)
  195. /* Product register */
  196. #define VPU_PRODUCT_CODE_REGISTER (BIT_BASE + 0x1044)
  197. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  198. static u32 s_vpu_reg_store[MAX_NUM_VPU_CORE][64];
  199. #endif
  200. #endif
  201. #define ReadVpuRegister(addr) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr)
  202. #define WriteVpuRegister(addr, val) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr) = (unsigned int)val
  203. #define WriteVpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
  204. #define vic_readl(addr) readl((void __iomem *)addr)
  205. #define vic_writel(val,addr) writel(val,(void __iomem *)addr)
  206. #define rstgen_Software_RESET_BASE_REG_ADDR 0x11840000
  207. #define rstgen_Software_RESET_assert0_OFFSET (0x0)
  208. #define rstgen_Software_RESET_status0_OFFSET (0x10)
  209. #define NBIT_RSTN_VENC_BRG_MAIN 26
  210. #define NBIT_RSTN_VENC_AXI 25
  211. #define NBIT_RSTN_VENC_BCLK 27
  212. #define NBIT_RSTN_VENC_CCLK 28
  213. #define NBIT_RSTN_VENC_APB 29
  214. #define clk_BASE_REG_ADDR 0x11800000
  215. #define clk_venc_axi_ctrl_REG_OFFSET (0xe4)
  216. #define clk_vencbrg_mainclk_ctrl_REG_OFFSET (0xe8)
  217. #define clk_venc_bclk_ctrl_REG_OFFSET (0xec)
  218. #define clk_venc_cclk_ctrl_REG_OFFSET (0xf0)
  219. #define clk_venc_apb_ctrl_REG_OFFSET (0xf4)
  220. static int vpu_alloc_dma_buffer(vpudrv_buffer_t *vb)
  221. {
  222. if (!vb)
  223. return -1;
  224. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  225. vb->phys_addr = (unsigned long)vmem_alloc(&s_vmem, vb->size, 0);
  226. if ((unsigned long)vb->phys_addr == (unsigned long)-1) {
  227. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  228. return -1;
  229. }
  230. vb->base = (unsigned long)(s_video_memory.base + (vb->phys_addr - s_video_memory.phys_addr));
  231. #else
  232. vb->base = (unsigned long)dma_alloc_coherent(vpu_dev, PAGE_ALIGN(vb->size), (dma_addr_t *) (&vb->phys_addr), GFP_DMA | GFP_KERNEL);
  233. if ((void *)(vb->base) == NULL) {
  234. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  235. return -1;
  236. }
  237. starfive_flush_dcache(vb->phys_addr,PAGE_ALIGN(vb->size));
  238. #endif
  239. return 0;
  240. }
  241. static void vpu_free_dma_buffer(vpudrv_buffer_t *vb)
  242. {
  243. if (!vb)
  244. return;
  245. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  246. if (vb->base)
  247. vmem_free(&s_vmem, vb->phys_addr, 0);
  248. #else
  249. if (vb->base)
  250. dma_free_coherent(vpu_dev, PAGE_ALIGN(vb->size), (void *)vb->base, vb->phys_addr);
  251. #endif
  252. }
  253. static int vpu_free_instances(struct file *filp)
  254. {
  255. vpudrv_instanace_list_t *vil, *n;
  256. vpudrv_instance_pool_t *vip;
  257. void *vip_base;
  258. int instance_pool_size_per_core;
  259. void *vdi_mutexes_base;
  260. const int PTHREAD_MUTEX_T_DESTROY_VALUE = 0xdead10cc;
  261. DPRINTK("[VPUDRV] vpu_free_instances\n");
  262. instance_pool_size_per_core = (s_instance_pool.size/MAX_NUM_VPU_CORE); /* s_instance_pool.size assigned to the size of all core once call VDI_IOCTL_GET_INSTANCE_POOL by user. */
  263. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  264. {
  265. if (vil->filp == filp) {
  266. vip_base = (void *)(s_instance_pool.base + (instance_pool_size_per_core*vil->core_idx));
  267. DPRINTK("[VPUDRV] vpu_free_instances detect instance crash instIdx=%d, coreIdx=%d, vip_base=%p, instance_pool_size_per_core=%d\n", (int)vil->inst_idx, (int)vil->core_idx, vip_base, (int)instance_pool_size_per_core);
  268. vip = (vpudrv_instance_pool_t *)vip_base;
  269. if (vip) {
  270. memset(&vip->codecInstPool[vil->inst_idx], 0x00, 4); /* only first 4 byte is key point(inUse of CodecInst in vpuapi) to free the corresponding instance. */
  271. #define PTHREAD_MUTEX_T_HANDLE_SIZE 4
  272. vdi_mutexes_base = (vip_base + (instance_pool_size_per_core - PTHREAD_MUTEX_T_HANDLE_SIZE*4));
  273. DPRINTK("[VPUDRV] vpu_free_instances : force to destroy vdi_mutexes_base=%p in userspace \n", vdi_mutexes_base);
  274. if (vdi_mutexes_base) {
  275. int i;
  276. for (i = 0; i < 4; i++) {
  277. memcpy(vdi_mutexes_base, &PTHREAD_MUTEX_T_DESTROY_VALUE, PTHREAD_MUTEX_T_HANDLE_SIZE);
  278. vdi_mutexes_base += PTHREAD_MUTEX_T_HANDLE_SIZE;
  279. }
  280. }
  281. }
  282. s_vpu_open_ref_count--;
  283. list_del(&vil->list);
  284. kfree(vil);
  285. }
  286. }
  287. return 1;
  288. }
  289. static int vpu_free_buffers(struct file *filp)
  290. {
  291. vpudrv_buffer_pool_t *pool, *n;
  292. vpudrv_buffer_t vb;
  293. DPRINTK("[VPUDRV] vpu_free_buffers\n");
  294. list_for_each_entry_safe(pool, n, &s_vbp_head, list)
  295. {
  296. if (pool->filp == filp) {
  297. vb = pool->vb;
  298. if (vb.base) {
  299. vpu_free_dma_buffer(&vb);
  300. list_del(&pool->list);
  301. kfree(pool);
  302. }
  303. }
  304. }
  305. return 0;
  306. }
  307. #ifdef SUPPORT_MULTI_INST_INTR
  308. static inline u32 get_inst_idx(u32 reg_val)
  309. {
  310. u32 inst_idx;
  311. int i;
  312. for (i=0; i < MAX_NUM_INSTANCE; i++)
  313. {
  314. if(((reg_val >> i)&0x01) == 1)
  315. break;
  316. }
  317. inst_idx = i;
  318. return inst_idx;
  319. }
  320. static s32 get_vpu_inst_idx(vpu_drv_context_t *dev, u32 *reason, u32 empty_inst, u32 done_inst, u32 seq_inst)
  321. {
  322. s32 inst_idx;
  323. u32 reg_val;
  324. u32 int_reason;
  325. int_reason = *reason;
  326. DPRINTK("[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  327. //printk(KERN_ERR "[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  328. if (int_reason & (1 << INT_WAVE5_BSBUF_EMPTY))
  329. {
  330. reg_val = (empty_inst & 0xffff);
  331. inst_idx = get_inst_idx(reg_val);
  332. *reason = (1 << INT_WAVE5_BSBUF_EMPTY);
  333. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  334. goto GET_VPU_INST_IDX_HANDLED;
  335. }
  336. if (int_reason & (1 << INT_WAVE5_INIT_SEQ))
  337. {
  338. reg_val = (seq_inst & 0xffff);
  339. inst_idx = get_inst_idx(reg_val);
  340. *reason = (1 << INT_WAVE5_INIT_SEQ);
  341. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO INIT_SEQ reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  342. goto GET_VPU_INST_IDX_HANDLED;
  343. }
  344. if (int_reason & (1 << INT_WAVE5_DEC_PIC))
  345. {
  346. reg_val = (done_inst & 0xffff);
  347. inst_idx = get_inst_idx(reg_val);
  348. *reason = (1 << INT_WAVE5_DEC_PIC);
  349. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  350. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  351. {
  352. u32 ll_inst_idx;
  353. reg_val = (done_inst >> 16);
  354. ll_inst_idx = get_inst_idx(reg_val);
  355. if (ll_inst_idx == inst_idx)
  356. *reason = ((1 << INT_WAVE5_DEC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY));
  357. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC and ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d, ll_inst_idx=%d\n", __func__, reg_val, inst_idx, ll_inst_idx);
  358. }
  359. goto GET_VPU_INST_IDX_HANDLED;
  360. }
  361. if (int_reason & (1 << INT_WAVE5_ENC_SET_PARAM))
  362. {
  363. reg_val = (seq_inst & 0xffff);
  364. inst_idx = get_inst_idx(reg_val);
  365. *reason = (1 << INT_WAVE5_ENC_SET_PARAM);
  366. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  367. goto GET_VPU_INST_IDX_HANDLED;
  368. }
  369. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  370. if (int_reason & (1 << INT_WAVE5_ENC_SRC_RELEASE))
  371. {
  372. reg_val = (done_inst & 0xffff);
  373. inst_idx = get_inst_idx(reg_val);
  374. *reason = (1 << INT_WAVE5_ENC_SRC_RELEASE);
  375. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  376. goto GET_VPU_INST_IDX_HANDLED;
  377. }
  378. #endif
  379. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  380. {
  381. reg_val = (done_inst >> 16);
  382. inst_idx = get_inst_idx(reg_val);
  383. *reason = (1 << INT_WAVE5_ENC_LOW_LATENCY);
  384. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  385. goto GET_VPU_INST_IDX_HANDLED;
  386. }
  387. inst_idx = -1;
  388. *reason = 0;
  389. DPRINTK("[VPUDRV] %s, UNKNOWN INTERRUPT REASON: %08x\n", __func__, int_reason);
  390. GET_VPU_INST_IDX_HANDLED:
  391. DPRINTK("[VPUDRV][-]%s, inst_idx=%d. *reason=0x%x\n", __func__, inst_idx, *reason);
  392. return inst_idx;
  393. }
  394. #endif
  395. static irqreturn_t vpu_irq_handler(int irq, void *dev_id)
  396. {
  397. vpu_drv_context_t *dev = (vpu_drv_context_t *)dev_id;
  398. /* this can be removed. it also work in VPU_WaitInterrupt of API function */
  399. int core;
  400. int product_code;
  401. #ifdef SUPPORT_MULTI_INST_INTR
  402. u32 intr_reason;
  403. s32 intr_inst_index;
  404. #endif
  405. DPRINTK("[VPUDRV][+]%s\n", __func__);
  406. #ifdef VPU_IRQ_CONTROL
  407. disable_irq_nosync(s_vpu_irq);
  408. #endif
  409. #ifdef SUPPORT_MULTI_INST_INTR
  410. intr_inst_index = 0;
  411. intr_reason = 0;
  412. #endif
  413. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  414. if (s_bit_firmware_info[core].size == 0) {/* it means that we didn't get an information the current core from API layer. No core activated.*/
  415. printk(KERN_ERR "[VPUDRV] : s_bit_firmware_info[core].size is zero\n");
  416. continue;
  417. }
  418. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  419. if (PRODUCT_CODE_W_SERIES(product_code)) {
  420. if (ReadVpuRegister(W5_VPU_VPU_INT_STS)) {
  421. #ifdef SUPPORT_MULTI_INST_INTR
  422. u32 empty_inst;
  423. u32 done_inst;
  424. u32 seq_inst;
  425. u32 i, reason, reason_clr;
  426. reason = ReadVpuRegister(W5_VPU_INT_REASON);
  427. empty_inst = ReadVpuRegister(W5_RET_BS_EMPTY_INST);
  428. done_inst = ReadVpuRegister(W5_RET_QUEUE_CMD_DONE_INST);
  429. seq_inst = ReadVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO);
  430. reason_clr = reason;
  431. DPRINTK("[VPUDRV] vpu_irq_handler reason=0x%x, empty_inst=0x%x, done_inst=0x%x, seq_inst=0x%x \n", reason, empty_inst, done_inst, seq_inst);
  432. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  433. if (0 == empty_inst && 0 == done_inst && 0 == seq_inst) break;
  434. intr_reason = reason;
  435. intr_inst_index = get_vpu_inst_idx(dev, &intr_reason, empty_inst, done_inst, seq_inst);
  436. DPRINTK("[VPUDRV] > instance_index: %d, intr_reason: %08x empty_inst: %08x done_inst: %08x seq_inst: %08x\n", intr_inst_index, intr_reason, empty_inst, done_inst, seq_inst);
  437. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  438. if (intr_reason == (1 << INT_WAVE5_BSBUF_EMPTY)) {
  439. empty_inst = empty_inst & ~(1 << intr_inst_index);
  440. WriteVpuRegister(W5_RET_BS_EMPTY_INST, empty_inst);
  441. if (0 == empty_inst) {
  442. reason &= ~(1<<INT_WAVE5_BSBUF_EMPTY);
  443. }
  444. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST Clear empty_inst=0x%x, intr_inst_index=%d\n", __func__, empty_inst, intr_inst_index);
  445. }
  446. if (intr_reason == (1 << INT_WAVE5_DEC_PIC))
  447. {
  448. done_inst = done_inst & ~(1 << intr_inst_index);
  449. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  450. if (0 == done_inst) {
  451. reason &= ~(1<<INT_WAVE5_DEC_PIC);
  452. }
  453. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  454. }
  455. if ((intr_reason == (1 << INT_WAVE5_INIT_SEQ)) || (intr_reason == (1 << INT_WAVE5_ENC_SET_PARAM)))
  456. {
  457. seq_inst = seq_inst & ~(1 << intr_inst_index);
  458. WriteVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO, seq_inst);
  459. if (0 == seq_inst) {
  460. reason &= ~(1<<INT_WAVE5_INIT_SEQ | 1<<INT_WAVE5_ENC_SET_PARAM);
  461. }
  462. DPRINTK("[VPUDRV] %s, W5_RET_SEQ_DONE_INSTANCE_INFO Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  463. }
  464. if ((intr_reason == (1 << INT_WAVE5_ENC_LOW_LATENCY)))
  465. {
  466. done_inst = (done_inst >> 16);
  467. done_inst = done_inst & ~(1 << intr_inst_index);
  468. done_inst = (done_inst << 16);
  469. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  470. if (0 == done_inst) {
  471. reason &= ~(1 << INT_WAVE5_ENC_LOW_LATENCY);
  472. }
  473. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST INT_WAVE5_ENC_LOW_LATENCY Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  474. }
  475. if (!kfifo_is_full(&s_interrupt_pending_q[intr_inst_index])) {
  476. if (intr_reason == ((1 << INT_WAVE5_ENC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY))) {
  477. u32 ll_intr_reason = (1 << INT_WAVE5_ENC_PIC);
  478. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &ll_intr_reason, sizeof(u32), &s_kfifo_lock);
  479. }
  480. else
  481. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  482. }
  483. else {
  484. printk(KERN_ERR "[VPUDRV] : kfifo_is_full kfifo_count=%d \n", kfifo_len(&s_interrupt_pending_q[intr_inst_index]));
  485. }
  486. }
  487. else {
  488. printk(KERN_ERR "[VPUDRV] : intr_inst_index is wrong intr_inst_index=%d \n", intr_inst_index);
  489. }
  490. }
  491. if (0 != reason)
  492. printk(KERN_ERR "INTERRUPT REASON REMAINED: %08x\n", reason);
  493. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, reason_clr);
  494. #else
  495. dev->interrupt_reason = ReadVpuRegister(W5_VPU_INT_REASON);
  496. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, dev->interrupt_reason);
  497. #endif
  498. WriteVpuRegister(W5_VPU_VINT_CLEAR, 0x1);
  499. }
  500. }
  501. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  502. if (ReadVpuRegister(BIT_INT_STS)) {
  503. #ifdef SUPPORT_MULTI_INST_INTR
  504. intr_reason = ReadVpuRegister(BIT_INT_REASON);
  505. intr_inst_index = 0; // in case of coda seriese. treats intr_inst_index is already 0
  506. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  507. #else
  508. dev->interrupt_reason = ReadVpuRegister(BIT_INT_REASON);
  509. #endif
  510. WriteVpuRegister(BIT_INT_CLEAR, 0x1);
  511. }
  512. }
  513. else {
  514. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  515. continue;
  516. }
  517. #ifdef SUPPORT_MULTI_INST_INTR
  518. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n\n", product_code, intr_reason);
  519. #else
  520. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n", product_code, dev->interrupt_reason);
  521. #endif
  522. }
  523. if (dev->async_queue)
  524. kill_fasync(&dev->async_queue, SIGIO, POLL_IN); /* notify the interrupt to user space */
  525. #ifdef SUPPORT_MULTI_INST_INTR
  526. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  527. s_interrupt_flag[intr_inst_index]= 1;
  528. wake_up_interruptible(&s_interrupt_wait_q[intr_inst_index]);
  529. }
  530. #else
  531. s_interrupt_flag = 1;
  532. wake_up_interruptible(&s_interrupt_wait_q);
  533. #endif
  534. DPRINTK("[VPUDRV][-]%s\n", __func__);
  535. return IRQ_HANDLED;
  536. }
  537. static int vpu_open(struct inode *inode, struct file *filp)
  538. {
  539. DPRINTK("[VPUDRV][+] %s\n", __func__);
  540. spin_lock(&s_vpu_lock);
  541. s_vpu_drv_context.open_count++;
  542. filp->private_data = (void *)(&s_vpu_drv_context);
  543. spin_unlock(&s_vpu_lock);
  544. DPRINTK("[VPUDRV][-] %s\n", __func__);
  545. return 0;
  546. }
  547. /*static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, u_long arg) // for kernel 2.6.9 of C&M*/
  548. static long vpu_ioctl(struct file *filp, u_int cmd, u_long arg)
  549. {
  550. int ret = 0;
  551. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  552. switch (cmd) {
  553. case VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY:
  554. {
  555. vpudrv_buffer_pool_t *vbp;
  556. DPRINTK("[VPUDRV][+]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  557. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  558. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  559. if (!vbp) {
  560. up(&s_vpu_sem);
  561. return -ENOMEM;
  562. }
  563. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  564. if (ret) {
  565. kfree(vbp);
  566. up(&s_vpu_sem);
  567. return -EFAULT;
  568. }
  569. ret = vpu_alloc_dma_buffer(&(vbp->vb));
  570. if (ret == -1) {
  571. ret = -ENOMEM;
  572. kfree(vbp);
  573. up(&s_vpu_sem);
  574. break;
  575. }
  576. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  577. if (ret) {
  578. kfree(vbp);
  579. ret = -EFAULT;
  580. up(&s_vpu_sem);
  581. break;
  582. }
  583. vbp->filp = filp;
  584. spin_lock(&s_vpu_lock);
  585. list_add(&vbp->list, &s_vbp_head);
  586. spin_unlock(&s_vpu_lock);
  587. up(&s_vpu_sem);
  588. }
  589. DPRINTK("[VPUDRV][-]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  590. }
  591. break;
  592. case VDI_IOCTL_FREE_PHYSICALMEMORY:
  593. {
  594. vpudrv_buffer_pool_t *vbp, *n;
  595. vpudrv_buffer_t vb;
  596. DPRINTK("[VPUDRV][+]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  597. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  598. ret = copy_from_user(&vb, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  599. if (ret) {
  600. up(&s_vpu_sem);
  601. return -EACCES;
  602. }
  603. if (vb.base)
  604. vpu_free_dma_buffer(&vb);
  605. spin_lock(&s_vpu_lock);
  606. list_for_each_entry_safe(vbp, n, &s_vbp_head, list)
  607. {
  608. if (vbp->vb.base == vb.base) {
  609. list_del(&vbp->list);
  610. kfree(vbp);
  611. break;
  612. }
  613. }
  614. spin_unlock(&s_vpu_lock);
  615. up(&s_vpu_sem);
  616. }
  617. DPRINTK("[VPUDRV][-]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  618. }
  619. break;
  620. case VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO:
  621. {
  622. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  623. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  624. if (s_video_memory.base != 0) {
  625. ret = copy_to_user((void __user *)arg, &s_video_memory, sizeof(vpudrv_buffer_t));
  626. if (ret != 0)
  627. ret = -EFAULT;
  628. } else {
  629. ret = -EFAULT;
  630. }
  631. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  632. #endif
  633. }
  634. break;
  635. case VDI_IOCTL_WAIT_INTERRUPT:
  636. {
  637. vpudrv_intr_info_t info;
  638. #ifdef SUPPORT_MULTI_INST_INTR
  639. u32 intr_inst_index;
  640. u32 intr_reason_in_q;
  641. u32 interrupt_flag_in_q;
  642. #endif
  643. DPRINTK("[VPUDRV][+]VDI_IOCTL_WAIT_INTERRUPT4\n");
  644. ret = copy_from_user(&info, (vpudrv_intr_info_t *)arg, sizeof(vpudrv_intr_info_t));
  645. if (ret != 0)
  646. {
  647. return -EFAULT;
  648. }
  649. #ifdef SUPPORT_MULTI_INST_INTR
  650. intr_inst_index = info.intr_inst_index;
  651. intr_reason_in_q = 0;
  652. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  653. if (interrupt_flag_in_q > 0)
  654. {
  655. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  656. DPRINTK("[VPUDRV] Interrupt Remain : intr_inst_index=%d, intr_reason_in_q=0x%x, interrupt_flag_in_q=%d\n", intr_inst_index, intr_reason_in_q, interrupt_flag_in_q);
  657. goto INTERRUPT_REMAIN_IN_QUEUE;
  658. }
  659. #endif
  660. #ifdef SUPPORT_MULTI_INST_INTR
  661. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  662. kt = ktime_set(0, info.timeout*1000*1000);
  663. ret = wait_event_interruptible_hrtimeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, kt);
  664. #else
  665. ret = wait_event_interruptible_timeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, msecs_to_jiffies(info.timeout));
  666. #endif
  667. #else
  668. ret = wait_event_interruptible_timeout(s_interrupt_wait_q, s_interrupt_flag != 0, msecs_to_jiffies(info.timeout));
  669. #endif
  670. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  671. if (ret == -ETIME) {
  672. //DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT timeout = %d \n", info.timeout);
  673. break;
  674. }
  675. #endif
  676. if (!ret) {
  677. ret = -ETIME;
  678. break;
  679. }
  680. if (signal_pending(current)) {
  681. ret = -ERESTARTSYS;
  682. break;
  683. }
  684. #ifdef SUPPORT_MULTI_INST_INTR
  685. intr_reason_in_q = 0;
  686. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  687. if (interrupt_flag_in_q > 0) {
  688. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  689. }
  690. else {
  691. dev->interrupt_reason[intr_inst_index] = 0;
  692. }
  693. #endif
  694. #ifdef SUPPORT_MULTI_INST_INTR
  695. DPRINTK("[VPUDRV] inst_index(%d), s_interrupt_flag(%d), reason(0x%08lx)\n", intr_inst_index, s_interrupt_flag[intr_inst_index], dev->interrupt_reason[intr_inst_index]);
  696. #else
  697. DPRINTK("[VPUDRV] s_interrupt_flag(%d), reason(0x%08lx)\n", s_interrupt_flag, dev->interrupt_reason);
  698. #endif
  699. #ifdef SUPPORT_MULTI_INST_INTR
  700. INTERRUPT_REMAIN_IN_QUEUE:
  701. info.intr_reason = dev->interrupt_reason[intr_inst_index];
  702. s_interrupt_flag[intr_inst_index] = 0;
  703. dev->interrupt_reason[intr_inst_index] = 0;
  704. #else
  705. info.intr_reason = dev->interrupt_reason;
  706. s_interrupt_flag = 0;
  707. dev->interrupt_reason = 0;
  708. #endif
  709. #ifdef VPU_IRQ_CONTROL
  710. enable_irq(s_vpu_irq);
  711. #endif
  712. ret = copy_to_user((void __user *)arg, &info, sizeof(vpudrv_intr_info_t));
  713. DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT\n");
  714. if (ret != 0)
  715. {
  716. return -EFAULT;
  717. }
  718. }
  719. break;
  720. case VDI_IOCTL_SET_CLOCK_GATE:
  721. {
  722. // u32 clkgate;
  723. // DPRINTK("[VPUDRV][+]VDI_IOCTL_SET_CLOCK_GATE\n");
  724. // if (get_user(clkgate, (u32 __user *) arg))
  725. // return -EFAULT;
  726. // #ifdef VPU_SUPPORT_CLOCK_CONTROL
  727. // if (clkgate)
  728. // //vpu_clk_enable(s_vpu_clk);
  729. // else
  730. // //vpu_clk_disable(s_vpu_clk);
  731. // #endif
  732. // DPRINTK("[VPUDRV][-]VDI_IOCTL_SET_CLOCK_GATE\n");
  733. }
  734. break;
  735. case VDI_IOCTL_GET_INSTANCE_POOL:
  736. {
  737. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_POOL\n");
  738. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  739. if (s_instance_pool.base != 0) {
  740. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  741. if (ret != 0)
  742. ret = -EFAULT;
  743. } else {
  744. ret = copy_from_user(&s_instance_pool, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  745. if (ret == 0) {
  746. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  747. s_instance_pool.size = PAGE_ALIGN(s_instance_pool.size);
  748. s_instance_pool.base = (unsigned long)vmalloc(s_instance_pool.size);
  749. s_instance_pool.phys_addr = s_instance_pool.base;
  750. if (s_instance_pool.base != 0)
  751. #else
  752. if (vpu_alloc_dma_buffer(&s_instance_pool) != -1)
  753. #endif
  754. {
  755. memset((void *)s_instance_pool.base, 0x0, s_instance_pool.size); /*clearing memory*/
  756. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  757. if (ret == 0) {
  758. /* success to get memory for instance pool */
  759. up(&s_vpu_sem);
  760. break;
  761. }
  762. }
  763. }
  764. ret = -EFAULT;
  765. }
  766. up(&s_vpu_sem);
  767. }
  768. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_INSTANCE_POOL\n");
  769. }
  770. break;
  771. case VDI_IOCTL_GET_COMMON_MEMORY:
  772. {
  773. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_COMMON_MEMORY\n");
  774. if (s_common_memory.base != 0) {
  775. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  776. if (ret != 0)
  777. ret = -EFAULT;
  778. } else {
  779. ret = copy_from_user(&s_common_memory, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  780. if (ret == 0) {
  781. if (vpu_alloc_dma_buffer(&s_common_memory) != -1) {
  782. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  783. if (ret == 0) {
  784. /* success to get memory for common memory */
  785. break;
  786. }
  787. }
  788. }
  789. ret = -EFAULT;
  790. }
  791. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_COMMON_MEMORY\n");
  792. }
  793. break;
  794. case VDI_IOCTL_OPEN_INSTANCE:
  795. {
  796. vpudrv_inst_info_t inst_info;
  797. vpudrv_instanace_list_t *vil, *n;
  798. vil = kzalloc(sizeof(*vil), GFP_KERNEL);
  799. if (!vil)
  800. return -ENOMEM;
  801. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  802. return -EFAULT;
  803. vil->inst_idx = inst_info.inst_idx;
  804. vil->core_idx = inst_info.core_idx;
  805. vil->filp = filp;
  806. spin_lock(&s_vpu_lock);
  807. list_add(&vil->list, &s_inst_list_head);
  808. inst_info.inst_open_count = 0; /* counting the current open instance number */
  809. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  810. {
  811. if (vil->core_idx == inst_info.core_idx)
  812. inst_info.inst_open_count++;
  813. }
  814. #ifdef SUPPORT_MULTI_INST_INTR
  815. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  816. #endif
  817. spin_unlock(&s_vpu_lock);
  818. s_vpu_open_ref_count++; /* flag just for that vpu is in opened or closed */
  819. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t))) {
  820. kfree(vil);
  821. return -EFAULT;
  822. }
  823. DPRINTK("[VPUDRV] VDI_IOCTL_OPEN_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  824. }
  825. break;
  826. case VDI_IOCTL_CLOSE_INSTANCE:
  827. {
  828. vpudrv_inst_info_t inst_info;
  829. vpudrv_instanace_list_t *vil, *n;
  830. u32 found = 0;
  831. DPRINTK("[VPUDRV][+]VDI_IOCTL_CLOSE_INSTANCE\n");
  832. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  833. return -EFAULT;
  834. spin_lock(&s_vpu_lock);
  835. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  836. {
  837. if (vil->inst_idx == inst_info.inst_idx && vil->core_idx == inst_info.core_idx) {
  838. list_del(&vil->list);
  839. kfree(vil);
  840. found = 1;
  841. break;
  842. }
  843. }
  844. if (0 == found) {
  845. spin_unlock(&s_vpu_lock);
  846. return -EINVAL;
  847. }
  848. inst_info.inst_open_count = 0; /* counting the current open instance number */
  849. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  850. {
  851. if (vil->core_idx == inst_info.core_idx)
  852. inst_info.inst_open_count++;
  853. }
  854. #ifdef SUPPORT_MULTI_INST_INTR
  855. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  856. #endif
  857. spin_unlock(&s_vpu_lock);
  858. s_vpu_open_ref_count--; /* flag just for that vpu is in opened or closed */
  859. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t)))
  860. return -EFAULT;
  861. DPRINTK("[VPUDRV] VDI_IOCTL_CLOSE_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  862. }
  863. break;
  864. case VDI_IOCTL_GET_INSTANCE_NUM:
  865. {
  866. vpudrv_inst_info_t inst_info;
  867. vpudrv_instanace_list_t *vil, *n;
  868. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_NUM\n");
  869. ret = copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t));
  870. if (ret != 0)
  871. break;
  872. spin_lock(&s_vpu_lock);
  873. inst_info.inst_open_count = 0;
  874. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  875. {
  876. if (vil->core_idx == inst_info.core_idx)
  877. inst_info.inst_open_count++;
  878. }
  879. spin_unlock(&s_vpu_lock);
  880. ret = copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t));
  881. DPRINTK("[VPUDRV] VDI_IOCTL_GET_INSTANCE_NUM core_idx=%d, inst_idx=%d, open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, inst_info.inst_open_count);
  882. }
  883. break;
  884. case VDI_IOCTL_RESET:
  885. {
  886. //vpu_hw_reset();
  887. }
  888. break;
  889. case VDI_IOCTL_GET_REGISTER_INFO:
  890. {
  891. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_REGISTER_INFO\n");
  892. ret = copy_to_user((void __user *)arg, &s_vpu_register, sizeof(vpudrv_buffer_t));
  893. if (ret != 0)
  894. ret = -EFAULT;
  895. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_REGISTER_INFO s_vpu_register.phys_addr==0x%lx, s_vpu_register.virt_addr=0x%lx, s_vpu_register.size=%d\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr, s_vpu_register.size);
  896. }
  897. break;
  898. case VDI_IOCTL_FLUSH_DCACHE:
  899. {
  900. vpudrv_flush_cache_t cache_info;
  901. //DPRINTK("[JPUDRV][+]VDI_IOCTL_FLUSH_DCACHE\n");
  902. ret = copy_from_user(&cache_info, (vpudrv_flush_cache_t *)arg, sizeof(vpudrv_flush_cache_t));
  903. if (ret != 0)
  904. ret = -EFAULT;
  905. if(cache_info.flag)
  906. starfive_flush_dcache(cache_info.start,cache_info.size);
  907. //DPRINTK("[JPUDRV][-]VDI_IOCTL_FLUSH_DCACHE\n");
  908. break;
  909. }
  910. default:
  911. {
  912. printk(KERN_ERR "[VPUDRV] No such IOCTL, cmd is %d\n", cmd);
  913. }
  914. break;
  915. }
  916. return ret;
  917. }
  918. static ssize_t vpu_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos)
  919. {
  920. return -1;
  921. }
  922. static ssize_t vpu_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos)
  923. {
  924. /* DPRINTK("[VPUDRV] vpu_write len=%d\n", (int)len); */
  925. if (!buf) {
  926. printk(KERN_ERR "[VPUDRV] vpu_write buf = NULL error \n");
  927. return -EFAULT;
  928. }
  929. if (len == sizeof(vpu_bit_firmware_info_t)) {
  930. vpu_bit_firmware_info_t *bit_firmware_info;
  931. bit_firmware_info = kmalloc(sizeof(vpu_bit_firmware_info_t), GFP_KERNEL);
  932. if (!bit_firmware_info) {
  933. printk(KERN_ERR "[VPUDRV] vpu_write bit_firmware_info allocation error \n");
  934. return -EFAULT;
  935. }
  936. if (copy_from_user(bit_firmware_info, buf, len)) {
  937. printk(KERN_ERR "[VPUDRV] vpu_write copy_from_user error for bit_firmware_info\n");
  938. return -EFAULT;
  939. }
  940. if (bit_firmware_info->size == sizeof(vpu_bit_firmware_info_t)) {
  941. DPRINTK("[VPUDRV] vpu_write set bit_firmware_info coreIdx=0x%x, reg_base_offset=0x%x size=0x%x, bit_code[0]=0x%x\n",
  942. bit_firmware_info->core_idx, (int)bit_firmware_info->reg_base_offset, bit_firmware_info->size, bit_firmware_info->bit_code[0]);
  943. if (bit_firmware_info->core_idx > MAX_NUM_VPU_CORE) {
  944. printk(KERN_ERR "[VPUDRV] vpu_write coreIdx[%d] is exceeded than MAX_NUM_VPU_CORE[%d]\n", bit_firmware_info->core_idx, MAX_NUM_VPU_CORE);
  945. return -ENODEV;
  946. }
  947. memcpy((void *)&s_bit_firmware_info[bit_firmware_info->core_idx], bit_firmware_info, sizeof(vpu_bit_firmware_info_t));
  948. kfree(bit_firmware_info);
  949. return len;
  950. }
  951. kfree(bit_firmware_info);
  952. }
  953. return -1;
  954. }
  955. static int vpu_release(struct inode *inode, struct file *filp)
  956. {
  957. int ret = 0;
  958. u32 open_count;
  959. #ifdef SUPPORT_MULTI_INST_INTR
  960. int i;
  961. #endif
  962. DPRINTK("[VPUDRV] vpu_release\n");
  963. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  964. /* found and free the not handled buffer by user applications */
  965. vpu_free_buffers(filp);
  966. /* found and free the not closed instance by user applications */
  967. vpu_free_instances(filp);
  968. spin_lock(&s_vpu_lock);
  969. s_vpu_drv_context.open_count--;
  970. open_count = s_vpu_drv_context.open_count;
  971. spin_unlock(&s_vpu_lock);
  972. if (open_count == 0) {
  973. #ifdef SUPPORT_MULTI_INST_INTR
  974. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  975. kfifo_reset(&s_interrupt_pending_q[i]);
  976. }
  977. #endif
  978. if (s_instance_pool.base) {
  979. DPRINTK("[VPUDRV] free instance pool\n");
  980. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  981. vfree((const void *)s_instance_pool.base);
  982. #else
  983. vpu_free_dma_buffer(&s_instance_pool);
  984. #endif
  985. s_instance_pool.base = 0;
  986. }
  987. }
  988. }
  989. up(&s_vpu_sem);
  990. return 0;
  991. }
  992. static int vpu_fasync(int fd, struct file *filp, int mode)
  993. {
  994. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  995. return fasync_helper(fd, filp, mode, &dev->async_queue);
  996. }
  997. static int vpu_map_to_register(struct file *fp, struct vm_area_struct *vm)
  998. {
  999. unsigned long pfn;
  1000. vm->vm_flags |= VM_IO | VM_RESERVED;
  1001. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1002. pfn = s_vpu_register.phys_addr >> PAGE_SHIFT;
  1003. return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1004. }
  1005. static int vpu_map_to_physical_memory(struct file *fp, struct vm_area_struct *vm)
  1006. {
  1007. vm->vm_flags |= VM_IO | VM_RESERVED;
  1008. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1009. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1010. }
  1011. static int vpu_map_to_instance_pool_memory(struct file *fp, struct vm_area_struct *vm)
  1012. {
  1013. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1014. int ret;
  1015. long length = vm->vm_end - vm->vm_start;
  1016. unsigned long start = vm->vm_start;
  1017. char *vmalloc_area_ptr = (char *)s_instance_pool.base;
  1018. unsigned long pfn;
  1019. vm->vm_flags |= VM_RESERVED;
  1020. /* loop over all pages, map it page individually */
  1021. while (length > 0)
  1022. {
  1023. pfn = vmalloc_to_pfn(vmalloc_area_ptr);
  1024. if ((ret = remap_pfn_range(vm, start, pfn, PAGE_SIZE, PAGE_SHARED)) < 0) {
  1025. return ret;
  1026. }
  1027. start += PAGE_SIZE;
  1028. vmalloc_area_ptr += PAGE_SIZE;
  1029. length -= PAGE_SIZE;
  1030. }
  1031. return 0;
  1032. #else
  1033. vm->vm_flags |= VM_RESERVED;
  1034. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1035. #endif
  1036. }
  1037. /*!
  1038. * @brief memory map interface for vpu file operation
  1039. * @return 0 on success or negative error code on error
  1040. */
  1041. static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
  1042. {
  1043. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1044. if (vm->vm_pgoff == 0)
  1045. return vpu_map_to_instance_pool_memory(fp, vm);
  1046. if (vm->vm_pgoff == (s_vpu_register.phys_addr>>PAGE_SHIFT))
  1047. return vpu_map_to_register(fp, vm);
  1048. return vpu_map_to_physical_memory(fp, vm);
  1049. #else
  1050. if (vm->vm_pgoff) {
  1051. if (vm->vm_pgoff == (s_instance_pool.phys_addr>>PAGE_SHIFT))
  1052. return vpu_map_to_instance_pool_memory(fp, vm);
  1053. return vpu_map_to_physical_memory(fp, vm);
  1054. } else {
  1055. return vpu_map_to_register(fp, vm);
  1056. }
  1057. #endif
  1058. }
  1059. struct file_operations vpu_fops = {
  1060. .owner = THIS_MODULE,
  1061. .open = vpu_open,
  1062. .read = vpu_read,
  1063. .write = vpu_write,
  1064. /*.ioctl = vpu_ioctl, // for kernel 2.6.9 of C&M*/
  1065. .unlocked_ioctl = vpu_ioctl,
  1066. .release = vpu_release,
  1067. .fasync = vpu_fasync,
  1068. .mmap = vpu_mmap,
  1069. };
  1070. static struct resource venc_resource[] = {
  1071. [0] = {
  1072. .start = VPU_REG_BASE_ADDR,
  1073. .end = VPU_REG_BASE_ADDR + VPU_REG_SIZE - 1,
  1074. .flags = IORESOURCE_MEM,
  1075. },
  1076. [1] = {
  1077. .start = VENC_IRQ_ADDR,
  1078. .end = VENC_IRQ_ADDR,
  1079. .flags = IORESOURCE_IRQ,
  1080. },
  1081. };
  1082. static int vpu_probe(struct platform_device *pdev)
  1083. {
  1084. int err = 0;
  1085. struct resource *res = NULL;
  1086. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1087. struct resource res_cma;
  1088. struct device_node *node;
  1089. #endif
  1090. DPRINTK("[VPUDRV] vpu_probe\n");
  1091. if(pdev){
  1092. vpu_dev = &pdev->dev;
  1093. vpu_dev->coherent_dma_mask = 0xffffffff;
  1094. //vpu_dev->dma_ops = NULL;
  1095. dev_info(vpu_dev,"device init.\n");
  1096. }
  1097. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1098. err = platform_device_add_resources(pdev, venc_resource, 2);
  1099. if (err) {
  1100. printk(KERN_ERR "could not add venc resource\n");
  1101. goto ERROR_PROVE_DEVICE;
  1102. }
  1103. #endif
  1104. if (pdev)
  1105. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1106. if (res) {/* if platform driver is implemented */
  1107. s_vpu_register.phys_addr = res->start;
  1108. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(res->start, res->end - res->start);
  1109. s_vpu_register.size = res->end - res->start;
  1110. DPRINTK("[VPUDRV] : vpu base address get from platform driver physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr);
  1111. } else {
  1112. s_vpu_register.phys_addr = VPU_REG_BASE_ADDR;
  1113. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(s_vpu_register.phys_addr, VPU_REG_SIZE);
  1114. s_vpu_register.size = VPU_REG_SIZE;
  1115. DPRINTK("[VPUDRV] : vpu base address get from defined value physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr, s_vpu_register.virt_addr);
  1116. }
  1117. /* get the major number of the character device */
  1118. if ((alloc_chrdev_region(&s_vpu_major, 0, 1, VPU_DEV_NAME)) < 0) {
  1119. err = -EBUSY;
  1120. printk(KERN_ERR "could not allocate major number\n");
  1121. goto ERROR_PROVE_DEVICE;
  1122. }
  1123. printk(KERN_INFO "SUCCESS alloc_chrdev_region\n");
  1124. /* initialize the device structure and register the device with the kernel */
  1125. cdev_init(&s_vpu_cdev, &vpu_fops);
  1126. if ((cdev_add(&s_vpu_cdev, s_vpu_major, 1)) < 0) {
  1127. err = -EBUSY;
  1128. printk(KERN_ERR "could not allocate chrdev\n");
  1129. goto ERROR_PROVE_DEVICE;
  1130. }
  1131. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1132. err = starfive_venc_clk_rst_init(pdev);
  1133. if (err){
  1134. goto ERROR_PROVE_DEVICE;
  1135. }
  1136. #else
  1137. vpu_clk_enable();
  1138. vpu_hw_reset();
  1139. #endif
  1140. #ifdef VPU_SUPPORT_ISR
  1141. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1142. if (pdev)
  1143. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1144. if (res) {/* if platform driver is implemented */
  1145. s_vpu_irq = res->start;
  1146. DPRINTK("[VPUDRV] : vpu irq number get from platform driver irq=0x%x\n", s_vpu_irq);
  1147. } else {
  1148. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1149. }
  1150. #else
  1151. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1152. #endif
  1153. err = request_irq(s_vpu_irq, vpu_irq_handler, 0, pdev->name, (void *)(&s_vpu_drv_context));
  1154. if (err) {
  1155. printk(KERN_ERR "[VPUDRV] : fail to register interrupt handler\n");
  1156. goto ERROR_PROVE_DEVICE;
  1157. }
  1158. #endif
  1159. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1160. printk("start memory-region: of_node:%#lx \n",(unsigned long)vpu_dev->of_node);
  1161. node = of_parse_phandle(vpu_dev->of_node, "memory-region", 0);
  1162. if(node){
  1163. dev_info(vpu_dev, "Get mem form memory-region\n");
  1164. of_address_to_resource(node, 0, &res_cma);
  1165. s_video_memory.size = resource_size(&res_cma);
  1166. s_video_memory.phys_addr = res_cma.start;
  1167. }else{
  1168. dev_info(vpu_dev, "Get mem form memory-region filed. please check the dts file.\n");
  1169. //dev_info(vpu_dev, "Using default cma reserved space..\n");
  1170. //s_video_memory.phys_addr = 0xa3000000;
  1171. //s_video_memory.size = 0x10000000;
  1172. return 0;
  1173. }
  1174. s_video_memory.base = (unsigned long)ioremap_nocache(DRAM_MEM2SYS(s_video_memory.phys_addr), PAGE_ALIGN(s_video_memory.size));
  1175. if (!s_video_memory.base) {
  1176. printk(KERN_ERR "[VPUDRV] : fail to remap video memory physical phys_addr==0x%lx, base==0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base, (int)s_video_memory.size);
  1177. goto ERROR_PROVE_DEVICE;
  1178. }
  1179. if (vmem_init(&s_vmem, s_video_memory.phys_addr, s_video_memory.size) < 0) {
  1180. printk(KERN_ERR "[VPUDRV] : fail to init vmem system\n");
  1181. goto ERROR_PROVE_DEVICE;
  1182. }
  1183. DPRINTK("[VPUDRV] success to probe vpu device with reserved video memory phys_addr==0x%lx, base = =0x%lx\n", s_video_memory.phys_addr, s_video_memory.base);
  1184. #else
  1185. DPRINTK("[VPUDRV] success to probe vpu device with non reserved video memory\n");
  1186. #endif
  1187. return 0;
  1188. ERROR_PROVE_DEVICE:
  1189. if (s_vpu_major)
  1190. unregister_chrdev_region(s_vpu_major, 1);
  1191. if (s_vpu_register.virt_addr)
  1192. iounmap((void *)s_vpu_register.virt_addr);
  1193. return err;
  1194. }
  1195. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1196. static int vpu_remove(struct platform_device *pdev)
  1197. {
  1198. DPRINTK("[VPUDRV] vpu_remove\n");
  1199. if (s_instance_pool.base) {
  1200. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1201. vfree((const void *)s_instance_pool.base);
  1202. #else
  1203. vpu_free_dma_buffer(&s_instance_pool);
  1204. #endif
  1205. s_instance_pool.base = 0;
  1206. }
  1207. if (s_common_memory.base) {
  1208. vpu_free_dma_buffer(&s_common_memory);
  1209. s_common_memory.base = 0;
  1210. }
  1211. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1212. if (s_video_memory.base) {
  1213. iounmap((void *)s_video_memory.base);
  1214. s_video_memory.base = 0;
  1215. vmem_exit(&s_vmem);
  1216. }
  1217. #endif
  1218. if (s_vpu_major > 0) {
  1219. cdev_del(&s_vpu_cdev);
  1220. unregister_chrdev_region(s_vpu_major, 1);
  1221. s_vpu_major = 0;
  1222. }
  1223. #ifdef VPU_SUPPORT_ISR
  1224. if (s_vpu_irq)
  1225. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1226. #endif
  1227. if (s_vpu_register.virt_addr)
  1228. iounmap((void *)s_vpu_register.virt_addr);
  1229. return 0;
  1230. }
  1231. #endif /*VPU_SUPPORT_PLATFORM_DRIVER_REGISTER*/
  1232. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  1233. #define W5_MAX_CODE_BUF_SIZE (512*1024)
  1234. #define W5_CMD_INIT_VPU (0x0001)
  1235. #define W5_CMD_SLEEP_VPU (0x0004)
  1236. #define W5_CMD_WAKEUP_VPU (0x0002)
  1237. static void Wave5BitIssueCommand(int core, u32 cmd)
  1238. {
  1239. WriteVpuRegister(W5_VPU_BUSY_STATUS, 1);
  1240. WriteVpuRegister(W5_COMMAND, cmd);
  1241. WriteVpuRegister(W5_VPU_HOST_INT_REQ, 1);
  1242. return;
  1243. }
  1244. static int vpu_suspend(struct platform_device *pdev, pm_message_t state)
  1245. {
  1246. int i;
  1247. int core;
  1248. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1249. int product_code;
  1250. DPRINTK("[VPUDRV] vpu_suspend\n");
  1251. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1252. starfive_venc_clk_enable(&pdev->dev);
  1253. #else
  1254. vpu_clk_enable();
  1255. #endif
  1256. if (s_vpu_open_ref_count > 0) {
  1257. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1258. if (s_bit_firmware_info[core].size == 0)
  1259. continue;
  1260. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1261. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1262. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1263. if (time_after(jiffies, timeout)) {
  1264. DPRINTK("SLEEP_VPU BUSY timeout");
  1265. goto DONE_SUSPEND;
  1266. }
  1267. }
  1268. Wave5BitIssueCommand(core, W5_CMD_SLEEP_VPU);
  1269. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1270. if (time_after(jiffies, timeout)) {
  1271. DPRINTK("SLEEP_VPU BUSY timeout");
  1272. goto DONE_SUSPEND;
  1273. }
  1274. }
  1275. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1276. DPRINTK("SLEEP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1277. goto DONE_SUSPEND;
  1278. }
  1279. }
  1280. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1281. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1282. if (time_after(jiffies, timeout))
  1283. goto DONE_SUSPEND;
  1284. }
  1285. for (i = 0; i < 64; i++)
  1286. s_vpu_reg_store[core][i] = ReadVpuRegister(BIT_BASE+(0x100+(i * 4)));
  1287. }
  1288. else {
  1289. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1290. goto DONE_SUSPEND;
  1291. }
  1292. }
  1293. }
  1294. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1295. starfive_venc_clk_disable(&pdev->dev);
  1296. #else
  1297. vpu_clk_disable();
  1298. #endif
  1299. return 0;
  1300. DONE_SUSPEND:
  1301. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1302. starfive_venc_clk_disable(&pdev->dev);
  1303. #else
  1304. vpu_clk_disable();
  1305. #endif
  1306. return -EAGAIN;
  1307. }
  1308. static int vpu_resume(struct platform_device *pdev)
  1309. {
  1310. int i;
  1311. int core;
  1312. u32 val;
  1313. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1314. int product_code;
  1315. unsigned long code_base;
  1316. u32 code_size;
  1317. u32 remap_size;
  1318. int regVal;
  1319. u32 hwOption = 0;
  1320. DPRINTK("[VPUDRV] vpu_resume\n");
  1321. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1322. starfive_venc_clk_enable(&pdev->dev);
  1323. #else
  1324. vpu_clk_enable();
  1325. #endif
  1326. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1327. if (s_bit_firmware_info[core].size == 0) {
  1328. continue;
  1329. }
  1330. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1331. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1332. code_base = s_common_memory.phys_addr;
  1333. /* ALIGN TO 4KB */
  1334. code_size = (W5_MAX_CODE_BUF_SIZE&~0xfff);
  1335. if (code_size < s_bit_firmware_info[core].size*2) {
  1336. goto DONE_WAKEUP;
  1337. }
  1338. regVal = 0;
  1339. WriteVpuRegister(W5_PO_CONF, regVal);
  1340. /* Reset All blocks */
  1341. regVal = 0x7ffffff;
  1342. WriteVpuRegister(W5_VPU_RESET_REQ, regVal); /*Reset All blocks*/
  1343. /* Waiting reset done */
  1344. while (ReadVpuRegister(W5_VPU_RESET_STATUS)) {
  1345. if (time_after(jiffies, timeout))
  1346. goto DONE_WAKEUP;
  1347. }
  1348. WriteVpuRegister(W5_VPU_RESET_REQ, 0);
  1349. /* remap page size */
  1350. remap_size = (code_size >> 12) & 0x1ff;
  1351. regVal = 0x80000000 | (W5_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remap_size;
  1352. WriteVpuRegister(W5_VPU_REMAP_CTRL, regVal);
  1353. WriteVpuRegister(W5_VPU_REMAP_VADDR,0x00000000); /* DO NOT CHANGE! */
  1354. WriteVpuRegister(W5_VPU_REMAP_PADDR,code_base);
  1355. WriteVpuRegister(W5_ADDR_CODE_BASE, code_base);
  1356. WriteVpuRegister(W5_CODE_SIZE, code_size);
  1357. WriteVpuRegister(W5_CODE_PARAM, 0);
  1358. WriteVpuRegister(W5_INIT_VPU_TIME_OUT_CNT, timeout);
  1359. WriteVpuRegister(W5_HW_OPTION, hwOption);
  1360. /* Interrupt */
  1361. if (product_code == WAVE521_CODE || product_code == WAVE521C_CODE ) {
  1362. regVal = (1<<INT_WAVE5_ENC_SET_PARAM);
  1363. regVal |= (1<<INT_WAVE5_ENC_PIC);
  1364. regVal |= (1<<INT_WAVE5_INIT_SEQ);
  1365. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1366. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1367. }
  1368. else {
  1369. // decoder
  1370. regVal = (1<<INT_WAVE5_INIT_SEQ);
  1371. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1372. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1373. }
  1374. WriteVpuRegister(W5_VPU_VINT_ENABLE, regVal);
  1375. Wave5BitIssueCommand(core, W5_CMD_INIT_VPU);
  1376. WriteVpuRegister(W5_VPU_REMAP_CORE_START, 1);
  1377. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1378. if (time_after(jiffies, timeout))
  1379. goto DONE_WAKEUP;
  1380. }
  1381. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1382. DPRINTK("WAKEUP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1383. goto DONE_WAKEUP;
  1384. }
  1385. }
  1386. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1387. WriteVpuRegister(BIT_CODE_RUN, 0);
  1388. /*---- LOAD BOOT CODE*/
  1389. for (i = 0; i < 512; i++) {
  1390. val = s_bit_firmware_info[core].bit_code[i];
  1391. WriteVpuRegister(BIT_CODE_DOWN, ((i << 16) | val));
  1392. }
  1393. for (i = 0 ; i < 64 ; i++)
  1394. WriteVpuRegister(BIT_BASE+(0x100+(i * 4)), s_vpu_reg_store[core][i]);
  1395. WriteVpuRegister(BIT_BUSY_FLAG, 1);
  1396. WriteVpuRegister(BIT_CODE_RESET, 1);
  1397. WriteVpuRegister(BIT_CODE_RUN, 1);
  1398. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1399. if (time_after(jiffies, timeout))
  1400. goto DONE_WAKEUP;
  1401. }
  1402. }
  1403. else {
  1404. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1405. goto DONE_WAKEUP;
  1406. }
  1407. }
  1408. if (s_vpu_open_ref_count == 0){
  1409. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1410. starfive_venc_clk_disable(&pdev->dev);
  1411. #else
  1412. vpu_clk_disable();
  1413. #endif
  1414. }
  1415. DONE_WAKEUP:
  1416. if (s_vpu_open_ref_count > 0){
  1417. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1418. starfive_venc_clk_enable(&pdev->dev);
  1419. #else
  1420. vpu_clk_enable();
  1421. #endif
  1422. }
  1423. return 0;
  1424. }
  1425. #else
  1426. #define vpu_suspend NULL
  1427. #define vpu_resume NULL
  1428. #endif /* !CONFIG_PM */
  1429. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1430. static const struct of_device_id vpu_of_id_table[] = {
  1431. { .compatible = "cm,cm521-vpu" },
  1432. {}
  1433. };
  1434. static struct platform_driver vpu_driver = {
  1435. .driver = {
  1436. .name = VPU_PLATFORM_DEVICE_NAME,
  1437. .of_match_table = of_match_ptr(vpu_of_id_table),
  1438. },
  1439. .probe = vpu_probe,
  1440. .remove = vpu_remove,
  1441. .suspend = vpu_suspend,
  1442. .resume = vpu_resume,
  1443. };
  1444. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1445. static int __init vpu_init(void)
  1446. {
  1447. int res;
  1448. #ifdef SUPPORT_MULTI_INST_INTR
  1449. int i;
  1450. #endif
  1451. DPRINTK("[VPUDRV] begin vpu_init\n");
  1452. #ifdef SUPPORT_MULTI_INST_INTR
  1453. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1454. init_waitqueue_head(&s_interrupt_wait_q[i]);
  1455. }
  1456. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1457. #define MAX_INTERRUPT_QUEUE (16*MAX_NUM_INSTANCE)
  1458. res = kfifo_alloc(&s_interrupt_pending_q[i], MAX_INTERRUPT_QUEUE*sizeof(u32), GFP_KERNEL);
  1459. if (res) {
  1460. DPRINTK("[VPUDRV] kfifo_alloc failed 0x%x\n", res);
  1461. }
  1462. }
  1463. #else
  1464. init_waitqueue_head(&s_interrupt_wait_q);
  1465. #endif
  1466. s_common_memory.base = 0;
  1467. s_instance_pool.base = 0;
  1468. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1469. res = platform_driver_register(&vpu_driver);
  1470. #else
  1471. res = vpu_probe(NULL);
  1472. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1473. DPRINTK("[VPUDRV] end vpu_init result=0x%x\n", res);
  1474. return res;
  1475. }
  1476. static void __exit vpu_exit(void)
  1477. {
  1478. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1479. starfive_venc_clk_disable(vpu_dev);
  1480. starfive_venc_rst_assert(vpu_dev);
  1481. #else
  1482. vpu_clk_disable();
  1483. #endif
  1484. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1485. DPRINTK("[VPUDRV] vpu_exit\n");
  1486. platform_driver_unregister(&vpu_driver);
  1487. #else /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1488. if (s_instance_pool.base) {
  1489. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1490. vfree((const void *)s_instance_pool.base);
  1491. #else
  1492. vpu_free_dma_buffer(&s_instance_pool);
  1493. #endif
  1494. s_instance_pool.base = 0;
  1495. }
  1496. if (s_common_memory.base) {
  1497. vpu_free_dma_buffer(&s_common_memory);
  1498. s_common_memory.base = 0;
  1499. }
  1500. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1501. if (s_video_memory.base) {
  1502. iounmap((void *)s_video_memory.base);
  1503. s_video_memory.base = 0;
  1504. vmem_exit(&s_vmem);
  1505. }
  1506. #endif
  1507. if (s_vpu_major > 0) {
  1508. cdev_del(&s_vpu_cdev);
  1509. unregister_chrdev_region(s_vpu_major, 1);
  1510. s_vpu_major = 0;
  1511. }
  1512. #ifdef VPU_SUPPORT_ISR
  1513. if (s_vpu_irq)
  1514. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1515. #endif
  1516. #ifdef SUPPORT_MULTI_INST_INTR
  1517. {
  1518. int i;
  1519. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1520. kfifo_free(&s_interrupt_pending_q[i]);
  1521. }
  1522. }
  1523. #endif
  1524. if (s_vpu_register.virt_addr) {
  1525. iounmap((void *)s_vpu_register.virt_addr);
  1526. s_vpu_register.virt_addr = 0x00;
  1527. }
  1528. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1529. return;
  1530. }
  1531. MODULE_AUTHOR("A customer using C&M VPU, Inc.");
  1532. MODULE_DESCRIPTION("VPU linux driver");
  1533. MODULE_LICENSE("GPL");
  1534. module_init(vpu_init);
  1535. module_exit(vpu_exit);
  1536. static void _set_reset(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg,int ibit)
  1537. {
  1538. unsigned int read_value;
  1539. read_value = vic_readl(p_assert_reg);
  1540. read_value &= ~(0x1<<ibit);
  1541. read_value |= (0x1&0x1)<<ibit;
  1542. vic_writel(read_value,p_assert_reg);
  1543. }
  1544. static void _clr_reset(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg,int ibit)
  1545. {
  1546. unsigned int read_value;
  1547. read_value = vic_readl(p_assert_reg);
  1548. read_value &= ~(0x1<<ibit);
  1549. read_value |= (0x0&0x1)<<ibit;
  1550. vic_writel(read_value,p_assert_reg);
  1551. }
  1552. static void _enable_clk(volatile unsigned long p_reg,int ibit)
  1553. {
  1554. unsigned int read_value;
  1555. read_value = vic_readl(p_reg);
  1556. read_value &= ~(0x1<<ibit);
  1557. read_value |= (0x1&0x1)<<ibit;
  1558. vic_writel(read_value,p_reg);
  1559. }
  1560. static void _disable_clk(volatile unsigned long p_reg,int ibit)
  1561. {
  1562. unsigned int read_value;
  1563. read_value = vic_readl(p_reg);
  1564. read_value &= ~(0x1<<ibit);
  1565. read_value |= (0x0&0x1)<<ibit;
  1566. vic_writel(read_value,p_reg);
  1567. }
  1568. static void _reset_assert(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg)
  1569. {
  1570. //_set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_BRG_MAIN);
  1571. _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_APB);
  1572. _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_AXI);
  1573. _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_BCLK);
  1574. _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_CCLK);
  1575. }
  1576. static void _reset_clear(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg)
  1577. {
  1578. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_BRG_MAIN);
  1579. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_AXI);
  1580. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_BCLK);
  1581. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_CCLK);
  1582. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_APB);
  1583. }
  1584. static int _reset(void)
  1585. {
  1586. volatile unsigned long p_breg = (unsigned long)ioremap_nocache(rstgen_Software_RESET_BASE_REG_ADDR,0x20);
  1587. if(!p_breg){
  1588. return -1;
  1589. }
  1590. _reset_assert(p_breg+rstgen_Software_RESET_assert0_OFFSET,p_breg+rstgen_Software_RESET_status0_OFFSET);
  1591. mdelay(1);
  1592. _reset_clear(p_breg+rstgen_Software_RESET_assert0_OFFSET,p_breg+rstgen_Software_RESET_status0_OFFSET);
  1593. iounmap((void *)p_breg);
  1594. return 0;
  1595. }
  1596. static int _clk_control(int enable)
  1597. {
  1598. volatile unsigned long p_breg = (unsigned long)ioremap_nocache(clk_BASE_REG_ADDR,0x100);
  1599. if(!p_breg){
  1600. return -1;
  1601. }
  1602. if(enable){
  1603. _enable_clk(p_breg+clk_venc_axi_ctrl_REG_OFFSET,31);
  1604. _enable_clk(p_breg+clk_vencbrg_mainclk_ctrl_REG_OFFSET,31);
  1605. _enable_clk(p_breg+clk_venc_bclk_ctrl_REG_OFFSET,31);
  1606. _enable_clk(p_breg+clk_venc_cclk_ctrl_REG_OFFSET,31);
  1607. _enable_clk(p_breg+clk_venc_apb_ctrl_REG_OFFSET,31);
  1608. }
  1609. else
  1610. {
  1611. _disable_clk(p_breg+clk_venc_axi_ctrl_REG_OFFSET,31);
  1612. _disable_clk(p_breg+clk_vencbrg_mainclk_ctrl_REG_OFFSET,31);
  1613. _disable_clk(p_breg+clk_venc_bclk_ctrl_REG_OFFSET,31);
  1614. _disable_clk(p_breg+clk_venc_cclk_ctrl_REG_OFFSET,31);
  1615. _disable_clk(p_breg+clk_venc_apb_ctrl_REG_OFFSET,31);
  1616. }
  1617. iounmap((void *)p_breg);
  1618. return 0;
  1619. }
  1620. int vpu_hw_reset(void)
  1621. {
  1622. _reset();
  1623. DPRINTK("[VPUDRV] request vpu reset from application. \n");
  1624. return 0;
  1625. }
  1626. int vpu_clk_enable(void)
  1627. {
  1628. _clk_control(1);
  1629. return 0;
  1630. }
  1631. void vpu_clk_disable(void)
  1632. {
  1633. _clk_control(0);
  1634. }