coda9.c 105 KB

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  1. /*
  2. * Copyright (c) 2019, Chips&Media
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions are met:
  7. *
  8. * 1. Redistributions of source code must retain the above copyright notice, this
  9. * list of conditions and the following disclaimer.
  10. * 2. Redistributions in binary form must reproduce the above copyright notice,
  11. * this list of conditions and the following disclaimer in the documentation
  12. * and/or other materials provided with the distribution.
  13. *
  14. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  15. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  16. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  17. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
  18. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  19. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  20. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  21. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  23. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24. */
  25. #include "coda9_vpuconfig.h"
  26. #include "product.h"
  27. #include "coda9_regdefine.h"
  28. #include "misc/debug.h"
  29. static void LoadBitCode(Uint32 coreIdx, PhysicalAddress codeBase, const Uint16 *codeWord, int codeSize)
  30. {
  31. int i;
  32. BYTE code[8];
  33. for (i=0; i<codeSize; i+=4) {
  34. // 2byte little endian variable to 1byte big endian buffer
  35. code[0] = (BYTE)(codeWord[i+0]>>8);
  36. code[1] = (BYTE)codeWord[i+0];
  37. code[2] = (BYTE)(codeWord[i+1]>>8);
  38. code[3] = (BYTE)codeWord[i+1];
  39. code[4] = (BYTE)(codeWord[i+2]>>8);
  40. code[5] = (BYTE)codeWord[i+2];
  41. code[6] = (BYTE)(codeWord[i+3]>>8);
  42. code[7] = (BYTE)codeWord[i+3];
  43. VpuWriteMem(coreIdx, codeBase+i*2, (BYTE *)code, 8, VDI_BIG_ENDIAN);
  44. }
  45. vdi_set_bit_firmware_to_pm(coreIdx, codeWord);
  46. }
  47. static RetCode BitLoadFirmware(Uint32 coreIdx, PhysicalAddress codeBase, const Uint16 *codeWord, int codeSize)
  48. {
  49. int i;
  50. Uint32 data;
  51. LoadBitCode(coreIdx, codeBase, codeWord, codeSize);
  52. VpuWriteReg(coreIdx, BIT_INT_ENABLE, 0);
  53. VpuWriteReg(coreIdx, BIT_CODE_RUN, 0);
  54. for (i=0; i<2048; ++i) {
  55. data = codeWord[i];
  56. VpuWriteReg(coreIdx, BIT_CODE_DOWN, (i << 16) | data);
  57. }
  58. return RETCODE_SUCCESS;
  59. }
  60. static void SetEncFrameMemInfo(CodecInst* pCodecInst)
  61. {
  62. Uint32 val;
  63. EncInfo* pEncInfo = &pCodecInst->CodecInfo->encInfo;
  64. switch (pCodecInst->productId) {
  65. case PRODUCT_ID_960:
  66. val = 0;
  67. if (pEncInfo->mapType) {
  68. if (pEncInfo->mapType == TILED_FRAME_MB_RASTER_MAP || pEncInfo->mapType == TILED_FIELD_MB_RASTER_MAP)
  69. val |= (pEncInfo->linear2TiledEnable<<11)|(0x03<<9)|(FORMAT_420<<6);
  70. else
  71. val |= (pEncInfo->linear2TiledEnable<<11)|(0x02<<9)|(FORMAT_420<<6);
  72. }
  73. val |= ((pEncInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  74. #if defined(SUPPORT_NV21) || defined(SUPPORT_ENC_NV21)
  75. val |= (pEncInfo->openParam.cbcrInterleave&pEncInfo->openParam.nv21) << 3;
  76. #endif
  77. val |= (pEncInfo->openParam.bwbEnable<<12);
  78. val |= pEncInfo->openParam.frameEndian;
  79. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  80. break;
  81. }
  82. return;
  83. }
  84. void Coda9BitIssueCommand(Uint32 coreIdx, CodecInst *inst, int cmd)
  85. {
  86. int instIdx = 0;
  87. int cdcMode = 0;
  88. int auxMode = 0;
  89. if (inst != NULL) // command is specific to instance
  90. {
  91. instIdx = inst->instIndex;
  92. cdcMode = inst->codecMode;
  93. auxMode = inst->codecModeAux;
  94. }
  95. if (inst) {
  96. if (inst->codecMode < AVC_ENC) {
  97. VpuWriteReg(coreIdx, BIT_WORK_BUF_ADDR, inst->CodecInfo->decInfo.vbWork.phys_addr);
  98. }
  99. else {
  100. VpuWriteReg(coreIdx, BIT_WORK_BUF_ADDR, inst->CodecInfo->encInfo.vbWork.phys_addr);
  101. }
  102. }
  103. VpuWriteReg(coreIdx, BIT_BUSY_FLAG, 1);
  104. VpuWriteReg(coreIdx, BIT_RUN_INDEX, instIdx);
  105. VpuWriteReg(coreIdx, BIT_RUN_COD_STD, cdcMode);
  106. VpuWriteReg(coreIdx, BIT_RUN_AUX_STD, auxMode);
  107. if (inst && inst->loggingEnable)
  108. vdi_log(coreIdx, cmd, 1);
  109. VpuWriteReg(coreIdx, BIT_RUN_COMMAND, cmd);
  110. }
  111. static void SetupCoda9Properties(Uint32 coreIdx, Uint32 productId)
  112. {
  113. VpuAttr* pAttr = &g_VpuCoreAttributes[coreIdx];
  114. Int32 val;
  115. char* pstr;
  116. /* Setup Attributes */
  117. pAttr = &g_VpuCoreAttributes[coreIdx];
  118. // Hardware version information
  119. val = VpuReadReg(coreIdx, VPU_PRODUCT_CODE_REGISTER);
  120. //val = 0x5110;
  121. if ((val&0xff00) == 0x3200) val = 0x3200;
  122. val = VpuReadReg(coreIdx, DBG_CONFIG_REPORT_0);
  123. pstr = (char*)&val;
  124. pAttr->productName[0] = pstr[3];
  125. pAttr->productName[1] = pstr[2];
  126. pAttr->productName[2] = pstr[1];
  127. pAttr->productName[3] = pstr[0];
  128. pAttr->productName[4] = 0;
  129. pAttr->supportDecoders = (1<<STD_AVC) |
  130. (1<<STD_VC1) |
  131. (1<<STD_MPEG2) |
  132. (1<<STD_MPEG4) |
  133. (1<<STD_H263) |
  134. (1<<STD_AVS) |
  135. (1<<STD_DIV3) |
  136. (1<<STD_RV) |
  137. (1<<STD_THO) |
  138. (1<<STD_VP8);
  139. /* Encoder */
  140. pAttr->supportEncoders = (1<<STD_AVC) | (1<<STD_MPEG4) | (1<<STD_H263);
  141. /* WTL */
  142. if (productId == PRODUCT_ID_960 || productId == PRODUCT_ID_980) {
  143. pAttr->supportWTL = 1;
  144. }
  145. /* Tiled2Linear */
  146. pAttr->supportTiled2Linear = 1;
  147. /* Maptypes */
  148. pAttr->supportMapTypes = (1<<LINEAR_FRAME_MAP) |
  149. (1<<TILED_FRAME_V_MAP) |
  150. (1<<TILED_FRAME_H_MAP) |
  151. (1<<TILED_FIELD_V_MAP) |
  152. (1<<TILED_MIXED_V_MAP) |
  153. (1<<TILED_FRAME_MB_RASTER_MAP) |
  154. (1<<TILED_FIELD_MB_RASTER_MAP);
  155. if (productId == PRODUCT_ID_980) {
  156. pAttr->supportMapTypes |= (1<<TILED_FRAME_NO_BANK_MAP) |
  157. (1<<TILED_FIELD_NO_BANK_MAP);
  158. }
  159. /* Linear2Tiled */
  160. if (productId == PRODUCT_ID_960 || productId == PRODUCT_ID_980) {
  161. pAttr->supportLinear2Tiled = 1;
  162. }
  163. /* Framebuffer Cache */
  164. if (productId == PRODUCT_ID_960)
  165. pAttr->framebufferCacheType = FramebufCacheMaverickI;
  166. else if (productId == PRODUCT_ID_980)
  167. pAttr->framebufferCacheType = FramebufCacheMaverickII;
  168. else
  169. pAttr->framebufferCacheType = FramebufCacheNone;
  170. /* AXI 128bit Bus */
  171. pAttr->support128bitBus = FALSE;
  172. pAttr->supportEndianMask = (1<<VDI_LITTLE_ENDIAN) | (1<<VDI_BIG_ENDIAN) | (1<<VDI_32BIT_LITTLE_ENDIAN) | (1<<VDI_32BIT_BIG_ENDIAN);
  173. pAttr->supportBitstreamMode = (1<<BS_MODE_INTERRUPT) | (1<<BS_MODE_PIC_END);
  174. pAttr->bitstreamBufferMargin = VPU_GBU_SIZE;
  175. pAttr->numberOfMemProtectRgns = 6;
  176. }
  177. Uint32 Coda9VpuGetProductId(Uint32 coreIdx)
  178. {
  179. Uint32 productId;
  180. Uint32 val;
  181. val = VpuReadReg(coreIdx, VPU_PRODUCT_CODE_REGISTER);
  182. //val = 0x5110;
  183. if (val == BODA950_CODE)
  184. productId = PRODUCT_ID_950;
  185. else if (val == CODA960_CODE)
  186. productId = PRODUCT_ID_960;
  187. else if (val == CODA980_CODE)
  188. productId = PRODUCT_ID_980;
  189. else
  190. productId = PRODUCT_ID_NONE;
  191. if (productId != PRODUCT_ID_NONE)
  192. SetupCoda9Properties(coreIdx, productId);
  193. return productId;
  194. }
  195. RetCode Coda9VpuGetVersion(Uint32 coreIdx, Uint32* versionInfo, Uint32* revision)
  196. {
  197. /* Get Firmware version */
  198. VpuWriteReg(coreIdx, RET_FW_VER_NUM , 0);
  199. Coda9BitIssueCommand(coreIdx, NULL, FIRMWARE_GET);
  200. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1)
  201. return RETCODE_VPU_RESPONSE_TIMEOUT;
  202. if (versionInfo != NULL) {
  203. *versionInfo = VpuReadReg(coreIdx, RET_FW_VER_NUM);
  204. }
  205. if (revision != NULL) {
  206. *revision = VpuReadReg(coreIdx, RET_FW_CODE_REV);
  207. }
  208. return RETCODE_SUCCESS;
  209. }
  210. RetCode Coda9VpuInit(Uint32 coreIdx, void* firmware, Uint32 size)
  211. {
  212. Uint32 data;
  213. vpu_buffer_t vb;
  214. PhysicalAddress tempBuffer;
  215. PhysicalAddress paraBuffer;
  216. PhysicalAddress codeBuffer;
  217. vdi_get_common_memory((unsigned long)coreIdx, &vb);
  218. codeBuffer = vb.phys_addr;
  219. tempBuffer = codeBuffer + CODE_BUF_SIZE;
  220. paraBuffer = tempBuffer + TEMP_BUF_SIZE;
  221. BitLoadFirmware(coreIdx, codeBuffer, (const Uint16 *)firmware, size);
  222. /* Clear registers */
  223. if (vdi_read_register(coreIdx, BIT_CUR_PC) == 0) {
  224. Uint32 i;
  225. for (i=0; i<64; i++) {
  226. vdi_write_register(coreIdx, (i*4) + 0x100, 0x0);
  227. }
  228. }
  229. VpuWriteReg(coreIdx, BIT_PARA_BUF_ADDR, paraBuffer);
  230. VpuWriteReg(coreIdx, BIT_CODE_BUF_ADDR, codeBuffer);
  231. VpuWriteReg(coreIdx, BIT_TEMP_BUF_ADDR, tempBuffer);
  232. VpuWriteReg(coreIdx, BIT_BIT_STREAM_CTRL, VPU_STREAM_ENDIAN);
  233. VpuWriteReg(coreIdx, BIT_FRAME_MEM_CTRL, CBCR_INTERLEAVE<<2|VPU_FRAME_ENDIAN); // Interleave bit position is modified
  234. VpuWriteReg(coreIdx, BIT_BIT_STREAM_PARAM, 0);
  235. VpuWriteReg(coreIdx, BIT_AXI_SRAM_USE, 0);
  236. VpuWriteReg(coreIdx, BIT_INT_ENABLE, 0);
  237. VpuWriteReg(coreIdx, BIT_ROLLBACK_STATUS, 0);
  238. data = (1<<INT_BIT_BIT_BUF_FULL);
  239. data |= (1<<INT_BIT_BIT_BUF_EMPTY);
  240. data |= (1<<INT_BIT_DEC_MB_ROWS);
  241. data |= (1<<INT_BIT_SEQ_INIT);
  242. data |= (1<<INT_BIT_DEC_FIELD);
  243. data |= (1<<INT_BIT_PIC_RUN);
  244. VpuWriteReg(coreIdx, BIT_INT_ENABLE, data);
  245. VpuWriteReg(coreIdx, BIT_INT_CLEAR, 0x1);
  246. VpuWriteReg(coreIdx, BIT_BUSY_FLAG, 0x1);
  247. VpuWriteReg(coreIdx, BIT_CODE_RESET, 1);
  248. VpuWriteReg(coreIdx, BIT_CODE_RUN, 1);
  249. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1)
  250. return RETCODE_VPU_RESPONSE_TIMEOUT;
  251. return RETCODE_SUCCESS;
  252. }
  253. RetCode Coda9VpuReInit(Uint32 coreIdx, void* firmware, Uint32 size)
  254. {
  255. vpu_buffer_t vb;
  256. PhysicalAddress tempBuffer;
  257. PhysicalAddress paraBuffer;
  258. PhysicalAddress codeBuffer;
  259. PhysicalAddress oldCodeBuffer;
  260. vdi_get_common_memory((unsigned long)coreIdx, &vb);
  261. codeBuffer = vb.phys_addr;
  262. tempBuffer = codeBuffer + CODE_BUF_SIZE;
  263. paraBuffer = tempBuffer + TEMP_BUF_SIZE;
  264. oldCodeBuffer = VpuReadReg(coreIdx, BIT_CODE_BUF_ADDR);
  265. VpuWriteReg(coreIdx, BIT_PARA_BUF_ADDR, paraBuffer);
  266. VpuWriteReg(coreIdx, BIT_CODE_BUF_ADDR, codeBuffer);
  267. VpuWriteReg(coreIdx, BIT_TEMP_BUF_ADDR, tempBuffer);
  268. if (oldCodeBuffer != codeBuffer) {
  269. LoadBitCode(coreIdx, codeBuffer, (const Uint16 *)firmware, size);
  270. }
  271. return RETCODE_SUCCESS;
  272. }
  273. Uint32 Coda9VpuIsInit(Uint32 coreIdx)
  274. {
  275. Uint32 pc;
  276. pc = VpuReadReg(coreIdx, BIT_CUR_PC);
  277. return pc;
  278. }
  279. Int32 Coda9VpuIsBusy(Uint32 coreIdx)
  280. {
  281. return VpuReadReg(coreIdx, BIT_BUSY_FLAG);
  282. }
  283. Int32 Coda9VpuWaitInterrupt(CodecInst* handle, Int32 timeout)
  284. {
  285. Int32 reason = 0;
  286. #ifdef SUPPORT_MULTI_INST_INTR
  287. reason = vdi_wait_interrupt(handle->coreIdx, 0, timeout);
  288. #else
  289. reason = vdi_wait_interrupt(handle->coreIdx, timeout);
  290. #endif
  291. if (reason != INTERRUPT_TIMEOUT_VALUE) {
  292. VpuWriteReg(handle->coreIdx, BIT_INT_CLEAR, 1); // clear HW signal
  293. }
  294. return reason;
  295. }
  296. RetCode Coda9VpuClearInterrupt(Uint32 coreIdx)
  297. {
  298. VpuWriteReg(coreIdx, BIT_INT_REASON, 0); // tell to F/W that HOST received an interrupt.
  299. return RETCODE_SUCCESS;
  300. }
  301. RetCode Coda9VpuReset(Uint32 coreIdx, SWResetMode resetMode)
  302. {
  303. Uint32 cmd;
  304. Int32 productId = Coda9VpuGetProductId(coreIdx);
  305. if (productId == PRODUCT_ID_960 || productId == PRODUCT_ID_980) {
  306. if (resetMode != SW_RESET_ON_BOOT) {
  307. cmd = VpuReadReg(coreIdx, BIT_RUN_COMMAND);
  308. if (cmd == DEC_SEQ_INIT || cmd == PIC_RUN) {
  309. if (VpuReadReg(coreIdx, BIT_BUSY_FLAG) || VpuReadReg(coreIdx, BIT_INT_REASON)) {
  310. #define MBC_SET_SUBBLK_EN (MBC_BASE+0xA0) // subblk_man_mode[20] cr_subblk_man_en[19:0]
  311. // stop all of pipeline
  312. VpuWriteReg(coreIdx, MBC_SET_SUBBLK_EN, ((1<<20) | 0));
  313. // force to set the end of Bitstream to be decoded.
  314. cmd = VpuReadReg(coreIdx, BIT_BIT_STREAM_PARAM);
  315. cmd |= 1 << 2;
  316. VpuWriteReg(coreIdx, BIT_BIT_STREAM_PARAM, cmd);
  317. cmd = VpuReadReg(coreIdx, BIT_RD_PTR);
  318. VpuWriteReg(coreIdx, BIT_WR_PTR, cmd);
  319. #ifdef SUPPORT_MULTI_INST_INTR
  320. cmd = vdi_wait_interrupt(coreIdx, 0, __VPU_BUSY_TIMEOUT);
  321. #else
  322. cmd = vdi_wait_interrupt(coreIdx, __VPU_BUSY_TIMEOUT);
  323. #endif
  324. if ((Int32)cmd != INTERRUPT_TIMEOUT_VALUE) {
  325. VpuWriteReg(coreIdx, BIT_INT_REASON, 0);
  326. VpuWriteReg(coreIdx, BIT_INT_CLEAR, 1); // clear HW signal
  327. }
  328. // now all of hardwares would be stop.
  329. }
  330. }
  331. }
  332. // Waiting for completion of BWB transaction first
  333. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, GDI_BWB_STATUS) == -1) {
  334. vdi_log(coreIdx, 0x10, 2);
  335. return RETCODE_VPU_RESPONSE_TIMEOUT;
  336. }
  337. // Waiting for completion of bus transaction
  338. // Step1 : No more request
  339. VpuWriteReg(coreIdx, GDI_BUS_CTRL, 0x11); // no more request {3'b0,no_more_req_sec,3'b0,no_more_req}
  340. // Step2 : Waiting for completion of bus transaction
  341. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, GDI_BUS_STATUS) == -1) {
  342. VpuWriteReg(coreIdx, GDI_BUS_CTRL, 0x00);
  343. vdi_log(coreIdx, 0x10, 2);
  344. return RETCODE_VPU_RESPONSE_TIMEOUT;
  345. }
  346. cmd = 0;
  347. // Software Reset Trigger
  348. if (resetMode != SW_RESET_ON_BOOT)
  349. cmd = VPU_SW_RESET_BPU_CORE | VPU_SW_RESET_BPU_BUS;
  350. cmd |= VPU_SW_RESET_VCE_CORE | VPU_SW_RESET_VCE_BUS;
  351. if (resetMode == SW_RESET_ON_BOOT)
  352. cmd |= VPU_SW_RESET_GDI_CORE | VPU_SW_RESET_GDI_BUS;// If you reset GDI, tiled map should be reconfigured
  353. VpuWriteReg(coreIdx, BIT_SW_RESET, cmd);
  354. // wait until reset is done
  355. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_SW_RESET_STATUS) == -1) {
  356. VpuWriteReg(coreIdx, BIT_SW_RESET, 0x00);
  357. VpuWriteReg(coreIdx, GDI_BUS_CTRL, 0x00);
  358. vdi_log(coreIdx, 0x10, 2);
  359. return RETCODE_VPU_RESPONSE_TIMEOUT;
  360. }
  361. VpuWriteReg(coreIdx, BIT_SW_RESET, 0);
  362. // Step3 : must clear GDI_BUS_CTRL after done SW_RESET
  363. VpuWriteReg(coreIdx, GDI_BUS_CTRL, 0x00);
  364. }
  365. else {
  366. vdi_log(coreIdx, 0x10, 0);
  367. return RETCODE_NOT_FOUND_VPU_DEVICE;
  368. }
  369. return RETCODE_SUCCESS;
  370. }
  371. RetCode Coda9VpuSleepWake(Uint32 coreIdx, int iSleepWake, const Uint16* code, Uint32 size)
  372. {
  373. static unsigned int regBk[64];
  374. int i=0;
  375. const Uint16* bit_code = NULL;
  376. if (code && size > 0)
  377. bit_code = code;
  378. if (!bit_code)
  379. return RETCODE_INVALID_PARAM;
  380. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  381. return RETCODE_VPU_RESPONSE_TIMEOUT;
  382. }
  383. if(iSleepWake==1)
  384. {
  385. for ( i = 0 ; i < 64 ; i++)
  386. regBk[i] = VpuReadReg(coreIdx, BIT_BASE + 0x100 + (i * 4));
  387. }
  388. else
  389. {
  390. VpuWriteReg(coreIdx, BIT_CODE_RUN, 0);
  391. for ( i = 0 ; i < 64 ; i++)
  392. VpuWriteReg(coreIdx, BIT_BASE + 0x100 + (i * 4), regBk[i]);
  393. VpuWriteReg(coreIdx, BIT_BUSY_FLAG, 1);
  394. VpuWriteReg(coreIdx, BIT_CODE_RESET, 1);
  395. VpuWriteReg(coreIdx, BIT_CODE_RUN, 1);
  396. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  397. return RETCODE_VPU_RESPONSE_TIMEOUT;
  398. }
  399. }
  400. return RETCODE_SUCCESS;
  401. }
  402. static RetCode SetupDecCodecInstance(Int32 productId, CodecInst* pCodec)
  403. {
  404. DecInfo* pDecInfo = &pCodec->CodecInfo->decInfo;
  405. pDecInfo->streamRdPtrRegAddr = BIT_RD_PTR;
  406. pDecInfo->streamWrPtrRegAddr = BIT_WR_PTR;
  407. pDecInfo->frameDisplayFlagRegAddr = BIT_FRM_DIS_FLG;
  408. pDecInfo->currentPC = BIT_CUR_PC;
  409. pDecInfo->busyFlagAddr = BIT_BUSY_FLAG;
  410. if (productId == PRODUCT_ID_960) {
  411. pDecInfo->dramCfg.rasBit = EM_RAS;
  412. pDecInfo->dramCfg.casBit = EM_CAS;
  413. pDecInfo->dramCfg.bankBit = EM_BANK;
  414. pDecInfo->dramCfg.busBit = EM_WIDTH;
  415. }
  416. return RETCODE_SUCCESS;
  417. }
  418. static RetCode SetupEncCodecInstance(Int32 productId, CodecInst* pCodec)
  419. {
  420. EncInfo* pEncInfo = &pCodec->CodecInfo->encInfo;
  421. pEncInfo->streamRdPtrRegAddr = BIT_RD_PTR;
  422. pEncInfo->streamWrPtrRegAddr = BIT_WR_PTR;
  423. pEncInfo->currentPC = BIT_CUR_PC;
  424. pEncInfo->busyFlagAddr = BIT_BUSY_FLAG;
  425. if (productId == PRODUCT_ID_960) {
  426. pEncInfo->dramCfg.rasBit = EM_RAS;
  427. pEncInfo->dramCfg.casBit = EM_CAS;
  428. pEncInfo->dramCfg.bankBit = EM_BANK;
  429. pEncInfo->dramCfg.busBit = EM_WIDTH;
  430. }
  431. return RETCODE_SUCCESS;
  432. }
  433. RetCode Coda9VpuBuildUpDecParam(CodecInst* pCodec, DecOpenParam* param)
  434. {
  435. RetCode ret = RETCODE_SUCCESS;
  436. Uint32 coreIdx;
  437. Uint32 productId;
  438. DecInfo* pDecInfo = &pCodec->CodecInfo->decInfo;
  439. coreIdx = pCodec->coreIdx;
  440. productId = Coda9VpuGetProductId(coreIdx);
  441. if ((ret=SetupDecCodecInstance(productId, pCodec)) != RETCODE_SUCCESS)
  442. return ret;
  443. if (param->vbWork.size) {
  444. pDecInfo->vbWork = param->vbWork;
  445. pDecInfo->workBufferAllocExt = 1;
  446. }
  447. else {
  448. pDecInfo->vbWork.size = WORK_BUF_SIZE;
  449. if (pCodec->codecMode == AVC_DEC)
  450. pDecInfo->vbWork.size += PS_SAVE_SIZE;
  451. if (vdi_allocate_dma_memory(pCodec->coreIdx, &pDecInfo->vbWork, DEC_WORK, pCodec->instIndex) < 0)
  452. return RETCODE_INSUFFICIENT_RESOURCE;
  453. param->vbWork = pDecInfo->vbWork;
  454. pDecInfo->workBufferAllocExt = 0;
  455. }
  456. if (productId == PRODUCT_ID_960) {
  457. pDecInfo->dramCfg.bankBit = EM_BANK;
  458. pDecInfo->dramCfg.casBit = EM_CAS;
  459. pDecInfo->dramCfg.rasBit = EM_RAS;
  460. pDecInfo->dramCfg.busBit = EM_WIDTH;
  461. }
  462. return ret;
  463. }
  464. RetCode Coda9VpuDecInitSeq(DecHandle handle)
  465. {
  466. CodecInst* pCodecInst = (CodecInst*)handle;
  467. DecInfo* pDecInfo = &pCodecInst->CodecInfo->decInfo;
  468. Uint32 val = 0;
  469. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_BB_START, pDecInfo->streamBufStartAddr);
  470. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_BB_SIZE, pDecInfo->streamBufSize / 1024); // size in KBytes
  471. if(pDecInfo->userDataEnable == TRUE) {
  472. val = 0;
  473. val |= (pDecInfo->userDataReportMode << 10);
  474. val |= (pDecInfo->userDataEnable << 5);
  475. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_OPTION, val);
  476. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_BASE_ADDR, pDecInfo->userDataBufAddr);
  477. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_BUF_SIZE, pDecInfo->userDataBufSize);
  478. }
  479. else {
  480. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_OPTION, 0);
  481. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_BASE_ADDR, 0);
  482. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_BUF_SIZE, 0);
  483. }
  484. val = 0;
  485. val |= (pDecInfo->reorderEnable<<1) & 0x2;
  486. val |= (pDecInfo->openParam.mp4DeblkEnable & 0x1);
  487. val |= (pDecInfo->avcErrorConcealMode << 2);
  488. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_OPTION, val);
  489. switch(pCodecInst->codecMode) {
  490. case VC1_DEC:
  491. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_VC1_STREAM_FMT, (0 << 3) & 0x08);
  492. break;
  493. case MP4_DEC:
  494. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_MP4_ASP_CLASS, (VPU_GMC_PROCESS_METHOD<<3)|pDecInfo->openParam.mp4Class);
  495. break;
  496. case AVC_DEC:
  497. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_X264_MV_EN, VPU_AVC_X264_SUPPORT);
  498. break;
  499. }
  500. if( pCodecInst->codecMode == AVC_DEC )
  501. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_SPP_CHUNK_SIZE, VPU_GBU_SIZE);
  502. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->streamWrPtrRegAddr, pDecInfo->streamWrPtr);
  503. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->streamRdPtrRegAddr, pDecInfo->streamRdPtr);
  504. if (pCodecInst->productId == PRODUCT_ID_980 || pCodecInst->productId == PRODUCT_ID_960) {
  505. pDecInfo->streamEndflag &= ~(3<<3);
  506. if (pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END)
  507. pDecInfo->streamEndflag |= (2<<3);
  508. else { // Interrupt Mode
  509. if (pDecInfo->seqInitEscape) {
  510. pDecInfo->streamEndflag |= (2<<3);
  511. }
  512. }
  513. }
  514. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM, pDecInfo->streamEndflag);
  515. val = pDecInfo->openParam.streamEndian;
  516. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_CTRL, val);
  517. if (pCodecInst->productId == PRODUCT_ID_980) {
  518. val = 0;
  519. val |= (pDecInfo->openParam.bwbEnable<<15);
  520. val |= (pDecInfo->wtlMode<<17)|(pDecInfo->tiled2LinearMode<<13)|(FORMAT_420<<6);
  521. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  522. val |= pDecInfo->openParam.frameEndian;
  523. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  524. }
  525. else if (pCodecInst->productId == PRODUCT_ID_960) {
  526. val = 0;
  527. val |= (pDecInfo->wtlEnable<<17);
  528. val |= (pDecInfo->openParam.bwbEnable<<12);
  529. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  530. val |= pDecInfo->openParam.frameEndian;
  531. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  532. }
  533. else {
  534. return RETCODE_NOT_FOUND_VPU_DEVICE;
  535. }
  536. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->frameDisplayFlagRegAddr, 0);
  537. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, DEC_SEQ_INIT);
  538. return RETCODE_SUCCESS;
  539. }
  540. RetCode Coda9VpuFiniSeq(CodecInst* instance)
  541. {
  542. Coda9BitIssueCommand(instance->coreIdx, instance, DEC_SEQ_END);
  543. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  544. return RETCODE_VPU_RESPONSE_TIMEOUT;
  545. }
  546. return RETCODE_SUCCESS;
  547. }
  548. RetCode Coda9VpuDecode(CodecInst* instance, DecParam* param)
  549. {
  550. CodecInst* pCodecInst;
  551. DecInfo* pDecInfo;
  552. Uint32 rotMir;
  553. Int32 val;
  554. vpu_instance_pool_t *vip;
  555. pCodecInst = instance;
  556. pDecInfo = &pCodecInst->CodecInfo->decInfo;
  557. vip = (vpu_instance_pool_t *)vdi_get_instance_pool(pCodecInst->coreIdx);
  558. if (!vip) {
  559. return RETCODE_INVALID_HANDLE;
  560. }
  561. rotMir = 0;
  562. if (pDecInfo->rotationEnable) {
  563. rotMir |= 0x10; // Enable rotator
  564. switch (pDecInfo->rotationAngle) {
  565. case 0:
  566. rotMir |= 0x0;
  567. break;
  568. case 90:
  569. rotMir |= 0x1;
  570. break;
  571. case 180:
  572. rotMir |= 0x2;
  573. break;
  574. case 270:
  575. rotMir |= 0x3;
  576. break;
  577. }
  578. }
  579. if (pDecInfo->mirrorEnable) {
  580. rotMir |= 0x10; // Enable rotator
  581. switch (pDecInfo->mirrorDirection) {
  582. case MIRDIR_NONE :
  583. rotMir |= 0x0;
  584. break;
  585. case MIRDIR_VER :
  586. rotMir |= 0x4;
  587. break;
  588. case MIRDIR_HOR :
  589. rotMir |= 0x8;
  590. break;
  591. case MIRDIR_HOR_VER :
  592. rotMir |= 0xc;
  593. break;
  594. }
  595. }
  596. if (pDecInfo->tiled2LinearEnable) {
  597. rotMir |= 0x10;
  598. }
  599. if (pDecInfo->deringEnable) {
  600. rotMir |= 0x20; // Enable Dering Filter
  601. }
  602. if (rotMir && !pDecInfo->rotatorOutputValid) {
  603. return RETCODE_ROTATOR_OUTPUT_NOT_SET;
  604. }
  605. VpuWriteReg(pCodecInst->coreIdx, RET_DEC_PIC_CROP_LEFT_RIGHT, 0); // frame crop information(left, right)
  606. VpuWriteReg(pCodecInst->coreIdx, RET_DEC_PIC_CROP_TOP_BOTTOM, 0); // frame crop information(top, bottom)
  607. if (pCodecInst->productId == PRODUCT_ID_960) {
  608. if (pDecInfo->mapType>LINEAR_FRAME_MAP && pDecInfo->mapType<=TILED_MIXED_V_MAP) {
  609. SetTiledFrameBase(pCodecInst->coreIdx, pDecInfo->mapCfg.tiledBaseAddr);
  610. }
  611. else {
  612. SetTiledFrameBase(pCodecInst->coreIdx, 0);
  613. }
  614. }
  615. if (pDecInfo->mapType != LINEAR_FRAME_MAP && pDecInfo->mapType != LINEAR_FIELD_MAP) {
  616. val = SetTiledMapType(pCodecInst->coreIdx, &pDecInfo->mapCfg, pDecInfo->mapType,
  617. (pDecInfo->stride > pDecInfo->frameBufferHeight)?pDecInfo->stride: pDecInfo->frameBufferHeight,
  618. pDecInfo->openParam.cbcrInterleave, &pDecInfo->dramCfg);
  619. } else {
  620. val = SetTiledMapType(pCodecInst->coreIdx, &pDecInfo->mapCfg, pDecInfo->mapType,
  621. pDecInfo->stride, pDecInfo->openParam.cbcrInterleave, &pDecInfo->dramCfg);
  622. }
  623. if (val == 0) {
  624. return RETCODE_INVALID_PARAM;
  625. }
  626. if (rotMir & 0x30) { // rotator or dering or tiled2linear enabled
  627. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_MODE, rotMir);
  628. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_INDEX, pDecInfo->rotatorOutput.myIndex);
  629. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_ADDR_Y, pDecInfo->rotatorOutput.bufY);
  630. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_ADDR_CB, pDecInfo->rotatorOutput.bufCb);
  631. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_ADDR_CR, pDecInfo->rotatorOutput.bufCr);
  632. if (pCodecInst->productId == PRODUCT_ID_980) {
  633. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_BOTTOM_Y, pDecInfo->rotatorOutput.bufYBot);
  634. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_BOTTOM_CB, pDecInfo->rotatorOutput.bufCbBot);
  635. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_BOTTOM_CR, pDecInfo->rotatorOutput.bufCrBot);
  636. }
  637. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_STRIDE, pDecInfo->rotatorStride);
  638. }
  639. else {
  640. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_MODE, rotMir);
  641. }
  642. if(pDecInfo->userDataEnable) {
  643. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_USER_DATA_BASE_ADDR, pDecInfo->userDataBufAddr);
  644. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_USER_DATA_BUF_SIZE, pDecInfo->userDataBufSize);
  645. }
  646. else {
  647. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_USER_DATA_BASE_ADDR, 0);
  648. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_USER_DATA_BUF_SIZE, 0);
  649. }
  650. val = 0;
  651. if (param->iframeSearchEnable == TRUE) { // if iframeSearch is Enable, other bit is ignore;
  652. val |= (pDecInfo->userDataReportMode <<10);
  653. if (pCodecInst->codecMode == AVC_DEC || pCodecInst->codecMode == VC1_DEC) {
  654. if (param->iframeSearchEnable==1)
  655. val |= (1<< 11) | (1<<2);
  656. else if (param->iframeSearchEnable==2)
  657. val |= (1<<2);
  658. }
  659. else {
  660. val |= (( param->iframeSearchEnable &0x1) << 2 );
  661. }
  662. }
  663. else {
  664. val |= (pDecInfo->userDataReportMode <<10);
  665. val |= (pDecInfo->userDataEnable << 5);
  666. val |= (param->skipframeMode << 3);
  667. }
  668. if (pCodecInst->productId == PRODUCT_ID_980) {
  669. if (pCodecInst->codecMode == AVC_DEC && pDecInfo->lowDelayInfo.lowDelayEn) {
  670. val |= (pDecInfo->lowDelayInfo.lowDelayEn <<18 );
  671. }
  672. }
  673. if (pCodecInst->codecMode == MP2_DEC) {
  674. val |= ((param->DecStdParam.mp2PicFlush&1)<<15);
  675. }
  676. if (pCodecInst->codecMode == RV_DEC) {
  677. val |= ((param->DecStdParam.rvDbkMode&0x0f)<<16);
  678. }
  679. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_OPTION, val);
  680. if (pCodecInst->productId == PRODUCT_ID_980) {
  681. if (pDecInfo->lowDelayInfo.lowDelayEn == TRUE) {
  682. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_NUM_ROWS, pDecInfo->lowDelayInfo.numRows);
  683. }
  684. else {
  685. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_NUM_ROWS, 0);
  686. }
  687. }
  688. val = 0;
  689. val = (
  690. (pDecInfo->secAxiInfo.u.coda9.useBitEnable&0x01)<<0 |
  691. (pDecInfo->secAxiInfo.u.coda9.useIpEnable&0x01)<<1 |
  692. (pDecInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01)<<2 |
  693. (pDecInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01)<<3 |
  694. (pDecInfo->secAxiInfo.u.coda9.useOvlEnable&0x01)<<4 |
  695. (pDecInfo->secAxiInfo.u.coda9.useBtpEnable&0x01)<<5 |
  696. (pDecInfo->secAxiInfo.u.coda9.useBitEnable&0x01)<<8 |
  697. (pDecInfo->secAxiInfo.u.coda9.useIpEnable&0x01)<<9 |
  698. (pDecInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01)<<10 |
  699. (pDecInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01)<<11 |
  700. (pDecInfo->secAxiInfo.u.coda9.useOvlEnable&0x01)<<12 |
  701. (pDecInfo->secAxiInfo.u.coda9.useBtpEnable&0x01)<<13 );
  702. VpuWriteReg(pCodecInst->coreIdx, BIT_AXI_SRAM_USE, val);
  703. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->streamWrPtrRegAddr, pDecInfo->streamWrPtr);
  704. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->streamRdPtrRegAddr, pDecInfo->streamRdPtr);
  705. pDecInfo->streamEndflag &= ~(3<<3);
  706. if (pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END)
  707. pDecInfo->streamEndflag |= (2<<3);
  708. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM, pDecInfo->streamEndflag);
  709. if (pCodecInst->productId == PRODUCT_ID_980) {
  710. val = 0;
  711. val |= (pDecInfo->openParam.bwbEnable<<15);
  712. val |= (pDecInfo->wtlMode<<17)|(pDecInfo->tiled2LinearMode<<13)|(pDecInfo->mapType<<9)|(FORMAT_420<<6);
  713. }
  714. else if (pCodecInst->productId == PRODUCT_ID_960) {
  715. val = 0;
  716. val |= (pDecInfo->wtlEnable<<17);
  717. val |= (pDecInfo->openParam.bwbEnable<<12);
  718. if (pDecInfo->mapType) {
  719. if (pDecInfo->mapType == TILED_FRAME_MB_RASTER_MAP || pDecInfo->mapType == TILED_FIELD_MB_RASTER_MAP)
  720. val |= (pDecInfo->tiled2LinearEnable<<11)|(0x03<<9)|(FORMAT_420<<6);
  721. else
  722. val |= (pDecInfo->tiled2LinearEnable<<11)|(0x02<<9)|(FORMAT_420<<6);
  723. }
  724. }
  725. else {
  726. return RETCODE_NOT_FOUND_VPU_DEVICE;
  727. }
  728. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  729. val |= pDecInfo->openParam.frameEndian;
  730. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  731. val = pDecInfo->openParam.streamEndian;
  732. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_CTRL, val);
  733. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, PIC_RUN);
  734. return RETCODE_SUCCESS;
  735. }
  736. RetCode Coda9VpuDecGetResult(CodecInst* instance, DecOutputInfo* result)
  737. {
  738. CodecInst* pCodecInst;
  739. DecInfo* pDecInfo;
  740. Uint32 val = 0;
  741. pCodecInst = instance;
  742. pDecInfo = &pCodecInst->CodecInfo->decInfo;
  743. if (pCodecInst->loggingEnable)
  744. vdi_log(pCodecInst->coreIdx, PIC_RUN, 0);
  745. result->warnInfo = 0;
  746. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_SUCCESS);
  747. result->decodingSuccess = val;
  748. if (result->decodingSuccess & (1UL<<31)) {
  749. return RETCODE_MEMORY_ACCESS_VIOLATION;
  750. }
  751. if( pCodecInst->codecMode == AVC_DEC ) {
  752. result->notSufficientPsBuffer = (val >> 3) & 0x1;
  753. result->notSufficientSliceBuffer = (val >> 2) & 0x1;
  754. result->refMissingFrameFlag = (val>>21) & 0x1;
  755. }
  756. result->chunkReuseRequired = 0;
  757. if (pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END) {
  758. switch (pCodecInst->codecMode) {
  759. case AVC_DEC:
  760. result->chunkReuseRequired = ((val >> 16) & 0x01); // in case of NPF frame
  761. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_DECODED_IDX);
  762. if (val == (Uint32)-1) {
  763. result->chunkReuseRequired = TRUE;
  764. }
  765. break;
  766. case MP2_DEC:
  767. case MP4_DEC:
  768. result->chunkReuseRequired = ((val >> 16) & 0x01);
  769. break;
  770. default:
  771. break;
  772. }
  773. }
  774. result->indexFrameDecoded = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_DECODED_IDX);
  775. result->indexFrameDisplay = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_DISPLAY_IDX);
  776. if (pDecInfo->mapType == LINEAR_FRAME_MAP) {
  777. result->indexFrameDecodedForTiled = -1;
  778. result->indexFrameDisplayForTiled = -1;
  779. }
  780. else {
  781. result->indexFrameDecodedForTiled = result->indexFrameDecoded;
  782. result->indexFrameDisplayForTiled = result->indexFrameDisplay;
  783. }
  784. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_SIZE); // decoding picture size
  785. result->decPicWidth = (val>>16) & 0xFFFF;
  786. result->decPicHeight = (val) & 0xFFFF;
  787. if (result->indexFrameDecoded >= 0 && result->indexFrameDecoded < MAX_GDI_IDX) {
  788. switch (pCodecInst->codecMode) {
  789. case VPX_DEC:
  790. if ( pCodecInst->codecModeAux == VPX_AUX_VP8 ) {
  791. // VP8 specific header information
  792. // h_scale[31:30] v_scale[29:28] pic_width[27:14] pic_height[13:0]
  793. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VP8_SCALE_INFO);
  794. result->vp8ScaleInfo.hScaleFactor = (val >> 30) & 0x03;
  795. result->vp8ScaleInfo.vScaleFactor = (val >> 28) & 0x03;
  796. result->vp8ScaleInfo.picWidth = (val >> 14) & 0x3FFF;
  797. result->vp8ScaleInfo.picHeight = (val >> 0) & 0x3FFF;
  798. // ref_idx_gold[31:24], ref_idx_altr[23:16], ref_idx_last[15: 8],
  799. // version_number[3:1], show_frame[0]
  800. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VP8_PIC_REPORT);
  801. result->vp8PicInfo.refIdxGold = (val >> 24) & 0x0FF;
  802. result->vp8PicInfo.refIdxAltr = (val >> 16) & 0x0FF;
  803. result->vp8PicInfo.refIdxLast = (val >> 8) & 0x0FF;
  804. result->vp8PicInfo.versionNumber = (val >> 1) & 0x07;
  805. result->vp8PicInfo.showFrame = (val >> 0) & 0x01;
  806. }
  807. break;
  808. case AVC_DEC:
  809. case AVS_DEC:
  810. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_CROP_LEFT_RIGHT); // frame crop information(left, right)
  811. pDecInfo->initialInfo.picCropRect.left = (val>>16) & 0xffff;
  812. pDecInfo->initialInfo.picCropRect.right = pDecInfo->initialInfo.picWidth - (val&0xffff);
  813. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_CROP_TOP_BOTTOM); // frame crop information(top, bottom)
  814. pDecInfo->initialInfo.picCropRect.top = (val>>16) & 0xffff;
  815. pDecInfo->initialInfo.picCropRect.bottom = pDecInfo->initialInfo.picHeight - (val&0xffff);
  816. break;
  817. case MP2_DEC:
  818. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_MP2_BAR_LEFT_RIGHT);
  819. pDecInfo->initialInfo.mp2BardataInfo.barLeft = ((val>>16) & 0xFFFF);
  820. pDecInfo->initialInfo.mp2BardataInfo.barRight = (val&0xFFFF);
  821. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_MP2_BAR_TOP_BOTTOM);
  822. pDecInfo->initialInfo.mp2BardataInfo.barTop = ((val>>16) & 0xFFFF);
  823. pDecInfo->initialInfo.mp2BardataInfo.barBottom = (val&0xFFFF);
  824. result->mp2BardataInfo = pDecInfo->initialInfo.mp2BardataInfo;
  825. result->mp2PicDispExtInfo.offsetNum = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MP2_OFFSET_NUM);
  826. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MP2_OFFSET1);
  827. result->mp2PicDispExtInfo.horizontalOffset1 = (Int16) (val >> 16) & 0xFFFF;
  828. result->mp2PicDispExtInfo.verticalOffset1 = (Int16) (val & 0xFFFF);
  829. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MP2_OFFSET2);
  830. result->mp2PicDispExtInfo.horizontalOffset2 = (Int16) (val >> 16) & 0xFFFF;
  831. result->mp2PicDispExtInfo.verticalOffset2 = (Int16) (val & 0xFFFF);
  832. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MP2_OFFSET3);
  833. result->mp2PicDispExtInfo.horizontalOffset3 = (Int16) (val >> 16) & 0xFFFF;
  834. result->mp2PicDispExtInfo.verticalOffset3 = (Int16) (val & 0xFFFF);
  835. break;
  836. }
  837. }
  838. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_TYPE);
  839. result->interlacedFrame = (val >> 18) & 0x1;
  840. result->topFieldFirst = (val >> 21) & 0x0001; // TopFieldFirst[21]
  841. if (result->interlacedFrame) {
  842. result->picTypeFirst = (val & 0x38) >> 3; // pic_type of 1st field
  843. result->picType = val & 7; // pic_type of 2nd field
  844. }
  845. else {
  846. result->picTypeFirst = PIC_TYPE_MAX; // no meaning
  847. result->picType = val & 7;
  848. }
  849. result->pictureStructure = (val >> 19) & 0x0003; // MbAffFlag[17], FieldPicFlag[16]
  850. result->repeatFirstField = (val >> 22) & 0x0001;
  851. result->progressiveFrame = (val >> 23) & 0x0003;
  852. if( pCodecInst->codecMode == AVC_DEC)
  853. {
  854. result->decFrameInfo = (val >> 15) & 0x0001;
  855. result->picStrPresent = (val >> 27) & 0x0001;
  856. result->picTimingStruct = (val >> 28) & 0x000f;
  857. //update picture type when IDR frame
  858. if (val & 0x40) { // 6th bit
  859. if (result->interlacedFrame)
  860. result->picTypeFirst = PIC_TYPE_IDR;
  861. else
  862. result->picType = PIC_TYPE_IDR;
  863. }
  864. result->decFrameInfo = (val >> 16) & 0x0003;
  865. if (result->indexFrameDisplay >= 0) {
  866. if (result->indexFrameDisplay == result->indexFrameDecoded)
  867. result->avcNpfFieldInfo = result->decFrameInfo;
  868. else
  869. result->avcNpfFieldInfo = pDecInfo->decOutInfo[result->indexFrameDisplay].decFrameInfo;
  870. }
  871. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_HRD_INFO);
  872. result->avcHrdInfo.cpbMinus1 = val>>2;
  873. result->avcHrdInfo.vclHrdParamFlag = (val>>1)&1;
  874. result->avcHrdInfo.nalHrdParamFlag = val&1;
  875. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VUI_INFO);
  876. result->avcVuiInfo.fixedFrameRateFlag = val &1;
  877. result->avcVuiInfo.timingInfoPresent = (val>>1) & 0x01;
  878. result->avcVuiInfo.chromaLocBotField = (val>>2) & 0x07;
  879. result->avcVuiInfo.chromaLocTopField = (val>>5) & 0x07;
  880. result->avcVuiInfo.chromaLocInfoPresent = (val>>8) & 0x01;
  881. result->avcVuiInfo.colorPrimaries = (val>>16) & 0xff;
  882. result->avcVuiInfo.colorDescPresent = (val>>24) & 0x01;
  883. result->avcVuiInfo.isExtSAR = (val>>25) & 0x01;
  884. result->avcVuiInfo.vidFullRange = (val>>26) & 0x01;
  885. result->avcVuiInfo.vidFormat = (val>>27) & 0x07;
  886. result->avcVuiInfo.vidSigTypePresent = (val>>30) & 0x01;
  887. result->avcVuiInfo.vuiParamPresent = (val>>31) & 0x01;
  888. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VUI_PIC_STRUCT);
  889. result->avcVuiInfo.vuiPicStructPresent = (val & 0x1);
  890. result->avcVuiInfo.vuiPicStruct = (val>>1);
  891. }
  892. if( pCodecInst->codecMode == MP2_DEC)
  893. {
  894. result->fieldSequence = (val >> 25) & 0x0007;
  895. result->frameDct = (val >> 28) & 0x0001;
  896. result->progressiveSequence = (val >> 29) & 0x0001;
  897. }
  898. result->fRateNumerator = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_FRATE_NR); //Frame rate, Aspect ratio can be changed frame by frame.
  899. result->fRateDenominator = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_FRATE_DR);
  900. if (pCodecInst->codecMode == AVC_DEC && result->fRateDenominator > 0)
  901. result->fRateDenominator *= 2;
  902. if (pCodecInst->codecMode == MP4_DEC)
  903. {
  904. result->mp4ModuloTimeBase = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MODULO_TIME_BASE);
  905. result->mp4TimeIncrement = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VOP_TIME_INCREMENT);
  906. }
  907. if (pCodecInst->codecMode == RV_DEC) {
  908. result->rvTr = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_RV_TR);
  909. result->rvTrB = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_RV_TR_BFRAME);
  910. }
  911. if (pCodecInst->codecMode == VPX_DEC) {
  912. result->aspectRateInfo = 0;
  913. }
  914. else {
  915. result->aspectRateInfo = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_ASPECT);
  916. }
  917. // User Data
  918. if (pDecInfo->userDataEnable) {
  919. int userDataNum;
  920. int userDataSize;
  921. BYTE tempBuf[8] = {0,};
  922. VpuReadMem(pCodecInst->coreIdx, pDecInfo->userDataBufAddr + 0, tempBuf, 8, VPU_USER_DATA_ENDIAN);
  923. val = ((tempBuf[0]<<24) & 0xFF000000) |
  924. ((tempBuf[1]<<16) & 0x00FF0000) |
  925. ((tempBuf[2]<< 8) & 0x0000FF00) |
  926. ((tempBuf[3]<< 0) & 0x000000FF);
  927. userDataNum = (val >> 16) & 0xFFFF;
  928. userDataSize = (val >> 0) & 0xFFFF;
  929. if (userDataNum == 0)
  930. userDataSize = 0;
  931. result->decOutputExtData.userDataNum = userDataNum;
  932. result->decOutputExtData.userDataSize = userDataSize;
  933. val = ((tempBuf[4]<<24) & 0xFF000000) |
  934. ((tempBuf[5]<<16) & 0x00FF0000) |
  935. ((tempBuf[6]<< 8) & 0x0000FF00) |
  936. ((tempBuf[7]<< 0) & 0x000000FF);
  937. if (userDataNum == 0)
  938. result->decOutputExtData.userDataBufFull = 0;
  939. else
  940. result->decOutputExtData.userDataBufFull = (val >> 16) & 0xFFFF;
  941. result->decOutputExtData.activeFormat = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_ATSC_USER_DATA_INFO)&0xf;
  942. }
  943. result->numOfErrMBs = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_ERR_MB);
  944. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_SUCCESS);
  945. result->sequenceChanged = ((val>>20) & 0x1);
  946. result->streamEndFlag = ((pDecInfo->streamEndflag>>2) & 0x01);
  947. if (pCodecInst->codecMode == VC1_DEC && result->indexFrameDisplay != -3) {
  948. if (pDecInfo->vc1BframeDisplayValid == 0) {
  949. if (result->picType == 2) {
  950. result->indexFrameDisplay = -3;
  951. } else {
  952. pDecInfo->vc1BframeDisplayValid = 1;
  953. }
  954. }
  955. }
  956. if (pCodecInst->codecMode == AVC_DEC && pCodecInst->codecModeAux == AVC_AUX_MVC)
  957. {
  958. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MVC_REPORT);
  959. result->mvcPicInfo.viewIdxDisplay = (val>>0) & 1;
  960. result->mvcPicInfo.viewIdxDecoded = (val>>1) & 1;
  961. }
  962. if (pCodecInst->codecMode == AVC_DEC)
  963. {
  964. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_AVC_FPA_SEI0);
  965. if ((int)val < 0) {
  966. result->avcFpaSei.exist = 0;
  967. }
  968. else {
  969. result->avcFpaSei.exist = 1;
  970. result->avcFpaSei.framePackingArrangementId = val;
  971. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_AVC_FPA_SEI1);
  972. result->avcFpaSei.contentInterpretationType = val&0x3F; // [5:0]
  973. result->avcFpaSei.framePackingArrangementType = (val >> 6)&0x7F; // [12:6]
  974. result->avcFpaSei.framePackingArrangementExtensionFlag = (val >> 13)&0x01; // [13]
  975. result->avcFpaSei.frame1SelfContainedFlag = (val >> 14)&0x01; // [14]
  976. result->avcFpaSei.frame0SelfContainedFlag = (val >> 15)&0x01; // [15]
  977. result->avcFpaSei.currentFrameIsFrame0Flag = (val >> 16)&0x01; // [16]
  978. result->avcFpaSei.fieldViewsFlag = (val >> 17)&0x01; // [17]
  979. result->avcFpaSei.frame0FlippedFlag = (val >> 18)&0x01; // [18]
  980. result->avcFpaSei.spatialFlippingFlag = (val >> 19)&0x01; // [19]
  981. result->avcFpaSei.quincunxSamplingFlag = (val >> 20)&0x01; // [20]
  982. result->avcFpaSei.framePackingArrangementCancelFlag = (val >> 21)&0x01; // [21]
  983. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_AVC_FPA_SEI2);
  984. result->avcFpaSei.framePackingArrangementRepetitionPeriod = val&0x7FFF; // [14:0]
  985. result->avcFpaSei.frame1GridPositionY = (val >> 16)&0x0F; // [19:16]
  986. result->avcFpaSei.frame1GridPositionX = (val >> 20)&0x0F; // [23:20]
  987. result->avcFpaSei.frame0GridPositionY = (val >> 24)&0x0F; // [27:24]
  988. result->avcFpaSei.frame0GridPositionX = (val >> 28)&0x0F; // [31:28]
  989. }
  990. result->avcPocTop = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_POC_TOP);
  991. result->avcPocBot = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_POC_BOT);
  992. if (result->interlacedFrame)
  993. {
  994. if (result->avcPocTop > result->avcPocBot) {
  995. result->avcPocPic = result->avcPocBot;
  996. } else {
  997. result->avcPocPic = result->avcPocTop;
  998. }
  999. }
  1000. else
  1001. result->avcPocPic = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_POC);
  1002. }
  1003. if (pCodecInst->codecMode == AVC_DEC)
  1004. {
  1005. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_AVC_SEI_RP_INFO);
  1006. if ((int)val < 0) {
  1007. result->avcRpSei.exist = 0;
  1008. }
  1009. else {
  1010. result->avcRpSei.exist = 1;
  1011. result->avcRpSei.changingSliceGroupIdc = val & 0x3; // [1:0]
  1012. result->avcRpSei.brokenLinkFlag = (val >> 2)&0x01; // [2]
  1013. result->avcRpSei.exactMatchFlag = (val >> 3)&0x01; // [3]
  1014. result->avcRpSei.recoveryFrameCnt = (val >> 4)&0x3F; // [9:4]
  1015. }
  1016. }
  1017. result->bytePosFrameStart = VpuReadReg(pCodecInst->coreIdx, BIT_BYTE_POS_FRAME_START);
  1018. result->bytePosFrameEnd = VpuReadReg(pCodecInst->coreIdx, BIT_BYTE_POS_FRAME_END);
  1019. if (result->indexFrameDecoded >= 0 && result->indexFrameDecoded < MAX_GDI_IDX)
  1020. pDecInfo->decOutInfo[result->indexFrameDecoded] = *result;
  1021. result->frameDisplayFlag = pDecInfo->frameDisplayFlag;
  1022. result->frameCycle = VpuReadReg(pCodecInst->coreIdx, BIT_FRAME_CYCLE);
  1023. return RETCODE_SUCCESS;
  1024. }
  1025. RetCode Coda9VpuDecSetBitstreamFlag(CodecInst* instance, BOOL running, BOOL eos)
  1026. {
  1027. Uint32 val;
  1028. DecInfo* pDecInfo;
  1029. pDecInfo = &instance->CodecInfo->decInfo;
  1030. if (eos&0x01) {
  1031. val = VpuReadReg(instance->coreIdx, BIT_BIT_STREAM_PARAM);
  1032. val |= 1 << 2;
  1033. pDecInfo->streamEndflag = val;
  1034. if (running == TRUE)
  1035. VpuWriteReg(instance->coreIdx, BIT_BIT_STREAM_PARAM, val);
  1036. return RETCODE_SUCCESS;
  1037. }
  1038. else {
  1039. val = VpuReadReg(instance->coreIdx, BIT_BIT_STREAM_PARAM);
  1040. val &= ~(1 << 2);
  1041. pDecInfo->streamEndflag = val;
  1042. if (running == TRUE)
  1043. VpuWriteReg(instance->coreIdx, BIT_BIT_STREAM_PARAM, val);
  1044. return RETCODE_SUCCESS;
  1045. }
  1046. }
  1047. RetCode Coda9VpuDecGetSeqInfo(CodecInst* instance, DecInitialInfo* info)
  1048. {
  1049. CodecInst* pCodecInst = NULL;
  1050. DecInfo* pDecInfo = NULL;
  1051. Uint32 val, val2;
  1052. pCodecInst = instance;
  1053. pDecInfo = &pCodecInst->CodecInfo->decInfo;
  1054. if (pCodecInst->loggingEnable) {
  1055. vdi_log(pCodecInst->coreIdx, DEC_SEQ_INIT, 0);
  1056. }
  1057. info->warnInfo = 0;
  1058. if (pDecInfo->openParam.bitstreamMode == BS_MODE_INTERRUPT && pDecInfo->seqInitEscape) {
  1059. pDecInfo->streamEndflag &= ~(3<<3);
  1060. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM, pDecInfo->streamEndflag);
  1061. pDecInfo->seqInitEscape = 0;
  1062. }
  1063. pDecInfo->streamRdPtr = VpuReadReg(instance->coreIdx, pDecInfo->streamRdPtrRegAddr);
  1064. pDecInfo->frameDisplayFlag = VpuReadReg(pCodecInst->coreIdx, pDecInfo->frameDisplayFlagRegAddr);
  1065. pDecInfo->streamEndflag = VpuReadReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM);
  1066. info->seqInitErrReason = 0;
  1067. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_SUCCESS);
  1068. if (val & (1UL<<31)) {
  1069. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1070. }
  1071. if ( pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END) {
  1072. if (val & (1<<4)) {
  1073. info->seqInitErrReason = (VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_SEQ_ERR_REASON));
  1074. return RETCODE_FAILURE;
  1075. }
  1076. }
  1077. if (val == 0) {
  1078. info->seqInitErrReason = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_SEQ_ERR_REASON);
  1079. return RETCODE_FAILURE;
  1080. }
  1081. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_SRC_SIZE);
  1082. info->picWidth = ( (val >> 16) & 0xffff );
  1083. info->picHeight = ( val & 0xffff );
  1084. info->lumaBitdepth = 8;
  1085. info->chromaBitdepth = 8;
  1086. info->fRateNumerator = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_FRATE_NR);
  1087. info->fRateDenominator = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_FRATE_DR);
  1088. if (pCodecInst->codecMode == AVC_DEC && info->fRateDenominator > 0) {
  1089. info->fRateDenominator *= 2;
  1090. }
  1091. if (pCodecInst->codecMode == MP4_DEC) {
  1092. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_INFO);
  1093. info->mp4ShortVideoHeader = (val >> 2) & 1;
  1094. info->mp4DataPartitionEnable = val & 1;
  1095. info->mp4ReversibleVlcEnable = info->mp4DataPartitionEnable ? ((val >> 1) & 1) : 0;
  1096. info->h263AnnexJEnable = (val >> 3) & 1;
  1097. }
  1098. else if (pCodecInst->codecMode == VPX_DEC && pCodecInst->codecModeAux == VPX_AUX_VP8) {
  1099. // h_scale[31:30] v_scale[29:28] pic_width[27:14] pic_height[13:0]
  1100. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_VP8_SCALE_INFO);
  1101. info->vp8ScaleInfo.hScaleFactor = (val >> 30) & 0x03;
  1102. info->vp8ScaleInfo.vScaleFactor = (val >> 28) & 0x03;
  1103. info->vp8ScaleInfo.picWidth = (val >> 14) & 0x3FFF;
  1104. info->vp8ScaleInfo.picHeight = (val >> 0) & 0x3FFF;
  1105. }
  1106. info->minFrameBufferCount = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_FRAME_NEED);
  1107. info->frameBufDelay = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_FRAME_DELAY);
  1108. if (pCodecInst->codecMode == AVC_DEC || pCodecInst->codecMode == MP2_DEC || pCodecInst->codecMode == AVS_DEC) {
  1109. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_CROP_LEFT_RIGHT);
  1110. val2 = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_CROP_TOP_BOTTOM);
  1111. info->picCropRect.left = ((val>>16) & 0xFFFF);
  1112. info->picCropRect.right = info->picWidth - (val & 0xFFFF);;
  1113. info->picCropRect.top = ((val2>>16) & 0xFFFF);
  1114. info->picCropRect.bottom = info->picHeight - (val2 & 0xFFFF);
  1115. val = (info->picWidth * info->picHeight * 3 / 2) / 1024;
  1116. info->normalSliceSize = val / 4;
  1117. info->worstSliceSize = val / 2;
  1118. }
  1119. else {
  1120. info->picCropRect.left = 0;
  1121. info->picCropRect.right = info->picWidth;
  1122. info->picCropRect.top = 0;
  1123. info->picCropRect.bottom = info->picHeight;
  1124. }
  1125. if (pCodecInst->codecMode == MP2_DEC) {
  1126. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_MP2_BAR_LEFT_RIGHT);
  1127. val2 = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_MP2_BAR_TOP_BOTTOM);
  1128. info->mp2BardataInfo.barLeft = ((val>>16) & 0xFFFF);
  1129. info->mp2BardataInfo.barRight = (val&0xFFFF);
  1130. info->mp2BardataInfo.barTop = ((val2>>16) & 0xFFFF);
  1131. info->mp2BardataInfo.barBottom = (val2&0xFFFF);
  1132. }
  1133. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_HEADER_REPORT);
  1134. info->profile = (val >> 0) & 0xFF;
  1135. info->level = (val >> 8) & 0xFF;
  1136. info->interlace = (val >> 16) & 0x01;
  1137. info->direct8x8Flag = (val >> 17) & 0x01;
  1138. info->vc1Psf = (val >> 18) & 0x01;
  1139. info->constraint_set_flag[0] = (val >> 19) & 0x01;
  1140. info->constraint_set_flag[1] = (val >> 20) & 0x01;
  1141. info->constraint_set_flag[2] = (val >> 21) & 0x01;
  1142. info->constraint_set_flag[3] = (val >> 22) & 0x01;
  1143. info->chromaFormatIDC = (val >> 23) & 0x03;
  1144. info->isExtSAR = (val >> 25) & 0x01;
  1145. info->maxNumRefFrm = (val >> 27) & 0x0f;
  1146. info->maxNumRefFrmFlag = (val >> 31) & 0x01;
  1147. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_ASPECT);
  1148. info->aspectRateInfo = val;
  1149. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_BIT_RATE);
  1150. info->bitRate = val;
  1151. if (pCodecInst->codecMode == AVC_DEC) {
  1152. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_VUI_INFO);
  1153. info->avcVuiInfo.fixedFrameRateFlag = val &1;
  1154. info->avcVuiInfo.timingInfoPresent = (val>>1) & 0x01;
  1155. info->avcVuiInfo.chromaLocBotField = (val>>2) & 0x07;
  1156. info->avcVuiInfo.chromaLocTopField = (val>>5) & 0x07;
  1157. info->avcVuiInfo.chromaLocInfoPresent = (val>>8) & 0x01;
  1158. info->avcVuiInfo.colorPrimaries = (val>>16) & 0xff;
  1159. info->avcVuiInfo.colorDescPresent = (val>>24) & 0x01;
  1160. info->avcVuiInfo.isExtSAR = (val>>25) & 0x01;
  1161. info->avcVuiInfo.vidFullRange = (val>>26) & 0x01;
  1162. info->avcVuiInfo.vidFormat = (val>>27) & 0x07;
  1163. info->avcVuiInfo.vidSigTypePresent = (val>>30) & 0x01;
  1164. info->avcVuiInfo.vuiParamPresent = (val>>31) & 0x01;
  1165. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_VUI_PIC_STRUCT);
  1166. info->avcVuiInfo.vuiPicStructPresent = (val & 0x1);
  1167. info->avcVuiInfo.vuiPicStruct = (val>>1);
  1168. }
  1169. if (pCodecInst->codecMode == MP2_DEC) {
  1170. // seq_ext info
  1171. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_EXT_INFO);
  1172. info->mp2LowDelay = val & 1;
  1173. info->mp2DispVerSize = (val>>1) & 0x3fff;
  1174. info->mp2DispHorSize = (val>>15) & 0x3fff;
  1175. if (pDecInfo->userDataEnable) {
  1176. Uint32 userDataNum = 0;
  1177. Uint32 userDataSize = 0;
  1178. BYTE tempBuf[8] = {0,};
  1179. // user data
  1180. VpuReadMem(pCodecInst->coreIdx, pDecInfo->userDataBufAddr, tempBuf, 8, VPU_USER_DATA_ENDIAN);
  1181. val = ((tempBuf[0]<<24) & 0xFF000000) |
  1182. ((tempBuf[1]<<16) & 0x00FF0000) |
  1183. ((tempBuf[2]<< 8) & 0x0000FF00) |
  1184. ((tempBuf[3]<< 0) & 0x000000FF);
  1185. userDataNum = (val >> 16) & 0xFFFF;
  1186. userDataSize = (val >> 0) & 0xFFFF;
  1187. if (userDataNum == 0) {
  1188. userDataSize = 0;
  1189. }
  1190. info->userDataNum = userDataNum;
  1191. info->userDataSize = userDataSize;
  1192. val = ((tempBuf[4]<<24) & 0xFF000000) |
  1193. ((tempBuf[5]<<16) & 0x00FF0000) |
  1194. ((tempBuf[6]<< 8) & 0x0000FF00) |
  1195. ((tempBuf[7]<< 0) & 0x000000FF);
  1196. if (userDataNum == 0) {
  1197. info->userDataBufFull = 0;
  1198. }
  1199. else {
  1200. info->userDataBufFull = (val >> 16) & 0xFFFF;
  1201. }
  1202. }
  1203. }
  1204. return RETCODE_SUCCESS;
  1205. }
  1206. RetCode Coda9VpuDecRegisterFramebuffer(CodecInst* instance)
  1207. {
  1208. CodecInst* pCodecInst;
  1209. DecInfo* pDecInfo;
  1210. PhysicalAddress paraBuffer;
  1211. vpu_buffer_t vb;
  1212. Uint32 val;
  1213. int i;
  1214. BYTE frameAddr[MAX_GDI_IDX][3][4];
  1215. BYTE colMvAddr[MAX_GDI_IDX][4];
  1216. pCodecInst = instance;
  1217. pDecInfo = &pCodecInst->CodecInfo->decInfo;
  1218. vdi_get_common_memory(pCodecInst->coreIdx, &vb);
  1219. paraBuffer = vb.phys_addr + CODE_BUF_SIZE + TEMP_BUF_SIZE;
  1220. pDecInfo->mapCfg.productId = pCodecInst->productId;
  1221. if (pDecInfo->mapType != LINEAR_FRAME_MAP && pDecInfo->mapType != LINEAR_FIELD_MAP) {
  1222. val = SetTiledMapType(pCodecInst->coreIdx, &pDecInfo->mapCfg, pDecInfo->mapType, (pDecInfo->stride > pDecInfo->frameBufferHeight)?pDecInfo->stride:pDecInfo->frameBufferHeight,
  1223. pDecInfo->openParam.cbcrInterleave, &pDecInfo->dramCfg);
  1224. }
  1225. else {
  1226. val = SetTiledMapType(pCodecInst->coreIdx, &pDecInfo->mapCfg, pDecInfo->mapType,pDecInfo->stride, pDecInfo->openParam.cbcrInterleave, &pDecInfo->dramCfg);
  1227. }
  1228. if (val == 0) {
  1229. return RETCODE_INVALID_PARAM;
  1230. }
  1231. //Allocate frame buffer
  1232. for (i=0; i<pDecInfo->numFbsForDecoding; i++) {
  1233. frameAddr[i][0][0] = (pDecInfo->frameBufPool[i].bufY >> 24) & 0xFF;
  1234. frameAddr[i][0][1] = (pDecInfo->frameBufPool[i].bufY >> 16) & 0xFF;
  1235. frameAddr[i][0][2] = (pDecInfo->frameBufPool[i].bufY >> 8) & 0xFF;
  1236. frameAddr[i][0][3] = (pDecInfo->frameBufPool[i].bufY >> 0) & 0xFF;
  1237. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1238. frameAddr[i][1][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1239. frameAddr[i][1][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1240. frameAddr[i][1][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1241. frameAddr[i][1][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1242. frameAddr[i][2][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1243. frameAddr[i][2][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1244. frameAddr[i][2][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1245. frameAddr[i][2][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1246. }
  1247. else {
  1248. frameAddr[i][2][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1249. frameAddr[i][2][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1250. frameAddr[i][2][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1251. frameAddr[i][2][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1252. frameAddr[i][1][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1253. frameAddr[i][1][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1254. frameAddr[i][1][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1255. frameAddr[i][1][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1256. }
  1257. }
  1258. VpuWriteMem(pCodecInst->coreIdx, paraBuffer, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1259. // MV allocation and register
  1260. if (pCodecInst->codecMode == AVC_DEC || pCodecInst->codecMode == VC1_DEC || pCodecInst->codecMode == MP4_DEC ||
  1261. pCodecInst->codecMode == RV_DEC || pCodecInst->codecMode == AVS_DEC)
  1262. {
  1263. int size_mvcolbuf;
  1264. vpu_buffer_t vbBuffer;
  1265. size_mvcolbuf = ((pDecInfo->initialInfo.picWidth+31)&~31)*((pDecInfo->initialInfo.picHeight+31)&~31);
  1266. size_mvcolbuf = (size_mvcolbuf*3)/2;
  1267. size_mvcolbuf = (size_mvcolbuf+4)/5;
  1268. size_mvcolbuf = ((size_mvcolbuf+7)/8)*8;
  1269. vbBuffer.size = size_mvcolbuf;
  1270. vbBuffer.phys_addr = 0;
  1271. for (i=0 ; i<pDecInfo->numFbsForDecoding ; i++) {
  1272. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, &vbBuffer, DEC_MV, pCodecInst->instIndex)<0){
  1273. return RETCODE_FAILURE;
  1274. }
  1275. pDecInfo->vbMV[i] = vbBuffer;
  1276. }
  1277. if (pCodecInst->codecMode == AVC_DEC) {
  1278. for (i=0; i<pDecInfo->numFbsForDecoding; i++) {
  1279. colMvAddr[i][0] = (pDecInfo->vbMV[i].phys_addr >> 24) & 0xFF;
  1280. colMvAddr[i][1] = (pDecInfo->vbMV[i].phys_addr >> 16) & 0xFF;
  1281. colMvAddr[i][2] = (pDecInfo->vbMV[i].phys_addr >> 8) & 0xFF;
  1282. colMvAddr[i][3] = (pDecInfo->vbMV[i].phys_addr >> 0) & 0xFF;
  1283. }
  1284. }
  1285. else {
  1286. colMvAddr[0][0] = (pDecInfo->vbMV[0].phys_addr >> 24) & 0xFF;
  1287. colMvAddr[0][1] = (pDecInfo->vbMV[0].phys_addr >> 16) & 0xFF;
  1288. colMvAddr[0][2] = (pDecInfo->vbMV[0].phys_addr >> 8) & 0xFF;
  1289. colMvAddr[0][3] = (pDecInfo->vbMV[0].phys_addr >> 0) & 0xFF;
  1290. }
  1291. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384, (BYTE*)colMvAddr, sizeof(colMvAddr), VDI_BIG_ENDIAN);
  1292. }
  1293. if (pCodecInst->productId == PRODUCT_ID_980) {
  1294. for (i=0; i<pDecInfo->numFbsForDecoding; i++) {
  1295. frameAddr[i][0][0] = (pDecInfo->frameBufPool[i].bufYBot >> 24) & 0xFF;
  1296. frameAddr[i][0][1] = (pDecInfo->frameBufPool[i].bufYBot >> 16) & 0xFF;
  1297. frameAddr[i][0][2] = (pDecInfo->frameBufPool[i].bufYBot >> 8) & 0xFF;
  1298. frameAddr[i][0][3] = (pDecInfo->frameBufPool[i].bufYBot >> 0) & 0xFF;
  1299. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1300. frameAddr[i][1][0] = (pDecInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1301. frameAddr[i][1][1] = (pDecInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1302. frameAddr[i][1][2] = (pDecInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1303. frameAddr[i][1][3] = (pDecInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1304. frameAddr[i][2][0] = (pDecInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1305. frameAddr[i][2][1] = (pDecInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1306. frameAddr[i][2][2] = (pDecInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1307. frameAddr[i][2][3] = (pDecInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1308. }
  1309. else {
  1310. frameAddr[i][2][0] = (pDecInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1311. frameAddr[i][2][1] = (pDecInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1312. frameAddr[i][2][2] = (pDecInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1313. frameAddr[i][2][3] = (pDecInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1314. frameAddr[i][1][0] = (pDecInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1315. frameAddr[i][1][1] = (pDecInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1316. frameAddr[i][1][2] = (pDecInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1317. frameAddr[i][1][3] = (pDecInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1318. }
  1319. }
  1320. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1321. if (pDecInfo->wtlEnable) {
  1322. int num = pDecInfo->numFbsForDecoding; /* start index of WTL fb array */
  1323. int end = pDecInfo->numFrameBuffers;
  1324. for (i=num; i<end; i++) {
  1325. frameAddr[i-num][0][0] = (pDecInfo->frameBufPool[i].bufY >> 24) & 0xFF;
  1326. frameAddr[i-num][0][1] = (pDecInfo->frameBufPool[i].bufY >> 16) & 0xFF;
  1327. frameAddr[i-num][0][2] = (pDecInfo->frameBufPool[i].bufY >> 8) & 0xFF;
  1328. frameAddr[i-num][0][3] = (pDecInfo->frameBufPool[i].bufY >> 0) & 0xFF;
  1329. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1330. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1331. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1332. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1333. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1334. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1335. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1336. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1337. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1338. }
  1339. else {
  1340. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1341. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1342. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1343. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1344. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1345. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1346. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1347. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1348. }
  1349. }
  1350. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128+384, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1351. if (pDecInfo->wtlMode == FF_FIELD ) {
  1352. for (i=num; i<num*2; i++) {
  1353. frameAddr[i-num][0][0] = (pDecInfo->frameBufPool[i].bufYBot >> 24) & 0xFF;
  1354. frameAddr[i-num][0][1] = (pDecInfo->frameBufPool[i].bufYBot >> 16) & 0xFF;
  1355. frameAddr[i-num][0][2] = (pDecInfo->frameBufPool[i].bufYBot >> 8) & 0xFF;
  1356. frameAddr[i-num][0][3] = (pDecInfo->frameBufPool[i].bufYBot >> 0) & 0xFF;
  1357. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1358. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1359. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1360. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1361. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1362. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1363. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1364. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1365. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1366. }
  1367. else {
  1368. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1369. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1370. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1371. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1372. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1373. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1374. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1375. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1376. }
  1377. }
  1378. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128+384+384, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1379. }
  1380. }
  1381. }
  1382. else {
  1383. if (pDecInfo->wtlEnable) {
  1384. int num = pDecInfo->numFbsForDecoding; /* start index of WTL fb array */
  1385. int end = pDecInfo->numFrameBuffers;
  1386. for (i=num; i<end; i++) {
  1387. frameAddr[i-num][0][0] = (pDecInfo->frameBufPool[i].bufY >> 24) & 0xFF;
  1388. frameAddr[i-num][0][1] = (pDecInfo->frameBufPool[i].bufY >> 16) & 0xFF;
  1389. frameAddr[i-num][0][2] = (pDecInfo->frameBufPool[i].bufY >> 8) & 0xFF;
  1390. frameAddr[i-num][0][3] = (pDecInfo->frameBufPool[i].bufY >> 0) & 0xFF;
  1391. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1392. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1393. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1394. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1395. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1396. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1397. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1398. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1399. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1400. }
  1401. else {
  1402. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1403. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1404. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1405. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1406. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1407. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1408. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1409. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1410. }
  1411. }
  1412. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128+384, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1413. }
  1414. }
  1415. if (!ConfigSecAXICoda9(pCodecInst->coreIdx, pCodecInst->codecMode, &pDecInfo->secAxiInfo, pDecInfo->initialInfo.picWidth,
  1416. pDecInfo->frameBufferHeight, pDecInfo->initialInfo.profile&0xff)) {
  1417. return RETCODE_INSUFFICIENT_RESOURCE;
  1418. }
  1419. // Tell the decoder how much frame buffers were allocated.
  1420. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_BUF_NUM, pDecInfo->numFrameBuffers);
  1421. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_BUF_STRIDE, pDecInfo->stride);
  1422. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_BIT_ADDR, pDecInfo->secAxiInfo.u.coda9.bufBitUse);
  1423. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_IPACDC_ADDR, pDecInfo->secAxiInfo.u.coda9.bufIpAcDcUse);
  1424. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_DBKY_ADDR, pDecInfo->secAxiInfo.u.coda9.bufDbkYUse);
  1425. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_DBKC_ADDR, pDecInfo->secAxiInfo.u.coda9.bufDbkCUse);
  1426. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_OVL_ADDR, pDecInfo->secAxiInfo.u.coda9.bufOvlUse);
  1427. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_BTP_ADDR, pDecInfo->secAxiInfo.u.coda9.bufBtpUse);
  1428. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_DELAY, pDecInfo->frameDelay);
  1429. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_CACHE_CONFIG, pDecInfo->cacheConfig.type2.CacheMode);
  1430. if (pCodecInst->codecMode == VPX_DEC) {
  1431. vpu_buffer_t *pvbSlice = &pDecInfo->vbSlice;
  1432. if (pvbSlice->size == 0) {
  1433. pvbSlice->size = VP8_MB_SAVE_SIZE;
  1434. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, pvbSlice, DEC_ETC, pCodecInst->instIndex) < 0) {
  1435. return RETCODE_INSUFFICIENT_RESOURCE;
  1436. }
  1437. }
  1438. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_MB_BUF_BASE, pvbSlice->phys_addr);
  1439. }
  1440. if (pCodecInst->codecMode == AVC_DEC) {
  1441. vpu_buffer_t *pvbSlice = &pDecInfo->vbSlice;
  1442. if (pvbSlice->size == 0) {
  1443. pvbSlice->size = SLICE_SAVE_SIZE;
  1444. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, pvbSlice, DEC_ETC, pCodecInst->instIndex) < 0) {
  1445. return RETCODE_INSUFFICIENT_RESOURCE;
  1446. }
  1447. }
  1448. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SLICE_BB_START, pvbSlice->phys_addr);
  1449. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SLICE_BB_SIZE, (pvbSlice->size/1024));
  1450. }
  1451. if (pCodecInst->productId == PRODUCT_ID_980) {
  1452. val = 0;
  1453. val |= (pDecInfo->openParam.bwbEnable<<15);
  1454. val |= (pDecInfo->wtlMode<<17)|(pDecInfo->tiled2LinearMode<<13)|(pDecInfo->mapType<<9)|(FORMAT_420<<6);
  1455. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  1456. val |= pDecInfo->openParam.frameEndian;
  1457. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  1458. }
  1459. else if (pCodecInst->productId == PRODUCT_ID_960) {
  1460. val = 0;
  1461. val |= (pDecInfo->wtlEnable<<17);
  1462. val |= (pDecInfo->openParam.bwbEnable<<12);
  1463. if (pDecInfo->mapType) {
  1464. if (pDecInfo->mapType == TILED_FRAME_MB_RASTER_MAP || pDecInfo->mapType == TILED_FIELD_MB_RASTER_MAP)
  1465. val |= (pDecInfo->tiled2LinearEnable<<11)|(0x03<<9)|(FORMAT_420<<6);
  1466. else
  1467. val |= (pDecInfo->tiled2LinearEnable<<11)|(0x02<<9)|(FORMAT_420<<6);
  1468. }
  1469. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  1470. val |= pDecInfo->openParam.frameEndian;
  1471. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  1472. }
  1473. else {
  1474. return RETCODE_NOT_FOUND_VPU_DEVICE;
  1475. }
  1476. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_MAX_DEC_SIZE, 0);
  1477. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, SET_FRAME_BUF);
  1478. if (vdi_wait_vpu_busy(pCodecInst->coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  1479. if (pCodecInst->loggingEnable)
  1480. vdi_log(pCodecInst->coreIdx, SET_FRAME_BUF, 2);
  1481. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1482. }
  1483. if (pCodecInst->loggingEnable)
  1484. vdi_log(pCodecInst->coreIdx, SET_FRAME_BUF, 0);
  1485. if (VpuReadReg(pCodecInst->coreIdx, RET_SET_FRAME_SUCCESS) & (1UL<<31)) {
  1486. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1487. }
  1488. return RETCODE_SUCCESS;
  1489. }
  1490. RetCode Coda9VpuDecFlush(CodecInst* instance, FramebufferIndex* framebufferIndexes, Uint32 size)
  1491. {
  1492. Uint32 i;
  1493. DecInfo* pDecInfo = &instance->CodecInfo->decInfo;
  1494. Coda9BitIssueCommand(instance->coreIdx, instance, DEC_BUF_FLUSH);
  1495. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  1496. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1497. }
  1498. pDecInfo->frameDisplayFlag = 0;
  1499. if (framebufferIndexes != NULL) {
  1500. for (i=0; i<size; i++) {
  1501. framebufferIndexes[i].linearIndex = -2;
  1502. framebufferIndexes[i].tiledIndex = -2;
  1503. }
  1504. }
  1505. return RETCODE_SUCCESS;
  1506. }
  1507. /************************************************************************/
  1508. /* Encoder */
  1509. /************************************************************************/
  1510. RetCode Coda9VpuBuildUpEncParam(CodecInst* pCodec, EncOpenParam* param)
  1511. {
  1512. RetCode ret = RETCODE_SUCCESS;
  1513. Uint32 coreIdx;
  1514. Int32 productId;
  1515. EncInfo* pEncInfo = &pCodec->CodecInfo->encInfo;
  1516. coreIdx = pCodec->coreIdx;
  1517. productId = Coda9VpuGetProductId(coreIdx);
  1518. if ((ret=SetupEncCodecInstance(productId, pCodec)) != RETCODE_SUCCESS)
  1519. return ret;
  1520. if (param->bitstreamFormat == STD_MPEG4 || param->bitstreamFormat == STD_H263)
  1521. pCodec->codecMode = MP4_ENC;
  1522. else if (param->bitstreamFormat == STD_AVC)
  1523. pCodec->codecMode = AVC_ENC;
  1524. pCodec->codecModeAux = 0;
  1525. if (productId == PRODUCT_ID_980) {
  1526. pEncInfo->ActivePPSIdx = 0;
  1527. pEncInfo->frameIdx = 0;
  1528. pEncInfo->fieldDone = 0;
  1529. }
  1530. pEncInfo->vbWork.size = WORK_BUF_SIZE;
  1531. if (vdi_allocate_dma_memory(pCodec->coreIdx, &pEncInfo->vbWork, ENC_WORK, pCodec->instIndex) < 0)
  1532. return RETCODE_INSUFFICIENT_RESOURCE;
  1533. pEncInfo->streamRdPtr = param->bitstreamBuffer;
  1534. pEncInfo->streamWrPtr = param->bitstreamBuffer;
  1535. pEncInfo->lineBufIntEn = param->lineBufIntEn;
  1536. pEncInfo->streamBufStartAddr = param->bitstreamBuffer;
  1537. pEncInfo->streamBufSize = param->bitstreamBufferSize;
  1538. pEncInfo->streamBufEndAddr = param->bitstreamBuffer + param->bitstreamBufferSize;
  1539. pEncInfo->stride = 0;
  1540. pEncInfo->vbFrame.size = 0;
  1541. pEncInfo->vbPPU.size = 0;
  1542. pEncInfo->frameAllocExt = 0;
  1543. pEncInfo->ppuAllocExt = 0;
  1544. pEncInfo->secAxiInfo.u.coda9.useBitEnable = 0;
  1545. pEncInfo->secAxiInfo.u.coda9.useIpEnable = 0;
  1546. pEncInfo->secAxiInfo.u.coda9.useDbkYEnable = 0;
  1547. pEncInfo->secAxiInfo.u.coda9.useDbkCEnable = 0;
  1548. pEncInfo->secAxiInfo.u.coda9.useOvlEnable = 0;
  1549. pEncInfo->rotationEnable = 0;
  1550. pEncInfo->mirrorEnable = 0;
  1551. pEncInfo->mirrorDirection = MIRDIR_NONE;
  1552. pEncInfo->rotationAngle = 0;
  1553. pEncInfo->initialInfoObtained = 0;
  1554. pEncInfo->ringBufferEnable = param->ringBufferEnable;
  1555. pEncInfo->linear2TiledEnable = param->linear2TiledEnable;
  1556. pEncInfo->linear2TiledMode = param->linear2TiledMode; // coda980 only
  1557. if (!pEncInfo->linear2TiledEnable)
  1558. pEncInfo->linear2TiledMode = 0;
  1559. /* Maverick Cache I */
  1560. osal_memset((void*)&pEncInfo->cacheConfig, 0x00, sizeof(MaverickCacheConfig));
  1561. if (productId == PRODUCT_ID_960) {
  1562. pEncInfo->dramCfg.bankBit = EM_BANK;
  1563. pEncInfo->dramCfg.casBit = EM_CAS;
  1564. pEncInfo->dramCfg.rasBit = EM_RAS;
  1565. pEncInfo->dramCfg.busBit = EM_WIDTH;
  1566. }
  1567. return ret;
  1568. }
  1569. RetCode Coda9VpuEncSetup(CodecInst* pCodecInst)
  1570. {
  1571. Int32 picWidth, picHeight;
  1572. Int32 data, val;
  1573. Int32 productId, rcEnable;
  1574. EncInfo* pEncInfo = &pCodecInst->CodecInfo->encInfo;
  1575. rcEnable = pEncInfo->openParam.rcEnable&0xf;
  1576. productId = pCodecInst->productId;
  1577. picWidth = pEncInfo->openParam.picWidth;
  1578. picHeight = pEncInfo->openParam.picHeight;
  1579. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_BB_START, pEncInfo->streamBufStartAddr);
  1580. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_BB_SIZE, pEncInfo->streamBufSize / 1024); // size in KB
  1581. // Rotation Left 90 or 270 case : Swap XY resolution for VPU internal usage
  1582. if (pEncInfo->rotationAngle == 90 || pEncInfo->rotationAngle == 270)
  1583. data = (picHeight<< 16) | picWidth;
  1584. else
  1585. data = (picWidth << 16) | picHeight;
  1586. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_SRC_SIZE, data);
  1587. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_SRC_F_RATE, pEncInfo->openParam.frameRateInfo);
  1588. if (pEncInfo->openParam.bitstreamFormat == STD_MPEG4) {
  1589. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_COD_STD, 3);
  1590. data = pEncInfo->openParam.EncStdParam.mp4Param.mp4IntraDcVlcThr << 2 |
  1591. pEncInfo->openParam.EncStdParam.mp4Param.mp4ReversibleVlcEnable << 1 |
  1592. pEncInfo->openParam.EncStdParam.mp4Param.mp4DataPartitionEnable;
  1593. data |= ((pEncInfo->openParam.EncStdParam.mp4Param.mp4HecEnable >0)? 1:0)<<5;
  1594. data |= ((pEncInfo->openParam.EncStdParam.mp4Param.mp4Verid == 2)? 0:1) << 6;
  1595. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_MP4_PARA, data);
  1596. if (productId == PRODUCT_ID_980)
  1597. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (VPU_ME_LINEBUFFER_MODE << 9) |
  1598. (pEncInfo->openParam.meBlkMode << 5) |
  1599. (pEncInfo->openParam.MEUseZeroPmv << 4) |
  1600. (pEncInfo->openParam.MESearchRangeY<<2) |
  1601. pEncInfo->openParam.MESearchRangeX);
  1602. else
  1603. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (pEncInfo->openParam.meBlkMode << 3) |
  1604. (pEncInfo->openParam.MEUseZeroPmv << 2) |
  1605. pEncInfo->openParam.MESearchRange);
  1606. }
  1607. else if (pEncInfo->openParam.bitstreamFormat == STD_H263) {
  1608. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_COD_STD, 11);
  1609. data = pEncInfo->openParam.EncStdParam.h263Param.h263AnnexIEnable << 3 |
  1610. pEncInfo->openParam.EncStdParam.h263Param.h263AnnexJEnable << 2 |
  1611. pEncInfo->openParam.EncStdParam.h263Param.h263AnnexKEnable << 1|
  1612. pEncInfo->openParam.EncStdParam.h263Param.h263AnnexTEnable;
  1613. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_263_PARA, data);
  1614. if (productId == PRODUCT_ID_980)
  1615. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (VPU_ME_LINEBUFFER_MODE << 9) |
  1616. (pEncInfo->openParam.meBlkMode << 5) |
  1617. (pEncInfo->openParam.MEUseZeroPmv << 4) |
  1618. (pEncInfo->openParam.MESearchRangeY<<2) |
  1619. pEncInfo->openParam.MESearchRangeX);
  1620. else
  1621. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (pEncInfo->openParam.meBlkMode << 3) |
  1622. (pEncInfo->openParam.MEUseZeroPmv << 2) |
  1623. pEncInfo->openParam.MESearchRange);
  1624. }
  1625. else if (pEncInfo->openParam.bitstreamFormat == STD_AVC) {
  1626. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_COD_STD, 0x0);
  1627. data = (pEncInfo->openParam.EncStdParam.avcParam.deblkFilterOffsetBeta & 15) << 12 |
  1628. (pEncInfo->openParam.EncStdParam.avcParam.deblkFilterOffsetAlpha & 15) << 8 |
  1629. pEncInfo->openParam.EncStdParam.avcParam.disableDeblk << 6 |
  1630. pEncInfo->openParam.EncStdParam.avcParam.constrainedIntraPredFlag << 5 |
  1631. (pEncInfo->openParam.EncStdParam.avcParam.chromaQpOffset & 31);
  1632. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_264_PARA, data);
  1633. if (productId == PRODUCT_ID_980) {
  1634. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (VPU_ME_LINEBUFFER_MODE << 9) |
  1635. (pEncInfo->openParam.meBlkMode << 5) |
  1636. (pEncInfo->openParam.MEUseZeroPmv << 4) |
  1637. (pEncInfo->openParam.MESearchRangeY<<2) |
  1638. pEncInfo->openParam.MESearchRangeX);
  1639. }
  1640. else {
  1641. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (pEncInfo->openParam.meBlkMode << 3) | (pEncInfo->openParam.MEUseZeroPmv << 2) | pEncInfo->openParam.MESearchRange);
  1642. }
  1643. }
  1644. if (productId == PRODUCT_ID_980) {
  1645. data = 0;
  1646. if (pEncInfo->openParam.sliceMode.sliceMode!=0) {
  1647. data = pEncInfo->openParam.sliceMode.sliceSize << 2 |
  1648. (pEncInfo->openParam.sliceMode.sliceSizeMode+1); // encoding mode 0,1,2
  1649. }
  1650. }
  1651. else {
  1652. data = pEncInfo->openParam.sliceMode.sliceSize << 2 |
  1653. pEncInfo->openParam.sliceMode.sliceSizeMode << 1 |
  1654. pEncInfo->openParam.sliceMode.sliceMode;
  1655. }
  1656. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_SLICE_MODE, data);
  1657. if (rcEnable) { // rate control enabled
  1658. if (productId == PRODUCT_ID_980) {
  1659. if (pEncInfo->openParam.bitstreamFormat == STD_AVC) {
  1660. int MinDeltaQp, MaxDeltaQp, QpMin, QpMax;
  1661. data = (pEncInfo->openParam.idrInterval << 21) | (pEncInfo->openParam.rcGopIQpOffsetEn<<20) | ((pEncInfo->openParam.rcGopIQpOffset & 0xF)<<16) | pEncInfo->openParam.gopSize ;
  1662. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, data);
  1663. data = (pEncInfo->openParam.frameSkipDisable) << 31 |
  1664. pEncInfo->openParam.rcInitDelay << 16 | 0;
  1665. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, data);
  1666. data = (pEncInfo->openParam.bitRate<<4)|(rcEnable);
  1667. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA2, data);
  1668. data = 0;
  1669. if (pEncInfo->openParam.maxIntraSize>0)
  1670. data = (1<<16) | (pEncInfo->openParam.maxIntraSize & 0xFFFF);
  1671. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_MAX_INTRA_SIZE, data);
  1672. if (pEncInfo->openParam.userMinDeltaQp<0)
  1673. MinDeltaQp = 0;
  1674. else
  1675. MinDeltaQp = (1<<6)|pEncInfo->openParam.userMinDeltaQp;
  1676. if (pEncInfo->openParam.userMaxDeltaQp<0)
  1677. MaxDeltaQp = 0;
  1678. else
  1679. MaxDeltaQp = (1<<6)|pEncInfo->openParam.userMaxDeltaQp;
  1680. if (pEncInfo->openParam.userQpMin<0)
  1681. QpMin = 0;
  1682. else
  1683. QpMin = (1<<6)|pEncInfo->openParam.userQpMin;
  1684. if (pEncInfo->openParam.userQpMax<0)
  1685. QpMax = 0;
  1686. else
  1687. QpMax = (1<<6)|pEncInfo->openParam.userQpMax;
  1688. data = MinDeltaQp<<24 | MaxDeltaQp<<16 | QpMin<<8 | QpMax;
  1689. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_QP_RANGE_SET, data);
  1690. }
  1691. else { // MP4
  1692. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, pEncInfo->openParam.gopSize);
  1693. data = (pEncInfo->openParam.frameSkipDisable) << 31 |
  1694. pEncInfo->openParam.rcInitDelay << 16 |
  1695. pEncInfo->openParam.bitRate<<1 | 1;
  1696. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, data);
  1697. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_QP_RANGE_SET, 0);
  1698. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA2, 0);
  1699. }
  1700. }
  1701. else {
  1702. /* coda960 ENCODER */
  1703. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, pEncInfo->openParam.gopSize);
  1704. data = (pEncInfo->openParam.frameSkipDisable) << 31 |
  1705. pEncInfo->openParam.rcInitDelay << 16 |
  1706. pEncInfo->openParam.bitRate<<1 | 1;
  1707. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, data);
  1708. }
  1709. }
  1710. else {
  1711. if (pEncInfo->openParam.bitstreamFormat == STD_AVC)
  1712. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, (pEncInfo->openParam.idrInterval << 21) | pEncInfo->openParam.gopSize);
  1713. else
  1714. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, pEncInfo->openParam.gopSize);
  1715. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, 0);
  1716. if (productId == PRODUCT_ID_980) {
  1717. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_QP_RANGE_SET, 0);
  1718. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA2, 0);
  1719. }
  1720. }
  1721. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_BUF_SIZE, pEncInfo->openParam.vbvBufferSize);
  1722. data = pEncInfo->openParam.intraRefreshNum | pEncInfo->openParam.ConscIntraRefreshEnable<<16;
  1723. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_INTRA_REFRESH, data);
  1724. data = 0;
  1725. if(pEncInfo->openParam.rcIntraQp>=0) {
  1726. data = (1 << 5);
  1727. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_INTRA_QP, pEncInfo->openParam.rcIntraQp);
  1728. }
  1729. else {
  1730. data = 0;
  1731. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_INTRA_QP, (Uint32)-1);
  1732. }
  1733. if (pCodecInst->codecMode == AVC_ENC) {
  1734. data |= (pEncInfo->openParam.EncStdParam.avcParam.audEnable << 2);
  1735. }
  1736. if(pEncInfo->openParam.userQpMax>=0) {
  1737. data |= (1<<6);
  1738. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_QP_MAX, pEncInfo->openParam.userQpMax);
  1739. }
  1740. else {
  1741. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_QP_MAX, 0);
  1742. }
  1743. if(pEncInfo->openParam.userGamma >= 0) {
  1744. data |= (1<<7);
  1745. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_GAMMA, pEncInfo->openParam.userGamma);
  1746. }
  1747. else {
  1748. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_GAMMA, 0);
  1749. }
  1750. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_OPTION, data);
  1751. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_INTERVAL_MODE, (pEncInfo->openParam.mbInterval<<2) | pEncInfo->openParam.rcIntervalMode);
  1752. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_INTRA_WEIGHT, pEncInfo->openParam.intraCostWeight);
  1753. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr, pEncInfo->streamWrPtr);
  1754. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamRdPtrRegAddr, pEncInfo->streamRdPtr);
  1755. SetEncFrameMemInfo(pCodecInst);
  1756. val = 0;
  1757. if (pEncInfo->ringBufferEnable == 0) {
  1758. if (pEncInfo->lineBufIntEn)
  1759. val |= (0x1<<6);
  1760. val |= (0x1<<5);
  1761. val |= (0x1<<4);
  1762. }
  1763. else {
  1764. val |= (0x1<<3);
  1765. }
  1766. val |= pEncInfo->openParam.streamEndian;
  1767. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_CTRL, val);
  1768. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, ENC_SEQ_INIT);
  1769. #ifdef SUPPORT_MULTI_INST_INTR
  1770. if (vdi_wait_interrupt(pCodecInst->coreIdx, 0, __VPU_BUSY_TIMEOUT) == -1) {
  1771. #else
  1772. if (vdi_wait_interrupt(pCodecInst->coreIdx, __VPU_BUSY_TIMEOUT) == -1) {
  1773. #endif
  1774. if (pCodecInst->loggingEnable)
  1775. vdi_log(pCodecInst->coreIdx, ENC_SEQ_INIT, 2);
  1776. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1777. }
  1778. VpuWriteReg(pCodecInst->coreIdx, BIT_INT_CLEAR, 1); // that is OK. HW signal already is clear by device driver
  1779. VpuWriteReg(pCodecInst->coreIdx, BIT_INT_REASON, 0);
  1780. if (pCodecInst->loggingEnable)
  1781. vdi_log(pCodecInst->coreIdx, ENC_SEQ_INIT, 0);
  1782. if (VpuReadReg(pCodecInst->coreIdx, RET_ENC_SEQ_END_SUCCESS) & (1UL<<31))
  1783. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1784. if (VpuReadReg(pCodecInst->coreIdx, RET_ENC_SEQ_END_SUCCESS) == 0)
  1785. return RETCODE_FAILURE;
  1786. pEncInfo->streamWrPtr = VpuReadReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr);
  1787. pEncInfo->streamEndflag = VpuReadReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM);
  1788. return RETCODE_SUCCESS;
  1789. }
  1790. RetCode Coda9VpuEncRegisterFramebuffer(CodecInst* instance)
  1791. {
  1792. CodecInst* pCodecInst = instance;
  1793. EncInfo* pEncInfo;
  1794. Int32 i, val;
  1795. RetCode ret;
  1796. PhysicalAddress paraBuffer;
  1797. BYTE frameAddr[MAX_FRAMEBUFFER_COUNT][3][4];
  1798. Int32 stride, height, mapType, num;
  1799. VpuAttr* pAttr = &g_VpuCoreAttributes[instance->coreIdx];
  1800. pEncInfo = &instance->CodecInfo->encInfo;
  1801. stride = pEncInfo->stride;
  1802. height = pEncInfo->frameBufferHeight;
  1803. mapType = pEncInfo->mapType;
  1804. if (pCodecInst->productId == PRODUCT_ID_960) {
  1805. pEncInfo->mapCfg.tiledBaseAddr = pEncInfo->vbFrame.phys_addr;
  1806. }
  1807. if (!ConfigSecAXICoda9(pCodecInst->coreIdx, instance->codecMode, &pEncInfo->secAxiInfo, stride, height, 0))
  1808. return RETCODE_INSUFFICIENT_RESOURCE;
  1809. if (pCodecInst->productId == PRODUCT_ID_960) {
  1810. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, mapType,stride, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  1811. }
  1812. else {
  1813. if (mapType != LINEAR_FRAME_MAP && mapType != LINEAR_FIELD_MAP)
  1814. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, mapType, (stride > height)?stride:height, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  1815. else
  1816. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, mapType,stride, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  1817. }
  1818. if (val == 0)
  1819. return RETCODE_INVALID_PARAM;
  1820. SetEncFrameMemInfo(pCodecInst);
  1821. paraBuffer = VpuReadReg(pCodecInst->coreIdx, BIT_PARA_BUF_ADDR);
  1822. // Let the decoder know the addresses of the frame buffers.
  1823. for (i=0; i<pEncInfo->numFrameBuffers; i++)
  1824. {
  1825. frameAddr[i][0][0] = (pEncInfo->frameBufPool[i].bufY >> 24) & 0xFF;
  1826. frameAddr[i][0][1] = (pEncInfo->frameBufPool[i].bufY >> 16) & 0xFF;
  1827. frameAddr[i][0][2] = (pEncInfo->frameBufPool[i].bufY >> 8) & 0xFF;
  1828. frameAddr[i][0][3] = (pEncInfo->frameBufPool[i].bufY >> 0) & 0xFF;
  1829. frameAddr[i][1][0] = (pEncInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1830. frameAddr[i][1][1] = (pEncInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1831. frameAddr[i][1][2] = (pEncInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1832. frameAddr[i][1][3] = (pEncInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1833. frameAddr[i][2][0] = (pEncInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1834. frameAddr[i][2][1] = (pEncInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1835. frameAddr[i][2][2] = (pEncInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1836. frameAddr[i][2][3] = (pEncInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1837. }
  1838. VpuWriteMem(pCodecInst->coreIdx, paraBuffer, (BYTE *)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1839. if (pCodecInst->productId == PRODUCT_ID_980) {
  1840. for (i=0; i<pEncInfo->numFrameBuffers; i++) {
  1841. frameAddr[i][0][0] = (pEncInfo->frameBufPool[i].bufYBot >> 24) & 0xFF;
  1842. frameAddr[i][0][1] = (pEncInfo->frameBufPool[i].bufYBot >> 16) & 0xFF;
  1843. frameAddr[i][0][2] = (pEncInfo->frameBufPool[i].bufYBot >> 8) & 0xFF;
  1844. frameAddr[i][0][3] = (pEncInfo->frameBufPool[i].bufYBot >> 0) & 0xFF;
  1845. frameAddr[i][1][0] = (pEncInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1846. frameAddr[i][1][1] = (pEncInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1847. frameAddr[i][1][2] = (pEncInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1848. frameAddr[i][1][3] = (pEncInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1849. frameAddr[i][2][0] = (pEncInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1850. frameAddr[i][2][1] = (pEncInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1851. frameAddr[i][2][2] = (pEncInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1852. frameAddr[i][2][3] = (pEncInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1853. }
  1854. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128, (BYTE *)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1855. }
  1856. // Tell the codec how much frame buffers were allocated.
  1857. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_BUF_NUM, pEncInfo->numFrameBuffers);
  1858. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_BUF_STRIDE, stride);
  1859. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_BIT_ADDR, pEncInfo->secAxiInfo.u.coda9.bufBitUse);
  1860. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_IPACDC_ADDR, pEncInfo->secAxiInfo.u.coda9.bufIpAcDcUse);
  1861. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_DBKY_ADDR, pEncInfo->secAxiInfo.u.coda9.bufDbkYUse);
  1862. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_DBKC_ADDR, pEncInfo->secAxiInfo.u.coda9.bufDbkCUse);
  1863. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_OVL_ADDR, pEncInfo->secAxiInfo.u.coda9.bufOvlUse);
  1864. if (pAttr->framebufferCacheType == FramebufCacheMaverickII) {
  1865. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_CACHE_CONFIG, pEncInfo->cacheConfig.type2.CacheMode);
  1866. }
  1867. else if (pAttr->framebufferCacheType == FramebufCacheMaverickI) {
  1868. // Maverick Cache Configuration
  1869. val = (pEncInfo->cacheConfig.type1.luma.cfg.PageSizeX << 28) |
  1870. (pEncInfo->cacheConfig.type1.luma.cfg.PageSizeY << 24) |
  1871. (pEncInfo->cacheConfig.type1.luma.cfg.CacheSizeX << 20) |
  1872. (pEncInfo->cacheConfig.type1.luma.cfg.CacheSizeY << 16) |
  1873. (pEncInfo->cacheConfig.type1.chroma.cfg.PageSizeX << 12) |
  1874. (pEncInfo->cacheConfig.type1.chroma.cfg.PageSizeY << 8) |
  1875. (pEncInfo->cacheConfig.type1.chroma.cfg.CacheSizeX << 4) |
  1876. (pEncInfo->cacheConfig.type1.chroma.cfg.CacheSizeY << 0);
  1877. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_CACHE_SIZE, val);
  1878. val = (pEncInfo->cacheConfig.type1.Bypass << 4) |
  1879. (pEncInfo->cacheConfig.type1.DualConf << 2) |
  1880. (pEncInfo->cacheConfig.type1.PageMerge << 0);
  1881. val = val << 24;
  1882. val |= (pEncInfo->cacheConfig.type1.luma.cfg.BufferSize << 16) |
  1883. (pEncInfo->cacheConfig.type1.chroma.cfg.BufferSize << 8) |
  1884. (pEncInfo->cacheConfig.type1.chroma.cfg.BufferSize << 8);
  1885. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_CACHE_CONFIG, val);
  1886. }
  1887. num = pEncInfo->numFrameBuffers;
  1888. if (pCodecInst->productId == PRODUCT_ID_960) {
  1889. Uint32 subsampleLumaSize = stride*height;
  1890. Uint32 subsampleChromaSize = stride*height/4; // FORMAT_420
  1891. vpu_buffer_t vbBuf;
  1892. FrameBuffer* pFb;
  1893. vbBuf.size = subsampleLumaSize + 2*subsampleChromaSize;
  1894. vbBuf.phys_addr = (PhysicalAddress)0;
  1895. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, &vbBuf, ENC_ETC, pCodecInst->instIndex) < 0) {
  1896. pEncInfo->vbSubSampFrame.size = 0;
  1897. pEncInfo->vbSubSampFrame.phys_addr = 0;
  1898. return RETCODE_INSUFFICIENT_RESOURCE;
  1899. }
  1900. pFb = &pEncInfo->frameBufPool[num];
  1901. pFb->bufY = vbBuf.phys_addr;
  1902. pFb->bufCb = (PhysicalAddress)-1;
  1903. pFb->bufCr = (PhysicalAddress)-1;
  1904. pFb->updateFbInfo = TRUE;
  1905. ret = UpdateFrameBufferAddr(LINEAR_FRAME_MAP, pFb, 1, subsampleLumaSize, subsampleChromaSize);
  1906. if (ret != RETCODE_SUCCESS) {
  1907. pEncInfo->vbSubSampFrame.size = 0;
  1908. pEncInfo->vbSubSampFrame.phys_addr = 0;
  1909. return RETCODE_INSUFFICIENT_RESOURCE;
  1910. }
  1911. pEncInfo->vbSubSampFrame = vbBuf;
  1912. num++;
  1913. // Set Sub-Sampling buffer for ME-Reference and DBK-Reconstruction
  1914. // BPU will swap below two buffer internally every pic by pic
  1915. val = GetXY2AXIAddr(&pEncInfo->mapCfg, 0, 0, 0, stride, pFb);
  1916. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SUBSAMP_A, val);
  1917. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SUBSAMP_B, val+(stride*height/2));
  1918. if (pCodecInst->codecMode == AVC_ENC && pCodecInst->codecModeAux == AVC_AUX_MVC) {
  1919. vbBuf.size = subsampleLumaSize + 2*subsampleChromaSize;
  1920. vbBuf.phys_addr = (PhysicalAddress)0;
  1921. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, &vbBuf, ENC_ETC, pCodecInst->instIndex) < 0) {
  1922. pEncInfo->vbSubSampFrame.size = 0;
  1923. pEncInfo->vbSubSampFrame.phys_addr = 0;
  1924. return RETCODE_INSUFFICIENT_RESOURCE;
  1925. }
  1926. pFb = &pEncInfo->frameBufPool[num];
  1927. pFb->bufY = vbBuf.phys_addr;
  1928. pFb->bufCb = (PhysicalAddress)-1;
  1929. pFb->bufCr = (PhysicalAddress)-1;
  1930. pFb->updateFbInfo = TRUE;
  1931. ret = UpdateFrameBufferAddr(LINEAR_FRAME_MAP, pFb, 1, subsampleLumaSize, subsampleChromaSize);
  1932. if (ret != RETCODE_SUCCESS) {
  1933. pEncInfo->vbMvcSubSampFrame.size = 0;
  1934. pEncInfo->vbMvcSubSampFrame.phys_addr = 0;
  1935. return RETCODE_INSUFFICIENT_RESOURCE;
  1936. }
  1937. pEncInfo->vbMvcSubSampFrame = vbBuf;
  1938. val = GetXY2AXIAddr(&pEncInfo->mapCfg, 0, 0, 0, stride, pFb);
  1939. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SUBSAMP_A_MVC, val);
  1940. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SUBSAMP_B_MVC, val+(stride*height/2));
  1941. }
  1942. }
  1943. if (pCodecInst->codecMode == MP4_ENC) {
  1944. // MPEG4 Encoder Data-Partitioned bitstream temporal buffer
  1945. pEncInfo->vbScratch.size = SIZE_MP4ENC_DATA_PARTITION;
  1946. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, &pEncInfo->vbScratch, ENC_ETC, pCodecInst->instIndex)<0)
  1947. return RETCODE_INSUFFICIENT_RESOURCE;
  1948. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_DP_BUF_BASE, pEncInfo->vbScratch.phys_addr);
  1949. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_DP_BUF_SIZE, pEncInfo->vbScratch.size>>10);
  1950. }
  1951. SetPendingInst(pCodecInst->coreIdx, pCodecInst);
  1952. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, SET_FRAME_BUF);
  1953. if (vdi_wait_vpu_busy(pCodecInst->coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  1954. if (pCodecInst->loggingEnable)
  1955. vdi_log(pCodecInst->coreIdx, SET_FRAME_BUF, 2);
  1956. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1957. }
  1958. if (pCodecInst->loggingEnable)
  1959. vdi_log(pCodecInst->coreIdx, SET_FRAME_BUF, 0);
  1960. if (VpuReadReg(pCodecInst->coreIdx, RET_SET_FRAME_SUCCESS) & (1UL<<31)) {
  1961. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1962. }
  1963. return RETCODE_SUCCESS;
  1964. }
  1965. RetCode Coda9VpuEncode(CodecInst* pCodecInst, EncParam* param)
  1966. {
  1967. EncInfo* pEncInfo;
  1968. FrameBuffer* pSrcFrame;
  1969. Uint32 rotMirMode;
  1970. Uint32 val;
  1971. vpu_instance_pool_t *vip;
  1972. #ifdef CLIP_PIC_DELTA_QP
  1973. int row_max_dqp_minus = 0;
  1974. int row_max_dqp_plus = 0;
  1975. #endif
  1976. pEncInfo = &pCodecInst->CodecInfo->encInfo;
  1977. vip = (vpu_instance_pool_t *)vdi_get_instance_pool(pCodecInst->coreIdx);
  1978. if (!vip) {
  1979. return RETCODE_INVALID_HANDLE;
  1980. }
  1981. pSrcFrame = param->sourceFrame;
  1982. rotMirMode = 0;
  1983. if (pEncInfo->rotationEnable == TRUE) {
  1984. switch (pEncInfo->rotationAngle) {
  1985. case 0:
  1986. rotMirMode |= 0x0;
  1987. break;
  1988. case 90:
  1989. rotMirMode |= 0x1;
  1990. break;
  1991. case 180:
  1992. rotMirMode |= 0x2;
  1993. break;
  1994. case 270:
  1995. rotMirMode |= 0x3;
  1996. break;
  1997. }
  1998. }
  1999. if (pEncInfo->mirrorEnable == TRUE) {
  2000. switch (pEncInfo->mirrorDirection) {
  2001. case MIRDIR_NONE :
  2002. rotMirMode |= 0x0;
  2003. break;
  2004. case MIRDIR_VER :
  2005. rotMirMode |= 0x4;
  2006. break;
  2007. case MIRDIR_HOR :
  2008. rotMirMode |= 0x8;
  2009. break;
  2010. case MIRDIR_HOR_VER :
  2011. rotMirMode |= 0xc;
  2012. break;
  2013. }
  2014. }
  2015. if (pCodecInst->productId == PRODUCT_ID_980) {
  2016. rotMirMode |= ((pSrcFrame->endian&0x03)<<16);
  2017. rotMirMode |= ((pSrcFrame->cbcrInterleave&0x01)<<18);
  2018. rotMirMode |= ((pSrcFrame->sourceLBurstEn&0x01)<<4);
  2019. }
  2020. else {
  2021. rotMirMode |= ((pSrcFrame->sourceLBurstEn&0x01)<<4);
  2022. #if defined(SUPPORT_NV21) || defined(SUPPORT_ENC_NV21)
  2023. rotMirMode |= ((pSrcFrame->cbcrInterleave&0x01)<<18);
  2024. rotMirMode |= pEncInfo->openParam.nv21 << 21;
  2025. #endif
  2026. }
  2027. if (pCodecInst->productId == PRODUCT_ID_980 && pCodecInst->codecMode == AVC_ENC)
  2028. {
  2029. }
  2030. if (pCodecInst->productId == PRODUCT_ID_960) {
  2031. if (pEncInfo->mapType > LINEAR_FRAME_MAP && pEncInfo->mapType <= TILED_MIXED_V_MAP) {
  2032. SetTiledFrameBase(pCodecInst->coreIdx, pEncInfo->vbFrame.phys_addr);
  2033. }
  2034. else {
  2035. SetTiledFrameBase(pCodecInst->coreIdx, 0);
  2036. }
  2037. }
  2038. if (pEncInfo->mapType != LINEAR_FRAME_MAP && pEncInfo->mapType != LINEAR_FIELD_MAP) {
  2039. if (pEncInfo->stride > pEncInfo->frameBufferHeight)
  2040. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, pEncInfo->mapType, pEncInfo->stride, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  2041. else
  2042. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, pEncInfo->mapType, pEncInfo->frameBufferHeight, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  2043. } else {
  2044. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, pEncInfo->mapType, pEncInfo->stride, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  2045. }
  2046. if (val == 0) {
  2047. return RETCODE_INVALID_PARAM;
  2048. }
  2049. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_ROT_MODE, rotMirMode);
  2050. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_QS, param->quantParam);
  2051. if (param->skipPicture) {
  2052. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_OPTION, 1);
  2053. }
  2054. else {
  2055. // Registering Source Frame Buffer information
  2056. // Hide GDI IF under FW level
  2057. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_INDEX, pSrcFrame->myIndex);
  2058. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_STRIDE, pSrcFrame->stride);
  2059. if (pEncInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  2060. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_Y, pSrcFrame->bufY);
  2061. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_CB, pSrcFrame->bufCb);
  2062. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_CR, pSrcFrame->bufCr);
  2063. }
  2064. else { // CBCR_ORDER_REVERSED (YV12)
  2065. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_Y, pSrcFrame->bufY);
  2066. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_CB, pSrcFrame->bufCr);
  2067. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_CR, pSrcFrame->bufCb);
  2068. }
  2069. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_OPTION, (param->forceIPicture << 1 & 0x2));
  2070. }
  2071. if (pEncInfo->ringBufferEnable == 0) {
  2072. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_BB_START, param->picStreamBufferAddr);
  2073. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_BB_SIZE, param->picStreamBufferSize/1024); // size in KB
  2074. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamRdPtrRegAddr, param->picStreamBufferAddr);
  2075. pEncInfo->streamRdPtr = param->picStreamBufferAddr;
  2076. }
  2077. val = 0;
  2078. val = (
  2079. (pEncInfo->secAxiInfo.u.coda9.useBitEnable&0x01)<<0 |
  2080. (pEncInfo->secAxiInfo.u.coda9.useIpEnable&0x01)<<1 |
  2081. (pEncInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01)<<2 |
  2082. (pEncInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01)<<3 |
  2083. (pEncInfo->secAxiInfo.u.coda9.useOvlEnable&0x01)<<4 |
  2084. (pEncInfo->secAxiInfo.u.coda9.useBtpEnable&0x01)<<5 |
  2085. (pEncInfo->secAxiInfo.u.coda9.useBitEnable&0x01)<<8 |
  2086. (pEncInfo->secAxiInfo.u.coda9.useIpEnable&0x01)<<9 |
  2087. (pEncInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01)<<10 |
  2088. (pEncInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01)<<11 |
  2089. (pEncInfo->secAxiInfo.u.coda9.useOvlEnable&0x01)<<12 |
  2090. (pEncInfo->secAxiInfo.u.coda9.useBtpEnable&0x01)<<13 );
  2091. VpuWriteReg(pCodecInst->coreIdx, BIT_AXI_SRAM_USE, val);
  2092. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr, pEncInfo->streamWrPtr);
  2093. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamRdPtrRegAddr, pEncInfo->streamRdPtr);
  2094. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM, pEncInfo->streamEndflag);
  2095. SetEncFrameMemInfo(pCodecInst);
  2096. val = 0;
  2097. if (pEncInfo->ringBufferEnable == 0) {
  2098. if (pEncInfo->lineBufIntEn)
  2099. val |= (0x1<<6);
  2100. val |= (0x1<<5);
  2101. val |= (0x1<<4);
  2102. }
  2103. else {
  2104. val |= (0x1<<3);
  2105. }
  2106. val |= pEncInfo->openParam.streamEndian;
  2107. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_CTRL, val);
  2108. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, PIC_RUN);
  2109. return RETCODE_SUCCESS;
  2110. }
  2111. RetCode Coda9VpuEncGetResult(CodecInst* pCodecInst, EncOutputInfo* info)
  2112. {
  2113. EncInfo* pEncInfo;
  2114. PhysicalAddress rdPtr;
  2115. PhysicalAddress wrPtr;
  2116. Uint32 pic_enc_result;
  2117. pEncInfo = &pCodecInst->CodecInfo->encInfo;
  2118. if (pCodecInst->loggingEnable)
  2119. vdi_log(pCodecInst->coreIdx, PIC_RUN, 0);
  2120. pic_enc_result = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_SUCCESS);
  2121. if (pic_enc_result & (1UL<<31)) {
  2122. return RETCODE_MEMORY_ACCESS_VIOLATION;
  2123. }
  2124. if (pCodecInst->productId == PRODUCT_ID_980) {
  2125. if (pic_enc_result & 2) { //top field coding done
  2126. if (!pEncInfo->fieldDone)
  2127. pEncInfo->fieldDone = 1;
  2128. }
  2129. else
  2130. {
  2131. pEncInfo->frameIdx = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_FRAME_NUM);
  2132. pEncInfo->fieldDone = 0;
  2133. }
  2134. }
  2135. info->picType = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_TYPE);
  2136. if (pEncInfo->ringBufferEnable == 0) {
  2137. rdPtr = VpuReadReg(pCodecInst->coreIdx, pEncInfo->streamRdPtrRegAddr);
  2138. wrPtr = VpuReadReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr);
  2139. info->bitstreamBuffer = rdPtr;
  2140. info->bitstreamSize = wrPtr - rdPtr;
  2141. }
  2142. info->numOfSlices = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_SLICE_NUM);
  2143. info->bitstreamWrapAround = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_FLAG);
  2144. info->reconFrameIndex = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_FRAME_IDX);
  2145. if (info->reconFrameIndex < MAX_REG_FRAME) {
  2146. info->reconFrame = pEncInfo->frameBufPool[info->reconFrameIndex];
  2147. }
  2148. info->encSrcIdx = info->reconFrameIndex;
  2149. pEncInfo->streamWrPtr = VpuReadReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr);
  2150. pEncInfo->streamEndflag = VpuReadReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM);
  2151. info->frameCycle = VpuReadReg(pCodecInst->coreIdx, BIT_FRAME_CYCLE);
  2152. info->rdPtr = pEncInfo->streamRdPtr;
  2153. info->wrPtr = pEncInfo->streamWrPtr;
  2154. return RETCODE_SUCCESS;
  2155. }
  2156. RetCode Coda9VpuEncGiveCommand(CodecInst* pCodecInst, CodecCommand cmd, void* param)
  2157. {
  2158. RetCode ret = RETCODE_SUCCESS;
  2159. UNREFERENCED_PARAMETER(cmd);
  2160. UNREFERENCED_PARAMETER(param);
  2161. switch (cmd) {
  2162. default:
  2163. ret = RETCODE_NOT_SUPPORTED_FEATURE;
  2164. }
  2165. return ret;
  2166. }