venc.c 61 KB

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  1. #include <linux/kernel.h>
  2. #include <linux/mm.h>
  3. #include <linux/interrupt.h>
  4. #include <linux/ioport.h>
  5. #include <linux/module.h>
  6. #include <linux/platform_device.h>
  7. #include <linux/dma-mapping.h>
  8. #include <linux/of.h>
  9. #include <linux/of_address.h>
  10. #include <linux/wait.h>
  11. #include <linux/list.h>
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/uaccess.h>
  15. #include <linux/cdev.h>
  16. #include <linux/slab.h>
  17. #include <linux/sched.h>
  18. #include <linux/version.h>
  19. #include <linux/kfifo.h>
  20. #include <linux/kthread.h>
  21. #include <linux/sched/signal.h>
  22. #include <soc/sifive/sifive_l2_cache.h>
  23. #include "../../../vpuapi/vpuconfig.h"
  24. #include "vpu.h"
  25. #include "venc-starfive.h"
  26. #include <linux/of_device.h>
  27. #include <linux/of_irq.h>
  28. #define starfive_flush_dcache(start, len) \
  29. sifive_l2_flush64_range(start, len)
  30. //#define ENABLE_DEBUG_MSG
  31. #ifdef ENABLE_DEBUG_MSG
  32. #define DPRINTK(args...) printk(KERN_INFO args);
  33. #else
  34. #define DPRINTK(args...)
  35. #endif
  36. /* definitions to be changed as customer configuration */
  37. /* if linux version is 5.15 or later, then can use clock and reset framework */
  38. #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)
  39. #define VPU_SUPPORT_CLOCK_CONTROL
  40. #endif
  41. /* if the driver want to use interrupt service from kernel ISR */
  42. #define VPU_SUPPORT_ISR
  43. #ifdef VPU_SUPPORT_ISR
  44. /* if the driver want to disable and enable IRQ whenever interrupt asserted. */
  45. //#define VPU_IRQ_CONTROL
  46. #endif
  47. /* if the platform driver knows the name of this driver */
  48. /* VPU_PLATFORM_DEVICE_NAME */
  49. #define VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  50. /* if this driver knows the dedicated video memory address */
  51. //#define VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  52. #define VPU_PLATFORM_DEVICE_NAME "venc"
  53. #define VPU_DEV_NAME "venc"
  54. /* if the platform driver knows this driver */
  55. /* the definition of VPU_REG_BASE_ADDR and VPU_REG_SIZE are not meaningful */
  56. #define VPU_REG_BASE_ADDR 0x118E0000
  57. #define VPU_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
  58. #define VENC_IRQ_ADDR 0x18
  59. #ifdef VPU_SUPPORT_ISR
  60. #define VPU_IRQ_NUM (26)
  61. #endif
  62. /* this definition is only for chipsnmedia FPGA board env */
  63. /* so for SOC env of customers can be ignored */
  64. #ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/
  65. # define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
  66. #endif
  67. struct device *vpu_dev;
  68. typedef struct vpu_drv_context_t {
  69. struct fasync_struct *async_queue;
  70. #ifdef SUPPORT_MULTI_INST_INTR
  71. unsigned long interrupt_reason[MAX_NUM_INSTANCE];
  72. #else
  73. unsigned long interrupt_reason;
  74. #endif
  75. u32 open_count; /*!<< device reference count. Not instance count */
  76. } vpu_drv_context_t;
  77. /* To track the allocated memory buffer */
  78. typedef struct vpudrv_buffer_pool_t {
  79. struct list_head list;
  80. struct vpudrv_buffer_t vb;
  81. struct file *filp;
  82. } vpudrv_buffer_pool_t;
  83. /* To track the instance index and buffer in instance pool */
  84. typedef struct vpudrv_instanace_list_t {
  85. struct list_head list;
  86. unsigned long inst_idx;
  87. unsigned long core_idx;
  88. struct file *filp;
  89. } vpudrv_instanace_list_t;
  90. typedef struct vpudrv_instance_pool_t {
  91. unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
  92. } vpudrv_instance_pool_t;
  93. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  94. #include "vmm.h"
  95. static video_mm_t s_vmem;
  96. static vpudrv_buffer_t s_video_memory = {0};
  97. #endif /*VPU_SUPPORT_RESERVED_VIDEO_MEMORY*/
  98. #ifndef VPU_SUPPORT_CLOCK_CONTROL
  99. static int vpu_hw_reset(void);
  100. static void vpu_clk_disable(void);
  101. static int vpu_clk_enable(void);
  102. #endif
  103. /* end customer definition */
  104. static vpudrv_buffer_t s_instance_pool = {0};
  105. static vpudrv_buffer_t s_common_memory = {0};
  106. static vpu_drv_context_t s_vpu_drv_context;
  107. static int s_vpu_major;
  108. static struct cdev s_vpu_cdev;
  109. static int s_vpu_open_ref_count;
  110. #ifdef VPU_SUPPORT_ISR
  111. static int s_vpu_irq = VPU_IRQ_NUM;
  112. #endif
  113. static vpudrv_buffer_t s_vpu_register = {0};
  114. #ifdef SUPPORT_MULTI_INST_INTR
  115. static int s_interrupt_flag[MAX_NUM_INSTANCE];
  116. static wait_queue_head_t s_interrupt_wait_q[MAX_NUM_INSTANCE];
  117. typedef struct kfifo kfifo_t;
  118. static kfifo_t s_interrupt_pending_q[MAX_NUM_INSTANCE];
  119. static spinlock_t s_kfifo_lock = __SPIN_LOCK_UNLOCKED(s_kfifo_lock);
  120. #else
  121. static int s_interrupt_flag;
  122. static wait_queue_head_t s_interrupt_wait_q;
  123. #endif
  124. static spinlock_t s_vpu_lock = __SPIN_LOCK_UNLOCKED(s_vpu_lock);
  125. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
  126. static DECLARE_MUTEX(s_vpu_sem);
  127. #else
  128. static DEFINE_SEMAPHORE(s_vpu_sem);
  129. #endif
  130. static struct list_head s_vbp_head = LIST_HEAD_INIT(s_vbp_head);
  131. static struct list_head s_inst_list_head = LIST_HEAD_INIT(s_inst_list_head);
  132. static vpu_bit_firmware_info_t s_bit_firmware_info[MAX_NUM_VPU_CORE];
  133. #ifdef CONFIG_PM
  134. /* implement to power management functions */
  135. #define BIT_BASE 0x0000
  136. #define BIT_CODE_RUN (BIT_BASE + 0x000)
  137. #define BIT_CODE_DOWN (BIT_BASE + 0x004)
  138. #define BIT_INT_CLEAR (BIT_BASE + 0x00C)
  139. #define BIT_INT_STS (BIT_BASE + 0x010)
  140. #define BIT_CODE_RESET (BIT_BASE + 0x014)
  141. #define BIT_INT_REASON (BIT_BASE + 0x174)
  142. #define BIT_BUSY_FLAG (BIT_BASE + 0x160)
  143. #define BIT_RUN_COMMAND (BIT_BASE + 0x164)
  144. #define BIT_RUN_INDEX (BIT_BASE + 0x168)
  145. #define BIT_RUN_COD_STD (BIT_BASE + 0x16C)
  146. /* WAVE5 registers */
  147. #define W5_REG_BASE 0x0000
  148. #define W5_VPU_BUSY_STATUS (W5_REG_BASE + 0x0070)
  149. #define W5_VPU_INT_REASON_CLEAR (W5_REG_BASE + 0x0034)
  150. #define W5_VPU_VINT_CLEAR (W5_REG_BASE + 0x003C)
  151. #define W5_VPU_VPU_INT_STS (W5_REG_BASE + 0x0044)
  152. #define W5_VPU_INT_REASON (W5_REG_BASE + 0x004c)
  153. #define W5_RET_FAIL_REASON (W5_REG_BASE + 0x010C)
  154. #ifdef SUPPORT_MULTI_INST_INTR
  155. #define W5_RET_BS_EMPTY_INST (W5_REG_BASE + 0x01E4)
  156. #define W5_RET_QUEUE_CMD_DONE_INST (W5_REG_BASE + 0x01E8)
  157. #define W5_RET_SEQ_DONE_INSTANCE_INFO (W5_REG_BASE + 0x01FC)
  158. typedef enum {
  159. INT_WAVE5_INIT_VPU = 0,
  160. INT_WAVE5_WAKEUP_VPU = 1,
  161. INT_WAVE5_SLEEP_VPU = 2,
  162. INT_WAVE5_CREATE_INSTANCE = 3,
  163. INT_WAVE5_FLUSH_INSTANCE = 4,
  164. INT_WAVE5_DESTORY_INSTANCE = 5,
  165. INT_WAVE5_INIT_SEQ = 6,
  166. INT_WAVE5_SET_FRAMEBUF = 7,
  167. INT_WAVE5_DEC_PIC = 8,
  168. INT_WAVE5_ENC_PIC = 8,
  169. INT_WAVE5_ENC_SET_PARAM = 9,
  170. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  171. INT_WAVE5_ENC_SRC_RELEASE = 10,
  172. #endif
  173. INT_WAVE5_ENC_LOW_LATENCY = 13,
  174. INT_WAVE5_DEC_QUERY = 14,
  175. INT_WAVE5_BSBUF_EMPTY = 15,
  176. INT_WAVE5_BSBUF_FULL = 15,
  177. } Wave5InterruptBit;
  178. #endif
  179. /* WAVE5 INIT, WAKEUP */
  180. #define W5_PO_CONF (W5_REG_BASE + 0x0000)
  181. #define W5_VPU_VINT_ENABLE (W5_REG_BASE + 0x0048)
  182. #define W5_VPU_RESET_REQ (W5_REG_BASE + 0x0050)
  183. #define W5_VPU_RESET_STATUS (W5_REG_BASE + 0x0054)
  184. #define W5_VPU_REMAP_CTRL (W5_REG_BASE + 0x0060)
  185. #define W5_VPU_REMAP_VADDR (W5_REG_BASE + 0x0064)
  186. #define W5_VPU_REMAP_PADDR (W5_REG_BASE + 0x0068)
  187. #define W5_VPU_REMAP_CORE_START (W5_REG_BASE + 0x006C)
  188. #define W5_REMAP_CODE_INDEX 0
  189. /* WAVE5 registers */
  190. #define W5_ADDR_CODE_BASE (W5_REG_BASE + 0x0110)
  191. #define W5_CODE_SIZE (W5_REG_BASE + 0x0114)
  192. #define W5_CODE_PARAM (W5_REG_BASE + 0x0118)
  193. #define W5_INIT_VPU_TIME_OUT_CNT (W5_REG_BASE + 0x0130)
  194. #define W5_HW_OPTION (W5_REG_BASE + 0x012C)
  195. #define W5_RET_SUCCESS (W5_REG_BASE + 0x0108)
  196. #define W5_COMMAND (W5_REG_BASE + 0x0100)
  197. #define W5_VPU_HOST_INT_REQ (W5_REG_BASE + 0x0038)
  198. /* Product register */
  199. #define VPU_PRODUCT_CODE_REGISTER (BIT_BASE + 0x1044)
  200. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  201. static u32 s_vpu_reg_store[MAX_NUM_VPU_CORE][64];
  202. #endif
  203. #endif
  204. #define ReadVpuRegister(addr) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr)
  205. #define WriteVpuRegister(addr, val) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr) = (unsigned int)val
  206. #define WriteVpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
  207. #define vic_readl(addr) readl((void __iomem *)addr)
  208. #define vic_writel(val,addr) writel(val,(void __iomem *)addr)
  209. #define rstgen_Software_RESET_BASE_REG_ADDR 0x11840000
  210. #define rstgen_Software_RESET_assert0_OFFSET (0x0)
  211. #define rstgen_Software_RESET_status0_OFFSET (0x10)
  212. #define NBIT_RSTN_VENC_BRG_MAIN 26
  213. #define NBIT_RSTN_VENC_AXI 25
  214. #define NBIT_RSTN_VENC_BCLK 27
  215. #define NBIT_RSTN_VENC_CCLK 28
  216. #define NBIT_RSTN_VENC_APB 29
  217. #define clk_BASE_REG_ADDR 0x11800000
  218. #define clk_venc_axi_ctrl_REG_OFFSET (0xe4)
  219. #define clk_vencbrg_mainclk_ctrl_REG_OFFSET (0xe8)
  220. #define clk_venc_bclk_ctrl_REG_OFFSET (0xec)
  221. #define clk_venc_cclk_ctrl_REG_OFFSET (0xf0)
  222. #define clk_venc_apb_ctrl_REG_OFFSET (0xf4)
  223. static int vpu_alloc_dma_buffer(vpudrv_buffer_t *vb)
  224. {
  225. if (!vb)
  226. return -1;
  227. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  228. vb->phys_addr = (unsigned long)vmem_alloc(&s_vmem, vb->size, 0);
  229. if ((unsigned long)vb->phys_addr == (unsigned long)-1) {
  230. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  231. return -1;
  232. }
  233. vb->base = (unsigned long)(s_video_memory.base + (vb->phys_addr - s_video_memory.phys_addr));
  234. #else
  235. vb->base = (unsigned long)dma_alloc_coherent(vpu_dev, PAGE_ALIGN(vb->size), (dma_addr_t *) (&vb->phys_addr), GFP_DMA | GFP_KERNEL);
  236. if ((void *)(vb->base) == NULL) {
  237. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  238. return -1;
  239. }
  240. starfive_flush_dcache(vb->phys_addr,PAGE_ALIGN(vb->size));
  241. #endif
  242. return 0;
  243. }
  244. static void vpu_free_dma_buffer(vpudrv_buffer_t *vb)
  245. {
  246. if (!vb)
  247. return;
  248. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  249. if (vb->base)
  250. vmem_free(&s_vmem, vb->phys_addr, 0);
  251. #else
  252. if (vb->base)
  253. dma_free_coherent(vpu_dev, PAGE_ALIGN(vb->size), (void *)vb->base, vb->phys_addr);
  254. #endif
  255. }
  256. static int vpu_free_instances(struct file *filp)
  257. {
  258. vpudrv_instanace_list_t *vil, *n;
  259. vpudrv_instance_pool_t *vip;
  260. void *vip_base;
  261. int instance_pool_size_per_core;
  262. void *vdi_mutexes_base;
  263. const int PTHREAD_MUTEX_T_DESTROY_VALUE = 0xdead10cc;
  264. DPRINTK("[VPUDRV] vpu_free_instances\n");
  265. instance_pool_size_per_core = (s_instance_pool.size/MAX_NUM_VPU_CORE); /* s_instance_pool.size assigned to the size of all core once call VDI_IOCTL_GET_INSTANCE_POOL by user. */
  266. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  267. {
  268. if (vil->filp == filp) {
  269. vip_base = (void *)(s_instance_pool.base + (instance_pool_size_per_core*vil->core_idx));
  270. DPRINTK("[VPUDRV] vpu_free_instances detect instance crash instIdx=%d, coreIdx=%d, vip_base=%p, instance_pool_size_per_core=%d\n", (int)vil->inst_idx, (int)vil->core_idx, vip_base, (int)instance_pool_size_per_core);
  271. vip = (vpudrv_instance_pool_t *)vip_base;
  272. if (vip) {
  273. memset(&vip->codecInstPool[vil->inst_idx], 0x00, 4); /* only first 4 byte is key point(inUse of CodecInst in vpuapi) to free the corresponding instance. */
  274. #define PTHREAD_MUTEX_T_HANDLE_SIZE 4
  275. vdi_mutexes_base = (vip_base + (instance_pool_size_per_core - PTHREAD_MUTEX_T_HANDLE_SIZE*4));
  276. DPRINTK("[VPUDRV] vpu_free_instances : force to destroy vdi_mutexes_base=%p in userspace \n", vdi_mutexes_base);
  277. if (vdi_mutexes_base) {
  278. int i;
  279. for (i = 0; i < 4; i++) {
  280. memcpy(vdi_mutexes_base, &PTHREAD_MUTEX_T_DESTROY_VALUE, PTHREAD_MUTEX_T_HANDLE_SIZE);
  281. vdi_mutexes_base += PTHREAD_MUTEX_T_HANDLE_SIZE;
  282. }
  283. }
  284. }
  285. s_vpu_open_ref_count--;
  286. list_del(&vil->list);
  287. kfree(vil);
  288. }
  289. }
  290. return 1;
  291. }
  292. static int vpu_free_buffers(struct file *filp)
  293. {
  294. vpudrv_buffer_pool_t *pool, *n;
  295. vpudrv_buffer_t vb;
  296. DPRINTK("[VPUDRV] vpu_free_buffers\n");
  297. list_for_each_entry_safe(pool, n, &s_vbp_head, list)
  298. {
  299. if (pool->filp == filp) {
  300. vb = pool->vb;
  301. if (vb.base) {
  302. vpu_free_dma_buffer(&vb);
  303. list_del(&pool->list);
  304. kfree(pool);
  305. }
  306. }
  307. }
  308. return 0;
  309. }
  310. #ifdef SUPPORT_MULTI_INST_INTR
  311. static inline u32 get_inst_idx(u32 reg_val)
  312. {
  313. u32 inst_idx;
  314. int i;
  315. for (i=0; i < MAX_NUM_INSTANCE; i++)
  316. {
  317. if(((reg_val >> i)&0x01) == 1)
  318. break;
  319. }
  320. inst_idx = i;
  321. return inst_idx;
  322. }
  323. static s32 get_vpu_inst_idx(vpu_drv_context_t *dev, u32 *reason, u32 empty_inst, u32 done_inst, u32 seq_inst)
  324. {
  325. s32 inst_idx;
  326. u32 reg_val;
  327. u32 int_reason;
  328. int_reason = *reason;
  329. DPRINTK("[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  330. //printk(KERN_ERR "[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  331. if (int_reason & (1 << INT_WAVE5_BSBUF_EMPTY))
  332. {
  333. reg_val = (empty_inst & 0xffff);
  334. inst_idx = get_inst_idx(reg_val);
  335. *reason = (1 << INT_WAVE5_BSBUF_EMPTY);
  336. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  337. goto GET_VPU_INST_IDX_HANDLED;
  338. }
  339. if (int_reason & (1 << INT_WAVE5_INIT_SEQ))
  340. {
  341. reg_val = (seq_inst & 0xffff);
  342. inst_idx = get_inst_idx(reg_val);
  343. *reason = (1 << INT_WAVE5_INIT_SEQ);
  344. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO INIT_SEQ reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  345. goto GET_VPU_INST_IDX_HANDLED;
  346. }
  347. if (int_reason & (1 << INT_WAVE5_DEC_PIC))
  348. {
  349. reg_val = (done_inst & 0xffff);
  350. inst_idx = get_inst_idx(reg_val);
  351. *reason = (1 << INT_WAVE5_DEC_PIC);
  352. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  353. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  354. {
  355. u32 ll_inst_idx;
  356. reg_val = (done_inst >> 16);
  357. ll_inst_idx = get_inst_idx(reg_val);
  358. if (ll_inst_idx == inst_idx)
  359. *reason = ((1 << INT_WAVE5_DEC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY));
  360. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC and ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d, ll_inst_idx=%d\n", __func__, reg_val, inst_idx, ll_inst_idx);
  361. }
  362. goto GET_VPU_INST_IDX_HANDLED;
  363. }
  364. if (int_reason & (1 << INT_WAVE5_ENC_SET_PARAM))
  365. {
  366. reg_val = (seq_inst & 0xffff);
  367. inst_idx = get_inst_idx(reg_val);
  368. *reason = (1 << INT_WAVE5_ENC_SET_PARAM);
  369. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  370. goto GET_VPU_INST_IDX_HANDLED;
  371. }
  372. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  373. if (int_reason & (1 << INT_WAVE5_ENC_SRC_RELEASE))
  374. {
  375. reg_val = (done_inst & 0xffff);
  376. inst_idx = get_inst_idx(reg_val);
  377. *reason = (1 << INT_WAVE5_ENC_SRC_RELEASE);
  378. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  379. goto GET_VPU_INST_IDX_HANDLED;
  380. }
  381. #endif
  382. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  383. {
  384. reg_val = (done_inst >> 16);
  385. inst_idx = get_inst_idx(reg_val);
  386. *reason = (1 << INT_WAVE5_ENC_LOW_LATENCY);
  387. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  388. goto GET_VPU_INST_IDX_HANDLED;
  389. }
  390. inst_idx = -1;
  391. *reason = 0;
  392. DPRINTK("[VPUDRV] %s, UNKNOWN INTERRUPT REASON: %08x\n", __func__, int_reason);
  393. GET_VPU_INST_IDX_HANDLED:
  394. DPRINTK("[VPUDRV][-]%s, inst_idx=%d. *reason=0x%x\n", __func__, inst_idx, *reason);
  395. return inst_idx;
  396. }
  397. #endif
  398. static irqreturn_t vpu_irq_handler(int irq, void *dev_id)
  399. {
  400. vpu_drv_context_t *dev = (vpu_drv_context_t *)dev_id;
  401. /* this can be removed. it also work in VPU_WaitInterrupt of API function */
  402. int core;
  403. int product_code;
  404. #ifdef SUPPORT_MULTI_INST_INTR
  405. u32 intr_reason;
  406. s32 intr_inst_index;
  407. #endif
  408. DPRINTK("[VPUDRV][+]%s\n", __func__);
  409. #ifdef VPU_IRQ_CONTROL
  410. disable_irq_nosync(s_vpu_irq);
  411. #endif
  412. #ifdef SUPPORT_MULTI_INST_INTR
  413. intr_inst_index = 0;
  414. intr_reason = 0;
  415. #endif
  416. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  417. if (s_bit_firmware_info[core].size == 0) {/* it means that we didn't get an information the current core from API layer. No core activated.*/
  418. printk(KERN_ERR "[VPUDRV] : s_bit_firmware_info[core].size is zero\n");
  419. continue;
  420. }
  421. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  422. if (PRODUCT_CODE_W_SERIES(product_code)) {
  423. if (ReadVpuRegister(W5_VPU_VPU_INT_STS)) {
  424. #ifdef SUPPORT_MULTI_INST_INTR
  425. u32 empty_inst;
  426. u32 done_inst;
  427. u32 seq_inst;
  428. u32 i, reason, reason_clr;
  429. reason = ReadVpuRegister(W5_VPU_INT_REASON);
  430. empty_inst = ReadVpuRegister(W5_RET_BS_EMPTY_INST);
  431. done_inst = ReadVpuRegister(W5_RET_QUEUE_CMD_DONE_INST);
  432. seq_inst = ReadVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO);
  433. reason_clr = reason;
  434. DPRINTK("[VPUDRV] vpu_irq_handler reason=0x%x, empty_inst=0x%x, done_inst=0x%x, seq_inst=0x%x \n", reason, empty_inst, done_inst, seq_inst);
  435. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  436. if (0 == empty_inst && 0 == done_inst && 0 == seq_inst) break;
  437. intr_reason = reason;
  438. intr_inst_index = get_vpu_inst_idx(dev, &intr_reason, empty_inst, done_inst, seq_inst);
  439. DPRINTK("[VPUDRV] > instance_index: %d, intr_reason: %08x empty_inst: %08x done_inst: %08x seq_inst: %08x\n", intr_inst_index, intr_reason, empty_inst, done_inst, seq_inst);
  440. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  441. if (intr_reason == (1 << INT_WAVE5_BSBUF_EMPTY)) {
  442. empty_inst = empty_inst & ~(1 << intr_inst_index);
  443. WriteVpuRegister(W5_RET_BS_EMPTY_INST, empty_inst);
  444. if (0 == empty_inst) {
  445. reason &= ~(1<<INT_WAVE5_BSBUF_EMPTY);
  446. }
  447. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST Clear empty_inst=0x%x, intr_inst_index=%d\n", __func__, empty_inst, intr_inst_index);
  448. }
  449. if (intr_reason == (1 << INT_WAVE5_DEC_PIC))
  450. {
  451. done_inst = done_inst & ~(1 << intr_inst_index);
  452. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  453. if (0 == done_inst) {
  454. reason &= ~(1<<INT_WAVE5_DEC_PIC);
  455. }
  456. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  457. }
  458. if ((intr_reason == (1 << INT_WAVE5_INIT_SEQ)) || (intr_reason == (1 << INT_WAVE5_ENC_SET_PARAM)))
  459. {
  460. seq_inst = seq_inst & ~(1 << intr_inst_index);
  461. WriteVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO, seq_inst);
  462. if (0 == seq_inst) {
  463. reason &= ~(1<<INT_WAVE5_INIT_SEQ | 1<<INT_WAVE5_ENC_SET_PARAM);
  464. }
  465. DPRINTK("[VPUDRV] %s, W5_RET_SEQ_DONE_INSTANCE_INFO Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  466. }
  467. if ((intr_reason == (1 << INT_WAVE5_ENC_LOW_LATENCY)))
  468. {
  469. done_inst = (done_inst >> 16);
  470. done_inst = done_inst & ~(1 << intr_inst_index);
  471. done_inst = (done_inst << 16);
  472. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  473. if (0 == done_inst) {
  474. reason &= ~(1 << INT_WAVE5_ENC_LOW_LATENCY);
  475. }
  476. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST INT_WAVE5_ENC_LOW_LATENCY Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  477. }
  478. if (!kfifo_is_full(&s_interrupt_pending_q[intr_inst_index])) {
  479. if (intr_reason == ((1 << INT_WAVE5_ENC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY))) {
  480. u32 ll_intr_reason = (1 << INT_WAVE5_ENC_PIC);
  481. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &ll_intr_reason, sizeof(u32), &s_kfifo_lock);
  482. }
  483. else
  484. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  485. }
  486. else {
  487. printk(KERN_ERR "[VPUDRV] : kfifo_is_full kfifo_count=%d \n", kfifo_len(&s_interrupt_pending_q[intr_inst_index]));
  488. }
  489. }
  490. else {
  491. printk(KERN_ERR "[VPUDRV] : intr_inst_index is wrong intr_inst_index=%d \n", intr_inst_index);
  492. }
  493. }
  494. if (0 != reason)
  495. printk(KERN_ERR "INTERRUPT REASON REMAINED: %08x\n", reason);
  496. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, reason_clr);
  497. #else
  498. dev->interrupt_reason = ReadVpuRegister(W5_VPU_INT_REASON);
  499. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, dev->interrupt_reason);
  500. #endif
  501. WriteVpuRegister(W5_VPU_VINT_CLEAR, 0x1);
  502. }
  503. }
  504. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  505. if (ReadVpuRegister(BIT_INT_STS)) {
  506. #ifdef SUPPORT_MULTI_INST_INTR
  507. intr_reason = ReadVpuRegister(BIT_INT_REASON);
  508. intr_inst_index = 0; // in case of coda seriese. treats intr_inst_index is already 0
  509. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  510. #else
  511. dev->interrupt_reason = ReadVpuRegister(BIT_INT_REASON);
  512. #endif
  513. WriteVpuRegister(BIT_INT_CLEAR, 0x1);
  514. }
  515. }
  516. else {
  517. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  518. continue;
  519. }
  520. #ifdef SUPPORT_MULTI_INST_INTR
  521. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n\n", product_code, intr_reason);
  522. #else
  523. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n", product_code, dev->interrupt_reason);
  524. #endif
  525. }
  526. if (dev->async_queue)
  527. kill_fasync(&dev->async_queue, SIGIO, POLL_IN); /* notify the interrupt to user space */
  528. #ifdef SUPPORT_MULTI_INST_INTR
  529. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  530. s_interrupt_flag[intr_inst_index]= 1;
  531. wake_up_interruptible(&s_interrupt_wait_q[intr_inst_index]);
  532. }
  533. #else
  534. s_interrupt_flag = 1;
  535. wake_up_interruptible(&s_interrupt_wait_q);
  536. #endif
  537. DPRINTK("[VPUDRV][-]%s\n", __func__);
  538. return IRQ_HANDLED;
  539. }
  540. static int vpu_open(struct inode *inode, struct file *filp)
  541. {
  542. DPRINTK("[VPUDRV][+] %s\n", __func__);
  543. spin_lock(&s_vpu_lock);
  544. s_vpu_drv_context.open_count++;
  545. filp->private_data = (void *)(&s_vpu_drv_context);
  546. spin_unlock(&s_vpu_lock);
  547. DPRINTK("[VPUDRV][-] %s\n", __func__);
  548. return 0;
  549. }
  550. /*static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, u_long arg) // for kernel 2.6.9 of C&M*/
  551. static long vpu_ioctl(struct file *filp, u_int cmd, u_long arg)
  552. {
  553. int ret = 0;
  554. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  555. switch (cmd) {
  556. case VDI_IOCTL_GET_PHYSICAL_MEMORY:
  557. {
  558. vpudrv_buffer_pool_t *vbp = NULL;
  559. void *user_address = NULL;
  560. struct task_struct *my_struct = NULL;
  561. struct mm_struct *mm = NULL;
  562. unsigned long address = 0;
  563. pgd_t *pgd = NULL;
  564. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  565. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  566. if (!vbp) {
  567. up(&s_vpu_sem);
  568. return -ENOMEM;
  569. }
  570. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  571. if (ret) {
  572. kfree(vbp);
  573. up(&s_vpu_sem);
  574. return -EFAULT;
  575. }
  576. user_address = (void *)vbp->vb.virt_addr;
  577. my_struct = get_current();
  578. mm = my_struct->mm;
  579. address = (unsigned long)user_address;
  580. pgd = pgd_offset(mm, address);
  581. if (!pgd_none(*pgd) && !pgd_bad(*pgd)) {
  582. p4d_t *p4d = p4d_offset(pgd, address);
  583. pud_t *pud = pud_offset(p4d, address);
  584. if (!pud_none(*pud) && !pud_bad(*pud)) {
  585. pmd_t *pmd = pmd_offset(pud, address);
  586. if (!pmd_none(*pmd) && !pmd_bad(*pmd)) {
  587. pte_t *pte = pte_offset_map(pmd, address);
  588. if (!pte_none(*pte)) {
  589. struct page *pg = pte_page(*pte);
  590. unsigned long phys = page_to_phys(pg);
  591. unsigned long virt = (unsigned long)phys_to_virt(phys);
  592. printk("phy address = %lx, virt = %lx\r\n", phys, virt);
  593. vbp->vb.phys_addr = phys;
  594. vbp->vb.base = virt;
  595. }
  596. pte_unmap(pte);
  597. }
  598. }
  599. }
  600. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  601. if (ret) {
  602. kfree(vbp);
  603. ret = -EFAULT;
  604. up(&s_vpu_sem);
  605. break;
  606. }
  607. vbp->filp = filp;
  608. spin_lock(&s_vpu_lock);
  609. list_add(&vbp->list, &s_vbp_head);
  610. spin_unlock(&s_vpu_lock);
  611. up(&s_vpu_sem);
  612. }
  613. }
  614. break;
  615. case VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY:
  616. {
  617. vpudrv_buffer_pool_t *vbp;
  618. DPRINTK("[VPUDRV][+]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  619. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  620. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  621. if (!vbp) {
  622. up(&s_vpu_sem);
  623. return -ENOMEM;
  624. }
  625. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  626. if (ret) {
  627. kfree(vbp);
  628. up(&s_vpu_sem);
  629. return -EFAULT;
  630. }
  631. ret = vpu_alloc_dma_buffer(&(vbp->vb));
  632. if (ret == -1) {
  633. ret = -ENOMEM;
  634. kfree(vbp);
  635. up(&s_vpu_sem);
  636. break;
  637. }
  638. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  639. if (ret) {
  640. kfree(vbp);
  641. ret = -EFAULT;
  642. up(&s_vpu_sem);
  643. break;
  644. }
  645. vbp->filp = filp;
  646. spin_lock(&s_vpu_lock);
  647. list_add(&vbp->list, &s_vbp_head);
  648. spin_unlock(&s_vpu_lock);
  649. up(&s_vpu_sem);
  650. }
  651. DPRINTK("[VPUDRV][-]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  652. }
  653. break;
  654. case VDI_IOCTL_FREE_PHYSICALMEMORY:
  655. {
  656. vpudrv_buffer_pool_t *vbp, *n;
  657. vpudrv_buffer_t vb;
  658. DPRINTK("[VPUDRV][+]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  659. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  660. ret = copy_from_user(&vb, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  661. if (ret) {
  662. up(&s_vpu_sem);
  663. return -EACCES;
  664. }
  665. if (vb.base)
  666. vpu_free_dma_buffer(&vb);
  667. spin_lock(&s_vpu_lock);
  668. list_for_each_entry_safe(vbp, n, &s_vbp_head, list)
  669. {
  670. if (vbp->vb.base == vb.base) {
  671. list_del(&vbp->list);
  672. kfree(vbp);
  673. break;
  674. }
  675. }
  676. spin_unlock(&s_vpu_lock);
  677. up(&s_vpu_sem);
  678. }
  679. DPRINTK("[VPUDRV][-]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  680. }
  681. break;
  682. case VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO:
  683. {
  684. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  685. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  686. if (s_video_memory.base != 0) {
  687. ret = copy_to_user((void __user *)arg, &s_video_memory, sizeof(vpudrv_buffer_t));
  688. if (ret != 0)
  689. ret = -EFAULT;
  690. } else {
  691. ret = -EFAULT;
  692. }
  693. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  694. #endif
  695. }
  696. break;
  697. case VDI_IOCTL_WAIT_INTERRUPT:
  698. {
  699. vpudrv_intr_info_t info;
  700. #ifdef SUPPORT_MULTI_INST_INTR
  701. u32 intr_inst_index;
  702. u32 intr_reason_in_q;
  703. u32 interrupt_flag_in_q;
  704. #endif
  705. DPRINTK("[VPUDRV][+]VDI_IOCTL_WAIT_INTERRUPT4\n");
  706. ret = copy_from_user(&info, (vpudrv_intr_info_t *)arg, sizeof(vpudrv_intr_info_t));
  707. if (ret != 0)
  708. {
  709. return -EFAULT;
  710. }
  711. #ifdef SUPPORT_MULTI_INST_INTR
  712. intr_inst_index = info.intr_inst_index;
  713. intr_reason_in_q = 0;
  714. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  715. if (interrupt_flag_in_q > 0)
  716. {
  717. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  718. DPRINTK("[VPUDRV] Interrupt Remain : intr_inst_index=%d, intr_reason_in_q=0x%x, interrupt_flag_in_q=%d\n", intr_inst_index, intr_reason_in_q, interrupt_flag_in_q);
  719. goto INTERRUPT_REMAIN_IN_QUEUE;
  720. }
  721. #endif
  722. #ifdef SUPPORT_MULTI_INST_INTR
  723. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  724. kt = ktime_set(0, info.timeout*1000*1000);
  725. ret = wait_event_interruptible_hrtimeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, kt);
  726. #else
  727. ret = wait_event_interruptible_timeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, msecs_to_jiffies(info.timeout));
  728. #endif
  729. #else
  730. ret = wait_event_interruptible_timeout(s_interrupt_wait_q, s_interrupt_flag != 0, msecs_to_jiffies(info.timeout));
  731. #endif
  732. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  733. if (ret == -ETIME) {
  734. //DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT timeout = %d \n", info.timeout);
  735. break;
  736. }
  737. #endif
  738. if (!ret) {
  739. ret = -ETIME;
  740. break;
  741. }
  742. if (signal_pending(current)) {
  743. ret = -ERESTARTSYS;
  744. break;
  745. }
  746. #ifdef SUPPORT_MULTI_INST_INTR
  747. intr_reason_in_q = 0;
  748. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  749. if (interrupt_flag_in_q > 0) {
  750. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  751. }
  752. else {
  753. dev->interrupt_reason[intr_inst_index] = 0;
  754. }
  755. #endif
  756. #ifdef SUPPORT_MULTI_INST_INTR
  757. DPRINTK("[VPUDRV] inst_index(%d), s_interrupt_flag(%d), reason(0x%08lx)\n", intr_inst_index, s_interrupt_flag[intr_inst_index], dev->interrupt_reason[intr_inst_index]);
  758. #else
  759. DPRINTK("[VPUDRV] s_interrupt_flag(%d), reason(0x%08lx)\n", s_interrupt_flag, dev->interrupt_reason);
  760. #endif
  761. #ifdef SUPPORT_MULTI_INST_INTR
  762. INTERRUPT_REMAIN_IN_QUEUE:
  763. info.intr_reason = dev->interrupt_reason[intr_inst_index];
  764. s_interrupt_flag[intr_inst_index] = 0;
  765. dev->interrupt_reason[intr_inst_index] = 0;
  766. #else
  767. info.intr_reason = dev->interrupt_reason;
  768. s_interrupt_flag = 0;
  769. dev->interrupt_reason = 0;
  770. #endif
  771. #ifdef VPU_IRQ_CONTROL
  772. enable_irq(s_vpu_irq);
  773. #endif
  774. ret = copy_to_user((void __user *)arg, &info, sizeof(vpudrv_intr_info_t));
  775. DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT\n");
  776. if (ret != 0)
  777. {
  778. return -EFAULT;
  779. }
  780. }
  781. break;
  782. case VDI_IOCTL_SET_CLOCK_GATE:
  783. {
  784. // u32 clkgate;
  785. // DPRINTK("[VPUDRV][+]VDI_IOCTL_SET_CLOCK_GATE\n");
  786. // if (get_user(clkgate, (u32 __user *) arg))
  787. // return -EFAULT;
  788. // #ifdef VPU_SUPPORT_CLOCK_CONTROL
  789. // if (clkgate)
  790. // //vpu_clk_enable(s_vpu_clk);
  791. // else
  792. // //vpu_clk_disable(s_vpu_clk);
  793. // #endif
  794. // DPRINTK("[VPUDRV][-]VDI_IOCTL_SET_CLOCK_GATE\n");
  795. }
  796. break;
  797. case VDI_IOCTL_GET_INSTANCE_POOL:
  798. {
  799. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_POOL\n");
  800. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  801. if (s_instance_pool.base != 0) {
  802. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  803. if (ret != 0)
  804. ret = -EFAULT;
  805. } else {
  806. ret = copy_from_user(&s_instance_pool, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  807. if (ret == 0) {
  808. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  809. s_instance_pool.size = PAGE_ALIGN(s_instance_pool.size);
  810. s_instance_pool.base = (unsigned long)vmalloc(s_instance_pool.size);
  811. s_instance_pool.phys_addr = s_instance_pool.base;
  812. if (s_instance_pool.base != 0)
  813. #else
  814. if (vpu_alloc_dma_buffer(&s_instance_pool) != -1)
  815. #endif
  816. {
  817. memset((void *)s_instance_pool.base, 0x0, s_instance_pool.size); /*clearing memory*/
  818. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  819. if (ret == 0) {
  820. /* success to get memory for instance pool */
  821. up(&s_vpu_sem);
  822. break;
  823. }
  824. }
  825. }
  826. ret = -EFAULT;
  827. }
  828. up(&s_vpu_sem);
  829. }
  830. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_INSTANCE_POOL\n");
  831. }
  832. break;
  833. case VDI_IOCTL_GET_COMMON_MEMORY:
  834. {
  835. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_COMMON_MEMORY\n");
  836. if (s_common_memory.base != 0) {
  837. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  838. if (ret != 0)
  839. ret = -EFAULT;
  840. } else {
  841. ret = copy_from_user(&s_common_memory, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  842. if (ret == 0) {
  843. if (vpu_alloc_dma_buffer(&s_common_memory) != -1) {
  844. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  845. if (ret == 0) {
  846. /* success to get memory for common memory */
  847. break;
  848. }
  849. }
  850. }
  851. ret = -EFAULT;
  852. }
  853. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_COMMON_MEMORY\n");
  854. }
  855. break;
  856. case VDI_IOCTL_OPEN_INSTANCE:
  857. {
  858. vpudrv_inst_info_t inst_info;
  859. vpudrv_instanace_list_t *vil, *n;
  860. vil = kzalloc(sizeof(*vil), GFP_KERNEL);
  861. if (!vil)
  862. return -ENOMEM;
  863. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  864. return -EFAULT;
  865. vil->inst_idx = inst_info.inst_idx;
  866. vil->core_idx = inst_info.core_idx;
  867. vil->filp = filp;
  868. spin_lock(&s_vpu_lock);
  869. list_add(&vil->list, &s_inst_list_head);
  870. inst_info.inst_open_count = 0; /* counting the current open instance number */
  871. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  872. {
  873. if (vil->core_idx == inst_info.core_idx)
  874. inst_info.inst_open_count++;
  875. }
  876. #ifdef SUPPORT_MULTI_INST_INTR
  877. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  878. #endif
  879. spin_unlock(&s_vpu_lock);
  880. s_vpu_open_ref_count++; /* flag just for that vpu is in opened or closed */
  881. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t))) {
  882. kfree(vil);
  883. return -EFAULT;
  884. }
  885. DPRINTK("[VPUDRV] VDI_IOCTL_OPEN_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  886. }
  887. break;
  888. case VDI_IOCTL_CLOSE_INSTANCE:
  889. {
  890. vpudrv_inst_info_t inst_info;
  891. vpudrv_instanace_list_t *vil, *n;
  892. u32 found = 0;
  893. DPRINTK("[VPUDRV][+]VDI_IOCTL_CLOSE_INSTANCE\n");
  894. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  895. return -EFAULT;
  896. spin_lock(&s_vpu_lock);
  897. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  898. {
  899. if (vil->inst_idx == inst_info.inst_idx && vil->core_idx == inst_info.core_idx) {
  900. list_del(&vil->list);
  901. kfree(vil);
  902. found = 1;
  903. break;
  904. }
  905. }
  906. if (0 == found) {
  907. spin_unlock(&s_vpu_lock);
  908. return -EINVAL;
  909. }
  910. inst_info.inst_open_count = 0; /* counting the current open instance number */
  911. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  912. {
  913. if (vil->core_idx == inst_info.core_idx)
  914. inst_info.inst_open_count++;
  915. }
  916. #ifdef SUPPORT_MULTI_INST_INTR
  917. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  918. #endif
  919. spin_unlock(&s_vpu_lock);
  920. s_vpu_open_ref_count--; /* flag just for that vpu is in opened or closed */
  921. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t)))
  922. return -EFAULT;
  923. DPRINTK("[VPUDRV] VDI_IOCTL_CLOSE_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  924. }
  925. break;
  926. case VDI_IOCTL_GET_INSTANCE_NUM:
  927. {
  928. vpudrv_inst_info_t inst_info;
  929. vpudrv_instanace_list_t *vil, *n;
  930. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_NUM\n");
  931. ret = copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t));
  932. if (ret != 0)
  933. break;
  934. spin_lock(&s_vpu_lock);
  935. inst_info.inst_open_count = 0;
  936. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  937. {
  938. if (vil->core_idx == inst_info.core_idx)
  939. inst_info.inst_open_count++;
  940. }
  941. spin_unlock(&s_vpu_lock);
  942. ret = copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t));
  943. DPRINTK("[VPUDRV] VDI_IOCTL_GET_INSTANCE_NUM core_idx=%d, inst_idx=%d, open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, inst_info.inst_open_count);
  944. }
  945. break;
  946. case VDI_IOCTL_RESET:
  947. {
  948. //vpu_hw_reset();
  949. }
  950. break;
  951. case VDI_IOCTL_GET_REGISTER_INFO:
  952. {
  953. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_REGISTER_INFO\n");
  954. ret = copy_to_user((void __user *)arg, &s_vpu_register, sizeof(vpudrv_buffer_t));
  955. if (ret != 0)
  956. ret = -EFAULT;
  957. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_REGISTER_INFO s_vpu_register.phys_addr==0x%lx, s_vpu_register.virt_addr=0x%lx, s_vpu_register.size=%d\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr, s_vpu_register.size);
  958. }
  959. break;
  960. case VDI_IOCTL_FLUSH_DCACHE:
  961. {
  962. vpudrv_flush_cache_t cache_info;
  963. //DPRINTK("[JPUDRV][+]VDI_IOCTL_FLUSH_DCACHE\n");
  964. ret = copy_from_user(&cache_info, (vpudrv_flush_cache_t *)arg, sizeof(vpudrv_flush_cache_t));
  965. if (ret != 0)
  966. ret = -EFAULT;
  967. if(cache_info.flag)
  968. starfive_flush_dcache(cache_info.start,cache_info.size);
  969. //DPRINTK("[JPUDRV][-]VDI_IOCTL_FLUSH_DCACHE\n");
  970. break;
  971. }
  972. default:
  973. {
  974. printk(KERN_ERR "[VPUDRV] No such IOCTL, cmd is %d\n", cmd);
  975. }
  976. break;
  977. }
  978. return ret;
  979. }
  980. static ssize_t vpu_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos)
  981. {
  982. return -1;
  983. }
  984. static ssize_t vpu_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos)
  985. {
  986. /* DPRINTK("[VPUDRV] vpu_write len=%d\n", (int)len); */
  987. if (!buf) {
  988. printk(KERN_ERR "[VPUDRV] vpu_write buf = NULL error \n");
  989. return -EFAULT;
  990. }
  991. if (len == sizeof(vpu_bit_firmware_info_t)) {
  992. vpu_bit_firmware_info_t *bit_firmware_info;
  993. bit_firmware_info = kmalloc(sizeof(vpu_bit_firmware_info_t), GFP_KERNEL);
  994. if (!bit_firmware_info) {
  995. printk(KERN_ERR "[VPUDRV] vpu_write bit_firmware_info allocation error \n");
  996. return -EFAULT;
  997. }
  998. if (copy_from_user(bit_firmware_info, buf, len)) {
  999. printk(KERN_ERR "[VPUDRV] vpu_write copy_from_user error for bit_firmware_info\n");
  1000. return -EFAULT;
  1001. }
  1002. if (bit_firmware_info->size == sizeof(vpu_bit_firmware_info_t)) {
  1003. DPRINTK("[VPUDRV] vpu_write set bit_firmware_info coreIdx=0x%x, reg_base_offset=0x%x size=0x%x, bit_code[0]=0x%x\n",
  1004. bit_firmware_info->core_idx, (int)bit_firmware_info->reg_base_offset, bit_firmware_info->size, bit_firmware_info->bit_code[0]);
  1005. if (bit_firmware_info->core_idx > MAX_NUM_VPU_CORE) {
  1006. printk(KERN_ERR "[VPUDRV] vpu_write coreIdx[%d] is exceeded than MAX_NUM_VPU_CORE[%d]\n", bit_firmware_info->core_idx, MAX_NUM_VPU_CORE);
  1007. return -ENODEV;
  1008. }
  1009. memcpy((void *)&s_bit_firmware_info[bit_firmware_info->core_idx], bit_firmware_info, sizeof(vpu_bit_firmware_info_t));
  1010. kfree(bit_firmware_info);
  1011. return len;
  1012. }
  1013. kfree(bit_firmware_info);
  1014. }
  1015. return -1;
  1016. }
  1017. static int vpu_release(struct inode *inode, struct file *filp)
  1018. {
  1019. int ret = 0;
  1020. u32 open_count;
  1021. #ifdef SUPPORT_MULTI_INST_INTR
  1022. int i;
  1023. #endif
  1024. DPRINTK("[VPUDRV] vpu_release\n");
  1025. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  1026. /* found and free the not handled buffer by user applications */
  1027. vpu_free_buffers(filp);
  1028. /* found and free the not closed instance by user applications */
  1029. vpu_free_instances(filp);
  1030. spin_lock(&s_vpu_lock);
  1031. s_vpu_drv_context.open_count--;
  1032. open_count = s_vpu_drv_context.open_count;
  1033. spin_unlock(&s_vpu_lock);
  1034. if (open_count == 0) {
  1035. #ifdef SUPPORT_MULTI_INST_INTR
  1036. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1037. kfifo_reset(&s_interrupt_pending_q[i]);
  1038. }
  1039. #endif
  1040. if (s_instance_pool.base) {
  1041. DPRINTK("[VPUDRV] free instance pool\n");
  1042. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1043. vfree((const void *)s_instance_pool.base);
  1044. #else
  1045. vpu_free_dma_buffer(&s_instance_pool);
  1046. #endif
  1047. s_instance_pool.base = 0;
  1048. }
  1049. }
  1050. }
  1051. up(&s_vpu_sem);
  1052. return 0;
  1053. }
  1054. static int vpu_fasync(int fd, struct file *filp, int mode)
  1055. {
  1056. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  1057. return fasync_helper(fd, filp, mode, &dev->async_queue);
  1058. }
  1059. static int vpu_map_to_register(struct file *fp, struct vm_area_struct *vm)
  1060. {
  1061. unsigned long pfn;
  1062. vm->vm_flags |= VM_IO | VM_RESERVED;
  1063. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1064. pfn = s_vpu_register.phys_addr >> PAGE_SHIFT;
  1065. return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1066. }
  1067. static int vpu_map_to_physical_memory(struct file *fp, struct vm_area_struct *vm)
  1068. {
  1069. vm->vm_flags |= VM_IO | VM_RESERVED;
  1070. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1071. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1072. }
  1073. static int vpu_map_to_instance_pool_memory(struct file *fp, struct vm_area_struct *vm)
  1074. {
  1075. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1076. int ret;
  1077. long length = vm->vm_end - vm->vm_start;
  1078. unsigned long start = vm->vm_start;
  1079. char *vmalloc_area_ptr = (char *)s_instance_pool.base;
  1080. unsigned long pfn;
  1081. vm->vm_flags |= VM_RESERVED;
  1082. /* loop over all pages, map it page individually */
  1083. while (length > 0)
  1084. {
  1085. pfn = vmalloc_to_pfn(vmalloc_area_ptr);
  1086. if ((ret = remap_pfn_range(vm, start, pfn, PAGE_SIZE, PAGE_SHARED)) < 0) {
  1087. return ret;
  1088. }
  1089. start += PAGE_SIZE;
  1090. vmalloc_area_ptr += PAGE_SIZE;
  1091. length -= PAGE_SIZE;
  1092. }
  1093. return 0;
  1094. #else
  1095. vm->vm_flags |= VM_RESERVED;
  1096. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1097. #endif
  1098. }
  1099. /*!
  1100. * @brief memory map interface for vpu file operation
  1101. * @return 0 on success or negative error code on error
  1102. */
  1103. static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
  1104. {
  1105. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1106. if (vm->vm_pgoff == 0)
  1107. return vpu_map_to_instance_pool_memory(fp, vm);
  1108. if (vm->vm_pgoff == (s_vpu_register.phys_addr>>PAGE_SHIFT))
  1109. return vpu_map_to_register(fp, vm);
  1110. return vpu_map_to_physical_memory(fp, vm);
  1111. #else
  1112. if (vm->vm_pgoff) {
  1113. if (vm->vm_pgoff == (s_instance_pool.phys_addr>>PAGE_SHIFT))
  1114. return vpu_map_to_instance_pool_memory(fp, vm);
  1115. return vpu_map_to_physical_memory(fp, vm);
  1116. } else {
  1117. return vpu_map_to_register(fp, vm);
  1118. }
  1119. #endif
  1120. }
  1121. struct file_operations vpu_fops = {
  1122. .owner = THIS_MODULE,
  1123. .open = vpu_open,
  1124. .read = vpu_read,
  1125. .write = vpu_write,
  1126. /*.ioctl = vpu_ioctl, // for kernel 2.6.9 of C&M*/
  1127. .unlocked_ioctl = vpu_ioctl,
  1128. .release = vpu_release,
  1129. .fasync = vpu_fasync,
  1130. .mmap = vpu_mmap,
  1131. };
  1132. static struct resource venc_resource[] = {
  1133. [0] = {
  1134. .start = VPU_REG_BASE_ADDR,
  1135. .end = VPU_REG_BASE_ADDR + VPU_REG_SIZE - 1,
  1136. .flags = IORESOURCE_MEM,
  1137. },
  1138. [1] = {
  1139. .start = VENC_IRQ_ADDR,
  1140. .end = VENC_IRQ_ADDR,
  1141. .flags = IORESOURCE_IRQ,
  1142. },
  1143. };
  1144. static int vpu_probe(struct platform_device *pdev)
  1145. {
  1146. int err = 0;
  1147. struct resource *res = NULL;
  1148. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1149. struct resource res_cma;
  1150. struct device_node *node;
  1151. #endif
  1152. DPRINTK("[VPUDRV] vpu_probe\n");
  1153. if(pdev){
  1154. vpu_dev = &pdev->dev;
  1155. vpu_dev->coherent_dma_mask = 0xffffffff;
  1156. //vpu_dev->dma_ops = NULL;
  1157. dev_info(vpu_dev,"device init.\n");
  1158. }
  1159. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1160. vpu_dev->of_node = of_find_node_by_name(NULL, "vpu_enc");
  1161. if (!(vpu_dev->of_node))
  1162. printk("The node of vpu_enc is not found in device tree.\n");
  1163. err = of_address_to_resource(vpu_dev->of_node, 0, &venc_resource[0]);
  1164. if (err) {
  1165. printk(KERN_ERR "could not find venc register address\n");
  1166. goto ERROR_PROVE_DEVICE;
  1167. }
  1168. venc_resource[1].start = irq_of_parse_and_map(vpu_dev->of_node, 0);
  1169. venc_resource[1].end = venc_resource[1].start;
  1170. err = platform_device_add_resources(pdev, venc_resource, 2);
  1171. if (err) {
  1172. printk(KERN_ERR "could not add venc resource\n");
  1173. goto ERROR_PROVE_DEVICE;
  1174. }
  1175. #endif
  1176. if (pdev)
  1177. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1178. if (res) {/* if platform driver is implemented */
  1179. s_vpu_register.phys_addr = res->start;
  1180. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(res->start, res->end - res->start);
  1181. s_vpu_register.size = res->end - res->start;
  1182. DPRINTK("[VPUDRV] : vpu base address get from platform driver physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr);
  1183. } else {
  1184. s_vpu_register.phys_addr = VPU_REG_BASE_ADDR;
  1185. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(s_vpu_register.phys_addr, VPU_REG_SIZE);
  1186. s_vpu_register.size = VPU_REG_SIZE;
  1187. DPRINTK("[VPUDRV] : vpu base address get from defined value physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr, s_vpu_register.virt_addr);
  1188. }
  1189. /* get the major number of the character device */
  1190. if ((alloc_chrdev_region(&s_vpu_major, 0, 1, VPU_DEV_NAME)) < 0) {
  1191. err = -EBUSY;
  1192. printk(KERN_ERR "could not allocate major number\n");
  1193. goto ERROR_PROVE_DEVICE;
  1194. }
  1195. printk(KERN_INFO "SUCCESS alloc_chrdev_region\n");
  1196. /* initialize the device structure and register the device with the kernel */
  1197. cdev_init(&s_vpu_cdev, &vpu_fops);
  1198. if ((cdev_add(&s_vpu_cdev, s_vpu_major, 1)) < 0) {
  1199. err = -EBUSY;
  1200. printk(KERN_ERR "could not allocate chrdev\n");
  1201. goto ERROR_PROVE_DEVICE;
  1202. }
  1203. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1204. err = starfive_venc_clk_rst_init(pdev);
  1205. if (err){
  1206. goto ERROR_PROVE_DEVICE;
  1207. }
  1208. #else
  1209. vpu_clk_enable();
  1210. vpu_hw_reset();
  1211. #endif
  1212. #ifdef VPU_SUPPORT_ISR
  1213. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1214. if (pdev)
  1215. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1216. if (res) {/* if platform driver is implemented */
  1217. s_vpu_irq = res->start;
  1218. DPRINTK("[VPUDRV] : vpu irq number get from platform driver irq=0x%x\n", s_vpu_irq);
  1219. } else {
  1220. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1221. }
  1222. #else
  1223. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1224. #endif
  1225. err = request_irq(s_vpu_irq, vpu_irq_handler, 0, pdev->name, (void *)(&s_vpu_drv_context));
  1226. if (err) {
  1227. printk(KERN_ERR "[VPUDRV] : fail to register interrupt handler\n");
  1228. goto ERROR_PROVE_DEVICE;
  1229. }
  1230. #endif
  1231. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1232. printk("start memory-region: of_node:%#lx \n",(unsigned long)vpu_dev->of_node);
  1233. node = of_parse_phandle(vpu_dev->of_node, "memory-region", 0);
  1234. if(node){
  1235. dev_info(vpu_dev, "Get mem form memory-region\n");
  1236. of_address_to_resource(node, 0, &res_cma);
  1237. s_video_memory.size = resource_size(&res_cma);
  1238. s_video_memory.phys_addr = res_cma.start;
  1239. }else{
  1240. dev_info(vpu_dev, "Get mem form memory-region filed. please check the dts file.\n");
  1241. //dev_info(vpu_dev, "Using default cma reserved space..\n");
  1242. //s_video_memory.phys_addr = 0xa3000000;
  1243. //s_video_memory.size = 0x10000000;
  1244. return 0;
  1245. }
  1246. s_video_memory.base = (unsigned long)ioremap_nocache(DRAM_MEM2SYS(s_video_memory.phys_addr), PAGE_ALIGN(s_video_memory.size));
  1247. if (!s_video_memory.base) {
  1248. printk(KERN_ERR "[VPUDRV] : fail to remap video memory physical phys_addr==0x%lx, base==0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base, (int)s_video_memory.size);
  1249. goto ERROR_PROVE_DEVICE;
  1250. }
  1251. if (vmem_init(&s_vmem, s_video_memory.phys_addr, s_video_memory.size) < 0) {
  1252. printk(KERN_ERR "[VPUDRV] : fail to init vmem system\n");
  1253. goto ERROR_PROVE_DEVICE;
  1254. }
  1255. DPRINTK("[VPUDRV] success to probe vpu device with reserved video memory phys_addr==0x%lx, base = =0x%lx\n", s_video_memory.phys_addr, s_video_memory.base);
  1256. #else
  1257. DPRINTK("[VPUDRV] success to probe vpu device with non reserved video memory\n");
  1258. #endif
  1259. return 0;
  1260. ERROR_PROVE_DEVICE:
  1261. if (s_vpu_major)
  1262. unregister_chrdev_region(s_vpu_major, 1);
  1263. if (s_vpu_register.virt_addr)
  1264. iounmap((void *)s_vpu_register.virt_addr);
  1265. return err;
  1266. }
  1267. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1268. static int vpu_remove(struct platform_device *pdev)
  1269. {
  1270. DPRINTK("[VPUDRV] vpu_remove\n");
  1271. if (s_instance_pool.base) {
  1272. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1273. vfree((const void *)s_instance_pool.base);
  1274. #else
  1275. vpu_free_dma_buffer(&s_instance_pool);
  1276. #endif
  1277. s_instance_pool.base = 0;
  1278. }
  1279. if (s_common_memory.base) {
  1280. vpu_free_dma_buffer(&s_common_memory);
  1281. s_common_memory.base = 0;
  1282. }
  1283. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1284. if (s_video_memory.base) {
  1285. iounmap((void *)s_video_memory.base);
  1286. s_video_memory.base = 0;
  1287. vmem_exit(&s_vmem);
  1288. }
  1289. #endif
  1290. if (s_vpu_major > 0) {
  1291. cdev_del(&s_vpu_cdev);
  1292. unregister_chrdev_region(s_vpu_major, 1);
  1293. s_vpu_major = 0;
  1294. }
  1295. #ifdef VPU_SUPPORT_ISR
  1296. if (s_vpu_irq)
  1297. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1298. #endif
  1299. if (s_vpu_register.virt_addr)
  1300. iounmap((void *)s_vpu_register.virt_addr);
  1301. return 0;
  1302. }
  1303. #endif /*VPU_SUPPORT_PLATFORM_DRIVER_REGISTER*/
  1304. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  1305. #define W5_MAX_CODE_BUF_SIZE (512*1024)
  1306. #define W5_CMD_INIT_VPU (0x0001)
  1307. #define W5_CMD_SLEEP_VPU (0x0004)
  1308. #define W5_CMD_WAKEUP_VPU (0x0002)
  1309. static void Wave5BitIssueCommand(int core, u32 cmd)
  1310. {
  1311. WriteVpuRegister(W5_VPU_BUSY_STATUS, 1);
  1312. WriteVpuRegister(W5_COMMAND, cmd);
  1313. WriteVpuRegister(W5_VPU_HOST_INT_REQ, 1);
  1314. return;
  1315. }
  1316. static int vpu_suspend(struct platform_device *pdev, pm_message_t state)
  1317. {
  1318. int i;
  1319. int core;
  1320. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1321. int product_code;
  1322. DPRINTK("[VPUDRV] vpu_suspend\n");
  1323. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1324. starfive_venc_clk_enable(&pdev->dev);
  1325. #else
  1326. vpu_clk_enable();
  1327. #endif
  1328. if (s_vpu_open_ref_count > 0) {
  1329. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1330. if (s_bit_firmware_info[core].size == 0)
  1331. continue;
  1332. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1333. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1334. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1335. if (time_after(jiffies, timeout)) {
  1336. DPRINTK("SLEEP_VPU BUSY timeout");
  1337. goto DONE_SUSPEND;
  1338. }
  1339. }
  1340. Wave5BitIssueCommand(core, W5_CMD_SLEEP_VPU);
  1341. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1342. if (time_after(jiffies, timeout)) {
  1343. DPRINTK("SLEEP_VPU BUSY timeout");
  1344. goto DONE_SUSPEND;
  1345. }
  1346. }
  1347. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1348. DPRINTK("SLEEP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1349. goto DONE_SUSPEND;
  1350. }
  1351. }
  1352. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1353. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1354. if (time_after(jiffies, timeout))
  1355. goto DONE_SUSPEND;
  1356. }
  1357. for (i = 0; i < 64; i++)
  1358. s_vpu_reg_store[core][i] = ReadVpuRegister(BIT_BASE+(0x100+(i * 4)));
  1359. }
  1360. else {
  1361. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1362. goto DONE_SUSPEND;
  1363. }
  1364. }
  1365. }
  1366. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1367. starfive_venc_clk_disable(&pdev->dev);
  1368. #else
  1369. vpu_clk_disable();
  1370. #endif
  1371. return 0;
  1372. DONE_SUSPEND:
  1373. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1374. starfive_venc_clk_disable(&pdev->dev);
  1375. #else
  1376. vpu_clk_disable();
  1377. #endif
  1378. return -EAGAIN;
  1379. }
  1380. static int vpu_resume(struct platform_device *pdev)
  1381. {
  1382. int i;
  1383. int core;
  1384. u32 val;
  1385. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1386. int product_code;
  1387. unsigned long code_base;
  1388. u32 code_size;
  1389. u32 remap_size;
  1390. int regVal;
  1391. u32 hwOption = 0;
  1392. DPRINTK("[VPUDRV] vpu_resume\n");
  1393. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1394. starfive_venc_clk_enable(&pdev->dev);
  1395. #else
  1396. vpu_clk_enable();
  1397. #endif
  1398. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1399. if (s_bit_firmware_info[core].size == 0) {
  1400. continue;
  1401. }
  1402. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1403. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1404. code_base = s_common_memory.phys_addr;
  1405. /* ALIGN TO 4KB */
  1406. code_size = (W5_MAX_CODE_BUF_SIZE&~0xfff);
  1407. if (code_size < s_bit_firmware_info[core].size*2) {
  1408. goto DONE_WAKEUP;
  1409. }
  1410. regVal = 0;
  1411. WriteVpuRegister(W5_PO_CONF, regVal);
  1412. /* Reset All blocks */
  1413. regVal = 0x7ffffff;
  1414. WriteVpuRegister(W5_VPU_RESET_REQ, regVal); /*Reset All blocks*/
  1415. /* Waiting reset done */
  1416. while (ReadVpuRegister(W5_VPU_RESET_STATUS)) {
  1417. if (time_after(jiffies, timeout))
  1418. goto DONE_WAKEUP;
  1419. }
  1420. WriteVpuRegister(W5_VPU_RESET_REQ, 0);
  1421. /* remap page size */
  1422. remap_size = (code_size >> 12) & 0x1ff;
  1423. regVal = 0x80000000 | (W5_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remap_size;
  1424. WriteVpuRegister(W5_VPU_REMAP_CTRL, regVal);
  1425. WriteVpuRegister(W5_VPU_REMAP_VADDR,0x00000000); /* DO NOT CHANGE! */
  1426. WriteVpuRegister(W5_VPU_REMAP_PADDR,code_base);
  1427. WriteVpuRegister(W5_ADDR_CODE_BASE, code_base);
  1428. WriteVpuRegister(W5_CODE_SIZE, code_size);
  1429. WriteVpuRegister(W5_CODE_PARAM, 0);
  1430. WriteVpuRegister(W5_INIT_VPU_TIME_OUT_CNT, timeout);
  1431. WriteVpuRegister(W5_HW_OPTION, hwOption);
  1432. /* Interrupt */
  1433. if (product_code == WAVE521_CODE || product_code == WAVE521C_CODE ) {
  1434. regVal = (1<<INT_WAVE5_ENC_SET_PARAM);
  1435. regVal |= (1<<INT_WAVE5_ENC_PIC);
  1436. regVal |= (1<<INT_WAVE5_INIT_SEQ);
  1437. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1438. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1439. }
  1440. else {
  1441. // decoder
  1442. regVal = (1<<INT_WAVE5_INIT_SEQ);
  1443. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1444. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1445. }
  1446. WriteVpuRegister(W5_VPU_VINT_ENABLE, regVal);
  1447. Wave5BitIssueCommand(core, W5_CMD_INIT_VPU);
  1448. WriteVpuRegister(W5_VPU_REMAP_CORE_START, 1);
  1449. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1450. if (time_after(jiffies, timeout))
  1451. goto DONE_WAKEUP;
  1452. }
  1453. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1454. DPRINTK("WAKEUP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1455. goto DONE_WAKEUP;
  1456. }
  1457. }
  1458. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1459. WriteVpuRegister(BIT_CODE_RUN, 0);
  1460. /*---- LOAD BOOT CODE*/
  1461. for (i = 0; i < 512; i++) {
  1462. val = s_bit_firmware_info[core].bit_code[i];
  1463. WriteVpuRegister(BIT_CODE_DOWN, ((i << 16) | val));
  1464. }
  1465. for (i = 0 ; i < 64 ; i++)
  1466. WriteVpuRegister(BIT_BASE+(0x100+(i * 4)), s_vpu_reg_store[core][i]);
  1467. WriteVpuRegister(BIT_BUSY_FLAG, 1);
  1468. WriteVpuRegister(BIT_CODE_RESET, 1);
  1469. WriteVpuRegister(BIT_CODE_RUN, 1);
  1470. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1471. if (time_after(jiffies, timeout))
  1472. goto DONE_WAKEUP;
  1473. }
  1474. }
  1475. else {
  1476. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1477. goto DONE_WAKEUP;
  1478. }
  1479. }
  1480. if (s_vpu_open_ref_count == 0){
  1481. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1482. starfive_venc_clk_disable(&pdev->dev);
  1483. #else
  1484. vpu_clk_disable();
  1485. #endif
  1486. }
  1487. DONE_WAKEUP:
  1488. if (s_vpu_open_ref_count > 0){
  1489. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1490. starfive_venc_clk_enable(&pdev->dev);
  1491. #else
  1492. vpu_clk_enable();
  1493. #endif
  1494. }
  1495. return 0;
  1496. }
  1497. #else
  1498. #define vpu_suspend NULL
  1499. #define vpu_resume NULL
  1500. #endif /* !CONFIG_PM */
  1501. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1502. static const struct of_device_id vpu_of_id_table[] = {
  1503. { .compatible = "cm,cm521-vpu" },
  1504. {}
  1505. };
  1506. static struct platform_driver vpu_driver = {
  1507. .driver = {
  1508. .name = VPU_PLATFORM_DEVICE_NAME,
  1509. .of_match_table = of_match_ptr(vpu_of_id_table),
  1510. },
  1511. .probe = vpu_probe,
  1512. .remove = vpu_remove,
  1513. .suspend = vpu_suspend,
  1514. .resume = vpu_resume,
  1515. };
  1516. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1517. static int __init vpu_init(void)
  1518. {
  1519. int res;
  1520. #ifdef SUPPORT_MULTI_INST_INTR
  1521. int i;
  1522. #endif
  1523. DPRINTK("[VPUDRV] begin vpu_init\n");
  1524. #ifdef SUPPORT_MULTI_INST_INTR
  1525. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1526. init_waitqueue_head(&s_interrupt_wait_q[i]);
  1527. }
  1528. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1529. #define MAX_INTERRUPT_QUEUE (16*MAX_NUM_INSTANCE)
  1530. res = kfifo_alloc(&s_interrupt_pending_q[i], MAX_INTERRUPT_QUEUE*sizeof(u32), GFP_KERNEL);
  1531. if (res) {
  1532. DPRINTK("[VPUDRV] kfifo_alloc failed 0x%x\n", res);
  1533. }
  1534. }
  1535. #else
  1536. init_waitqueue_head(&s_interrupt_wait_q);
  1537. #endif
  1538. s_common_memory.base = 0;
  1539. s_instance_pool.base = 0;
  1540. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1541. res = platform_driver_register(&vpu_driver);
  1542. #else
  1543. res = vpu_probe(NULL);
  1544. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1545. DPRINTK("[VPUDRV] end vpu_init result=0x%x\n", res);
  1546. return res;
  1547. }
  1548. static void __exit vpu_exit(void)
  1549. {
  1550. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1551. starfive_venc_clk_disable(vpu_dev);
  1552. starfive_venc_rst_assert(vpu_dev);
  1553. #else
  1554. vpu_clk_disable();
  1555. #endif
  1556. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1557. DPRINTK("[VPUDRV] vpu_exit\n");
  1558. platform_driver_unregister(&vpu_driver);
  1559. #else /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1560. if (s_instance_pool.base) {
  1561. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1562. vfree((const void *)s_instance_pool.base);
  1563. #else
  1564. vpu_free_dma_buffer(&s_instance_pool);
  1565. #endif
  1566. s_instance_pool.base = 0;
  1567. }
  1568. if (s_common_memory.base) {
  1569. vpu_free_dma_buffer(&s_common_memory);
  1570. s_common_memory.base = 0;
  1571. }
  1572. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1573. if (s_video_memory.base) {
  1574. iounmap((void *)s_video_memory.base);
  1575. s_video_memory.base = 0;
  1576. vmem_exit(&s_vmem);
  1577. }
  1578. #endif
  1579. if (s_vpu_major > 0) {
  1580. cdev_del(&s_vpu_cdev);
  1581. unregister_chrdev_region(s_vpu_major, 1);
  1582. s_vpu_major = 0;
  1583. }
  1584. #ifdef VPU_SUPPORT_ISR
  1585. if (s_vpu_irq)
  1586. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1587. #endif
  1588. #ifdef SUPPORT_MULTI_INST_INTR
  1589. {
  1590. int i;
  1591. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1592. kfifo_free(&s_interrupt_pending_q[i]);
  1593. }
  1594. }
  1595. #endif
  1596. if (s_vpu_register.virt_addr) {
  1597. iounmap((void *)s_vpu_register.virt_addr);
  1598. s_vpu_register.virt_addr = 0x00;
  1599. }
  1600. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1601. return;
  1602. }
  1603. MODULE_AUTHOR("A customer using C&M VPU, Inc.");
  1604. MODULE_DESCRIPTION("VPU linux driver");
  1605. MODULE_LICENSE("GPL");
  1606. module_init(vpu_init);
  1607. module_exit(vpu_exit);
  1608. static void _set_reset(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg,int ibit)
  1609. {
  1610. unsigned int read_value;
  1611. read_value = vic_readl(p_assert_reg);
  1612. read_value &= ~(0x1<<ibit);
  1613. read_value |= (0x1&0x1)<<ibit;
  1614. vic_writel(read_value,p_assert_reg);
  1615. }
  1616. static void _clr_reset(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg,int ibit)
  1617. {
  1618. unsigned int read_value;
  1619. read_value = vic_readl(p_assert_reg);
  1620. read_value &= ~(0x1<<ibit);
  1621. read_value |= (0x0&0x1)<<ibit;
  1622. vic_writel(read_value,p_assert_reg);
  1623. }
  1624. static void _enable_clk(volatile unsigned long p_reg,int ibit)
  1625. {
  1626. unsigned int read_value;
  1627. read_value = vic_readl(p_reg);
  1628. read_value &= ~(0x1<<ibit);
  1629. read_value |= (0x1&0x1)<<ibit;
  1630. vic_writel(read_value,p_reg);
  1631. }
  1632. static void _disable_clk(volatile unsigned long p_reg,int ibit)
  1633. {
  1634. unsigned int read_value;
  1635. read_value = vic_readl(p_reg);
  1636. read_value &= ~(0x1<<ibit);
  1637. read_value |= (0x0&0x1)<<ibit;
  1638. vic_writel(read_value,p_reg);
  1639. }
  1640. static void _reset_assert(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg)
  1641. {
  1642. //_set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_BRG_MAIN);
  1643. _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_APB);
  1644. _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_AXI);
  1645. _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_BCLK);
  1646. _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_CCLK);
  1647. }
  1648. static void _reset_clear(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg)
  1649. {
  1650. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_BRG_MAIN);
  1651. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_AXI);
  1652. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_BCLK);
  1653. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_CCLK);
  1654. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_APB);
  1655. }
  1656. static int _reset(void)
  1657. {
  1658. volatile unsigned long p_breg = (unsigned long)ioremap_nocache(rstgen_Software_RESET_BASE_REG_ADDR,0x20);
  1659. if(!p_breg){
  1660. return -1;
  1661. }
  1662. _reset_assert(p_breg+rstgen_Software_RESET_assert0_OFFSET,p_breg+rstgen_Software_RESET_status0_OFFSET);
  1663. mdelay(1);
  1664. _reset_clear(p_breg+rstgen_Software_RESET_assert0_OFFSET,p_breg+rstgen_Software_RESET_status0_OFFSET);
  1665. iounmap((void *)p_breg);
  1666. return 0;
  1667. }
  1668. static int _clk_control(int enable)
  1669. {
  1670. volatile unsigned long p_breg = (unsigned long)ioremap_nocache(clk_BASE_REG_ADDR,0x100);
  1671. if(!p_breg){
  1672. return -1;
  1673. }
  1674. if(enable){
  1675. _enable_clk(p_breg+clk_venc_axi_ctrl_REG_OFFSET,31);
  1676. _enable_clk(p_breg+clk_vencbrg_mainclk_ctrl_REG_OFFSET,31);
  1677. _enable_clk(p_breg+clk_venc_bclk_ctrl_REG_OFFSET,31);
  1678. _enable_clk(p_breg+clk_venc_cclk_ctrl_REG_OFFSET,31);
  1679. _enable_clk(p_breg+clk_venc_apb_ctrl_REG_OFFSET,31);
  1680. }
  1681. else
  1682. {
  1683. _disable_clk(p_breg+clk_venc_axi_ctrl_REG_OFFSET,31);
  1684. // _disable_clk(p_breg+clk_vencbrg_mainclk_ctrl_REG_OFFSET,31);
  1685. _disable_clk(p_breg+clk_venc_bclk_ctrl_REG_OFFSET,31);
  1686. _disable_clk(p_breg+clk_venc_cclk_ctrl_REG_OFFSET,31);
  1687. _disable_clk(p_breg+clk_venc_apb_ctrl_REG_OFFSET,31);
  1688. }
  1689. iounmap((void *)p_breg);
  1690. return 0;
  1691. }
  1692. int vpu_hw_reset(void)
  1693. {
  1694. _reset();
  1695. DPRINTK("[VPUDRV] request vpu reset from application. \n");
  1696. return 0;
  1697. }
  1698. int vpu_clk_enable(void)
  1699. {
  1700. _clk_control(1);
  1701. return 0;
  1702. }
  1703. void vpu_clk_disable(void)
  1704. {
  1705. _clk_control(0);
  1706. }