vdec.c 68 KB

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  1. #include <linux/kernel.h>
  2. #include <linux/mm.h>
  3. #include <linux/interrupt.h>
  4. #include <linux/ioport.h>
  5. #include <linux/module.h>
  6. #include <linux/platform_device.h>
  7. #include <linux/dma-mapping.h>
  8. #include <linux/of.h>
  9. #include <linux/wait.h>
  10. #include <linux/list.h>
  11. #include <linux/clk.h>
  12. #include <linux/delay.h>
  13. #include <linux/uaccess.h>
  14. #include <linux/cdev.h>
  15. #include <linux/slab.h>
  16. #include <linux/of_address.h>
  17. #include <linux/sched.h>
  18. #include <linux/sched/signal.h>
  19. #include <linux/version.h>
  20. #include <linux/kfifo.h>
  21. #include <linux/kthread.h>
  22. #include <asm/io.h>
  23. #include <soc/sifive/sifive_l2_cache.h>
  24. #include "../../../vpuapi/vpuconfig.h"
  25. #include "vpu.h"
  26. #include "vdec-starfive.h"
  27. #define starfive_flush_dcache(start, len) \
  28. sifive_l2_flush64_range(start, len)
  29. //#define ENABLE_DEBUG_MSG
  30. #ifdef ENABLE_DEBUG_MSG
  31. #define DPRINTK(args...) printk(KERN_INFO args);
  32. #else
  33. #define DPRINTK(args...)
  34. #endif
  35. /* definitions to be changed as customer configuration */
  36. /* if linux version is 5.15 or later, then can use clock and reset framework */
  37. #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)
  38. #define VPU_SUPPORT_CLOCK_CONTROL
  39. #endif
  40. /* if the driver want to use interrupt service from kernel ISR */
  41. #define VPU_SUPPORT_ISR
  42. #ifdef VPU_SUPPORT_ISR
  43. /* if the driver want to disable and enable IRQ whenever interrupt asserted. */
  44. //#define VPU_IRQ_CONTROL
  45. #endif
  46. /* if the platform driver knows the name of this driver */
  47. /* VPU_PLATFORM_DEVICE_NAME */
  48. #define VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  49. /* if this driver knows the dedicated video memory address */
  50. //#define VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  51. #define VPU_PLATFORM_DEVICE_NAME "vdec"
  52. #define VPU_CLK_NAME "vcodec"
  53. #define VPU_DEV_NAME "vdec"
  54. /* if the platform driver knows this driver */
  55. /* the definition of VPU_REG_BASE_ADDR and VPU_REG_SIZE are not meaningful */
  56. #define VPU_REG_BASE_ADDR 0x118F0000
  57. #define VPU_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
  58. #ifdef VPU_SUPPORT_ISR
  59. #define VPU_IRQ_NUM (23)
  60. #endif
  61. /* this definition is only for chipsnmedia FPGA board env */
  62. /* so for SOC env of customers can be ignored */
  63. #ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/
  64. #define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
  65. #endif
  66. struct device *vpu_dev;
  67. typedef struct vpu_drv_context_t {
  68. struct fasync_struct *async_queue;
  69. #ifdef SUPPORT_MULTI_INST_INTR
  70. unsigned long interrupt_reason[MAX_NUM_INSTANCE];
  71. #else
  72. unsigned long interrupt_reason;
  73. #endif
  74. u32 open_count; /*!<< device reference count. Not instance count */
  75. } vpu_drv_context_t;
  76. /* To track the allocated memory buffer */
  77. typedef struct vpudrv_buffer_pool_t {
  78. struct list_head list;
  79. struct vpudrv_buffer_t vb;
  80. struct file *filp;
  81. } vpudrv_buffer_pool_t;
  82. /* To track the instance index and buffer in instance pool */
  83. typedef struct vpudrv_instanace_list_t {
  84. struct list_head list;
  85. unsigned long inst_idx;
  86. unsigned long core_idx;
  87. struct file *filp;
  88. } vpudrv_instanace_list_t;
  89. typedef struct vpudrv_instance_pool_t {
  90. unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
  91. } vpudrv_instance_pool_t;
  92. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  93. #include "vmm.h"
  94. static video_mm_t s_vmem;
  95. static vpudrv_buffer_t s_video_memory = {0};
  96. #endif /*VPU_SUPPORT_RESERVED_VIDEO_MEMORY*/
  97. static int vpu_hw_reset(void);
  98. static void vpu_clk_disable(struct clk *clk);
  99. static int vpu_clk_enable(struct clk *clk);
  100. static struct clk *vpu_clk_get(struct device *dev);
  101. static void vpu_clk_put(struct clk *clk);
  102. /* end customer definition */
  103. static vpudrv_buffer_t s_instance_pool = {0};
  104. static vpudrv_buffer_t s_common_memory = {0};
  105. static vpu_drv_context_t s_vpu_drv_context;
  106. static int s_vpu_major;
  107. static struct cdev s_vpu_cdev;
  108. static struct clk *s_vpu_clk;
  109. static int s_vpu_open_ref_count;
  110. #ifdef VPU_SUPPORT_ISR
  111. static int s_vpu_irq = VPU_IRQ_NUM;
  112. #endif
  113. static vpudrv_buffer_t s_vpu_register = {0};
  114. #ifdef SUPPORT_MULTI_INST_INTR
  115. static int s_interrupt_flag[MAX_NUM_INSTANCE];
  116. static wait_queue_head_t s_interrupt_wait_q[MAX_NUM_INSTANCE];
  117. typedef struct kfifo kfifo_t;
  118. static kfifo_t s_interrupt_pending_q[MAX_NUM_INSTANCE];
  119. static spinlock_t s_kfifo_lock = __SPIN_LOCK_UNLOCKED(s_kfifo_lock);
  120. #else
  121. static int s_interrupt_flag;
  122. static wait_queue_head_t s_interrupt_wait_q;
  123. #endif
  124. static spinlock_t s_vpu_lock = __SPIN_LOCK_UNLOCKED(s_vpu_lock);
  125. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
  126. static DECLARE_MUTEX(s_vpu_sem);
  127. #else
  128. static DEFINE_SEMAPHORE(s_vpu_sem);
  129. #endif
  130. static struct list_head s_vbp_head = LIST_HEAD_INIT(s_vbp_head);
  131. static struct list_head s_inst_list_head = LIST_HEAD_INIT(s_inst_list_head);
  132. static vpu_bit_firmware_info_t s_bit_firmware_info[MAX_NUM_VPU_CORE];
  133. //#ifdef CONFIG_PM
  134. /* implement to power management functions */
  135. #define BIT_BASE 0x0000
  136. #define BIT_CODE_RUN (BIT_BASE + 0x000)
  137. #define BIT_CODE_DOWN (BIT_BASE + 0x004)
  138. #define BIT_INT_CLEAR (BIT_BASE + 0x00C)
  139. #define BIT_INT_STS (BIT_BASE + 0x010)
  140. #define BIT_CODE_RESET (BIT_BASE + 0x014)
  141. #define BIT_INT_REASON (BIT_BASE + 0x174)
  142. #define BIT_BUSY_FLAG (BIT_BASE + 0x160)
  143. #define BIT_RUN_COMMAND (BIT_BASE + 0x164)
  144. #define BIT_RUN_INDEX (BIT_BASE + 0x168)
  145. #define BIT_RUN_COD_STD (BIT_BASE + 0x16C)
  146. /* WAVE5 registers */
  147. #define W5_REG_BASE 0x0000
  148. #define W5_VPU_BUSY_STATUS (W5_REG_BASE + 0x0070)
  149. #define W5_VPU_INT_REASON_CLEAR (W5_REG_BASE + 0x0034)
  150. #define W5_VPU_VINT_CLEAR (W5_REG_BASE + 0x003C)
  151. #define W5_VPU_VPU_INT_STS (W5_REG_BASE + 0x0044)
  152. #define W5_VPU_INT_REASON (W5_REG_BASE + 0x004c)
  153. #define W5_RET_FAIL_REASON (W5_REG_BASE + 0x010C)
  154. #ifdef SUPPORT_MULTI_INST_INTR
  155. #define W5_RET_BS_EMPTY_INST (W5_REG_BASE + 0x01E4)
  156. #define W5_RET_QUEUE_CMD_DONE_INST (W5_REG_BASE + 0x01E8)
  157. #define W5_RET_SEQ_DONE_INSTANCE_INFO (W5_REG_BASE + 0x01FC)
  158. typedef enum {
  159. INT_WAVE5_INIT_VPU = 0,
  160. INT_WAVE5_WAKEUP_VPU = 1,
  161. INT_WAVE5_SLEEP_VPU = 2,
  162. INT_WAVE5_CREATE_INSTANCE = 3,
  163. INT_WAVE5_FLUSH_INSTANCE = 4,
  164. INT_WAVE5_DESTORY_INSTANCE = 5,
  165. INT_WAVE5_INIT_SEQ = 6,
  166. INT_WAVE5_SET_FRAMEBUF = 7,
  167. INT_WAVE5_DEC_PIC = 8,
  168. INT_WAVE5_ENC_PIC = 8,
  169. INT_WAVE5_ENC_SET_PARAM = 9,
  170. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  171. INT_WAVE5_ENC_SRC_RELEASE = 10,
  172. #endif
  173. INT_WAVE5_ENC_LOW_LATENCY = 13,
  174. INT_WAVE5_DEC_QUERY = 14,
  175. INT_WAVE5_BSBUF_EMPTY = 15,
  176. INT_WAVE5_BSBUF_FULL = 15,
  177. } Wave5InterruptBit;
  178. #endif
  179. /* WAVE5 INIT, WAKEUP */
  180. #define W5_PO_CONF (W5_REG_BASE + 0x0000)
  181. #define W5_VPU_VINT_ENABLE (W5_REG_BASE + 0x0048)
  182. #define W5_VPU_RESET_REQ (W5_REG_BASE + 0x0050)
  183. #define W5_VPU_RESET_STATUS (W5_REG_BASE + 0x0054)
  184. #define W5_VPU_REMAP_CTRL (W5_REG_BASE + 0x0060)
  185. #define W5_VPU_REMAP_VADDR (W5_REG_BASE + 0x0064)
  186. #define W5_VPU_REMAP_PADDR (W5_REG_BASE + 0x0068)
  187. #define W5_VPU_REMAP_CORE_START (W5_REG_BASE + 0x006C)
  188. #define W5_REMAP_CODE_INDEX 0
  189. /* WAVE5 registers */
  190. #define W5_ADDR_CODE_BASE (W5_REG_BASE + 0x0110)
  191. #define W5_CODE_SIZE (W5_REG_BASE + 0x0114)
  192. #define W5_CODE_PARAM (W5_REG_BASE + 0x0118)
  193. #define W5_INIT_VPU_TIME_OUT_CNT (W5_REG_BASE + 0x0130)
  194. #define W5_HW_OPTION (W5_REG_BASE + 0x012C)
  195. #define W5_RET_SUCCESS (W5_REG_BASE + 0x0108)
  196. #define W5_COMMAND (W5_REG_BASE + 0x0100)
  197. #define W5_VPU_HOST_INT_REQ (W5_REG_BASE + 0x0038)
  198. /* Product register */
  199. #define VPU_PRODUCT_CODE_REGISTER (BIT_BASE + 0x1044)
  200. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  201. static u32 s_vpu_reg_store[MAX_NUM_VPU_CORE][64];
  202. #endif
  203. //#endif //CONFIG_PM
  204. #define ReadVpuRegister(addr) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr)
  205. #define WriteVpuRegister(addr, val) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr) = (unsigned int)val
  206. #define WriteVpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
  207. #define vic_readl(addr) readl((void __iomem *)addr)
  208. #define vic_writel(val,addr) writel(val,(void __iomem *)addr)
  209. #define rstgen_Software_RESET_BASE_REG_ADDR 0x11840000
  210. #define rstgen_Software_RESET_assert0_OFFSET (0x0)
  211. #define rstgen_Software_RESET_status0_OFFSET (0x10)
  212. #define NBIT_RSTN_VDEC_BRG_MAIN 13
  213. #define NBIT_RSTN_VDEC_AXI 14
  214. #define NBIT_RSTN_VDEC_BCLK 15
  215. #define NBIT_RSTN_VDEC_CCLK 16
  216. #define NBIT_RSTN_VDEC_APB 17
  217. #define clk_BASE_REG_ADDR 0x11800000
  218. #define clk_vdec_axi_ctrl_REG_OFFSET (0xac)
  219. #define clk_vdecbrg_mainclk_ctrl_REG_OFFSET (0xb0)
  220. #define clk_vdec_bclk_ctrl_REG_OFFSET (0xb4)
  221. #define clk_vdec_cclk_ctrl_REG_OFFSET (0xb8)
  222. #define clk_vdec_apb_ctrl_REG_OFFSET (0xbc)
  223. static int vpu_alloc_dma_buffer(vpudrv_buffer_t *vb)
  224. {
  225. if (!vb)
  226. return -1;
  227. DPRINTK("[VPUDRV] vpu_alloc_dma_buffer \n");
  228. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  229. vb->phys_addr = (unsigned long)vmem_alloc(&s_vmem, vb->size, 0);
  230. if ((unsigned long)vb->phys_addr == (unsigned long)-1) {
  231. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  232. return -1;
  233. }
  234. vb->base = (unsigned long)(s_video_memory.base + (vb->phys_addr - s_video_memory.phys_addr));
  235. #else
  236. vb->base = (unsigned long)dma_alloc_coherent(vpu_dev, PAGE_ALIGN(vb->size), (dma_addr_t *) (&vb->phys_addr), GFP_DMA | GFP_KERNEL);
  237. if ((void *)(vb->base) == NULL) {
  238. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  239. return -1;
  240. }
  241. starfive_flush_dcache(vb->phys_addr,PAGE_ALIGN(vb->size));
  242. #endif
  243. return 0;
  244. }
  245. static void vpu_free_dma_buffer(vpudrv_buffer_t *vb)
  246. {
  247. if (!vb)
  248. return;
  249. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  250. if (vb->base)
  251. vmem_free(&s_vmem, vb->phys_addr, 0);
  252. #else
  253. if (vb->base)
  254. dma_free_coherent(vpu_dev, PAGE_ALIGN(vb->size), (void *)vb->base, vb->phys_addr);
  255. #endif
  256. }
  257. static int vpu_free_instances(struct file *filp)
  258. {
  259. vpudrv_instanace_list_t *vil, *n;
  260. vpudrv_instance_pool_t *vip;
  261. void *vip_base;
  262. int instance_pool_size_per_core;
  263. void *vdi_mutexes_base;
  264. const int PTHREAD_MUTEX_T_DESTROY_VALUE = 0xdead10cc;
  265. DPRINTK("[VPUDRV] vpu_free_instances\n");
  266. instance_pool_size_per_core = (s_instance_pool.size/MAX_NUM_VPU_CORE); /* s_instance_pool.size assigned to the size of all core once call VDI_IOCTL_GET_INSTANCE_POOL by user. */
  267. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  268. {
  269. if (vil->filp == filp) {
  270. vip_base = (void *)(s_instance_pool.base + (instance_pool_size_per_core*vil->core_idx));
  271. DPRINTK("[VPUDRV] vpu_free_instances detect instance crash instIdx=%d, coreIdx=%d, vip_base=%p, instance_pool_size_per_core=%d\n", (int)vil->inst_idx, (int)vil->core_idx, vip_base, (int)instance_pool_size_per_core);
  272. vip = (vpudrv_instance_pool_t *)vip_base;
  273. if (vip) {
  274. memset(&vip->codecInstPool[vil->inst_idx], 0x00, 4); /* only first 4 byte is key point(inUse of CodecInst in vpuapi) to free the corresponding instance. */
  275. #define PTHREAD_MUTEX_T_HANDLE_SIZE 4
  276. vdi_mutexes_base = (vip_base + (instance_pool_size_per_core - PTHREAD_MUTEX_T_HANDLE_SIZE*4));
  277. DPRINTK("[VPUDRV] vpu_free_instances : force to destroy vdi_mutexes_base=%p in userspace \n", vdi_mutexes_base);
  278. if (vdi_mutexes_base) {
  279. int i;
  280. for (i = 0; i < 4; i++) {
  281. memcpy(vdi_mutexes_base, &PTHREAD_MUTEX_T_DESTROY_VALUE, PTHREAD_MUTEX_T_HANDLE_SIZE);
  282. vdi_mutexes_base += PTHREAD_MUTEX_T_HANDLE_SIZE;
  283. }
  284. }
  285. }
  286. s_vpu_open_ref_count--;
  287. list_del(&vil->list);
  288. kfree(vil);
  289. }
  290. }
  291. return 1;
  292. }
  293. static int vpu_free_buffers(struct file *filp)
  294. {
  295. vpudrv_buffer_pool_t *pool, *n;
  296. vpudrv_buffer_t vb;
  297. DPRINTK("[VPUDRV] vpu_free_buffers\n");
  298. list_for_each_entry_safe(pool, n, &s_vbp_head, list)
  299. {
  300. if (pool->filp == filp) {
  301. vb = pool->vb;
  302. if (vb.base) {
  303. vpu_free_dma_buffer(&vb);
  304. list_del(&pool->list);
  305. kfree(pool);
  306. }
  307. }
  308. }
  309. return 0;
  310. }
  311. #ifdef SUPPORT_MULTI_INST_INTR
  312. static inline u32 get_inst_idx(u32 reg_val)
  313. {
  314. u32 inst_idx;
  315. int i;
  316. for (i=0; i < MAX_NUM_INSTANCE; i++)
  317. {
  318. if(((reg_val >> i)&0x01) == 1)
  319. break;
  320. }
  321. inst_idx = i;
  322. return inst_idx;
  323. }
  324. static s32 get_vpu_inst_idx(vpu_drv_context_t *dev, u32 *reason, u32 empty_inst, u32 done_inst, u32 seq_inst)
  325. {
  326. s32 inst_idx;
  327. u32 reg_val;
  328. u32 int_reason;
  329. int_reason = *reason;
  330. DPRINTK("[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  331. //printk(KERN_ERR "[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  332. if (int_reason & (1 << INT_WAVE5_BSBUF_EMPTY))
  333. {
  334. reg_val = (empty_inst & 0xffff);
  335. inst_idx = get_inst_idx(reg_val);
  336. *reason = (1 << INT_WAVE5_BSBUF_EMPTY);
  337. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  338. goto GET_VPU_INST_IDX_HANDLED;
  339. }
  340. if (int_reason & (1 << INT_WAVE5_INIT_SEQ))
  341. {
  342. reg_val = (seq_inst & 0xffff);
  343. inst_idx = get_inst_idx(reg_val);
  344. *reason = (1 << INT_WAVE5_INIT_SEQ);
  345. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO INIT_SEQ reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  346. goto GET_VPU_INST_IDX_HANDLED;
  347. }
  348. if (int_reason & (1 << INT_WAVE5_DEC_PIC))
  349. {
  350. reg_val = (done_inst & 0xffff);
  351. inst_idx = get_inst_idx(reg_val);
  352. *reason = (1 << INT_WAVE5_DEC_PIC);
  353. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  354. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  355. {
  356. u32 ll_inst_idx;
  357. reg_val = (done_inst >> 16);
  358. ll_inst_idx = get_inst_idx(reg_val);
  359. if (ll_inst_idx == inst_idx)
  360. *reason = ((1 << INT_WAVE5_DEC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY));
  361. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC and ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d, ll_inst_idx=%d\n", __func__, reg_val, inst_idx, ll_inst_idx);
  362. }
  363. goto GET_VPU_INST_IDX_HANDLED;
  364. }
  365. if (int_reason & (1 << INT_WAVE5_ENC_SET_PARAM))
  366. {
  367. reg_val = (seq_inst & 0xffff);
  368. inst_idx = get_inst_idx(reg_val);
  369. *reason = (1 << INT_WAVE5_ENC_SET_PARAM);
  370. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  371. goto GET_VPU_INST_IDX_HANDLED;
  372. }
  373. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  374. if (int_reason & (1 << INT_WAVE5_ENC_SRC_RELEASE))
  375. {
  376. reg_val = (done_inst & 0xffff);
  377. inst_idx = get_inst_idx(reg_val);
  378. *reason = (1 << INT_WAVE5_ENC_SRC_RELEASE);
  379. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  380. goto GET_VPU_INST_IDX_HANDLED;
  381. }
  382. #endif
  383. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  384. {
  385. reg_val = (done_inst >> 16);
  386. inst_idx = get_inst_idx(reg_val);
  387. *reason = (1 << INT_WAVE5_ENC_LOW_LATENCY);
  388. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  389. goto GET_VPU_INST_IDX_HANDLED;
  390. }
  391. inst_idx = -1;
  392. *reason = 0;
  393. DPRINTK("[VPUDRV] %s, UNKNOWN INTERRUPT REASON: %08x\n", __func__, int_reason);
  394. GET_VPU_INST_IDX_HANDLED:
  395. DPRINTK("[VPUDRV][-]%s, inst_idx=%d. *reason=0x%x\n", __func__, inst_idx, *reason);
  396. return inst_idx;
  397. }
  398. #endif
  399. static irqreturn_t vpu_irq_handler(int irq, void *dev_id)
  400. {
  401. vpu_drv_context_t *dev = (vpu_drv_context_t *)dev_id;
  402. /* this can be removed. it also work in VPU_WaitInterrupt of API function */
  403. int core;
  404. int product_code;
  405. #ifdef SUPPORT_MULTI_INST_INTR
  406. u32 intr_reason;
  407. s32 intr_inst_index;
  408. #endif
  409. DPRINTK("[VPUDRV][+]%s\n", __func__);
  410. #ifdef VPU_IRQ_CONTROL
  411. disable_irq_nosync(s_vpu_irq);
  412. #endif
  413. #ifdef SUPPORT_MULTI_INST_INTR
  414. intr_inst_index = 0;
  415. intr_reason = 0;
  416. #endif
  417. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  418. if (s_bit_firmware_info[core].size == 0) {/* it means that we didn't get an information the current core from API layer. No core activated.*/
  419. printk(KERN_ERR "[VPUDRV] : s_bit_firmware_info[core].size is zero\n");
  420. continue;
  421. }
  422. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  423. if (PRODUCT_CODE_W_SERIES(product_code)) {
  424. if (ReadVpuRegister(W5_VPU_VPU_INT_STS)) {
  425. #ifdef SUPPORT_MULTI_INST_INTR
  426. u32 empty_inst;
  427. u32 done_inst;
  428. u32 seq_inst;
  429. u32 i, reason, reason_clr;
  430. reason = ReadVpuRegister(W5_VPU_INT_REASON);
  431. empty_inst = ReadVpuRegister(W5_RET_BS_EMPTY_INST);
  432. done_inst = ReadVpuRegister(W5_RET_QUEUE_CMD_DONE_INST);
  433. seq_inst = ReadVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO);
  434. reason_clr = reason;
  435. DPRINTK("[VPUDRV] vpu_irq_handler reason=0x%x, empty_inst=0x%x, done_inst=0x%x, seq_inst=0x%x \n", reason, empty_inst, done_inst, seq_inst);
  436. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  437. if (0 == empty_inst && 0 == done_inst && 0 == seq_inst) break;
  438. intr_reason = reason;
  439. intr_inst_index = get_vpu_inst_idx(dev, &intr_reason, empty_inst, done_inst, seq_inst);
  440. DPRINTK("[VPUDRV] > instance_index: %d, intr_reason: %08x empty_inst: %08x done_inst: %08x seq_inst: %08x\n", intr_inst_index, intr_reason, empty_inst, done_inst, seq_inst);
  441. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  442. if (intr_reason == (1 << INT_WAVE5_BSBUF_EMPTY)) {
  443. empty_inst = empty_inst & ~(1 << intr_inst_index);
  444. WriteVpuRegister(W5_RET_BS_EMPTY_INST, empty_inst);
  445. if (0 == empty_inst) {
  446. reason &= ~(1<<INT_WAVE5_BSBUF_EMPTY);
  447. }
  448. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST Clear empty_inst=0x%x, intr_inst_index=%d\n", __func__, empty_inst, intr_inst_index);
  449. }
  450. if (intr_reason == (1 << INT_WAVE5_DEC_PIC))
  451. {
  452. done_inst = done_inst & ~(1 << intr_inst_index);
  453. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  454. if (0 == done_inst) {
  455. reason &= ~(1<<INT_WAVE5_DEC_PIC);
  456. }
  457. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  458. }
  459. if ((intr_reason == (1 << INT_WAVE5_INIT_SEQ)) || (intr_reason == (1 << INT_WAVE5_ENC_SET_PARAM)))
  460. {
  461. seq_inst = seq_inst & ~(1 << intr_inst_index);
  462. WriteVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO, seq_inst);
  463. if (0 == seq_inst) {
  464. reason &= ~(1<<INT_WAVE5_INIT_SEQ | 1<<INT_WAVE5_ENC_SET_PARAM);
  465. }
  466. DPRINTK("[VPUDRV] %s, W5_RET_SEQ_DONE_INSTANCE_INFO Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  467. }
  468. if ((intr_reason == (1 << INT_WAVE5_ENC_LOW_LATENCY)))
  469. {
  470. done_inst = (done_inst >> 16);
  471. done_inst = done_inst & ~(1 << intr_inst_index);
  472. done_inst = (done_inst << 16);
  473. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  474. if (0 == done_inst) {
  475. reason &= ~(1 << INT_WAVE5_ENC_LOW_LATENCY);
  476. }
  477. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST INT_WAVE5_ENC_LOW_LATENCY Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  478. }
  479. if (!kfifo_is_full(&s_interrupt_pending_q[intr_inst_index])) {
  480. if (intr_reason == ((1 << INT_WAVE5_ENC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY))) {
  481. u32 ll_intr_reason = (1 << INT_WAVE5_ENC_PIC);
  482. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &ll_intr_reason, sizeof(u32), &s_kfifo_lock);
  483. }
  484. else
  485. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  486. }
  487. else {
  488. printk(KERN_ERR "[VPUDRV] : kfifo_is_full kfifo_count=%d \n", kfifo_len(&s_interrupt_pending_q[intr_inst_index]));
  489. }
  490. }
  491. else {
  492. printk(KERN_ERR "[VPUDRV] : intr_inst_index is wrong intr_inst_index=%d \n", intr_inst_index);
  493. }
  494. }
  495. if (0 != reason)
  496. printk(KERN_ERR "INTERRUPT REASON REMAINED: %08x\n", reason);
  497. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, reason_clr);
  498. #else
  499. dev->interrupt_reason = ReadVpuRegister(W5_VPU_INT_REASON);
  500. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, dev->interrupt_reason);
  501. #endif
  502. WriteVpuRegister(W5_VPU_VINT_CLEAR, 0x1);
  503. }
  504. }
  505. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  506. if (ReadVpuRegister(BIT_INT_STS)) {
  507. #ifdef SUPPORT_MULTI_INST_INTR
  508. intr_reason = ReadVpuRegister(BIT_INT_REASON);
  509. intr_inst_index = 0; // in case of coda seriese. treats intr_inst_index is already 0
  510. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  511. #else
  512. dev->interrupt_reason = ReadVpuRegister(BIT_INT_REASON);
  513. #endif
  514. WriteVpuRegister(BIT_INT_CLEAR, 0x1);
  515. }
  516. }
  517. else {
  518. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  519. continue;
  520. }
  521. #ifdef SUPPORT_MULTI_INST_INTR
  522. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n\n", product_code, intr_reason);
  523. #else
  524. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n", product_code, dev->interrupt_reason);
  525. #endif
  526. }
  527. if (dev->async_queue)
  528. kill_fasync(&dev->async_queue, SIGIO, POLL_IN); /* notify the interrupt to user space */
  529. #ifdef SUPPORT_MULTI_INST_INTR
  530. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  531. s_interrupt_flag[intr_inst_index]= 1;
  532. wake_up_interruptible(&s_interrupt_wait_q[intr_inst_index]);
  533. }
  534. #else
  535. s_interrupt_flag = 1;
  536. wake_up_interruptible(&s_interrupt_wait_q);
  537. #endif
  538. DPRINTK("[VPUDRV][-]%s\n", __func__);
  539. return IRQ_HANDLED;
  540. }
  541. static int vpu_open(struct inode *inode, struct file *filp)
  542. {
  543. DPRINTK("[VPUDRV][+] %s\n", __func__);
  544. spin_lock(&s_vpu_lock);
  545. s_vpu_drv_context.open_count++;
  546. filp->private_data = (void *)(&s_vpu_drv_context);
  547. spin_unlock(&s_vpu_lock);
  548. DPRINTK("[VPUDRV][-] %s\n", __func__);
  549. return 0;
  550. }
  551. /*static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, u_long arg) // for kernel 2.6.9 of C&M*/
  552. static long vpu_ioctl(struct file *filp, u_int cmd, u_long arg)
  553. {
  554. int ret = 0;
  555. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  556. switch (cmd) {
  557. case VDI_IOCTL_GET_PHYSICAL_MEMORY:
  558. {
  559. vpudrv_buffer_pool_t *vbp;
  560. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  561. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  562. if (!vbp) {
  563. up(&s_vpu_sem);
  564. return -ENOMEM;
  565. }
  566. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  567. if (ret) {
  568. kfree(vbp);
  569. up(&s_vpu_sem);
  570. return -EFAULT;
  571. }
  572. void *user_address = (void *)vbp->vb.virt_addr;
  573. struct task_struct *my_struct = get_current();
  574. struct mm_struct *mm = my_struct->mm;
  575. unsigned long address = (unsigned long)user_address;
  576. pgd_t *pgd = pgd_offset(mm, address);
  577. if (!pgd_none(*pgd) && !pgd_bad(*pgd)) {
  578. p4d_t *p4d = p4d_offset(pgd, address);
  579. pud_t *pud = pud_offset(p4d, address);
  580. if (!pud_none(*pud) && !pud_bad(*pud)) {
  581. pmd_t *pmd = pmd_offset(pud, address);
  582. if (!pmd_none(*pmd) && !pmd_bad(*pmd)) {
  583. pte_t *pte = pte_offset_map(pmd, address);
  584. if (!pte_none(*pte)) {
  585. struct page *pg = pte_page(*pte);
  586. unsigned long phys = page_to_phys(pg);
  587. unsigned long virt = (unsigned long)phys_to_virt(phys);
  588. printk("phy address = %lx, virt = %lx\r\n", phys, virt);
  589. vbp->vb.phys_addr = phys;
  590. vbp->vb.base = virt;
  591. }
  592. pte_unmap(pte);
  593. }
  594. }
  595. }
  596. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  597. if (ret) {
  598. kfree(vbp);
  599. ret = -EFAULT;
  600. up(&s_vpu_sem);
  601. break;
  602. }
  603. vbp->filp = filp;
  604. spin_lock(&s_vpu_lock);
  605. list_add(&vbp->list, &s_vbp_head);
  606. spin_unlock(&s_vpu_lock);
  607. up(&s_vpu_sem);
  608. }
  609. }
  610. break;
  611. case VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY:
  612. {
  613. vpudrv_buffer_pool_t *vbp;
  614. DPRINTK("[VPUDRV][+]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  615. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  616. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  617. if (!vbp) {
  618. up(&s_vpu_sem);
  619. return -ENOMEM;
  620. }
  621. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  622. if (ret) {
  623. kfree(vbp);
  624. up(&s_vpu_sem);
  625. return -EFAULT;
  626. }
  627. ret = vpu_alloc_dma_buffer(&(vbp->vb));
  628. if (ret == -1) {
  629. ret = -ENOMEM;
  630. kfree(vbp);
  631. up(&s_vpu_sem);
  632. break;
  633. }
  634. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  635. if (ret) {
  636. kfree(vbp);
  637. ret = -EFAULT;
  638. up(&s_vpu_sem);
  639. break;
  640. }
  641. vbp->filp = filp;
  642. spin_lock(&s_vpu_lock);
  643. list_add(&vbp->list, &s_vbp_head);
  644. spin_unlock(&s_vpu_lock);
  645. up(&s_vpu_sem);
  646. }
  647. DPRINTK("[VPUDRV][-]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  648. }
  649. break;
  650. case VDI_IOCTL_FREE_PHYSICALMEMORY:
  651. {
  652. vpudrv_buffer_pool_t *vbp, *n;
  653. vpudrv_buffer_t vb;
  654. DPRINTK("[VPUDRV][+]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  655. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  656. ret = copy_from_user(&vb, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  657. if (ret) {
  658. up(&s_vpu_sem);
  659. return -EACCES;
  660. }
  661. if (vb.base)
  662. vpu_free_dma_buffer(&vb);
  663. spin_lock(&s_vpu_lock);
  664. list_for_each_entry_safe(vbp, n, &s_vbp_head, list)
  665. {
  666. if (vbp->vb.base == vb.base) {
  667. list_del(&vbp->list);
  668. kfree(vbp);
  669. break;
  670. }
  671. }
  672. spin_unlock(&s_vpu_lock);
  673. up(&s_vpu_sem);
  674. }
  675. DPRINTK("[VPUDRV][-]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  676. }
  677. break;
  678. case VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO:
  679. {
  680. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  681. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  682. if (s_video_memory.base != 0) {
  683. ret = copy_to_user((void __user *)arg, &s_video_memory, sizeof(vpudrv_buffer_t));
  684. if (ret != 0)
  685. ret = -EFAULT;
  686. } else {
  687. ret = -EFAULT;
  688. }
  689. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  690. #endif
  691. }
  692. break;
  693. case VDI_IOCTL_WAIT_INTERRUPT:
  694. {
  695. vpudrv_intr_info_t info;
  696. #ifdef SUPPORT_MULTI_INST_INTR
  697. u32 intr_inst_index;
  698. u32 intr_reason_in_q;
  699. u32 interrupt_flag_in_q;
  700. #endif
  701. DPRINTK("[VPUDRV][+]VDI_IOCTL_WAIT_INTERRUPT\n");
  702. ret = copy_from_user(&info, (vpudrv_intr_info_t *)arg, sizeof(vpudrv_intr_info_t));
  703. if (ret != 0)
  704. {
  705. return -EFAULT;
  706. }
  707. #ifdef SUPPORT_MULTI_INST_INTR
  708. intr_inst_index = info.intr_inst_index;
  709. intr_reason_in_q = 0;
  710. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  711. if (interrupt_flag_in_q > 0)
  712. {
  713. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  714. DPRINTK("[VPUDRV] Interrupt Remain : intr_inst_index=%d, intr_reason_in_q=0x%x, interrupt_flag_in_q=%d\n", intr_inst_index, intr_reason_in_q, interrupt_flag_in_q);
  715. goto INTERRUPT_REMAIN_IN_QUEUE;
  716. }
  717. #endif
  718. #ifdef SUPPORT_MULTI_INST_INTR
  719. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  720. kt = ktime_set(0, info.timeout*1000*1000);
  721. ret = wait_event_interruptible_hrtimeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, kt);
  722. #else
  723. ret = wait_event_interruptible_timeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, msecs_to_jiffies(info.timeout));
  724. #endif
  725. #else
  726. ret = wait_event_interruptible_timeout(s_interrupt_wait_q, s_interrupt_flag != 0, msecs_to_jiffies(info.timeout));
  727. #endif
  728. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  729. if (ret == -ETIME) {
  730. //DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT timeout = %d \n", info.timeout);
  731. break;
  732. }
  733. #endif
  734. if (!ret) {
  735. ret = -ETIME;
  736. break;
  737. }
  738. if (signal_pending(current)) {
  739. ret = -ERESTARTSYS;
  740. break;
  741. }
  742. #ifdef SUPPORT_MULTI_INST_INTR
  743. intr_reason_in_q = 0;
  744. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  745. if (interrupt_flag_in_q > 0) {
  746. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  747. }
  748. else {
  749. dev->interrupt_reason[intr_inst_index] = 0;
  750. }
  751. #endif
  752. #ifdef SUPPORT_MULTI_INST_INTR
  753. DPRINTK("[VPUDRV] inst_index(%d), s_interrupt_flag(%d), reason(0x%08lx)\n", intr_inst_index, s_interrupt_flag[intr_inst_index], dev->interrupt_reason[intr_inst_index]);
  754. #else
  755. DPRINTK("[VPUDRV] s_interrupt_flag(%d), reason(0x%08lx)\n", s_interrupt_flag, dev->interrupt_reason);
  756. #endif
  757. #ifdef SUPPORT_MULTI_INST_INTR
  758. INTERRUPT_REMAIN_IN_QUEUE:
  759. info.intr_reason = dev->interrupt_reason[intr_inst_index];
  760. s_interrupt_flag[intr_inst_index] = 0;
  761. dev->interrupt_reason[intr_inst_index] = 0;
  762. #else
  763. info.intr_reason = dev->interrupt_reason;
  764. s_interrupt_flag = 0;
  765. dev->interrupt_reason = 0;
  766. #endif
  767. #ifdef VPU_IRQ_CONTROL
  768. enable_irq(s_vpu_irq);
  769. #endif
  770. ret = copy_to_user((void __user *)arg, &info, sizeof(vpudrv_intr_info_t));
  771. DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT\n");
  772. if (ret != 0)
  773. {
  774. return -EFAULT;
  775. }
  776. }
  777. break;
  778. case VDI_IOCTL_SET_CLOCK_GATE:
  779. {
  780. #ifndef VPU_SUPPORT_CLOCK_CONTROL
  781. u32 clkgate;
  782. DPRINTK("[VPUDRV][+]VDI_IOCTL_SET_CLOCK_GATE\n");
  783. if (get_user(clkgate, (u32 __user *) arg))
  784. return -EFAULT;
  785. if (clkgate)
  786. vpu_clk_enable(s_vpu_clk);
  787. else
  788. vpu_clk_disable(s_vpu_clk);
  789. DPRINTK("[VPUDRV][-]VDI_IOCTL_SET_CLOCK_GATE\n");
  790. #endif
  791. }
  792. break;
  793. case VDI_IOCTL_GET_INSTANCE_POOL:
  794. {
  795. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_POOL\n");
  796. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  797. if (s_instance_pool.base != 0) {
  798. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  799. if (ret != 0)
  800. ret = -EFAULT;
  801. } else {
  802. ret = copy_from_user(&s_instance_pool, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  803. if (ret == 0) {
  804. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  805. s_instance_pool.size = PAGE_ALIGN(s_instance_pool.size);
  806. s_instance_pool.base = (unsigned long)vmalloc(s_instance_pool.size);
  807. s_instance_pool.phys_addr = s_instance_pool.base;
  808. if (s_instance_pool.base != 0)
  809. #else
  810. if (vpu_alloc_dma_buffer(&s_instance_pool) != -1)
  811. #endif
  812. {
  813. memset((void *)s_instance_pool.base, 0x0, s_instance_pool.size); /*clearing memory*/
  814. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  815. if (ret == 0) {
  816. /* success to get memory for instance pool */
  817. up(&s_vpu_sem);
  818. break;
  819. }
  820. }
  821. }
  822. ret = -EFAULT;
  823. }
  824. up(&s_vpu_sem);
  825. }
  826. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_INSTANCE_POOL\n");
  827. }
  828. break;
  829. case VDI_IOCTL_GET_COMMON_MEMORY:
  830. {
  831. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_COMMON_MEMORY\n");
  832. if (s_common_memory.base != 0) {
  833. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  834. if (ret != 0)
  835. ret = -EFAULT;
  836. } else {
  837. ret = copy_from_user(&s_common_memory, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  838. if (ret == 0) {
  839. if (vpu_alloc_dma_buffer(&s_common_memory) != -1) {
  840. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  841. if (ret == 0) {
  842. /* success to get memory for common memory */
  843. break;
  844. }
  845. }
  846. }
  847. ret = -EFAULT;
  848. }
  849. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_COMMON_MEMORY\n");
  850. }
  851. break;
  852. case VDI_IOCTL_OPEN_INSTANCE:
  853. {
  854. vpudrv_inst_info_t inst_info;
  855. vpudrv_instanace_list_t *vil, *n;
  856. vil = kzalloc(sizeof(*vil), GFP_KERNEL);
  857. if (!vil)
  858. return -ENOMEM;
  859. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  860. return -EFAULT;
  861. vil->inst_idx = inst_info.inst_idx;
  862. vil->core_idx = inst_info.core_idx;
  863. vil->filp = filp;
  864. spin_lock(&s_vpu_lock);
  865. list_add(&vil->list, &s_inst_list_head);
  866. inst_info.inst_open_count = 0; /* counting the current open instance number */
  867. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  868. {
  869. if (vil->core_idx == inst_info.core_idx)
  870. inst_info.inst_open_count++;
  871. }
  872. #ifdef SUPPORT_MULTI_INST_INTR
  873. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  874. #endif
  875. spin_unlock(&s_vpu_lock);
  876. s_vpu_open_ref_count++; /* flag just for that vpu is in opened or closed */
  877. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t))) {
  878. kfree(vil);
  879. return -EFAULT;
  880. }
  881. DPRINTK("[VPUDRV] VDI_IOCTL_OPEN_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  882. }
  883. break;
  884. case VDI_IOCTL_CLOSE_INSTANCE:
  885. {
  886. vpudrv_inst_info_t inst_info;
  887. vpudrv_instanace_list_t *vil, *n;
  888. u32 found = 0;
  889. DPRINTK("[VPUDRV][+]VDI_IOCTL_CLOSE_INSTANCE\n");
  890. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  891. return -EFAULT;
  892. spin_lock(&s_vpu_lock);
  893. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  894. {
  895. if (vil->inst_idx == inst_info.inst_idx && vil->core_idx == inst_info.core_idx) {
  896. list_del(&vil->list);
  897. kfree(vil);
  898. found = 1;
  899. break;
  900. }
  901. }
  902. if (0 == found) {
  903. spin_unlock(&s_vpu_lock);
  904. return -EINVAL;
  905. }
  906. inst_info.inst_open_count = 0; /* counting the current open instance number */
  907. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  908. {
  909. if (vil->core_idx == inst_info.core_idx)
  910. inst_info.inst_open_count++;
  911. }
  912. #ifdef SUPPORT_MULTI_INST_INTR
  913. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  914. #endif
  915. spin_unlock(&s_vpu_lock);
  916. s_vpu_open_ref_count--; /* flag just for that vpu is in opened or closed */
  917. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t)))
  918. return -EFAULT;
  919. DPRINTK("[VPUDRV] VDI_IOCTL_CLOSE_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  920. }
  921. break;
  922. case VDI_IOCTL_GET_INSTANCE_NUM:
  923. {
  924. vpudrv_inst_info_t inst_info;
  925. vpudrv_instanace_list_t *vil, *n;
  926. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_NUM\n");
  927. ret = copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t));
  928. if (ret != 0)
  929. break;
  930. spin_lock(&s_vpu_lock);
  931. inst_info.inst_open_count = 0;
  932. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  933. {
  934. if (vil->core_idx == inst_info.core_idx)
  935. inst_info.inst_open_count++;
  936. }
  937. spin_unlock(&s_vpu_lock);
  938. ret = copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t));
  939. DPRINTK("[VPUDRV] VDI_IOCTL_GET_INSTANCE_NUM core_idx=%d, inst_idx=%d, open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, inst_info.inst_open_count);
  940. }
  941. break;
  942. case VDI_IOCTL_RESET:
  943. {
  944. #ifndef VPU_SUPPORT_CLOCK_CONTROL
  945. vpu_hw_reset();
  946. #endif
  947. }
  948. break;
  949. case VDI_IOCTL_GET_REGISTER_INFO:
  950. {
  951. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_REGISTER_INFO\n");
  952. ret = copy_to_user((void __user *)arg, &s_vpu_register, sizeof(vpudrv_buffer_t));
  953. if (ret != 0)
  954. ret = -EFAULT;
  955. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_REGISTER_INFO s_vpu_register.phys_addr==0x%lx, s_vpu_register.virt_addr=0x%lx, s_vpu_register.size=%d\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr, s_vpu_register.size);
  956. }
  957. break;
  958. case VDI_IOCTL_FLUSH_DCACHE:
  959. {
  960. vpudrv_flush_cache_t cache_info;
  961. ret = copy_from_user(&cache_info, (vpudrv_flush_cache_t *)arg, sizeof(vpudrv_flush_cache_t));
  962. if (ret != 0)
  963. ret = -EFAULT;
  964. if(cache_info.flag)
  965. starfive_flush_dcache(cache_info.start,cache_info.size);
  966. break;
  967. }
  968. default:
  969. {
  970. printk(KERN_ERR "[VPUDRV] No such IOCTL, cmd is %d\n", cmd);
  971. }
  972. break;
  973. }
  974. return ret;
  975. }
  976. static ssize_t vpu_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos)
  977. {
  978. return -1;
  979. }
  980. static ssize_t vpu_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos)
  981. {
  982. /* DPRINTK("[VPUDRV] vpu_write len=%d\n", (int)len); */
  983. if (!buf) {
  984. printk(KERN_ERR "[VPUDRV] vpu_write buf = NULL error \n");
  985. return -EFAULT;
  986. }
  987. if (len == sizeof(vpu_bit_firmware_info_t)) {
  988. vpu_bit_firmware_info_t *bit_firmware_info;
  989. bit_firmware_info = kmalloc(sizeof(vpu_bit_firmware_info_t), GFP_KERNEL);
  990. if (!bit_firmware_info) {
  991. printk(KERN_ERR "[VPUDRV] vpu_write bit_firmware_info allocation error \n");
  992. return -EFAULT;
  993. }
  994. if (copy_from_user(bit_firmware_info, buf, len)) {
  995. printk(KERN_ERR "[VPUDRV] vpu_write copy_from_user error for bit_firmware_info\n");
  996. return -EFAULT;
  997. }
  998. if (bit_firmware_info->size == sizeof(vpu_bit_firmware_info_t)) {
  999. DPRINTK("[VPUDRV] vpu_write set bit_firmware_info coreIdx=0x%x, reg_base_offset=0x%x size=0x%x, bit_code[0]=0x%x\n",
  1000. bit_firmware_info->core_idx, (int)bit_firmware_info->reg_base_offset, bit_firmware_info->size, bit_firmware_info->bit_code[0]);
  1001. if (bit_firmware_info->core_idx > MAX_NUM_VPU_CORE) {
  1002. printk(KERN_ERR "[VPUDRV] vpu_write coreIdx[%d] is exceeded than MAX_NUM_VPU_CORE[%d]\n", bit_firmware_info->core_idx, MAX_NUM_VPU_CORE);
  1003. return -ENODEV;
  1004. }
  1005. memcpy((void *)&s_bit_firmware_info[bit_firmware_info->core_idx], bit_firmware_info, sizeof(vpu_bit_firmware_info_t));
  1006. kfree(bit_firmware_info);
  1007. return len;
  1008. }
  1009. kfree(bit_firmware_info);
  1010. }
  1011. return -1;
  1012. }
  1013. static int vpu_release(struct inode *inode, struct file *filp)
  1014. {
  1015. int ret = 0;
  1016. u32 open_count;
  1017. #ifdef SUPPORT_MULTI_INST_INTR
  1018. int i;
  1019. #endif
  1020. DPRINTK("[VPUDRV] vpu_release\n");
  1021. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  1022. /* found and free the not handled buffer by user applications */
  1023. vpu_free_buffers(filp);
  1024. /* found and free the not closed instance by user applications */
  1025. vpu_free_instances(filp);
  1026. spin_lock(&s_vpu_lock);
  1027. s_vpu_drv_context.open_count--;
  1028. open_count = s_vpu_drv_context.open_count;
  1029. spin_unlock(&s_vpu_lock);
  1030. if (open_count == 0) {
  1031. #ifdef SUPPORT_MULTI_INST_INTR
  1032. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1033. kfifo_reset(&s_interrupt_pending_q[i]);
  1034. }
  1035. #endif
  1036. if (s_instance_pool.base) {
  1037. DPRINTK("[VPUDRV] free instance pool\n");
  1038. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1039. vfree((const void *)s_instance_pool.base);
  1040. #else
  1041. vpu_free_dma_buffer(&s_instance_pool);
  1042. #endif
  1043. s_instance_pool.base = 0;
  1044. }
  1045. }
  1046. }
  1047. up(&s_vpu_sem);
  1048. return 0;
  1049. }
  1050. static int vpu_fasync(int fd, struct file *filp, int mode)
  1051. {
  1052. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  1053. return fasync_helper(fd, filp, mode, &dev->async_queue);
  1054. }
  1055. static int vpu_map_to_register(struct file *fp, struct vm_area_struct *vm)
  1056. {
  1057. unsigned long pfn;
  1058. vm->vm_flags |= VM_IO | VM_RESERVED;
  1059. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1060. pfn = s_vpu_register.phys_addr >> PAGE_SHIFT;
  1061. return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1062. }
  1063. static int vpu_map_to_physical_memory(struct file *fp, struct vm_area_struct *vm)
  1064. {
  1065. vm->vm_flags |= VM_IO | VM_RESERVED;
  1066. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1067. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1068. }
  1069. static int vpu_map_to_instance_pool_memory(struct file *fp, struct vm_area_struct *vm)
  1070. {
  1071. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1072. int ret;
  1073. long length = vm->vm_end - vm->vm_start;
  1074. unsigned long start = vm->vm_start;
  1075. char *vmalloc_area_ptr = (char *)s_instance_pool.base;
  1076. unsigned long pfn;
  1077. vm->vm_flags |= VM_RESERVED;
  1078. /* loop over all pages, map it page individually */
  1079. while (length > 0)
  1080. {
  1081. pfn = vmalloc_to_pfn(vmalloc_area_ptr);
  1082. if ((ret = remap_pfn_range(vm, start, pfn, PAGE_SIZE, PAGE_SHARED)) < 0) {
  1083. return ret;
  1084. }
  1085. start += PAGE_SIZE;
  1086. vmalloc_area_ptr += PAGE_SIZE;
  1087. length -= PAGE_SIZE;
  1088. }
  1089. return 0;
  1090. #else
  1091. vm->vm_flags |= VM_RESERVED;
  1092. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1093. #endif
  1094. }
  1095. /*!
  1096. * @brief memory map interface for vpu file operation
  1097. * @return 0 on success or negative error code on error
  1098. */
  1099. static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
  1100. {
  1101. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1102. if (vm->vm_pgoff == 0)
  1103. return vpu_map_to_instance_pool_memory(fp, vm);
  1104. if (vm->vm_pgoff == (s_vpu_register.phys_addr>>PAGE_SHIFT))
  1105. return vpu_map_to_register(fp, vm);
  1106. return vpu_map_to_physical_memory(fp, vm);
  1107. #else
  1108. if (vm->vm_pgoff) {
  1109. if (vm->vm_pgoff == (s_instance_pool.phys_addr>>PAGE_SHIFT))
  1110. return vpu_map_to_instance_pool_memory(fp, vm);
  1111. return vpu_map_to_physical_memory(fp, vm);
  1112. } else {
  1113. return vpu_map_to_register(fp, vm);
  1114. }
  1115. #endif
  1116. }
  1117. struct file_operations vpu_fops = {
  1118. .owner = THIS_MODULE,
  1119. .open = vpu_open,
  1120. .read = vpu_read,
  1121. .write = vpu_write,
  1122. /*.ioctl = vpu_ioctl, // for kernel 2.6.9 of C&M*/
  1123. .unlocked_ioctl = vpu_ioctl,
  1124. .release = vpu_release,
  1125. .fasync = vpu_fasync,
  1126. .mmap = vpu_mmap,
  1127. };
  1128. static int vpu_probe(struct platform_device *pdev)
  1129. {
  1130. int err = 0;
  1131. struct resource *res = NULL;
  1132. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1133. struct resource res_cma;
  1134. struct device_node *node;
  1135. #endif
  1136. DPRINTK("[VPUDRV] vpu_probe\n");
  1137. if(pdev){
  1138. vpu_dev = &pdev->dev;
  1139. vpu_dev->coherent_dma_mask = 0xffffffff;;
  1140. //vpu_dev->dma_ops = NULL;
  1141. dev_info(vpu_dev,"device init.\n");
  1142. }
  1143. if (pdev)
  1144. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1145. if (res) {/* if platform driver is implemented */
  1146. s_vpu_register.phys_addr = res->start;
  1147. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(res->start, res->end - res->start);
  1148. s_vpu_register.size = res->end - res->start;
  1149. DPRINTK("[VPUDRV] : vpu base address get from platform driver physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr);
  1150. } else {
  1151. s_vpu_register.phys_addr = VPU_REG_BASE_ADDR;
  1152. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(s_vpu_register.phys_addr, VPU_REG_SIZE);
  1153. s_vpu_register.size = VPU_REG_SIZE;
  1154. DPRINTK("[VPUDRV] : vpu base address get from defined value physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr, s_vpu_register.virt_addr);
  1155. }
  1156. /* get the major number of the character device */
  1157. if ((alloc_chrdev_region(&s_vpu_major, 0, 1, VPU_DEV_NAME)) < 0) {
  1158. err = -EBUSY;
  1159. printk(KERN_ERR "could not allocate major number\n");
  1160. goto ERROR_PROVE_DEVICE;
  1161. }
  1162. printk(KERN_INFO "SUCCESS alloc_chrdev_region\n");
  1163. /* initialize the device structure and register the device with the kernel */
  1164. cdev_init(&s_vpu_cdev, &vpu_fops);
  1165. if ((cdev_add(&s_vpu_cdev, s_vpu_major, 1)) < 0) {
  1166. err = -EBUSY;
  1167. printk(KERN_ERR "could not allocate chrdev\n");
  1168. goto ERROR_PROVE_DEVICE;
  1169. }
  1170. #ifndef VPU_SUPPORT_CLOCK_CONTROL
  1171. if (pdev)
  1172. s_vpu_clk = vpu_clk_get(&pdev->dev);
  1173. else
  1174. s_vpu_clk = vpu_clk_get(NULL);
  1175. if (!s_vpu_clk)
  1176. printk(KERN_ERR "[VPUDRV] : not support clock controller.\n");
  1177. else
  1178. DPRINTK("[VPUDRV] : get clock controller s_vpu_clk=%p\n", s_vpu_clk);
  1179. #endif
  1180. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1181. err = starfive_vdec_clk_rst_init(pdev);
  1182. if (err){
  1183. goto ERROR_PROVE_DEVICE;
  1184. }
  1185. #else
  1186. vpu_clk_enable(s_vpu_clk);
  1187. vpu_hw_reset();
  1188. #endif
  1189. #ifdef VPU_SUPPORT_ISR
  1190. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1191. if (pdev)
  1192. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1193. if (res) {/* if platform driver is implemented */
  1194. s_vpu_irq = res->start;
  1195. DPRINTK("[VPUDRV] : vpu irq number get from platform driver irq=0x%x\n", s_vpu_irq);
  1196. } else {
  1197. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1198. }
  1199. #else
  1200. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1201. #endif
  1202. err = request_irq(s_vpu_irq, vpu_irq_handler, 0, pdev->name, (void *)(&s_vpu_drv_context));
  1203. if (err) {
  1204. printk(KERN_ERR "[VPUDRV] : fail to register interrupt handler\n");
  1205. goto ERROR_PROVE_DEVICE;
  1206. }
  1207. #endif
  1208. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1209. node = of_parse_phandle(vpu_dev->of_node, "memory-region", 0);
  1210. if(node){
  1211. dev_info(vpu_dev, "Get mem form memory-region\n");
  1212. of_address_to_resource(node, 0, &res_cma);
  1213. s_video_memory.size = resource_size(&res_cma);
  1214. s_video_memory.phys_addr = res_cma.start;
  1215. }else{
  1216. dev_info(vpu_dev, "Get mem form memory-region fiiled.please check the dts file.\n");
  1217. return 0;
  1218. }
  1219. s_video_memory.base = (unsigned long)ioremap_nocache(DRAM_MEM2SYS(s_video_memory.phys_addr), PAGE_ALIGN(s_video_memory.size));
  1220. if (!s_video_memory.base) {
  1221. printk(KERN_ERR "[VPUDRV] : fail to remap video memory physical phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base, (int)s_video_memory.size);
  1222. goto ERROR_PROVE_DEVICE;
  1223. }
  1224. if (vmem_init(&s_vmem, s_video_memory.phys_addr, s_video_memory.size) < 0) {
  1225. printk(KERN_ERR "[VPUDRV] : fail to init vmem system\n");
  1226. goto ERROR_PROVE_DEVICE;
  1227. }
  1228. DPRINTK("[VPUDRV] success to probe vpu device with reserved video memory phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base,s_video_memory.size);
  1229. #else
  1230. DPRINTK("[VPUDRV] success to probe vpu device with non reserved video memory\n");
  1231. #endif
  1232. return 0;
  1233. ERROR_PROVE_DEVICE:
  1234. if (s_vpu_major)
  1235. unregister_chrdev_region(s_vpu_major, 1);
  1236. if (s_vpu_register.virt_addr)
  1237. iounmap((void *)s_vpu_register.virt_addr);
  1238. return err;
  1239. }
  1240. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1241. static int vpu_remove(struct platform_device *pdev)
  1242. {
  1243. DPRINTK("[VPUDRV] vpu_remove\n");
  1244. if (s_instance_pool.base) {
  1245. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1246. vfree((const void *)s_instance_pool.base);
  1247. #else
  1248. vpu_free_dma_buffer(&s_instance_pool);
  1249. #endif
  1250. s_instance_pool.base = 0;
  1251. }
  1252. if (s_common_memory.base) {
  1253. vpu_free_dma_buffer(&s_common_memory);
  1254. s_common_memory.base = 0;
  1255. }
  1256. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1257. if (s_video_memory.base) {
  1258. iounmap((void *)s_video_memory.base);
  1259. s_video_memory.base = 0;
  1260. vmem_exit(&s_vmem);
  1261. }
  1262. #endif
  1263. if (s_vpu_major > 0) {
  1264. cdev_del(&s_vpu_cdev);
  1265. unregister_chrdev_region(s_vpu_major, 1);
  1266. s_vpu_major = 0;
  1267. }
  1268. #ifdef VPU_SUPPORT_ISR
  1269. if (s_vpu_irq)
  1270. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1271. #endif
  1272. if (s_vpu_register.virt_addr)
  1273. iounmap((void *)s_vpu_register.virt_addr);
  1274. #ifndef VPU_SUPPORT_CLOCK_CONTROL
  1275. vpu_clk_put(s_vpu_clk);
  1276. #endif
  1277. return 0;
  1278. }
  1279. #endif /*VPU_SUPPORT_PLATFORM_DRIVER_REGISTER*/
  1280. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  1281. #define W5_MAX_CODE_BUF_SIZE (512*1024)
  1282. #define W5_CMD_INIT_VPU (0x0001)
  1283. #define W5_CMD_SLEEP_VPU (0x0004)
  1284. #define W5_CMD_WAKEUP_VPU (0x0002)
  1285. static void Wave5BitIssueCommand(int core, u32 cmd)
  1286. {
  1287. WriteVpuRegister(W5_VPU_BUSY_STATUS, 1);
  1288. WriteVpuRegister(W5_COMMAND, cmd);
  1289. WriteVpuRegister(W5_VPU_HOST_INT_REQ, 1);
  1290. return;
  1291. }
  1292. static int vpu_suspend(struct platform_device *pdev, pm_message_t state)
  1293. {
  1294. int i;
  1295. int core;
  1296. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1297. int product_code;
  1298. DPRINTK("[VPUDRV] vpu_suspend\n");
  1299. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1300. starfive_vdec_clk_enable(&pdev->dev);
  1301. #else
  1302. vpu_clk_enable(s_vpu_clk);
  1303. #endif
  1304. if (s_vpu_open_ref_count > 0) {
  1305. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1306. if (s_bit_firmware_info[core].size == 0)
  1307. continue;
  1308. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1309. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1310. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1311. if (time_after(jiffies, timeout)) {
  1312. DPRINTK("SLEEP_VPU BUSY timeout");
  1313. goto DONE_SUSPEND;
  1314. }
  1315. }
  1316. Wave5BitIssueCommand(core, W5_CMD_SLEEP_VPU);
  1317. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1318. if (time_after(jiffies, timeout)) {
  1319. DPRINTK("SLEEP_VPU BUSY timeout");
  1320. goto DONE_SUSPEND;
  1321. }
  1322. }
  1323. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1324. DPRINTK("SLEEP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1325. goto DONE_SUSPEND;
  1326. }
  1327. }
  1328. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1329. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1330. if (time_after(jiffies, timeout))
  1331. goto DONE_SUSPEND;
  1332. }
  1333. for (i = 0; i < 64; i++)
  1334. s_vpu_reg_store[core][i] = ReadVpuRegister(BIT_BASE+(0x100+(i * 4)));
  1335. }
  1336. else {
  1337. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1338. goto DONE_SUSPEND;
  1339. }
  1340. }
  1341. }
  1342. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1343. starfive_vdec_clk_disable(&pdev->dev);
  1344. #else
  1345. vpu_clk_disable(s_vpu_clk);
  1346. #endif
  1347. return 0;
  1348. DONE_SUSPEND:
  1349. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1350. starfive_vdec_clk_disable(&pdev->dev);
  1351. #else
  1352. vpu_clk_disable(s_vpu_clk);
  1353. #endif
  1354. return -EAGAIN;
  1355. }
  1356. static int vpu_resume(struct platform_device *pdev)
  1357. {
  1358. int i;
  1359. int core;
  1360. u32 val;
  1361. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1362. int product_code;
  1363. unsigned long code_base;
  1364. u32 code_size;
  1365. u32 remap_size;
  1366. int regVal;
  1367. u32 hwOption = 0;
  1368. DPRINTK("[VPUDRV] vpu_resume\n");
  1369. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1370. starfive_vdec_clk_enable(&pdev->dev);
  1371. #else
  1372. vpu_clk_enable(s_vpu_clk);
  1373. #endif
  1374. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1375. if (s_bit_firmware_info[core].size == 0) {
  1376. continue;
  1377. }
  1378. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1379. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1380. code_base = s_common_memory.phys_addr;
  1381. /* ALIGN TO 4KB */
  1382. code_size = (W5_MAX_CODE_BUF_SIZE&~0xfff);
  1383. if (code_size < s_bit_firmware_info[core].size*2) {
  1384. goto DONE_WAKEUP;
  1385. }
  1386. regVal = 0;
  1387. WriteVpuRegister(W5_PO_CONF, regVal);
  1388. /* Reset All blocks */
  1389. regVal = 0x7ffffff;
  1390. WriteVpuRegister(W5_VPU_RESET_REQ, regVal); /*Reset All blocks*/
  1391. /* Waiting reset done */
  1392. while (ReadVpuRegister(W5_VPU_RESET_STATUS)) {
  1393. if (time_after(jiffies, timeout))
  1394. goto DONE_WAKEUP;
  1395. }
  1396. WriteVpuRegister(W5_VPU_RESET_REQ, 0);
  1397. /* remap page size */
  1398. remap_size = (code_size >> 12) & 0x1ff;
  1399. regVal = 0x80000000 | (W5_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remap_size;
  1400. WriteVpuRegister(W5_VPU_REMAP_CTRL, regVal);
  1401. WriteVpuRegister(W5_VPU_REMAP_VADDR,0x00000000); /* DO NOT CHANGE! */
  1402. WriteVpuRegister(W5_VPU_REMAP_PADDR,code_base);
  1403. WriteVpuRegister(W5_ADDR_CODE_BASE, code_base);
  1404. WriteVpuRegister(W5_CODE_SIZE, code_size);
  1405. WriteVpuRegister(W5_CODE_PARAM, 0);
  1406. WriteVpuRegister(W5_INIT_VPU_TIME_OUT_CNT, timeout);
  1407. WriteVpuRegister(W5_HW_OPTION, hwOption);
  1408. /* Interrupt */
  1409. if (product_code == WAVE521_CODE || product_code == WAVE521C_CODE ) {
  1410. regVal = (1<<INT_WAVE5_ENC_SET_PARAM);
  1411. regVal |= (1<<INT_WAVE5_ENC_PIC);
  1412. regVal |= (1<<INT_WAVE5_INIT_SEQ);
  1413. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1414. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1415. }
  1416. else {
  1417. // decoder
  1418. regVal = (1<<INT_WAVE5_INIT_SEQ);
  1419. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1420. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1421. }
  1422. WriteVpuRegister(W5_VPU_VINT_ENABLE, regVal);
  1423. Wave5BitIssueCommand(core, W5_CMD_INIT_VPU);
  1424. WriteVpuRegister(W5_VPU_REMAP_CORE_START, 1);
  1425. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1426. if (time_after(jiffies, timeout))
  1427. goto DONE_WAKEUP;
  1428. }
  1429. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1430. DPRINTK("WAKEUP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1431. goto DONE_WAKEUP;
  1432. }
  1433. }
  1434. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1435. WriteVpuRegister(BIT_CODE_RUN, 0);
  1436. /*---- LOAD BOOT CODE*/
  1437. for (i = 0; i < 512; i++) {
  1438. val = s_bit_firmware_info[core].bit_code[i];
  1439. WriteVpuRegister(BIT_CODE_DOWN, ((i << 16) | val));
  1440. }
  1441. for (i = 0 ; i < 64 ; i++)
  1442. WriteVpuRegister(BIT_BASE+(0x100+(i * 4)), s_vpu_reg_store[core][i]);
  1443. WriteVpuRegister(BIT_BUSY_FLAG, 1);
  1444. WriteVpuRegister(BIT_CODE_RESET, 1);
  1445. WriteVpuRegister(BIT_CODE_RUN, 1);
  1446. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1447. if (time_after(jiffies, timeout))
  1448. goto DONE_WAKEUP;
  1449. }
  1450. }
  1451. else {
  1452. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1453. goto DONE_WAKEUP;
  1454. }
  1455. }
  1456. if (s_vpu_open_ref_count == 0){
  1457. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1458. starfive_vdec_clk_disable(&pdev->dev);
  1459. #else
  1460. vpu_clk_disable(s_vpu_clk);
  1461. #endif
  1462. }
  1463. DONE_WAKEUP:
  1464. if (s_vpu_open_ref_count > 0){
  1465. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1466. starfive_vdec_clk_enable(&pdev->dev);
  1467. #else
  1468. vpu_clk_enable(s_vpu_clk);
  1469. #endif
  1470. }
  1471. return 0;
  1472. }
  1473. #else
  1474. #define vpu_suspend NULL
  1475. #define vpu_resume NULL
  1476. #endif /* !CONFIG_PM */
  1477. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1478. static const struct of_device_id cm_vpu_match[] = {
  1479. {
  1480. .compatible = "c&m,cm511-vpu",
  1481. },
  1482. {
  1483. },
  1484. };
  1485. MODULE_DEVICE_TABLE(of, cm_vpu_match);
  1486. static struct platform_driver vpu_driver = {
  1487. .driver = {
  1488. .name = VPU_PLATFORM_DEVICE_NAME,
  1489. .of_match_table = cm_vpu_match,
  1490. },
  1491. .probe = vpu_probe,
  1492. .remove = vpu_remove,
  1493. .suspend = vpu_suspend,
  1494. .resume = vpu_resume,
  1495. };
  1496. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1497. static int __init vpu_init(void)
  1498. {
  1499. int res;
  1500. #ifdef SUPPORT_MULTI_INST_INTR
  1501. int i;
  1502. #endif
  1503. DPRINTK("[VPUDRV] begin vpu_init\n");
  1504. #ifdef SUPPORT_MULTI_INST_INTR
  1505. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1506. init_waitqueue_head(&s_interrupt_wait_q[i]);
  1507. }
  1508. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1509. #define MAX_INTERRUPT_QUEUE (16*MAX_NUM_INSTANCE)
  1510. res = kfifo_alloc(&s_interrupt_pending_q[i], MAX_INTERRUPT_QUEUE*sizeof(u32), GFP_KERNEL);
  1511. if (res) {
  1512. DPRINTK("[VPUDRV] kfifo_alloc failed 0x%x\n", res);
  1513. }
  1514. }
  1515. #else
  1516. init_waitqueue_head(&s_interrupt_wait_q);
  1517. #endif
  1518. s_common_memory.base = 0;
  1519. s_instance_pool.base = 0;
  1520. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1521. res = platform_driver_register(&vpu_driver);
  1522. #else
  1523. res = vpu_probe(NULL);
  1524. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1525. DPRINTK("[VPUDRV] end vpu_init result=0x%x\n", res);
  1526. return res;
  1527. }
  1528. static void __exit vpu_exit(void)
  1529. {
  1530. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1531. starfive_vdec_clk_disable(vpu_dev);
  1532. starfive_vdec_rst_assert(vpu_dev);
  1533. #endif
  1534. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1535. DPRINTK("[VPUDRV] vpu_exit\n");
  1536. platform_driver_unregister(&vpu_driver);
  1537. #else /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1538. #ifndef VPU_SUPPORT_CLOCK_CONTROL
  1539. vpu_clk_disable(s_vpu_clk);
  1540. vpu_clk_put(s_vpu_clk);
  1541. #endif
  1542. if (s_instance_pool.base) {
  1543. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1544. vfree((const void *)s_instance_pool.base);
  1545. #else
  1546. vpu_free_dma_buffer(&s_instance_pool);
  1547. #endif
  1548. s_instance_pool.base = 0;
  1549. }
  1550. if (s_common_memory.base) {
  1551. vpu_free_dma_buffer(&s_common_memory);
  1552. s_common_memory.base = 0;
  1553. }
  1554. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1555. if (s_video_memory.base) {
  1556. iounmap((void *)s_video_memory.base);
  1557. s_video_memory.base = 0;
  1558. vmem_exit(&s_vmem);
  1559. }
  1560. #endif
  1561. if (s_vpu_major > 0) {
  1562. cdev_del(&s_vpu_cdev);
  1563. unregister_chrdev_region(s_vpu_major, 1);
  1564. s_vpu_major = 0;
  1565. }
  1566. #ifdef VPU_SUPPORT_ISR
  1567. if (s_vpu_irq)
  1568. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1569. #endif
  1570. #ifdef SUPPORT_MULTI_INST_INTR
  1571. {
  1572. int i;
  1573. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1574. kfifo_free(&s_interrupt_pending_q[i]);
  1575. }
  1576. }
  1577. #endif
  1578. if (s_vpu_register.virt_addr) {
  1579. iounmap((void *)s_vpu_register.virt_addr);
  1580. s_vpu_register.virt_addr = 0x00;
  1581. }
  1582. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1583. return;
  1584. }
  1585. MODULE_AUTHOR("A customer using C&M VPU, Inc.");
  1586. MODULE_DESCRIPTION("VPU linux driver");
  1587. MODULE_LICENSE("GPL");
  1588. module_init(vpu_init);
  1589. module_exit(vpu_exit);
  1590. static void _set_reset(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg,int ibit)
  1591. {
  1592. unsigned int read_value;
  1593. read_value = vic_readl(p_assert_reg);
  1594. read_value &= ~(0x1<<ibit);
  1595. read_value |= (0x1&0x1)<<ibit;
  1596. vic_writel(read_value,p_assert_reg);
  1597. do {
  1598. read_value = (vic_readl(p_status_reg))>>ibit;
  1599. read_value &= 0x1;
  1600. } while(read_value!=0x0);
  1601. }
  1602. static void _clr_reset(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg,int ibit)
  1603. {
  1604. unsigned int read_value;
  1605. read_value = vic_readl(p_assert_reg);
  1606. read_value &= ~(0x1<<ibit);
  1607. read_value |= (0x0&0x1)<<ibit;
  1608. vic_writel(read_value,p_assert_reg);
  1609. do {
  1610. read_value = (vic_readl(p_status_reg))>>ibit;
  1611. read_value &= 0x1;
  1612. } while(read_value!=0x1);
  1613. }
  1614. static void _enable_clk(volatile unsigned long p_reg,int ibit)
  1615. {
  1616. unsigned int read_value;
  1617. read_value = vic_readl(p_reg);
  1618. read_value &= ~(0x1<<ibit);
  1619. read_value |= (0x1&0x1)<<ibit;
  1620. vic_writel(read_value,p_reg);
  1621. }
  1622. static void _disable_clk(volatile unsigned long p_reg,int ibit)
  1623. {
  1624. unsigned int read_value;
  1625. read_value = vic_readl(p_reg);
  1626. read_value &= ~(0x1<<ibit);
  1627. read_value |= (0x0&0x1)<<ibit;
  1628. vic_writel(read_value,p_reg);
  1629. }
  1630. static void _reset_assert(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg)
  1631. {
  1632. //_set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_BRG_MAIN);
  1633. _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_APB);
  1634. _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_AXI);
  1635. _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_BCLK);
  1636. _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_CCLK);
  1637. }
  1638. static void _reset_clear(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg)
  1639. {
  1640. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_BRG_MAIN);
  1641. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_AXI);
  1642. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_BCLK);
  1643. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_CCLK);
  1644. _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_APB);
  1645. }
  1646. static int _reset(void)
  1647. {
  1648. volatile unsigned long p_breg = (unsigned long)ioremap_nocache(rstgen_Software_RESET_BASE_REG_ADDR,0x20);
  1649. if(!p_breg){
  1650. return -1;
  1651. }
  1652. _reset_assert(p_breg+rstgen_Software_RESET_assert0_OFFSET,p_breg+rstgen_Software_RESET_status0_OFFSET);
  1653. mdelay(1);
  1654. _reset_clear(p_breg+rstgen_Software_RESET_assert0_OFFSET,p_breg+rstgen_Software_RESET_status0_OFFSET);
  1655. iounmap((void *)p_breg);
  1656. return 0;
  1657. }
  1658. static int _clk_control(int enable)
  1659. {
  1660. volatile unsigned long p_breg = (unsigned long)ioremap_nocache(clk_BASE_REG_ADDR,0x100);
  1661. if(!p_breg){
  1662. return -1;
  1663. }
  1664. if(enable){
  1665. _enable_clk(p_breg+clk_vdec_axi_ctrl_REG_OFFSET,31);
  1666. _enable_clk(p_breg+clk_vdecbrg_mainclk_ctrl_REG_OFFSET,31);
  1667. _enable_clk(p_breg+clk_vdec_bclk_ctrl_REG_OFFSET,31);
  1668. _enable_clk(p_breg+clk_vdec_cclk_ctrl_REG_OFFSET,31);
  1669. _enable_clk(p_breg+clk_vdec_apb_ctrl_REG_OFFSET,31);
  1670. }
  1671. else
  1672. {
  1673. _disable_clk(p_breg+clk_vdec_axi_ctrl_REG_OFFSET,31);
  1674. // _disable_clk(p_breg+clk_vdecbrg_mainclk_ctrl_REG_OFFSET,31);
  1675. _disable_clk(p_breg+clk_vdec_bclk_ctrl_REG_OFFSET,31);
  1676. _disable_clk(p_breg+clk_vdec_cclk_ctrl_REG_OFFSET,31);
  1677. _disable_clk(p_breg+clk_vdec_apb_ctrl_REG_OFFSET,31);
  1678. }
  1679. iounmap((void *)p_breg);
  1680. return 0;
  1681. }
  1682. int vpu_hw_reset(void)
  1683. {
  1684. _reset();
  1685. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1686. return 0;
  1687. }
  1688. struct clk *vpu_clk_get(struct device *dev)
  1689. {
  1690. return clk_get(dev, VPU_CLK_NAME);
  1691. }
  1692. void vpu_clk_put(struct clk *clk)
  1693. {
  1694. if (!(clk == NULL || IS_ERR(clk)))
  1695. clk_put(clk);
  1696. }
  1697. int vpu_clk_enable(struct clk *clk)
  1698. {
  1699. if (!(clk == NULL || IS_ERR(clk))) {
  1700. /* the bellow is for C&M EVB.*/
  1701. /*
  1702. {
  1703. struct clk *s_vpuext_clk = NULL;
  1704. s_vpuext_clk = clk_get(NULL, "vcore");
  1705. if (s_vpuext_clk)
  1706. {
  1707. DPRINTK("[VPUDRV] vcore clk=%p\n", s_vpuext_clk);
  1708. clk_enable(s_vpuext_clk);
  1709. }
  1710. DPRINTK("[VPUDRV] vbus clk=%p\n", s_vpuext_clk);
  1711. if (s_vpuext_clk)
  1712. {
  1713. s_vpuext_clk = clk_get(NULL, "vbus");
  1714. clk_enable(s_vpuext_clk);
  1715. }
  1716. }
  1717. */
  1718. /* for C&M EVB. */
  1719. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1720. //customers needs implementation to turn on clock like clk_enable(clk)
  1721. return 1;
  1722. }
  1723. _clk_control(1);
  1724. return 0;
  1725. }
  1726. void vpu_clk_disable(struct clk *clk)
  1727. {
  1728. if (!(clk == NULL || IS_ERR(clk))) {
  1729. DPRINTK("[VPUDRV] vpu_clk_disable\n");
  1730. //customers needs implementation to turn off clock like clk_disable(clk)
  1731. }
  1732. _clk_control(0);
  1733. }