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@@ -19,9 +19,15 @@
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#include <linux/kfifo.h>
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#include <linux/kthread.h>
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#include <linux/sched/signal.h>
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-#include <soc/starfive/vic7100.h>
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+#include <soc/sifive/sifive_l2_cache.h>
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#include "../../../vpuapi/vpuconfig.h"
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#include "vpu.h"
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+#include "venc-starfive.h"
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+
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+#include <linux/of_device.h>
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+
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+#define starfive_flush_dcache(start, len) \
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+ sifive_l2_flush64_range(start, len)
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//#define ENABLE_DEBUG_MSG
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#ifdef ENABLE_DEBUG_MSG
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@@ -31,8 +37,10 @@
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#endif
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/* definitions to be changed as customer configuration */
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-/* if you want to have clock gating scheme frame by frame */
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- #define VPU_SUPPORT_CLOCK_CONTROL
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+/* if linux version is 5.15 or later, then can use clock and reset framework */
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+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)
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+#define VPU_SUPPORT_CLOCK_CONTROL
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+#endif
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/* if the driver want to use interrupt service from kernel ISR */
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#define VPU_SUPPORT_ISR
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@@ -50,7 +58,6 @@
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//#define VPU_SUPPORT_RESERVED_VIDEO_MEMORY
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#define VPU_PLATFORM_DEVICE_NAME "venc"
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-#define VPU_CLK_NAME "vcoenc"
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#define VPU_DEV_NAME "venc"
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/* if the platform driver knows this driver */
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@@ -58,6 +65,7 @@
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#define VPU_REG_BASE_ADDR 0x118E0000
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#define VPU_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
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+#define VENC_IRQ_ADDR 0x18
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#ifdef VPU_SUPPORT_ISR
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#define VPU_IRQ_NUM (26)
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@@ -109,10 +117,8 @@ static vpudrv_buffer_t s_video_memory = {0};
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#endif /*VPU_SUPPORT_RESERVED_VIDEO_MEMORY*/
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static int vpu_hw_reset(void);
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-static void vpu_clk_disable(struct clk *clk);
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-static int vpu_clk_enable(struct clk *clk);
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-static struct clk *vpu_clk_get(struct device *dev);
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-static void vpu_clk_put(struct clk *clk);
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+static void vpu_clk_disable(void);
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+static int vpu_clk_enable(void);
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/* end customer definition */
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static vpudrv_buffer_t s_instance_pool = {0};
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@@ -121,7 +127,6 @@ static vpu_drv_context_t s_vpu_drv_context;
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static int s_vpu_major;
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static struct cdev s_vpu_cdev;
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-static struct clk *s_vpu_clk;
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static int s_vpu_open_ref_count;
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#ifdef VPU_SUPPORT_ISR
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static int s_vpu_irq = VPU_IRQ_NUM;
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@@ -240,6 +245,24 @@ static u32 s_vpu_reg_store[MAX_NUM_VPU_CORE][64];
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#define WriteVpuRegister(addr, val) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr) = (unsigned int)val
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#define WriteVpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
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+#define vic_readl(addr) readl((void __iomem *)addr)
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+#define vic_writel(val,addr) writel(val,(void __iomem *)addr)
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+
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+#define rstgen_Software_RESET_BASE_REG_ADDR 0x11840000
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+#define rstgen_Software_RESET_assert0_OFFSET (0x0)
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+#define rstgen_Software_RESET_status0_OFFSET (0x10)
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+#define NBIT_RSTN_VENC_BRG_MAIN 26
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+#define NBIT_RSTN_VENC_AXI 25
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+#define NBIT_RSTN_VENC_BCLK 27
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+#define NBIT_RSTN_VENC_CCLK 28
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+#define NBIT_RSTN_VENC_APB 29
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+
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+#define clk_BASE_REG_ADDR 0x11800000
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+#define clk_venc_axi_ctrl_REG_OFFSET (0xe4)
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+#define clk_vencbrg_mainclk_ctrl_REG_OFFSET (0xe8)
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+#define clk_venc_bclk_ctrl_REG_OFFSET (0xec)
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+#define clk_venc_cclk_ctrl_REG_OFFSET (0xf0)
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+#define clk_venc_apb_ctrl_REG_OFFSET (0xf4)
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static int vpu_alloc_dma_buffer(vpudrv_buffer_t *vb)
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{
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@@ -814,18 +837,18 @@ INTERRUPT_REMAIN_IN_QUEUE:
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case VDI_IOCTL_SET_CLOCK_GATE:
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{
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- u32 clkgate;
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-
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- DPRINTK("[VPUDRV][+]VDI_IOCTL_SET_CLOCK_GATE\n");
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- if (get_user(clkgate, (u32 __user *) arg))
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- return -EFAULT;
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-#ifdef VPU_SUPPORT_CLOCK_CONTROL
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- if (clkgate)
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- vpu_clk_enable(s_vpu_clk);
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- else
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- vpu_clk_disable(s_vpu_clk);
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-#endif
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- DPRINTK("[VPUDRV][-]VDI_IOCTL_SET_CLOCK_GATE\n");
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+// u32 clkgate;
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+
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+// DPRINTK("[VPUDRV][+]VDI_IOCTL_SET_CLOCK_GATE\n");
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+// if (get_user(clkgate, (u32 __user *) arg))
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+// return -EFAULT;
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+// #ifdef VPU_SUPPORT_CLOCK_CONTROL
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+// if (clkgate)
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+// //vpu_clk_enable(s_vpu_clk);
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+// else
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+// //vpu_clk_disable(s_vpu_clk);
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+// #endif
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+// DPRINTK("[VPUDRV][-]VDI_IOCTL_SET_CLOCK_GATE\n");
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}
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break;
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@@ -1007,7 +1030,7 @@ INTERRUPT_REMAIN_IN_QUEUE:
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break;
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case VDI_IOCTL_RESET:
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{
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- vpu_hw_reset();
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+ //vpu_hw_reset();
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}
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break;
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case VDI_IOCTL_GET_REGISTER_INFO:
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@@ -1231,6 +1254,20 @@ struct file_operations vpu_fops = {
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.mmap = vpu_mmap,
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};
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+static struct resource venc_resource[] = {
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+
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+ [0] = {
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+ .start = VPU_REG_BASE_ADDR,
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+ .end = VPU_REG_BASE_ADDR + VPU_REG_SIZE - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+
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+ [1] = {
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+ .start = VENC_IRQ_ADDR,
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+ .end = VENC_IRQ_ADDR,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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static int vpu_probe(struct platform_device *pdev)
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{
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@@ -1250,6 +1287,14 @@ static int vpu_probe(struct platform_device *pdev)
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dev_info(vpu_dev,"device init.\n");
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}
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+#ifdef VPU_SUPPORT_CLOCK_CONTROL
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+ err = platform_device_add_resources(pdev, venc_resource, 2);
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+ if (err) {
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+ printk(KERN_ERR "could not add venc resource\n");
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+ goto ERROR_PROVE_DEVICE;
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+ }
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+#endif
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+
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if (pdev)
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (res) {/* if platform driver is implemented */
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@@ -1282,19 +1327,14 @@ static int vpu_probe(struct platform_device *pdev)
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goto ERROR_PROVE_DEVICE;
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}
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- if (pdev)
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- s_vpu_clk = vpu_clk_get(&pdev->dev);
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- else
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- s_vpu_clk = vpu_clk_get(NULL);
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-
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- if (!s_vpu_clk)
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- printk(KERN_ERR "[VPUDRV] : not support clock controller.\n");
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- else
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- DPRINTK("[VPUDRV] : get clock controller s_vpu_clk=%p\n", s_vpu_clk);
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-
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#ifdef VPU_SUPPORT_CLOCK_CONTROL
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+ err = starfive_venc_clk_rst_init(pdev);
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+ if (err){
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+ goto ERROR_PROVE_DEVICE;
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+ }
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#else
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- vpu_clk_enable(s_vpu_clk);
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+ vpu_clk_enable();
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+ vpu_hw_reset();
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#endif
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#ifdef VPU_SUPPORT_ISR
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@@ -1310,7 +1350,6 @@ static int vpu_probe(struct platform_device *pdev)
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#else
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DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
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#endif
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-
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err = request_irq(s_vpu_irq, vpu_irq_handler, 0, pdev->name, (void *)(&s_vpu_drv_context));
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if (err) {
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printk(KERN_ERR "[VPUDRV] : fail to register interrupt handler\n");
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@@ -1405,8 +1444,6 @@ static int vpu_remove(struct platform_device *pdev)
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if (s_vpu_register.virt_addr)
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iounmap((void *)s_vpu_register.virt_addr);
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- vpu_clk_put(s_vpu_clk);
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-
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return 0;
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}
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#endif /*VPU_SUPPORT_PLATFORM_DRIVER_REGISTER*/
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@@ -1435,7 +1472,11 @@ static int vpu_suspend(struct platform_device *pdev, pm_message_t state)
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DPRINTK("[VPUDRV] vpu_suspend\n");
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- vpu_clk_enable(s_vpu_clk);
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+#ifdef VPU_SUPPORT_CLOCK_CONTROL
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+ starfive_venc_clk_enable(&pdev->dev);
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+#else
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+ vpu_clk_enable();
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+#endif
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if (s_vpu_open_ref_count > 0) {
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for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
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@@ -1480,12 +1521,19 @@ static int vpu_suspend(struct platform_device *pdev, pm_message_t state)
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}
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}
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- vpu_clk_disable(s_vpu_clk);
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+#ifdef VPU_SUPPORT_CLOCK_CONTROL
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+ starfive_venc_clk_disable(&pdev->dev);
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+#else
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+ vpu_clk_disable();
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+#endif
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return 0;
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DONE_SUSPEND:
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-
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- vpu_clk_disable(s_vpu_clk);
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+#ifdef VPU_SUPPORT_CLOCK_CONTROL
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+ starfive_venc_clk_disable(&pdev->dev);
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+#else
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+ vpu_clk_disable();
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+#endif
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return -EAGAIN;
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@@ -1507,7 +1555,11 @@ static int vpu_resume(struct platform_device *pdev)
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DPRINTK("[VPUDRV] vpu_resume\n");
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- vpu_clk_enable(s_vpu_clk);
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+#ifdef VPU_SUPPORT_CLOCK_CONTROL
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+ starfive_venc_clk_enable(&pdev->dev);
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+#else
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+ vpu_clk_enable();
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+#endif
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for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
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@@ -1611,14 +1663,25 @@ static int vpu_resume(struct platform_device *pdev)
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}
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- if (s_vpu_open_ref_count == 0)
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- vpu_clk_disable(s_vpu_clk);
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+ if (s_vpu_open_ref_count == 0){
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+#ifdef VPU_SUPPORT_CLOCK_CONTROL
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+ starfive_venc_clk_disable(&pdev->dev);
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+#else
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+ vpu_clk_disable();
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+#endif
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+ }
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+
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DONE_WAKEUP:
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- if (s_vpu_open_ref_count > 0)
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- vpu_clk_enable(s_vpu_clk);
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-
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+ if (s_vpu_open_ref_count > 0){
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+#ifdef VPU_SUPPORT_CLOCK_CONTROL
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+ starfive_venc_clk_enable(&pdev->dev);
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+#else
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+ vpu_clk_enable();
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+#endif
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+ }
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+
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return 0;
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}
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#else
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@@ -1680,6 +1743,13 @@ static int __init vpu_init(void)
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static void __exit vpu_exit(void)
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{
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+#ifdef VPU_SUPPORT_CLOCK_CONTROL
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+ starfive_venc_clk_disable(vpu_dev);
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+ starfive_venc_rst_assert(vpu_dev);
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+#else
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+ vpu_clk_disable();
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+#endif
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+
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#ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
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DPRINTK("[VPUDRV] vpu_exit\n");
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@@ -1687,12 +1757,6 @@ static void __exit vpu_exit(void)
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#else /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
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-#ifdef VPU_SUPPORT_CLOCK_CONTROL
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-#else
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- vpu_clk_disable(s_vpu_clk);
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-#endif
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- vpu_clk_put(s_vpu_clk);
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-
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if (s_instance_pool.base) {
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#ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
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vfree((const void *)s_instance_pool.base);
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@@ -1753,59 +1817,124 @@ MODULE_LICENSE("GPL");
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module_init(vpu_init);
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module_exit(vpu_exit);
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-int vpu_hw_reset(void)
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+static void _set_reset(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg,int ibit)
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{
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- DPRINTK("[VPUDRV] request vpu reset from application. \n");
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- return 0;
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+ unsigned int read_value;
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+ read_value = vic_readl(p_assert_reg);
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+ read_value &= ~(0x1<<ibit);
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+ read_value |= (0x1&0x1)<<ibit;
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+ vic_writel(read_value,p_assert_reg);
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+
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}
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-struct clk *vpu_clk_get(struct device *dev)
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+static void _clr_reset(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg,int ibit)
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{
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- return clk_get(dev, VPU_CLK_NAME);
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+ unsigned int read_value;
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+ read_value = vic_readl(p_assert_reg);
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+ read_value &= ~(0x1<<ibit);
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+ read_value |= (0x0&0x1)<<ibit;
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+ vic_writel(read_value,p_assert_reg);
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+
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}
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-void vpu_clk_put(struct clk *clk)
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+
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+static void _enable_clk(volatile unsigned long p_reg,int ibit)
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{
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- if (!(clk == NULL || IS_ERR(clk)))
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- clk_put(clk);
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+ unsigned int read_value;
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+ read_value = vic_readl(p_reg);
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+ read_value &= ~(0x1<<ibit);
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+ read_value |= (0x1&0x1)<<ibit;
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+ vic_writel(read_value,p_reg);
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}
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-int vpu_clk_enable(struct clk *clk)
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+
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+static void _disable_clk(volatile unsigned long p_reg,int ibit)
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{
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- if (!(clk == NULL || IS_ERR(clk))) {
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- /* the bellow is for C&M EVB.*/
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- /*
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- {
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- struct clk *s_vpuext_clk = NULL;
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- s_vpuext_clk = clk_get(NULL, "vcore");
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- if (s_vpuext_clk)
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- {
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- DPRINTK("[VPUDRV] vcore clk=%p\n", s_vpuext_clk);
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- clk_enable(s_vpuext_clk);
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- }
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+ unsigned int read_value;
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+ read_value = vic_readl(p_reg);
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+ read_value &= ~(0x1<<ibit);
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+ read_value |= (0x0&0x1)<<ibit;
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+ vic_writel(read_value,p_reg);
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+}
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- DPRINTK("[VPUDRV] vbus clk=%p\n", s_vpuext_clk);
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- if (s_vpuext_clk)
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- {
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- s_vpuext_clk = clk_get(NULL, "vbus");
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- clk_enable(s_vpuext_clk);
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- }
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- }
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- */
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- /* for C&M EVB. */
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+static void _reset_assert(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg)
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+{
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+ //_set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_BRG_MAIN);
|
|
|
+ _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_APB);
|
|
|
+ _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_AXI);
|
|
|
+ _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_BCLK);
|
|
|
+ _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_CCLK);
|
|
|
+}
|
|
|
|
|
|
- DPRINTK("[VPUDRV] vpu_clk_enable\n");
|
|
|
- //customers needs implementation to turn on clock like clk_enable(clk)
|
|
|
- return 1;
|
|
|
- }
|
|
|
+static void _reset_clear(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg)
|
|
|
+{
|
|
|
+ _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_BRG_MAIN);
|
|
|
+ _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_AXI);
|
|
|
+ _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_BCLK);
|
|
|
+ _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_CCLK);
|
|
|
+ _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VENC_APB);
|
|
|
+}
|
|
|
|
|
|
- return 0;
|
|
|
+static int _reset(void)
|
|
|
+{
|
|
|
+ volatile unsigned long p_breg = (unsigned long)ioremap_nocache(rstgen_Software_RESET_BASE_REG_ADDR,0x20);
|
|
|
+
|
|
|
+ if(!p_breg){
|
|
|
+ return -1;
|
|
|
+ }
|
|
|
+
|
|
|
+ _reset_assert(p_breg+rstgen_Software_RESET_assert0_OFFSET,p_breg+rstgen_Software_RESET_status0_OFFSET);
|
|
|
+
|
|
|
+ mdelay(1);
|
|
|
+
|
|
|
+ _reset_clear(p_breg+rstgen_Software_RESET_assert0_OFFSET,p_breg+rstgen_Software_RESET_status0_OFFSET);
|
|
|
+
|
|
|
+ iounmap((void *)p_breg);
|
|
|
+
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
-void vpu_clk_disable(struct clk *clk)
|
|
|
+static int _clk_control(int enable)
|
|
|
{
|
|
|
- if (!(clk == NULL || IS_ERR(clk))) {
|
|
|
- DPRINTK("[VPUDRV] vpu_clk_disable\n");
|
|
|
- //customers needs implementation to turn off clock like clk_disable(clk)
|
|
|
- }
|
|
|
+ volatile unsigned long p_breg = (unsigned long)ioremap_nocache(clk_BASE_REG_ADDR,0x100);
|
|
|
+ if(!p_breg){
|
|
|
+ return -1;
|
|
|
+ }
|
|
|
+
|
|
|
+ if(enable){
|
|
|
+ _enable_clk(p_breg+clk_venc_axi_ctrl_REG_OFFSET,31);
|
|
|
+ _enable_clk(p_breg+clk_vencbrg_mainclk_ctrl_REG_OFFSET,31);
|
|
|
+ _enable_clk(p_breg+clk_venc_bclk_ctrl_REG_OFFSET,31);
|
|
|
+ _enable_clk(p_breg+clk_venc_cclk_ctrl_REG_OFFSET,31);
|
|
|
+ _enable_clk(p_breg+clk_venc_apb_ctrl_REG_OFFSET,31);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ _disable_clk(p_breg+clk_venc_axi_ctrl_REG_OFFSET,31);
|
|
|
+ _disable_clk(p_breg+clk_vencbrg_mainclk_ctrl_REG_OFFSET,31);
|
|
|
+ _disable_clk(p_breg+clk_venc_bclk_ctrl_REG_OFFSET,31);
|
|
|
+ _disable_clk(p_breg+clk_venc_cclk_ctrl_REG_OFFSET,31);
|
|
|
+ _disable_clk(p_breg+clk_venc_apb_ctrl_REG_OFFSET,31);
|
|
|
+ }
|
|
|
+
|
|
|
+ iounmap((void *)p_breg);
|
|
|
+
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
+int vpu_hw_reset(void)
|
|
|
+{
|
|
|
+ _reset();
|
|
|
+ DPRINTK("[VPUDRV] request vpu reset from application. \n");
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+int vpu_clk_enable(void)
|
|
|
+{
|
|
|
+ _clk_control(1);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
|
|
|
+void vpu_clk_disable(void)
|
|
|
+{
|
|
|
+ _clk_control(0);
|
|
|
+}
|