Cpuid.h 133 KB

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  1. /** @file
  2. CPUID leaf definitions.
  3. Provides defines for CPUID leaf indexes. Data structures are provided for
  4. registers returned by a CPUID leaf that contain one or more bit fields.
  5. If a register returned is a single 32-bit value, then a data structure is
  6. not provided for that register.
  7. Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
  8. This program and the accompanying materials are licensed and made available under
  9. the terms and conditions of the BSD License which accompanies this distribution.
  10. The full text of the license may be found at
  11. http://opensource.org/licenses/bsd-license.php
  12. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14. @par Specification Reference:
  15. Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
  16. November 2018, CPUID instruction.
  17. **/
  18. #ifndef __CPUID_H__
  19. #define __CPUID_H__
  20. /**
  21. CPUID Signature Information
  22. @param EAX CPUID_SIGNATURE (0x00)
  23. @retval EAX Returns the highest value the CPUID instruction recognizes for
  24. returning basic processor information. The value is returned is
  25. processor specific.
  26. @retval EBX First 4 characters of a vendor identification string.
  27. @retval ECX Last 4 characters of a vendor identification string.
  28. @retval EDX Middle 4 characters of a vendor identification string.
  29. <b>Example usage</b>
  30. @code
  31. UINT32 Eax;
  32. UINT32 Ebx;
  33. UINT32 Ecx;
  34. UINT32 Edx;
  35. AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
  36. @endcode
  37. **/
  38. #define CPUID_SIGNATURE 0x00
  39. ///
  40. /// @{ CPUID signature values returned by Intel processors
  41. ///
  42. #define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u')
  43. #define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I')
  44. #define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l')
  45. ///
  46. /// @}
  47. ///
  48. /**
  49. CPUID Version Information
  50. @param EAX CPUID_VERSION_INFO (0x01)
  51. @retval EAX Returns Model, Family, Stepping Information described by the
  52. type CPUID_VERSION_INFO_EAX.
  53. @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by
  54. the type CPUID_VERSION_INFO_EBX.
  55. @retval ECX CPU Feature Information described by the type
  56. CPUID_VERSION_INFO_ECX.
  57. @retval EDX CPU Feature Information described by the type
  58. CPUID_VERSION_INFO_EDX.
  59. <b>Example usage</b>
  60. @code
  61. CPUID_VERSION_INFO_EAX Eax;
  62. CPUID_VERSION_INFO_EBX Ebx;
  63. CPUID_VERSION_INFO_ECX Ecx;
  64. CPUID_VERSION_INFO_EDX Edx;
  65. AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
  66. @endcode
  67. **/
  68. #define CPUID_VERSION_INFO 0x01
  69. /**
  70. CPUID Version Information returned in EAX for CPUID leaf
  71. #CPUID_VERSION_INFO.
  72. **/
  73. typedef union {
  74. ///
  75. /// Individual bit fields
  76. ///
  77. struct {
  78. UINT32 SteppingId:4; ///< [Bits 3:0] Stepping ID
  79. UINT32 Model:4; ///< [Bits 7:4] Model
  80. UINT32 FamilyId:4; ///< [Bits 11:8] Family
  81. UINT32 ProcessorType:2; ///< [Bits 13:12] Processor Type
  82. UINT32 Reserved1:2; ///< [Bits 15:14] Reserved
  83. UINT32 ExtendedModelId:4; ///< [Bits 19:16] Extended Model ID
  84. UINT32 ExtendedFamilyId:8; ///< [Bits 27:20] Extended Family ID
  85. UINT32 Reserved2:4; ///< Reserved
  86. } Bits;
  87. ///
  88. /// All bit fields as a 32-bit value
  89. ///
  90. UINT32 Uint32;
  91. } CPUID_VERSION_INFO_EAX;
  92. ///
  93. /// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType
  94. ///
  95. #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00
  96. #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01
  97. #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02
  98. ///
  99. /// @}
  100. ///
  101. /**
  102. CPUID Version Information returned in EBX for CPUID leaf
  103. #CPUID_VERSION_INFO.
  104. **/
  105. typedef union {
  106. ///
  107. /// Individual bit fields
  108. ///
  109. struct {
  110. ///
  111. /// [Bits 7:0] Provides an entry into a brand string table that contains
  112. /// brand strings for IA-32 processors.
  113. ///
  114. UINT32 BrandIndex:8;
  115. ///
  116. /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH
  117. /// and CLFLUSHOPT instructions in 8-byte increments. This field was
  118. /// introduced in the Pentium 4 processor.
  119. ///
  120. UINT32 CacheLineSize:8;
  121. ///
  122. /// [Bits 23:16] Maximum number of addressable IDs for logical processors
  123. /// in this physical package.
  124. ///
  125. /// @note
  126. /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is
  127. /// the number of unique initial APICIDs reserved for addressing different
  128. /// logical processors in a physical package. This field is only valid if
  129. /// CPUID.1.EDX.HTT[bit 28]= 1.
  130. ///
  131. UINT32 MaximumAddressableIdsForLogicalProcessors:8;
  132. ///
  133. /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the
  134. /// processor during power up. This field was introduced in the Pentium 4
  135. /// processor.
  136. ///
  137. UINT32 InitialLocalApicId:8;
  138. } Bits;
  139. ///
  140. /// All bit fields as a 32-bit value
  141. ///
  142. UINT32 Uint32;
  143. } CPUID_VERSION_INFO_EBX;
  144. /**
  145. CPUID Version Information returned in ECX for CPUID leaf
  146. #CPUID_VERSION_INFO.
  147. **/
  148. typedef union {
  149. ///
  150. /// Individual bit fields
  151. ///
  152. struct {
  153. ///
  154. /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the
  155. /// processor supports this technology
  156. ///
  157. UINT32 SSE3:1;
  158. ///
  159. /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ
  160. /// instruction. Carryless Multiplication
  161. ///
  162. UINT32 PCLMULQDQ:1;
  163. ///
  164. /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports
  165. /// DS area using 64-bit layout.
  166. ///
  167. UINT32 DTES64:1;
  168. ///
  169. /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports
  170. /// this feature.
  171. ///
  172. UINT32 MONITOR:1;
  173. ///
  174. /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor
  175. /// supports the extensions to the Debug Store feature to allow for branch
  176. /// message storage qualified by CPL
  177. ///
  178. UINT32 DS_CPL:1;
  179. ///
  180. /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the
  181. /// processor supports this technology.
  182. ///
  183. UINT32 VMX:1;
  184. ///
  185. /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor
  186. /// supports this technology
  187. ///
  188. UINT32 SMX:1;
  189. ///
  190. /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates
  191. /// that the processor supports this technology
  192. ///
  193. UINT32 EIST:1;
  194. ///
  195. /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor
  196. /// supports this technology
  197. ///
  198. UINT32 TM2:1;
  199. ///
  200. /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming
  201. /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction
  202. /// extensions are not present in the processor.
  203. ///
  204. UINT32 SSSE3:1;
  205. ///
  206. /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode
  207. /// can be set to either adaptive mode or shared mode. A value of 0 indicates
  208. /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR
  209. /// Bit 24 (L1 Data Cache Context Mode) for details
  210. ///
  211. UINT32 CNXT_ID:1;
  212. ///
  213. /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE
  214. /// MSR for silicon debug
  215. ///
  216. UINT32 SDBG:1;
  217. ///
  218. /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple
  219. /// Add) extensions using YMM state.
  220. ///
  221. UINT32 FMA:1;
  222. ///
  223. /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature
  224. /// is available.
  225. ///
  226. UINT32 CMPXCHG16B:1;
  227. ///
  228. /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor
  229. /// supports changing IA32_MISC_ENABLE[Bit 23].
  230. ///
  231. UINT32 xTPR_Update_Control:1;
  232. ///
  233. /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the
  234. /// processor supports the performance and debug feature indication MSR
  235. /// IA32_PERF_CAPABILITIES.
  236. ///
  237. UINT32 PDCM:1;
  238. UINT32 Reserved:1;
  239. ///
  240. /// [Bit 17] Process-context identifiers. A value of 1 indicates that the
  241. /// processor supports PCIDs and that software may set CR4.PCIDE to 1.
  242. ///
  243. UINT32 PCID:1;
  244. ///
  245. /// [Bit 18] A value of 1 indicates the processor supports the ability to
  246. /// prefetch data from a memory mapped device. Direct Cache Access.
  247. ///
  248. UINT32 DCA:1;
  249. ///
  250. /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.
  251. ///
  252. UINT32 SSE4_1:1;
  253. ///
  254. /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.
  255. ///
  256. UINT32 SSE4_2:1;
  257. ///
  258. /// [Bit 21] A value of 1 indicates that the processor supports x2APIC
  259. /// feature.
  260. ///
  261. UINT32 x2APIC:1;
  262. ///
  263. /// [Bit 22] A value of 1 indicates that the processor supports MOVBE
  264. /// instruction.
  265. ///
  266. UINT32 MOVBE:1;
  267. ///
  268. /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT
  269. /// instruction.
  270. ///
  271. UINT32 POPCNT:1;
  272. ///
  273. /// [Bit 24] A value of 1 indicates that the processor's local APIC timer
  274. /// supports one-shot operation using a TSC deadline value.
  275. ///
  276. UINT32 TSC_Deadline:1;
  277. ///
  278. /// [Bit 25] A value of 1 indicates that the processor supports the AESNI
  279. /// instruction extensions.
  280. ///
  281. UINT32 AESNI:1;
  282. ///
  283. /// [Bit 26] A value of 1 indicates that the processor supports the
  284. /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV
  285. /// instructions, and XCR0.
  286. ///
  287. UINT32 XSAVE:1;
  288. ///
  289. /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]
  290. /// to enable XSETBV/XGETBV instructions to access XCR0 and to support
  291. /// processor extended state management using XSAVE/XRSTOR.
  292. ///
  293. UINT32 OSXSAVE:1;
  294. ///
  295. /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction
  296. /// extensions.
  297. ///
  298. UINT32 AVX:1;
  299. ///
  300. /// [Bit 29] A value of 1 indicates that processor supports 16-bit
  301. /// floating-point conversion instructions.
  302. ///
  303. UINT32 F16C:1;
  304. ///
  305. /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.
  306. ///
  307. UINT32 RDRAND:1;
  308. ///
  309. /// [Bit 31] Always returns 0.
  310. ///
  311. UINT32 NotUsed:1;
  312. } Bits;
  313. ///
  314. /// All bit fields as a 32-bit value
  315. ///
  316. UINT32 Uint32;
  317. } CPUID_VERSION_INFO_ECX;
  318. /**
  319. CPUID Version Information returned in EDX for CPUID leaf
  320. #CPUID_VERSION_INFO.
  321. **/
  322. typedef union {
  323. ///
  324. /// Individual bit fields
  325. ///
  326. struct {
  327. ///
  328. /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.
  329. ///
  330. UINT32 FPU:1;
  331. ///
  332. /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,
  333. /// including CR4.VME for controlling the feature, CR4.PVI for protected
  334. /// mode virtual interrupts, software interrupt indirection, expansion of
  335. /// the TSS with the software indirection bitmap, and EFLAGS.VIF and
  336. /// EFLAGS.VIP flags.
  337. ///
  338. UINT32 VME:1;
  339. ///
  340. /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including
  341. /// CR4.DE for controlling the feature, and optional trapping of accesses to
  342. /// DR4 and DR5.
  343. ///
  344. UINT32 DE:1;
  345. ///
  346. /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,
  347. /// including CR4.PSE for controlling the feature, the defined dirty bit in
  348. /// PDE (Page Directory Entries), optional reserved bit trapping in CR3,
  349. /// PDEs, and PTEs.
  350. ///
  351. UINT32 PSE:1;
  352. ///
  353. /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,
  354. /// including CR4.TSD for controlling privilege.
  355. ///
  356. UINT32 TSC:1;
  357. ///
  358. /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The
  359. /// RDMSR and WRMSR instructions are supported. Some of the MSRs are
  360. /// implementation dependent.
  361. ///
  362. UINT32 MSR:1;
  363. ///
  364. /// [Bit 6] Physical Address Extension. Physical addresses greater than 32
  365. /// bits are supported: extended page table entry formats, an extra level in
  366. /// the page translation tables is defined, 2-MByte pages are supported
  367. /// instead of 4 Mbyte pages if PAE bit is 1.
  368. ///
  369. UINT32 PAE:1;
  370. ///
  371. /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine
  372. /// Checks, including CR4.MCE for controlling the feature. This feature does
  373. /// not define the model-specific implementations of machine-check error
  374. /// logging, reporting, and processor shutdowns. Machine Check exception
  375. /// handlers may have to depend on processor version to do model specific
  376. /// processing of the exception, or test for the presence of the Machine
  377. /// Check feature.
  378. ///
  379. UINT32 MCE:1;
  380. ///
  381. /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)
  382. /// instruction is supported (implicitly locked and atomic).
  383. ///
  384. UINT32 CX8:1;
  385. ///
  386. /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable
  387. /// Interrupt Controller (APIC), responding to memory mapped commands in the
  388. /// physical address range FFFE0000H to FFFE0FFFH (by default - some
  389. /// processors permit the APIC to be relocated).
  390. ///
  391. UINT32 APIC:1;
  392. UINT32 Reserved1:1;
  393. ///
  394. /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT
  395. /// and associated MSRs are supported.
  396. ///
  397. UINT32 SEP:1;
  398. ///
  399. /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap
  400. /// MSR contains feature bits that describe what memory types are supported,
  401. /// how many variable MTRRs are supported, and whether fixed MTRRs are
  402. /// supported.
  403. ///
  404. UINT32 MTRR:1;
  405. ///
  406. /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure
  407. /// entries that map a page, indicating TLB entries that are common to
  408. /// different processes and need not be flushed. The CR4.PGE bit controls
  409. /// this feature.
  410. ///
  411. UINT32 PGE:1;
  412. ///
  413. /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine
  414. /// Check Architecture of reporting machine errors is supported. The MCG_CAP
  415. /// MSR contains feature bits describing how many banks of error reporting
  416. /// MSRs are supported.
  417. ///
  418. UINT32 MCA:1;
  419. ///
  420. /// [Bit 15] Conditional Move Instructions. The conditional move instruction
  421. /// CMOV is supported. In addition, if x87 FPU is present as indicated by the
  422. /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.
  423. ///
  424. UINT32 CMOV:1;
  425. ///
  426. /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This
  427. /// feature augments the Memory Type Range Registers (MTRRs), allowing an
  428. /// operating system to specify attributes of memory accessed through a
  429. /// linear address on a 4KB granularity.
  430. ///
  431. UINT32 PAT:1;
  432. ///
  433. /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical
  434. /// memory beyond 4 GBytes are supported with 32-bit paging. This feature
  435. /// indicates that upper bits of the physical address of a 4-MByte page are
  436. /// encoded in bits 20:13 of the page-directory entry. Such physical
  437. /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.
  438. ///
  439. UINT32 PSE_36:1;
  440. ///
  441. /// [Bit 18] Processor Serial Number. The processor supports the 96-bit
  442. /// processor identification number feature and the feature is enabled.
  443. ///
  444. UINT32 PSN:1;
  445. ///
  446. /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.
  447. ///
  448. UINT32 CLFSH:1;
  449. UINT32 Reserved2:1;
  450. ///
  451. /// [Bit 21] Debug Store. The processor supports the ability to write debug
  452. /// information into a memory resident buffer. This feature is used by the
  453. /// branch trace store (BTS) and precise event-based sampling (PEBS)
  454. /// facilities.
  455. ///
  456. UINT32 DS:1;
  457. ///
  458. /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The
  459. /// processor implements internal MSRs that allow processor temperature to
  460. /// be monitored and processor performance to be modulated in predefined
  461. /// duty cycles under software control.
  462. ///
  463. UINT32 ACPI:1;
  464. ///
  465. /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX
  466. /// technology.
  467. ///
  468. UINT32 MMX:1;
  469. ///
  470. /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR
  471. /// instructions are supported for fast save and restore of the floating
  472. /// point context. Presence of this bit also indicates that CR4.OSFXSR is
  473. /// available for an operating system to indicate that it supports the
  474. /// FXSAVE and FXRSTOR instructions.
  475. ///
  476. UINT32 FXSR:1;
  477. ///
  478. /// [Bit 25] SSE. The processor supports the SSE extensions.
  479. ///
  480. UINT32 SSE:1;
  481. ///
  482. /// [Bit 26] SSE2. The processor supports the SSE2 extensions.
  483. ///
  484. UINT32 SSE2:1;
  485. ///
  486. /// [Bit 27] Self Snoop. The processor supports the management of
  487. /// conflicting memory types by performing a snoop of its own cache
  488. /// structure for transactions issued to the bus.
  489. ///
  490. UINT32 SS:1;
  491. ///
  492. /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT
  493. /// indicates there is only a single logical processor in the package and
  494. /// software should assume only a single APIC ID is reserved. A value of 1
  495. /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of
  496. /// addressable IDs for logical processors in this package) is valid for the
  497. /// package.
  498. ///
  499. UINT32 HTT:1;
  500. ///
  501. /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor
  502. /// automatic thermal control circuitry (TCC).
  503. ///
  504. UINT32 TM:1;
  505. UINT32 Reserved3:1;
  506. ///
  507. /// [Bit 31] Pending Break Enable. The processor supports the use of the
  508. /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is
  509. /// asserted) to signal the processor that an interrupt is pending and that
  510. /// the processor should return to normal operation to handle the interrupt.
  511. /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.
  512. ///
  513. UINT32 PBE:1;
  514. } Bits;
  515. ///
  516. /// All bit fields as a 32-bit value
  517. ///
  518. UINT32 Uint32;
  519. } CPUID_VERSION_INFO_EDX;
  520. /**
  521. CPUID Cache and TLB Information
  522. @param EAX CPUID_CACHE_INFO (0x02)
  523. @retval EAX Cache and TLB Information described by the type
  524. CPUID_CACHE_INFO_CACHE_TLB.
  525. CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns
  526. 0x01 and must be ignored. Only valid if
  527. CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
  528. @retval EBX Cache and TLB Information described by the type
  529. CPUID_CACHE_INFO_CACHE_TLB. Only valid if
  530. CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
  531. @retval ECX Cache and TLB Information described by the type
  532. CPUID_CACHE_INFO_CACHE_TLB. Only valid if
  533. CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
  534. @retval EDX Cache and TLB Information described by the type
  535. CPUID_CACHE_INFO_CACHE_TLB. Only valid if
  536. CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
  537. <b>Example usage</b>
  538. @code
  539. CPUID_CACHE_INFO_CACHE_TLB Eax;
  540. CPUID_CACHE_INFO_CACHE_TLB Ebx;
  541. CPUID_CACHE_INFO_CACHE_TLB Ecx;
  542. CPUID_CACHE_INFO_CACHE_TLB Edx;
  543. AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
  544. @endcode
  545. <b>Cache Descriptor values</b>
  546. <table>
  547. <tr><th>Value </th><th> Type </th><th> Description </th></tr>
  548. <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr>
  549. <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr>
  550. <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr>
  551. <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr>
  552. <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr>
  553. <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr>
  554. <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative,
  555. 32 byte line size</td></tr>
  556. <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative,
  557. 32 byte line size</td></tr>
  558. <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative,
  559. 64 byte line size</td></tr>
  560. <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr>
  561. <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr>
  562. <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>
  563. <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr>
  564. <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr>
  565. <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr>
  566. <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr>
  567. <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size,
  568. 2 lines per sector</td></tr>
  569. <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size,
  570. 2 lines per sector</td></tr>
  571. <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr>
  572. <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size,
  573. 2 lines per sector</td></tr>
  574. <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size,
  575. 2 lines per sector</td></tr>
  576. <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative,
  577. 64 byte line size</td></tr>
  578. <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative,
  579. 64 byte line size</td></tr>
  580. <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache,
  581. no 3rd-level cache</td></tr>
  582. <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr>
  583. <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr>
  584. <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr>
  585. <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr>
  586. <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr>
  587. <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr>
  588. <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr>
  589. <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr>
  590. <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size
  591. (Intel Xeon processor MP, Family 0FH, Model 06H)<BR>
  592. 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
  593. <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr>
  594. <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr>
  595. <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr>
  596. <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr>
  597. <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr>
  598. <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr>
  599. <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr>
  600. <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr>
  601. <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr>
  602. <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr>
  603. <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>
  604. <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>
  605. <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>
  606. <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>
  607. <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>
  608. <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>
  609. <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>
  610. <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>
  611. <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>
  612. <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 2 MByte or 4 MByte pages, 4-way set associative,
  613. 32 entries and a separate array with 1 GByte pages, 4-way set associative,
  614. 4 entries</td></tr>
  615. <tr><td> 0x64 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 512 entries</td></tr>
  616. <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>
  617. <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>
  618. <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>
  619. <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr>
  620. <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr>
  621. <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr>
  622. <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr>
  623. <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr>
  624. <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr>
  625. <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr>
  626. <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr>
  627. <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr>
  628. <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size,
  629. 2 lines per sector</td></tr>
  630. <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size,
  631. 2 lines per sector</td></tr>
  632. <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size,
  633. 2 lines per sector</td></tr>
  634. <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size,
  635. 2 lines per sector</td></tr>
  636. <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr>
  637. <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr>
  638. <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr>
  639. <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr>
  640. <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr>
  641. <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr>
  642. <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr>
  643. <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
  644. <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
  645. <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr>
  646. <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
  647. <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr>
  648. <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr>
  649. <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
  650. <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr>
  651. <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr>
  652. <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative,
  653. 128 entries</td></tr>
  654. <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr>
  655. <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr>
  656. <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative,
  657. 1024 entries</td></tr>
  658. <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>
  659. <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,
  660. 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>
  661. <tr><td> 0xC4 </td><td> DTLB </td><td> DTLB: 2M/4M Byte pages, 4-way associative, 32 entries</td></tr>
  662. <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>
  663. <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
  664. <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>
  665. <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr>
  666. <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
  667. <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr>
  668. <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr>
  669. <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr>
  670. <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr>
  671. <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr>
  672. <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr>
  673. <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
  674. <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr>
  675. <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr>
  676. <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr>
  677. <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>
  678. <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr>
  679. <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr>
  680. <tr><td> 0xFE </td><td> General </td><td> CPUID leaf 2 does not report TLB descriptor information; use CPUID
  681. leaf 18H to query TLB and other address translation parameters.</td></tr>
  682. <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information,
  683. use CPUID leaf 4 to query cache parameters</td></tr>
  684. </table>
  685. **/
  686. #define CPUID_CACHE_INFO 0x02
  687. /**
  688. CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID
  689. leaf #CPUID_CACHE_INFO.
  690. **/
  691. typedef union {
  692. ///
  693. /// Individual bit fields
  694. ///
  695. struct {
  696. UINT32 Reserved:31;
  697. ///
  698. /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.
  699. /// if 1, then none of the cache descriptor bytes in the register are valid.
  700. ///
  701. UINT32 NotValid:1;
  702. } Bits;
  703. ///
  704. /// Array of Cache and TLB descriptor bytes
  705. ///
  706. UINT8 CacheDescriptor[4];
  707. ///
  708. /// All bit fields as a 32-bit value
  709. ///
  710. UINT32 Uint32;
  711. } CPUID_CACHE_INFO_CACHE_TLB;
  712. /**
  713. CPUID Processor Serial Number
  714. Processor serial number (PSN) is not supported in the Pentium 4 processor
  715. or later. On all models, use the PSN flag (returned using CPUID) to check
  716. for PSN support before accessing the feature.
  717. @param EAX CPUID_SERIAL_NUMBER (0x03)
  718. @retval EAX Reserved.
  719. @retval EBX Reserved.
  720. @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in
  721. Pentium III processor only; otherwise, the value in this
  722. register is reserved.)
  723. @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in
  724. Pentium III processor only; otherwise, the value in this
  725. register is reserved.)
  726. <b>Example usage</b>
  727. @code
  728. UINT32 Ecx;
  729. UINT32 Edx;
  730. AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);
  731. @endcode
  732. **/
  733. #define CPUID_SERIAL_NUMBER 0x03
  734. /**
  735. CPUID Cache Parameters
  736. @param EAX CPUID_CACHE_PARAMS (0x04)
  737. @param ECX Cache Level. Valid values start at 0. Software can enumerate
  738. the deterministic cache parameters for each level of the cache
  739. hierarchy starting with an index value of 0, until the
  740. parameters report the value associated with the CacheType
  741. field in CPUID_CACHE_PARAMS_EAX is 0.
  742. @retval EAX Returns cache type information described by the type
  743. CPUID_CACHE_PARAMS_EAX.
  744. @retval EBX Returns cache line and associativity information described by
  745. the type CPUID_CACHE_PARAMS_EBX.
  746. @retval ECX Returns the number of sets in the cache.
  747. @retval EDX Returns cache WINVD/INVD behavior described by the type
  748. CPUID_CACHE_PARAMS_EDX.
  749. <b>Example usage</b>
  750. @code
  751. UINT32 CacheLevel;
  752. CPUID_CACHE_PARAMS_EAX Eax;
  753. CPUID_CACHE_PARAMS_EBX Ebx;
  754. UINT32 Ecx;
  755. CPUID_CACHE_PARAMS_EDX Edx;
  756. CacheLevel = 0;
  757. do {
  758. AsmCpuidEx (
  759. CPUID_CACHE_PARAMS, CacheLevel,
  760. &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32
  761. );
  762. CacheLevel++;
  763. } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
  764. @endcode
  765. **/
  766. #define CPUID_CACHE_PARAMS 0x04
  767. /**
  768. CPUID Cache Parameters Information returned in EAX for CPUID leaf
  769. #CPUID_CACHE_PARAMS.
  770. **/
  771. typedef union {
  772. ///
  773. /// Individual bit fields
  774. ///
  775. struct {
  776. ///
  777. /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,
  778. /// then there is no information for the requested cache level.
  779. ///
  780. UINT32 CacheType:5;
  781. ///
  782. /// [Bits 7:5] Cache level (Starts at 1).
  783. ///
  784. UINT32 CacheLevel:3;
  785. ///
  786. /// [Bit 8] Self Initializing cache level (does not need SW initialization).
  787. ///
  788. UINT32 SelfInitializingCache:1;
  789. ///
  790. /// [Bit 9] Fully Associative cache.
  791. ///
  792. UINT32 FullyAssociativeCache:1;
  793. ///
  794. /// [Bits 13:10] Reserved.
  795. ///
  796. UINT32 Reserved:4;
  797. ///
  798. /// [Bits 25:14] Maximum number of addressable IDs for logical processors
  799. /// sharing this cache.
  800. ///
  801. /// Add one to the return value to get the result.
  802. /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14])
  803. /// is the number of unique initial APIC IDs reserved for addressing
  804. /// different logical processors sharing this cache.
  805. ///
  806. UINT32 MaximumAddressableIdsForLogicalProcessors:12;
  807. ///
  808. /// [Bits 31:26] Maximum number of addressable IDs for processor cores in
  809. /// the physical package.
  810. ///
  811. /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26])
  812. /// is the number of unique Core_IDs reserved for addressing different
  813. /// processor cores in a physical package. Core ID is a subset of bits of
  814. /// the initial APIC ID.
  815. /// The returned value is constant for valid initial values in ECX. Valid
  816. /// ECX values start from 0.
  817. ///
  818. UINT32 MaximumAddressableIdsForProcessorCores:6;
  819. } Bits;
  820. ///
  821. /// All bit fields as a 32-bit value
  822. ///
  823. UINT32 Uint32;
  824. } CPUID_CACHE_PARAMS_EAX;
  825. ///
  826. /// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType
  827. ///
  828. #define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00
  829. #define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01
  830. #define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02
  831. #define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03
  832. ///
  833. /// @}
  834. ///
  835. /**
  836. CPUID Cache Parameters Information returned in EBX for CPUID leaf
  837. #CPUID_CACHE_PARAMS.
  838. **/
  839. typedef union {
  840. ///
  841. /// Individual bit fields
  842. ///
  843. struct {
  844. ///
  845. /// [Bits 11:0] System Coherency Line Size. Add one to the return value to
  846. /// get the result.
  847. ///
  848. UINT32 LineSize:12;
  849. ///
  850. /// [Bits 21:12] Physical Line Partitions. Add one to the return value to
  851. /// get the result.
  852. ///
  853. UINT32 LinePartitions:10;
  854. ///
  855. /// [Bits 31:22] Ways of associativity. Add one to the return value to get
  856. /// the result.
  857. ///
  858. UINT32 Ways:10;
  859. } Bits;
  860. ///
  861. /// All bit fields as a 32-bit value
  862. ///
  863. UINT32 Uint32;
  864. } CPUID_CACHE_PARAMS_EBX;
  865. /**
  866. CPUID Cache Parameters Information returned in EDX for CPUID leaf
  867. #CPUID_CACHE_PARAMS.
  868. **/
  869. typedef union {
  870. ///
  871. /// Individual bit fields
  872. ///
  873. struct {
  874. ///
  875. /// [Bit 0] Write-Back Invalidate/Invalidate.
  876. /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level
  877. /// caches for threads sharing this cache.
  878. /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of
  879. /// non-originating threads sharing this cache.
  880. ///
  881. UINT32 Invalidate:1;
  882. ///
  883. /// [Bit 1] Cache Inclusiveness.
  884. /// 0 = Cache is not inclusive of lower cache levels.
  885. /// 1 = Cache is inclusive of lower cache levels.
  886. ///
  887. UINT32 CacheInclusiveness:1;
  888. ///
  889. /// [Bit 2] Complex Cache Indexing.
  890. /// 0 = Direct mapped cache.
  891. /// 1 = A complex function is used to index the cache, potentially using all
  892. /// address bits.
  893. ///
  894. UINT32 ComplexCacheIndexing:1;
  895. UINT32 Reserved:29;
  896. } Bits;
  897. ///
  898. /// All bit fields as a 32-bit value
  899. ///
  900. UINT32 Uint32;
  901. } CPUID_CACHE_PARAMS_EDX;
  902. /**
  903. CPUID MONITOR/MWAIT Information
  904. @param EAX CPUID_MONITOR_MWAIT (0x05)
  905. @retval EAX Smallest monitor-line size in bytes described by the type
  906. CPUID_MONITOR_MWAIT_EAX.
  907. @retval EBX Largest monitor-line size in bytes described by the type
  908. CPUID_MONITOR_MWAIT_EBX.
  909. @retval ECX Enumeration of Monitor-Mwait extensions support described by
  910. the type CPUID_MONITOR_MWAIT_ECX.
  911. @retval EDX Sub C-states supported described by the type
  912. CPUID_MONITOR_MWAIT_EDX.
  913. <b>Example usage</b>
  914. @code
  915. CPUID_MONITOR_MWAIT_EAX Eax;
  916. CPUID_MONITOR_MWAIT_EBX Ebx;
  917. CPUID_MONITOR_MWAIT_ECX Ecx;
  918. CPUID_MONITOR_MWAIT_EDX Edx;
  919. AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
  920. @endcode
  921. **/
  922. #define CPUID_MONITOR_MWAIT 0x05
  923. /**
  924. CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf
  925. #CPUID_MONITOR_MWAIT.
  926. **/
  927. typedef union {
  928. ///
  929. /// Individual bit fields
  930. ///
  931. struct {
  932. ///
  933. /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's
  934. /// monitor granularity).
  935. ///
  936. UINT32 SmallestMonitorLineSize:16;
  937. UINT32 Reserved:16;
  938. } Bits;
  939. ///
  940. /// All bit fields as a 32-bit value
  941. ///
  942. UINT32 Uint32;
  943. } CPUID_MONITOR_MWAIT_EAX;
  944. /**
  945. CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf
  946. #CPUID_MONITOR_MWAIT.
  947. **/
  948. typedef union {
  949. ///
  950. /// Individual bit fields
  951. ///
  952. struct {
  953. ///
  954. /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's
  955. /// monitor granularity).
  956. ///
  957. UINT32 LargestMonitorLineSize:16;
  958. UINT32 Reserved:16;
  959. } Bits;
  960. ///
  961. /// All bit fields as a 32-bit value
  962. ///
  963. UINT32 Uint32;
  964. } CPUID_MONITOR_MWAIT_EBX;
  965. /**
  966. CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf
  967. #CPUID_MONITOR_MWAIT.
  968. **/
  969. typedef union {
  970. ///
  971. /// Individual bit fields
  972. ///
  973. struct {
  974. ///
  975. /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,
  976. /// and EDX are valid.
  977. ///
  978. UINT32 ExtensionsSupported:1;
  979. ///
  980. /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when
  981. /// interrupts disabled.
  982. ///
  983. UINT32 InterruptAsBreak:1;
  984. UINT32 Reserved:30;
  985. } Bits;
  986. ///
  987. /// All bit fields as a 32-bit value
  988. ///
  989. UINT32 Uint32;
  990. } CPUID_MONITOR_MWAIT_ECX;
  991. /**
  992. CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf
  993. #CPUID_MONITOR_MWAIT.
  994. @note
  995. The definition of C0 through C7 states for MWAIT extension are
  996. processor-specific C-states, not ACPI C-states.
  997. **/
  998. typedef union {
  999. ///
  1000. /// Individual bit fields
  1001. ///
  1002. struct {
  1003. ///
  1004. /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.
  1005. ///
  1006. UINT32 C0States:4;
  1007. ///
  1008. /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.
  1009. ///
  1010. UINT32 C1States:4;
  1011. ///
  1012. /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.
  1013. ///
  1014. UINT32 C2States:4;
  1015. ///
  1016. /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.
  1017. ///
  1018. UINT32 C3States:4;
  1019. ///
  1020. /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.
  1021. ///
  1022. UINT32 C4States:4;
  1023. ///
  1024. /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.
  1025. ///
  1026. UINT32 C5States:4;
  1027. ///
  1028. /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.
  1029. ///
  1030. UINT32 C6States:4;
  1031. ///
  1032. /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.
  1033. ///
  1034. UINT32 C7States:4;
  1035. } Bits;
  1036. ///
  1037. /// All bit fields as a 32-bit value
  1038. ///
  1039. UINT32 Uint32;
  1040. } CPUID_MONITOR_MWAIT_EDX;
  1041. /**
  1042. CPUID Thermal and Power Management
  1043. @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06)
  1044. @retval EAX Thermal and power management features described by the type
  1045. CPUID_THERMAL_POWER_MANAGEMENT_EAX.
  1046. @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor
  1047. described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX.
  1048. @retval ECX Performance features described by the type
  1049. CPUID_THERMAL_POWER_MANAGEMENT_ECX.
  1050. @retval EDX Reserved.
  1051. <b>Example usage</b>
  1052. @code
  1053. CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;
  1054. CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;
  1055. CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;
  1056. AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
  1057. @endcode
  1058. **/
  1059. #define CPUID_THERMAL_POWER_MANAGEMENT 0x06
  1060. /**
  1061. CPUID Thermal and Power Management Information returned in EAX for CPUID leaf
  1062. #CPUID_THERMAL_POWER_MANAGEMENT.
  1063. **/
  1064. typedef union {
  1065. ///
  1066. /// Individual bit fields
  1067. ///
  1068. struct {
  1069. ///
  1070. /// [Bit 0] Digital temperature sensor is supported if set.
  1071. ///
  1072. UINT32 DigitalTemperatureSensor:1;
  1073. ///
  1074. /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).
  1075. ///
  1076. UINT32 TurboBoostTechnology:1;
  1077. ///
  1078. /// [Bit 2] APIC-Timer-always-running feature is supported if set.
  1079. ///
  1080. UINT32 ARAT:1;
  1081. UINT32 Reserved1:1;
  1082. ///
  1083. /// [Bit 4] Power limit notification controls are supported if set.
  1084. ///
  1085. UINT32 PLN:1;
  1086. ///
  1087. /// [Bit 5] Clock modulation duty cycle extension is supported if set.
  1088. ///
  1089. UINT32 ECMD:1;
  1090. ///
  1091. /// [Bit 6] Package thermal management is supported if set.
  1092. ///
  1093. UINT32 PTM:1;
  1094. ///
  1095. /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,
  1096. /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
  1097. ///
  1098. UINT32 HWP:1;
  1099. ///
  1100. /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.
  1101. ///
  1102. UINT32 HWP_Notification:1;
  1103. ///
  1104. /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.
  1105. ///
  1106. UINT32 HWP_Activity_Window:1;
  1107. ///
  1108. /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.
  1109. ///
  1110. UINT32 HWP_Energy_Performance_Preference:1;
  1111. ///
  1112. /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.
  1113. ///
  1114. UINT32 HWP_Package_Level_Request:1;
  1115. UINT32 Reserved2:1;
  1116. ///
  1117. /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,
  1118. /// IA32_THREAD_STALL MSRs are supported if set.
  1119. ///
  1120. UINT32 HDC:1;
  1121. ///
  1122. /// [Bit 14] Intel Turbo Boost Max Technology 3.0 available.
  1123. ///
  1124. UINT32 TurboBoostMaxTechnology30:1;
  1125. ///
  1126. /// [Bit 15] HWP Capabilities.
  1127. /// Highest Performance change is supported if set.
  1128. ///
  1129. UINT32 HWPCapabilities:1;
  1130. ///
  1131. /// [Bit 16] HWP PECI override is supported if set.
  1132. ///
  1133. UINT32 HWPPECIOverride:1;
  1134. ///
  1135. /// [Bit 17] Flexible HWP is supported if set.
  1136. ///
  1137. UINT32 FlexibleHWP:1;
  1138. ///
  1139. /// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.
  1140. ///
  1141. UINT32 FastAccessMode:1;
  1142. UINT32 Reserved4:1;
  1143. ///
  1144. /// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if set.
  1145. ///
  1146. UINT32 IgnoringIdleLogicalProcessorHWPRequest:1;
  1147. UINT32 Reserved5:11;
  1148. } Bits;
  1149. ///
  1150. /// All bit fields as a 32-bit value
  1151. ///
  1152. UINT32 Uint32;
  1153. } CPUID_THERMAL_POWER_MANAGEMENT_EAX;
  1154. /**
  1155. CPUID Thermal and Power Management Information returned in EBX for CPUID leaf
  1156. #CPUID_THERMAL_POWER_MANAGEMENT.
  1157. **/
  1158. typedef union {
  1159. ///
  1160. /// Individual bit fields
  1161. ///
  1162. struct {
  1163. ///
  1164. /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.
  1165. ///
  1166. UINT32 InterruptThresholds:4;
  1167. UINT32 Reserved:28;
  1168. } Bits;
  1169. ///
  1170. /// All bit fields as a 32-bit value
  1171. ///
  1172. UINT32 Uint32;
  1173. } CPUID_THERMAL_POWER_MANAGEMENT_EBX;
  1174. /**
  1175. CPUID Thermal and Power Management Information returned in ECX for CPUID leaf
  1176. #CPUID_THERMAL_POWER_MANAGEMENT.
  1177. **/
  1178. typedef union {
  1179. ///
  1180. /// Individual bit fields
  1181. ///
  1182. struct {
  1183. ///
  1184. /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF
  1185. /// and IA32_APERF). The capability to provide a measure of delivered
  1186. /// processor performance (since last reset of the counters), as a percentage
  1187. /// of the expected processor performance when running at the TSC frequency.
  1188. ///
  1189. UINT32 HardwareCoordinationFeedback:1;
  1190. UINT32 Reserved1:2;
  1191. ///
  1192. /// [Bit 3] If this bit is set, then the processor supports performance-energy
  1193. /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS
  1194. /// (1B0H).
  1195. ///
  1196. UINT32 PerformanceEnergyBias:1;
  1197. UINT32 Reserved2:28;
  1198. } Bits;
  1199. ///
  1200. /// All bit fields as a 32-bit value
  1201. ///
  1202. UINT32 Uint32;
  1203. } CPUID_THERMAL_POWER_MANAGEMENT_ECX;
  1204. /**
  1205. CPUID Structured Extended Feature Flags Enumeration
  1206. @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)
  1207. @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00).
  1208. @note
  1209. If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
  1210. index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.
  1211. @retval EAX The maximum input value for ECX to retrieve sub-leaf information.
  1212. @retval EBX Structured Extended Feature Flags described by the type
  1213. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.
  1214. @retval EBX Structured Extended Feature Flags described by the type
  1215. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.
  1216. @retval EDX Reserved.
  1217. <b>Example usage</b>
  1218. @code
  1219. UINT32 Eax;
  1220. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
  1221. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;
  1222. UINT32 SubLeaf;
  1223. AsmCpuidEx (
  1224. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
  1225. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
  1226. &Eax, NULL, NULL, NULL
  1227. );
  1228. for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {
  1229. AsmCpuidEx (
  1230. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
  1231. SubLeaf,
  1232. NULL, &Ebx.Uint32, &Ecx.Uint32, NULL
  1233. );
  1234. }
  1235. @endcode
  1236. **/
  1237. #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07
  1238. ///
  1239. /// CPUID Structured Extended Feature Flags Enumeration sub-leaf
  1240. ///
  1241. #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00
  1242. /**
  1243. CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf
  1244. #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
  1245. #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
  1246. **/
  1247. typedef union {
  1248. ///
  1249. /// Individual bit fields
  1250. ///
  1251. struct {
  1252. ///
  1253. /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
  1254. ///
  1255. UINT32 FSGSBASE:1;
  1256. ///
  1257. /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.
  1258. ///
  1259. UINT32 IA32_TSC_ADJUST:1;
  1260. ///
  1261. /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT
  1262. /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".
  1263. ///
  1264. UINT32 SGX:1;
  1265. ///
  1266. /// [Bit 3] If 1 indicates the processor supports the first group of advanced
  1267. /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)
  1268. ///
  1269. UINT32 BMI1:1;
  1270. ///
  1271. /// [Bit 4] Hardware Lock Elision
  1272. ///
  1273. UINT32 HLE:1;
  1274. ///
  1275. /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.
  1276. ///
  1277. UINT32 AVX2:1;
  1278. ///
  1279. /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.
  1280. ///
  1281. UINT32 FDP_EXCPTN_ONLY:1;
  1282. ///
  1283. /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.
  1284. ///
  1285. UINT32 SMEP:1;
  1286. ///
  1287. /// [Bit 8] If 1 indicates the processor supports the second group of
  1288. /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,
  1289. /// SARX, SHLX, SHRX)
  1290. ///
  1291. UINT32 BMI2:1;
  1292. ///
  1293. /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.
  1294. ///
  1295. UINT32 EnhancedRepMovsbStosb:1;
  1296. ///
  1297. /// [Bit 10] If 1, supports INVPCID instruction for system software that
  1298. /// manages process-context identifiers.
  1299. ///
  1300. UINT32 INVPCID:1;
  1301. ///
  1302. /// [Bit 11] Restricted Transactional Memory
  1303. ///
  1304. UINT32 RTM:1;
  1305. ///
  1306. /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
  1307. /// Monitoring capability if 1.
  1308. ///
  1309. UINT32 RDT_M:1;
  1310. ///
  1311. /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.
  1312. ///
  1313. UINT32 DeprecateFpuCsDs:1;
  1314. ///
  1315. /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.
  1316. ///
  1317. UINT32 MPX:1;
  1318. ///
  1319. /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
  1320. /// Allocation capability if 1.
  1321. ///
  1322. UINT32 RDT_A:1;
  1323. ///
  1324. /// [Bit 16] AVX512F.
  1325. ///
  1326. UINT32 AVX512F:1;
  1327. ///
  1328. /// [Bit 17] AVX512DQ.
  1329. ///
  1330. UINT32 AVX512DQ:1;
  1331. ///
  1332. /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.
  1333. ///
  1334. UINT32 RDSEED:1;
  1335. ///
  1336. /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX
  1337. /// instructions.
  1338. ///
  1339. UINT32 ADX:1;
  1340. ///
  1341. /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC
  1342. /// instructions) if 1.
  1343. ///
  1344. UINT32 SMAP:1;
  1345. ///
  1346. /// [Bit 21] AVX512_IFMA.
  1347. ///
  1348. UINT32 AVX512_IFMA:1;
  1349. UINT32 Reserved6:1;
  1350. ///
  1351. /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.
  1352. ///
  1353. UINT32 CLFLUSHOPT:1;
  1354. ///
  1355. /// [Bit 24] If 1 indicates the processor supports the CLWB instruction.
  1356. ///
  1357. UINT32 CLWB:1;
  1358. ///
  1359. /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace
  1360. /// extensions.
  1361. ///
  1362. UINT32 IntelProcessorTrace:1;
  1363. ///
  1364. /// [Bit 26] AVX512PF. (Intel Xeon Phi only.).
  1365. ///
  1366. UINT32 AVX512PF:1;
  1367. ///
  1368. /// [Bit 27] AVX512ER. (Intel Xeon Phi only.).
  1369. ///
  1370. UINT32 AVX512ER:1;
  1371. ///
  1372. /// [Bit 28] AVX512CD.
  1373. ///
  1374. UINT32 AVX512CD:1;
  1375. ///
  1376. /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R)
  1377. /// SHA Extensions) if 1.
  1378. ///
  1379. UINT32 SHA:1;
  1380. ///
  1381. /// [Bit 30] AVX512BW.
  1382. ///
  1383. UINT32 AVX512BW:1;
  1384. ///
  1385. /// [Bit 31] AVX512VL.
  1386. ///
  1387. UINT32 AVX512VL:1;
  1388. } Bits;
  1389. ///
  1390. /// All bit fields as a 32-bit value
  1391. ///
  1392. UINT32 Uint32;
  1393. } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX;
  1394. /**
  1395. CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf
  1396. #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
  1397. #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
  1398. **/
  1399. typedef union {
  1400. ///
  1401. /// Individual bit fields
  1402. ///
  1403. struct {
  1404. ///
  1405. /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.
  1406. /// (Intel Xeon Phi only.)
  1407. ///
  1408. UINT32 PREFETCHWT1:1;
  1409. ///
  1410. /// [Bit 1] AVX512_VBMI.
  1411. ///
  1412. UINT32 AVX512_VBMI:1;
  1413. ///
  1414. /// [Bit 2] Supports user-mode instruction prevention if 1.
  1415. ///
  1416. UINT32 UMIP:1;
  1417. ///
  1418. /// [Bit 3] Supports protection keys for user-mode pages if 1.
  1419. ///
  1420. UINT32 PKU:1;
  1421. ///
  1422. /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the
  1423. /// RDPKRU/WRPKRU instructions).
  1424. ///
  1425. UINT32 OSPKE:1;
  1426. UINT32 Reserved5:9;
  1427. ///
  1428. /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).
  1429. ///
  1430. UINT32 AVX512_VPOPCNTDQ:1;
  1431. UINT32 Reserved7:1;
  1432. ///
  1433. /// [Bits 16] Supports 5-level paging if 1.
  1434. ///
  1435. UINT32 FiveLevelPage:1;
  1436. ///
  1437. /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions
  1438. /// in 64-bit mode.
  1439. ///
  1440. UINT32 MAWAU:5;
  1441. ///
  1442. /// [Bit 22] RDPID and IA32_TSC_AUX are available if 1.
  1443. ///
  1444. UINT32 RDPID:1;
  1445. UINT32 Reserved3:7;
  1446. ///
  1447. /// [Bit 30] Supports SGX Launch Configuration if 1.
  1448. ///
  1449. UINT32 SGX_LC:1;
  1450. UINT32 Reserved4:1;
  1451. } Bits;
  1452. ///
  1453. /// All bit fields as a 32-bit value
  1454. ///
  1455. UINT32 Uint32;
  1456. } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX;
  1457. /**
  1458. CPUID Structured Extended Feature Flags Enumeration in EDX for CPUID leaf
  1459. #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
  1460. #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
  1461. **/
  1462. typedef union {
  1463. ///
  1464. /// Individual bit fields
  1465. ///
  1466. struct {
  1467. ///
  1468. /// [Bit 1:0] Reserved.
  1469. ///
  1470. UINT32 Reserved1:2;
  1471. ///
  1472. /// [Bit 2] AVX512_4VNNIW. (Intel Xeon Phi only.)
  1473. ///
  1474. UINT32 AVX512_4VNNIW:1;
  1475. ///
  1476. /// [Bit 3] AVX512_4FMAPS. (Intel Xeon Phi only.)
  1477. ///
  1478. UINT32 AVX512_4FMAPS:1;
  1479. ///
  1480. /// [Bit 25:4] Reserved.
  1481. ///
  1482. UINT32 Reserved2:22;
  1483. ///
  1484. /// [Bit 26] Enumerates support for indirect branch restricted speculation
  1485. /// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors
  1486. /// that set this bit support the IA32_SPEC_CTRL MSR and the IA32_PRED_CMD
  1487. /// MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and
  1488. /// IA32_PRED_CMD[0] (IBPB).
  1489. ///
  1490. UINT32 EnumeratesSupportForIBRSAndIBPB:1;
  1491. ///
  1492. /// [Bit 27] Enumerates support for single thread indirect branch
  1493. /// predictors (STIBP). Processors that set this bit support the
  1494. /// IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1]
  1495. /// (STIBP).
  1496. ///
  1497. UINT32 EnumeratesSupportForSTIBP:1;
  1498. ///
  1499. /// [Bit 28] Enumerates support for L1D_FLUSH. Processors that set this bit
  1500. /// support the IA32_FLUSH_CMD MSR. They allow software to set
  1501. /// IA32_FLUSH_CMD[0] (L1D_FLUSH).
  1502. ///
  1503. UINT32 EnumeratesSupportForL1D_FLUSH:1;
  1504. ///
  1505. /// [Bit 29] Enumerates support for the IA32_ARCH_CAPABILITIES MSR.
  1506. ///
  1507. UINT32 EnumeratesSupportForCapability:1;
  1508. ///
  1509. /// [Bit 30] Reserved.
  1510. ///
  1511. UINT32 Reserved3:1;
  1512. ///
  1513. /// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD).
  1514. /// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow
  1515. /// software to set IA32_SPEC_CTRL[2] (SSBD).
  1516. ///
  1517. UINT32 EnumeratesSupportForSSBD:1;
  1518. } Bits;
  1519. ///
  1520. /// All bit fields as a 32-bit value
  1521. ///
  1522. UINT32 Uint32;
  1523. } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX;
  1524. /**
  1525. CPUID Direct Cache Access Information
  1526. @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09)
  1527. @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).
  1528. @retval EBX Reserved.
  1529. @retval ECX Reserved.
  1530. @retval EDX Reserved.
  1531. <b>Example usage</b>
  1532. @code
  1533. UINT32 Eax;
  1534. AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);
  1535. @endcode
  1536. **/
  1537. #define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09
  1538. /**
  1539. CPUID Architectural Performance Monitoring
  1540. @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)
  1541. @retval EAX Architectural Performance Monitoring information described by
  1542. the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.
  1543. @retval EBX Architectural Performance Monitoring information described by
  1544. the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.
  1545. @retval ECX Reserved.
  1546. @retval EDX Architectural Performance Monitoring information described by
  1547. the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.
  1548. <b>Example usage</b>
  1549. @code
  1550. CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;
  1551. CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;
  1552. CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;
  1553. AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);
  1554. @endcode
  1555. **/
  1556. #define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A
  1557. /**
  1558. CPUID Architectural Performance Monitoring EAX for CPUID leaf
  1559. #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
  1560. **/
  1561. typedef union {
  1562. ///
  1563. /// Individual bit fields
  1564. ///
  1565. struct {
  1566. ///
  1567. /// [Bit 7:0] Version ID of architectural performance monitoring.
  1568. ///
  1569. UINT32 ArchPerfMonVerID:8;
  1570. ///
  1571. /// [Bits 15:8] Number of general-purpose performance monitoring counter
  1572. /// per logical processor.
  1573. ///
  1574. /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous
  1575. /// block of MSR address space. Each performance event select register is
  1576. /// paired with a corresponding performance counter in the 0C1H address
  1577. /// block.
  1578. ///
  1579. UINT32 PerformanceMonitorCounters:8;
  1580. ///
  1581. /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.
  1582. ///
  1583. /// The bit width of an IA32_PMCx MSR. This the number of valid bits for
  1584. /// read operation. On write operations, the lower-order 32 bits of the MSR
  1585. /// may be written with any value, and the high-order bits are sign-extended
  1586. /// from the value of bit 31.
  1587. ///
  1588. UINT32 PerformanceMonitorCounterWidth:8;
  1589. ///
  1590. /// [Bits 31:24] Length of EBX bit vector to enumerate architectural
  1591. /// performance monitoring events.
  1592. ///
  1593. UINT32 EbxBitVectorLength:8;
  1594. } Bits;
  1595. ///
  1596. /// All bit fields as a 32-bit value
  1597. ///
  1598. UINT32 Uint32;
  1599. } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX;
  1600. /**
  1601. CPUID Architectural Performance Monitoring EBX for CPUID leaf
  1602. #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
  1603. **/
  1604. typedef union {
  1605. ///
  1606. /// Individual bit fields
  1607. ///
  1608. struct {
  1609. ///
  1610. /// [Bit 0] Core cycle event not available if 1.
  1611. ///
  1612. UINT32 UnhaltedCoreCycles:1;
  1613. ///
  1614. /// [Bit 1] Instruction retired event not available if 1.
  1615. ///
  1616. UINT32 InstructionsRetired:1;
  1617. ///
  1618. /// [Bit 2] Reference cycles event not available if 1.
  1619. ///
  1620. UINT32 UnhaltedReferenceCycles:1;
  1621. ///
  1622. /// [Bit 3] Last-level cache reference event not available if 1.
  1623. ///
  1624. UINT32 LastLevelCacheReferences:1;
  1625. ///
  1626. /// [Bit 4] Last-level cache misses event not available if 1.
  1627. ///
  1628. UINT32 LastLevelCacheMisses:1;
  1629. ///
  1630. /// [Bit 5] Branch instruction retired event not available if 1.
  1631. ///
  1632. UINT32 BranchInstructionsRetired:1;
  1633. ///
  1634. /// [Bit 6] Branch mispredict retired event not available if 1.
  1635. ///
  1636. UINT32 AllBranchMispredictRetired:1;
  1637. UINT32 Reserved:25;
  1638. } Bits;
  1639. ///
  1640. /// All bit fields as a 32-bit value
  1641. ///
  1642. UINT32 Uint32;
  1643. } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX;
  1644. /**
  1645. CPUID Architectural Performance Monitoring EDX for CPUID leaf
  1646. #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
  1647. **/
  1648. typedef union {
  1649. ///
  1650. /// Individual bit fields
  1651. ///
  1652. struct {
  1653. ///
  1654. /// [Bits 4:0] Number of fixed-function performance counters
  1655. /// (if Version ID > 1).
  1656. ///
  1657. UINT32 FixedFunctionPerformanceCounters:5;
  1658. ///
  1659. /// [Bits 12:5] Bit width of fixed-function performance counters
  1660. /// (if Version ID > 1).
  1661. ///
  1662. UINT32 FixedFunctionPerformanceCounterWidth:8;
  1663. UINT32 Reserved1:2;
  1664. ///
  1665. /// [Bits 15] AnyThread deprecation.
  1666. ///
  1667. UINT32 AnyThreadDeprecation:1;
  1668. UINT32 Reserved2:16;
  1669. } Bits;
  1670. ///
  1671. /// All bit fields as a 32-bit value
  1672. ///
  1673. UINT32 Uint32;
  1674. } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX;
  1675. /**
  1676. CPUID Extended Topology Information
  1677. @note
  1678. CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first
  1679. checking for the existence of Leaf 1FH before using leaf 0BH.
  1680. Most of Leaf 0BH output depends on the initial value in ECX. The EDX output
  1681. of leaf 0BH is always valid and does not vary with input value in ECX. Output
  1682. value in ECX[7:0] always equals input value in ECX[7:0].
  1683. Sub-leaf index 0 enumerates SMT level. Each subsequent higher sub-leaf index
  1684. enumerates a higher-level topological entity in hierarchical order.
  1685. For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and
  1686. EBX will return 0.
  1687. If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],
  1688. other input values with ECX > n also return 0 in ECX[15:8].
  1689. @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B)
  1690. @param ECX Level number
  1691. @retval EAX Extended topology information described by the type
  1692. CPUID_EXTENDED_TOPOLOGY_EAX.
  1693. @retval EBX Extended topology information described by the type
  1694. CPUID_EXTENDED_TOPOLOGY_EBX.
  1695. @retval ECX Extended topology information described by the type
  1696. CPUID_EXTENDED_TOPOLOGY_ECX.
  1697. @retval EDX x2APIC ID the current logical processor.
  1698. <b>Example usage</b>
  1699. @code
  1700. CPUID_EXTENDED_TOPOLOGY_EAX Eax;
  1701. CPUID_EXTENDED_TOPOLOGY_EBX Ebx;
  1702. CPUID_EXTENDED_TOPOLOGY_ECX Ecx;
  1703. UINT32 Edx;
  1704. UINT32 LevelNumber;
  1705. LevelNumber = 0;
  1706. do {
  1707. AsmCpuidEx (
  1708. CPUID_EXTENDED_TOPOLOGY, LevelNumber,
  1709. &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx
  1710. );
  1711. LevelNumber++;
  1712. } while (Eax.Bits.ApicIdShift != 0);
  1713. @endcode
  1714. **/
  1715. #define CPUID_EXTENDED_TOPOLOGY 0x0B
  1716. /**
  1717. CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
  1718. **/
  1719. typedef union {
  1720. ///
  1721. /// Individual bit fields
  1722. ///
  1723. struct {
  1724. ///
  1725. /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique
  1726. /// topology ID of the next level type. All logical processors with the
  1727. /// same next level ID share current level.
  1728. ///
  1729. /// @note
  1730. /// Software should use this field (EAX[4:0]) to enumerate processor
  1731. /// topology of the system.
  1732. ///
  1733. UINT32 ApicIdShift:5;
  1734. UINT32 Reserved:27;
  1735. } Bits;
  1736. ///
  1737. /// All bit fields as a 32-bit value
  1738. ///
  1739. UINT32 Uint32;
  1740. } CPUID_EXTENDED_TOPOLOGY_EAX;
  1741. /**
  1742. CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
  1743. **/
  1744. typedef union {
  1745. ///
  1746. /// Individual bit fields
  1747. ///
  1748. struct {
  1749. ///
  1750. /// [Bits 15:0] Number of logical processors at this level type. The number
  1751. /// reflects configuration as shipped by Intel.
  1752. ///
  1753. /// @note
  1754. /// Software must not use EBX[15:0] to enumerate processor topology of the
  1755. /// system. This value in this field (EBX[15:0]) is only intended for
  1756. /// display/diagnostic purposes. The actual number of logical processors
  1757. /// available to BIOS/OS/Applications may be different from the value of
  1758. /// EBX[15:0], depending on software and platform hardware configurations.
  1759. ///
  1760. UINT32 LogicalProcessors:16;
  1761. UINT32 Reserved:16;
  1762. } Bits;
  1763. ///
  1764. /// All bit fields as a 32-bit value
  1765. ///
  1766. UINT32 Uint32;
  1767. } CPUID_EXTENDED_TOPOLOGY_EBX;
  1768. /**
  1769. CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
  1770. **/
  1771. typedef union {
  1772. ///
  1773. /// Individual bit fields
  1774. ///
  1775. struct {
  1776. ///
  1777. /// [Bits 7:0] Level number. Same value in ECX input.
  1778. ///
  1779. UINT32 LevelNumber:8;
  1780. ///
  1781. /// [Bits 15:8] Level type.
  1782. ///
  1783. /// @note
  1784. /// The value of the "level type" field is not related to level numbers in
  1785. /// any way, higher "level type" values do not mean higher levels.
  1786. ///
  1787. UINT32 LevelType:8;
  1788. UINT32 Reserved:16;
  1789. } Bits;
  1790. ///
  1791. /// All bit fields as a 32-bit value
  1792. ///
  1793. UINT32 Uint32;
  1794. } CPUID_EXTENDED_TOPOLOGY_ECX;
  1795. ///
  1796. /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
  1797. ///
  1798. #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00
  1799. #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01
  1800. #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02
  1801. ///
  1802. /// @}
  1803. ///
  1804. /**
  1805. CPUID Extended State Information
  1806. @param EAX CPUID_EXTENDED_STATE (0x0D)
  1807. @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00).
  1808. CPUID_EXTENDED_STATE_SUB_LEAF (0x01).
  1809. CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).
  1810. Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.
  1811. **/
  1812. #define CPUID_EXTENDED_STATE 0x0D
  1813. /**
  1814. CPUID Extended State Information Main Leaf
  1815. @param EAX CPUID_EXTENDED_STATE (0x0D)
  1816. @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)
  1817. @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n]
  1818. can be set to 1 only if EAX[n] is 1. The format of the extended
  1819. state main leaf is described by the type
  1820. CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.
  1821. @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
  1822. area) required by enabled features in XCR0. May be different than
  1823. ECX if some features at the end of the XSAVE save area are not
  1824. enabled.
  1825. @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
  1826. area) of the XSAVE/XRSTOR save area required by all supported
  1827. features in the processor, i.e., all the valid bit fields in XCR0.
  1828. @retval EDX Reports the supported bits of the upper 32 bits of XCR0.
  1829. XCR0[n+32] can be set to 1 only if EDX[n] is 1.
  1830. <b>Example usage</b>
  1831. @code
  1832. CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;
  1833. UINT32 Ebx;
  1834. UINT32 Ecx;
  1835. UINT32 Edx;
  1836. AsmCpuidEx (
  1837. CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,
  1838. &Eax.Uint32, &Ebx, &Ecx, &Edx
  1839. );
  1840. @endcode
  1841. **/
  1842. #define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00
  1843. /**
  1844. CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
  1845. sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.
  1846. **/
  1847. typedef union {
  1848. ///
  1849. /// Individual bit fields
  1850. ///
  1851. struct {
  1852. ///
  1853. /// [Bit 0] x87 state.
  1854. ///
  1855. UINT32 x87:1;
  1856. ///
  1857. /// [Bit 1] SSE state.
  1858. ///
  1859. UINT32 SSE:1;
  1860. ///
  1861. /// [Bit 2] AVX state.
  1862. ///
  1863. UINT32 AVX:1;
  1864. ///
  1865. /// [Bits 4:3] MPX state.
  1866. ///
  1867. UINT32 MPX:2;
  1868. ///
  1869. /// [Bits 7:5] AVX-512 state.
  1870. ///
  1871. UINT32 AVX_512:3;
  1872. ///
  1873. /// [Bit 8] Used for IA32_XSS.
  1874. ///
  1875. UINT32 IA32_XSS:1;
  1876. ///
  1877. /// [Bit 9] PKRU state.
  1878. ///
  1879. UINT32 PKRU:1;
  1880. UINT32 Reserved1:3;
  1881. ///
  1882. /// [Bit 13] Used for IA32_XSS, part 2.
  1883. ///
  1884. UINT32 IA32_XSS_2:1;
  1885. UINT32 Reserved2:18;
  1886. } Bits;
  1887. ///
  1888. /// All bit fields as a 32-bit value
  1889. ///
  1890. UINT32 Uint32;
  1891. } CPUID_EXTENDED_STATE_MAIN_LEAF_EAX;
  1892. /**
  1893. CPUID Extended State Information Sub Leaf
  1894. @param EAX CPUID_EXTENDED_STATE (0x0D)
  1895. @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01)
  1896. @retval EAX The format of the extended state sub-leaf is described by the
  1897. type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.
  1898. @retval EBX The size in bytes of the XSAVE area containing all states
  1899. enabled by XCRO | IA32_XSS.
  1900. @retval ECX The format of the extended state sub-leaf is described by the
  1901. type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.
  1902. @retval EDX Reports the supported bits of the upper 32 bits of the
  1903. IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.
  1904. <b>Example usage</b>
  1905. @code
  1906. CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;
  1907. UINT32 Ebx;
  1908. CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;
  1909. UINT32 Edx;
  1910. AsmCpuidEx (
  1911. CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,
  1912. &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx
  1913. );
  1914. @endcode
  1915. **/
  1916. #define CPUID_EXTENDED_STATE_SUB_LEAF 0x01
  1917. /**
  1918. CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
  1919. sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
  1920. **/
  1921. typedef union {
  1922. ///
  1923. /// Individual bit fields
  1924. ///
  1925. struct {
  1926. ///
  1927. /// [Bit 0] XSAVEOPT is available.
  1928. ///
  1929. UINT32 XSAVEOPT:1;
  1930. ///
  1931. /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.
  1932. ///
  1933. UINT32 XSAVEC:1;
  1934. ///
  1935. /// [Bit 2] Supports XGETBV with ECX = 1 if set.
  1936. ///
  1937. UINT32 XGETBV:1;
  1938. ///
  1939. /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.
  1940. ///
  1941. UINT32 XSAVES:1;
  1942. UINT32 Reserved:28;
  1943. } Bits;
  1944. ///
  1945. /// All bit fields as a 32-bit value
  1946. ///
  1947. UINT32 Uint32;
  1948. } CPUID_EXTENDED_STATE_SUB_LEAF_EAX;
  1949. /**
  1950. CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
  1951. sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
  1952. **/
  1953. typedef union {
  1954. ///
  1955. /// Individual bit fields
  1956. ///
  1957. struct {
  1958. ///
  1959. /// [Bits 7:0] Used for XCR0.
  1960. ///
  1961. UINT32 XCR0:1;
  1962. ///
  1963. /// [Bit 8] PT STate.
  1964. ///
  1965. UINT32 PT:1;
  1966. ///
  1967. /// [Bit 9] Used for XCR0.
  1968. ///
  1969. UINT32 XCR0_1:1;
  1970. UINT32 Reserved1:3;
  1971. ///
  1972. /// [Bit 13] HWP state.
  1973. ///
  1974. UINT32 HWPState:1;
  1975. UINT32 Reserved8:18;
  1976. } Bits;
  1977. ///
  1978. /// All bit fields as a 32-bit value
  1979. ///
  1980. UINT32 Uint32;
  1981. } CPUID_EXTENDED_STATE_SUB_LEAF_ECX;
  1982. /**
  1983. CPUID Extended State Information Size and Offset Sub Leaf
  1984. @note
  1985. Leaf 0DH output depends on the initial value in ECX.
  1986. Each sub-leaf index (starting at position 2) is supported if it corresponds to
  1987. a supported bit in either the XCR0 register or the IA32_XSS MSR.
  1988. If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
  1989. n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1
  1990. returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0
  1991. returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].
  1992. @param EAX CPUID_EXTENDED_STATE (0x0D)
  1993. @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based
  1994. on supported bits in XCR0 or IA32_XSS_MSR.
  1995. @retval EAX The size in bytes (from the offset specified in EBX) of the save
  1996. area for an extended state feature associated with a valid
  1997. sub-leaf index, n.
  1998. @retval EBX The offset in bytes of this extended state component's save area
  1999. from the beginning of the XSAVE/XRSTOR area. This field reports
  2000. 0 if the sub-leaf index, n, does not map to a valid bit in the
  2001. XCR0 register.
  2002. @retval ECX The format of the extended state components's save area as
  2003. described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX.
  2004. This field reports 0 if the sub-leaf index, n, is invalid.
  2005. @retval EDX This field reports 0 if the sub-leaf index, n, is invalid;
  2006. otherwise it is reserved.
  2007. <b>Example usage</b>
  2008. @code
  2009. UINT32 Eax;
  2010. UINT32 Ebx;
  2011. CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;
  2012. UINT32 Edx;
  2013. UINTN SubLeaf;
  2014. for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
  2015. AsmCpuidEx (
  2016. CPUID_EXTENDED_STATE, SubLeaf,
  2017. &Eax, &Ebx, &Ecx.Uint32, &Edx
  2018. );
  2019. }
  2020. @endcode
  2021. **/
  2022. #define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02
  2023. /**
  2024. CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
  2025. sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.
  2026. **/
  2027. typedef union {
  2028. ///
  2029. /// Individual bit fields
  2030. ///
  2031. struct {
  2032. ///
  2033. /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is
  2034. /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported
  2035. /// in XCR0.
  2036. ///
  2037. UINT32 XSS:1;
  2038. ///
  2039. /// [Bit 1] is set if, when the compacted format of an XSAVE area is used,
  2040. /// this extended state component located on the next 64-byte boundary
  2041. /// following the preceding state component (otherwise, it is located
  2042. /// immediately following the preceding state component).
  2043. ///
  2044. UINT32 Compacted:1;
  2045. UINT32 Reserved:30;
  2046. } Bits;
  2047. ///
  2048. /// All bit fields as a 32-bit value
  2049. ///
  2050. UINT32 Uint32;
  2051. } CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX;
  2052. /**
  2053. CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
  2054. @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
  2055. @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00).
  2056. CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).
  2057. **/
  2058. #define CPUID_INTEL_RDT_MONITORING 0x0F
  2059. /**
  2060. CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
  2061. Enumeration Sub-leaf
  2062. @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
  2063. @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00)
  2064. @retval EAX Reserved.
  2065. @retval EBX Maximum range (zero-based) of RMID within this physical
  2066. processor of all types.
  2067. @retval ECX Reserved.
  2068. @retval EDX L3 Cache Intel RDT Monitoring Information Enumeration described by
  2069. the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX.
  2070. <b>Example usage</b>
  2071. @code
  2072. UINT32 Ebx;
  2073. CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
  2074. AsmCpuidEx (
  2075. CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,
  2076. NULL, &Ebx, NULL, &Edx.Uint32
  2077. );
  2078. @endcode
  2079. **/
  2080. #define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00
  2081. /**
  2082. CPUID Intel RDT Monitoring Information EDX for CPUID leaf
  2083. #CPUID_INTEL_RDT_MONITORING, sub-leaf
  2084. #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF.
  2085. **/
  2086. typedef union {
  2087. ///
  2088. /// Individual bit fields
  2089. ///
  2090. struct {
  2091. UINT32 Reserved1:1;
  2092. ///
  2093. /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.
  2094. ///
  2095. UINT32 L3CacheRDT_M:1;
  2096. UINT32 Reserved2:30;
  2097. } Bits;
  2098. ///
  2099. /// All bit fields as a 32-bit value
  2100. ///
  2101. UINT32 Uint32;
  2102. } CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX;
  2103. /**
  2104. CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf
  2105. @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
  2106. @param ECX CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01)
  2107. @retval EAX Reserved.
  2108. @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).
  2109. @retval ECX Maximum range (zero-based) of RMID of this resource type.
  2110. @retval EDX L3 Cache Intel RDT Monitoring Capability information described by the
  2111. type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX.
  2112. <b>Example usage</b>
  2113. @code
  2114. UINT32 Ebx;
  2115. UINT32 Ecx;
  2116. CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;
  2117. AsmCpuidEx (
  2118. CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,
  2119. NULL, &Ebx, &Ecx, &Edx.Uint32
  2120. );
  2121. @endcode
  2122. **/
  2123. #define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01
  2124. /**
  2125. CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf
  2126. #CPUID_INTEL_RDT_MONITORING, sub-leaf
  2127. #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF.
  2128. **/
  2129. typedef union {
  2130. ///
  2131. /// Individual bit fields
  2132. ///
  2133. struct {
  2134. ///
  2135. /// [Bit 0] Supports L3 occupancy monitoring if 1.
  2136. ///
  2137. UINT32 L3CacheOccupancyMonitoring:1;
  2138. ///
  2139. /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.
  2140. ///
  2141. UINT32 L3CacheTotalBandwidthMonitoring:1;
  2142. ///
  2143. /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.
  2144. ///
  2145. UINT32 L3CacheLocalBandwidthMonitoring:1;
  2146. UINT32 Reserved:29;
  2147. } Bits;
  2148. ///
  2149. /// All bit fields as a 32-bit value
  2150. ///
  2151. UINT32 Uint32;
  2152. } CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX;
  2153. /**
  2154. CPUID Intel Resource Director Technology (Intel RDT) Allocation Information
  2155. @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10).
  2156. @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).
  2157. CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).
  2158. CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).
  2159. **/
  2160. #define CPUID_INTEL_RDT_ALLOCATION 0x10
  2161. /**
  2162. Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf
  2163. @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
  2164. @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).
  2165. @retval EAX Reserved.
  2166. @retval EBX L3 and L2 Cache Allocation Technology information described by
  2167. the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX.
  2168. @retval ECX Reserved.
  2169. @retval EDX Reserved.
  2170. <b>Example usage</b>
  2171. @code
  2172. CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;
  2173. AsmCpuidEx (
  2174. CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,
  2175. NULL, &Ebx.Uint32, NULL, NULL
  2176. );
  2177. @endcode
  2178. **/
  2179. #define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00
  2180. /**
  2181. CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf
  2182. #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
  2183. #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF.
  2184. **/
  2185. typedef union {
  2186. ///
  2187. /// Individual bit fields
  2188. ///
  2189. struct {
  2190. UINT32 Reserved1:1;
  2191. ///
  2192. /// [Bit 1] Supports L3 Cache Allocation Technology if 1.
  2193. ///
  2194. UINT32 L3CacheAllocation:1;
  2195. ///
  2196. /// [Bit 2] Supports L2 Cache Allocation Technology if 1.
  2197. ///
  2198. UINT32 L2CacheAllocation:1;
  2199. ///
  2200. /// [Bit 3] Supports Memory Bandwidth Allocation if 1.
  2201. ///
  2202. UINT32 MemoryBandwidth:1;
  2203. UINT32 Reserved3:28;
  2204. } Bits;
  2205. ///
  2206. /// All bit fields as a 32-bit value
  2207. ///
  2208. UINT32 Uint32;
  2209. } CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX;
  2210. /**
  2211. L3 Cache Allocation Technology Enumeration Sub-leaf
  2212. @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
  2213. @param ECX CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01)
  2214. @retval EAX RESID L3 Cache Allocation Technology information described by
  2215. the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX.
  2216. @retval EBX Bit-granular map of isolation/contention of allocation units.
  2217. @retval ECX RESID L3 Cache Allocation Technology information described by
  2218. the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX.
  2219. @retval EDX RESID L3 Cache Allocation Technology information described by
  2220. the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX.
  2221. <b>Example usage</b>
  2222. @code
  2223. CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;
  2224. UINT32 Ebx;
  2225. CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;
  2226. CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;
  2227. AsmCpuidEx (
  2228. CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,
  2229. &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32
  2230. );
  2231. @endcode
  2232. **/
  2233. #define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01
  2234. /**
  2235. CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf
  2236. #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
  2237. #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
  2238. **/
  2239. typedef union {
  2240. ///
  2241. /// Individual bit fields
  2242. ///
  2243. struct {
  2244. ///
  2245. /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
  2246. /// using minus-one notation.
  2247. ///
  2248. UINT32 CapacityLength:5;
  2249. UINT32 Reserved:27;
  2250. } Bits;
  2251. ///
  2252. /// All bit fields as a 32-bit value
  2253. ///
  2254. UINT32 Uint32;
  2255. } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX;
  2256. /**
  2257. CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf
  2258. #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
  2259. #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
  2260. **/
  2261. typedef union {
  2262. ///
  2263. /// Individual bit fields
  2264. ///
  2265. struct {
  2266. UINT32 Reserved3:2;
  2267. ///
  2268. /// [Bit 2] Code and Data Prioritization Technology supported if 1.
  2269. ///
  2270. UINT32 CodeDataPrioritization:1;
  2271. UINT32 Reserved2:29;
  2272. } Bits;
  2273. ///
  2274. /// All bit fields as a 32-bit value
  2275. ///
  2276. UINT32 Uint32;
  2277. } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX;
  2278. /**
  2279. CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf
  2280. #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
  2281. #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
  2282. **/
  2283. typedef union {
  2284. ///
  2285. /// Individual bit fields
  2286. ///
  2287. struct {
  2288. ///
  2289. /// [Bits 15:0] Highest COS number supported for this ResID.
  2290. ///
  2291. UINT32 HighestCosNumber:16;
  2292. UINT32 Reserved:16;
  2293. } Bits;
  2294. ///
  2295. /// All bit fields as a 32-bit value
  2296. ///
  2297. UINT32 Uint32;
  2298. } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX;
  2299. /**
  2300. L2 Cache Allocation Technology Enumeration Sub-leaf
  2301. @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
  2302. @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02)
  2303. @retval EAX RESID L2 Cache Allocation Technology information described by
  2304. the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX.
  2305. @retval EBX Bit-granular map of isolation/contention of allocation units.
  2306. @retval ECX Reserved.
  2307. @retval EDX RESID L2 Cache Allocation Technology information described by
  2308. the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX.
  2309. <b>Example usage</b>
  2310. @code
  2311. CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;
  2312. UINT32 Ebx;
  2313. CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;
  2314. AsmCpuidEx (
  2315. CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,
  2316. &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
  2317. );
  2318. @endcode
  2319. **/
  2320. #define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02
  2321. /**
  2322. CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf
  2323. #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
  2324. #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.
  2325. **/
  2326. typedef union {
  2327. ///
  2328. /// Individual bit fields
  2329. ///
  2330. struct {
  2331. ///
  2332. /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
  2333. /// using minus-one notation.
  2334. ///
  2335. UINT32 CapacityLength:5;
  2336. UINT32 Reserved:27;
  2337. } Bits;
  2338. ///
  2339. /// All bit fields as a 32-bit value
  2340. ///
  2341. UINT32 Uint32;
  2342. } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX;
  2343. /**
  2344. CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf
  2345. #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
  2346. #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.
  2347. **/
  2348. typedef union {
  2349. ///
  2350. /// Individual bit fields
  2351. ///
  2352. struct {
  2353. ///
  2354. /// [Bits 15:0] Highest COS number supported for this ResID.
  2355. ///
  2356. UINT32 HighestCosNumber:16;
  2357. UINT32 Reserved:16;
  2358. } Bits;
  2359. ///
  2360. /// All bit fields as a 32-bit value
  2361. ///
  2362. UINT32 Uint32;
  2363. } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX;
  2364. /**
  2365. Memory Bandwidth Allocation Enumeration Sub-leaf
  2366. @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
  2367. @param ECX CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF (0x03)
  2368. @retval EAX RESID memory bandwidth Allocation Technology information
  2369. described by the type
  2370. CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX.
  2371. @retval EBX Reserved.
  2372. @retval ECX RESID memory bandwidth Allocation Technology information
  2373. described by the type
  2374. CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX.
  2375. @retval EDX RESID memory bandwidth Allocation Technology information
  2376. described by the type
  2377. CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX.
  2378. <b>Example usage</b>
  2379. @code
  2380. CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX Eax;
  2381. UINT32 Ebx;
  2382. CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX Ecx;
  2383. CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx;
  2384. AsmCpuidEx (
  2385. CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,
  2386. &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
  2387. );
  2388. @endcode
  2389. **/
  2390. #define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03
  2391. /**
  2392. CPUID memory bandwidth Allocation Technology Information EAX for CPUID leaf
  2393. #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
  2394. #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
  2395. **/
  2396. typedef union {
  2397. ///
  2398. /// Individual bit fields
  2399. ///
  2400. struct {
  2401. ///
  2402. /// [Bits 11:0] Reports the maximum MBA throttling value supported for
  2403. /// the corresponding ResID using minus-one notation.
  2404. ///
  2405. UINT32 MaximumMBAThrottling:12;
  2406. UINT32 Reserved:20;
  2407. } Bits;
  2408. ///
  2409. /// All bit fields as a 32-bit value
  2410. ///
  2411. UINT32 Uint32;
  2412. } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX;
  2413. /**
  2414. CPUID memory bandwidth Allocation Technology Information ECX for CPUID leaf
  2415. #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
  2416. #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
  2417. **/
  2418. typedef union {
  2419. ///
  2420. /// Individual bit fields
  2421. ///
  2422. struct {
  2423. ///
  2424. /// [Bits 1:0] Reserved.
  2425. ///
  2426. UINT32 Reserved1:2;
  2427. ///
  2428. /// [Bits 3] Reports whether the response of the delay values is linear.
  2429. ///
  2430. UINT32 Liner:1;
  2431. UINT32 Reserved2:29;
  2432. } Bits;
  2433. ///
  2434. /// All bit fields as a 32-bit value
  2435. ///
  2436. UINT32 Uint32;
  2437. } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX;
  2438. /**
  2439. CPUID memory bandwidth Allocation Technology Information EDX for CPUID leaf
  2440. #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
  2441. #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
  2442. **/
  2443. typedef union {
  2444. ///
  2445. /// Individual bit fields
  2446. ///
  2447. struct {
  2448. ///
  2449. /// [Bits 15:0] Highest COS number supported for this ResID.
  2450. ///
  2451. UINT32 HighestCosNumber:16;
  2452. UINT32 Reserved:16;
  2453. } Bits;
  2454. ///
  2455. /// All bit fields as a 32-bit value
  2456. ///
  2457. UINT32 Uint32;
  2458. } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX;
  2459. /**
  2460. Intel SGX resource capability and configuration.
  2461. See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".
  2462. If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying
  2463. CPUID with EAX=12H on Intel SGX resource capability and configuration.
  2464. @param EAX CPUID_INTEL_SGX (0x12)
  2465. @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00).
  2466. CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01).
  2467. CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02).
  2468. Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0])
  2469. until the sub-leaf type is invalid.
  2470. **/
  2471. #define CPUID_INTEL_SGX 0x12
  2472. /**
  2473. Sub-Leaf 0 Enumeration of Intel SGX Capabilities.
  2474. Enumerates Intel SGX capability, including enclave instruction opcode support.
  2475. @param EAX CPUID_INTEL_SGX (0x12)
  2476. @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)
  2477. @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
  2478. described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.
  2479. @retval EBX MISCSELECT: Reports the bit vector of supported extended features
  2480. that can be written to the MISC region of the SSA.
  2481. @retval ECX Reserved.
  2482. @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
  2483. described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.
  2484. <b>Example usage</b>
  2485. @code
  2486. CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;
  2487. UINT32 Ebx;
  2488. CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;
  2489. AsmCpuidEx (
  2490. CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,
  2491. &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
  2492. );
  2493. @endcode
  2494. **/
  2495. #define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00
  2496. /**
  2497. Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,
  2498. sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
  2499. **/
  2500. typedef union {
  2501. ///
  2502. /// Individual bit fields
  2503. ///
  2504. struct {
  2505. ///
  2506. /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.
  2507. ///
  2508. UINT32 SGX1:1;
  2509. ///
  2510. /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.
  2511. ///
  2512. UINT32 SGX2:1;
  2513. UINT32 Reserved1:3;
  2514. ///
  2515. /// [Bit 5] If 1, indicates Intel SGX supports ENCLV instruction leaves
  2516. /// EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT.
  2517. ///
  2518. UINT32 ENCLV:1;
  2519. ///
  2520. /// [Bit 6] If 1, indicates Intel SGX supports ENCLS instruction leaves ETRACKC,
  2521. /// ERDINFO, ELDBC, and ELDUC.
  2522. ///
  2523. UINT32 ENCLS:1;
  2524. UINT32 Reserved2:25;
  2525. } Bits;
  2526. ///
  2527. /// All bit fields as a 32-bit value
  2528. ///
  2529. UINT32 Uint32;
  2530. } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX;
  2531. /**
  2532. Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX,
  2533. sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
  2534. **/
  2535. typedef union {
  2536. ///
  2537. /// Individual bit fields
  2538. ///
  2539. struct {
  2540. ///
  2541. /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes
  2542. /// when not in 64-bit mode.
  2543. ///
  2544. UINT32 MaxEnclaveSize_Not64:8;
  2545. ///
  2546. /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes
  2547. /// when operating in 64-bit mode.
  2548. ///
  2549. UINT32 MaxEnclaveSize_64:8;
  2550. UINT32 Reserved:16;
  2551. } Bits;
  2552. ///
  2553. /// All bit fields as a 32-bit value
  2554. ///
  2555. UINT32 Uint32;
  2556. } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX;
  2557. /**
  2558. Sub-Leaf 1 Enumeration of Intel SGX Capabilities.
  2559. Enumerates Intel SGX capability of processor state configuration and enclave
  2560. configuration in the SECS structure.
  2561. @param EAX CPUID_INTEL_SGX (0x12)
  2562. @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)
  2563. @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can
  2564. set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE
  2565. only if EAX[n] is 1, where n < 32.
  2566. @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can
  2567. set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE
  2568. only if EBX[n] is 1, where n < 32.
  2569. @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can
  2570. set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE
  2571. only if ECX[n] is 1, where n < 32.
  2572. @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can
  2573. set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE
  2574. only if EDX[n] is 1, where n < 32.
  2575. <b>Example usage</b>
  2576. @code
  2577. UINT32 Eax;
  2578. UINT32 Ebx;
  2579. UINT32 Ecx;
  2580. UINT32 Edx;
  2581. AsmCpuidEx (
  2582. CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,
  2583. &Eax, &Ebx, &Ecx, &Edx
  2584. );
  2585. @endcode
  2586. **/
  2587. #define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01
  2588. /**
  2589. Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.
  2590. Enumerates available EPC resources.
  2591. @param EAX CPUID_INTEL_SGX (0x12)
  2592. @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)
  2593. @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
  2594. Resources is described by the type
  2595. CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.
  2596. @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
  2597. Resources is described by the type
  2598. CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.
  2599. @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
  2600. Resources is described by the type
  2601. CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.
  2602. @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
  2603. Resources is described by the type
  2604. CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.
  2605. <b>Example usage</b>
  2606. @code
  2607. CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;
  2608. CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;
  2609. CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;
  2610. CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;
  2611. AsmCpuidEx (
  2612. CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF,
  2613. &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
  2614. );
  2615. @endcode
  2616. **/
  2617. #define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02
  2618. /**
  2619. Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID
  2620. leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
  2621. **/
  2622. typedef union {
  2623. ///
  2624. /// Individual bit fields
  2625. ///
  2626. struct {
  2627. ///
  2628. /// [Bit 3:0] Sub-leaf-type encoding.
  2629. /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0.
  2630. /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC)
  2631. /// in EBX:EAX and EDX:ECX.
  2632. /// All other encoding are reserved.
  2633. ///
  2634. UINT32 SubLeafType:4;
  2635. UINT32 Reserved:8;
  2636. ///
  2637. /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of
  2638. /// the base of the EPC section.
  2639. ///
  2640. UINT32 LowAddressOfEpcSection:20;
  2641. } Bits;
  2642. ///
  2643. /// All bit fields as a 32-bit value
  2644. ///
  2645. UINT32 Uint32;
  2646. } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX;
  2647. /**
  2648. Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID
  2649. leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
  2650. **/
  2651. typedef union {
  2652. ///
  2653. /// Individual bit fields
  2654. ///
  2655. struct {
  2656. ///
  2657. /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of
  2658. /// the base of the EPC section.
  2659. ///
  2660. UINT32 HighAddressOfEpcSection:20;
  2661. UINT32 Reserved:12;
  2662. } Bits;
  2663. ///
  2664. /// All bit fields as a 32-bit value
  2665. ///
  2666. UINT32 Uint32;
  2667. } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX;
  2668. /**
  2669. Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID
  2670. leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
  2671. **/
  2672. typedef union {
  2673. ///
  2674. /// Individual bit fields
  2675. ///
  2676. struct {
  2677. ///
  2678. /// [Bit 3:0] The EPC section encoding.
  2679. /// 0000b: Not valid.
  2680. /// 0001b: The EPC section is confidentiality, integrity and replay protected.
  2681. /// All other encoding are reserved.
  2682. ///
  2683. UINT32 EpcSection:4;
  2684. UINT32 Reserved:8;
  2685. ///
  2686. /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the
  2687. /// corresponding EPC section within the Processor Reserved Memory.
  2688. ///
  2689. UINT32 LowSizeOfEpcSection:20;
  2690. } Bits;
  2691. ///
  2692. /// All bit fields as a 32-bit value
  2693. ///
  2694. UINT32 Uint32;
  2695. } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX;
  2696. /**
  2697. Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID
  2698. leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
  2699. **/
  2700. typedef union {
  2701. ///
  2702. /// Individual bit fields
  2703. ///
  2704. struct {
  2705. ///
  2706. /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the
  2707. /// corresponding EPC section within the Processor Reserved Memory.
  2708. ///
  2709. UINT32 HighSizeOfEpcSection:20;
  2710. UINT32 Reserved:12;
  2711. } Bits;
  2712. ///
  2713. /// All bit fields as a 32-bit value
  2714. ///
  2715. UINT32 Uint32;
  2716. } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX;
  2717. /**
  2718. CPUID Intel Processor Trace Information
  2719. @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14)
  2720. @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00).
  2721. CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).
  2722. **/
  2723. #define CPUID_INTEL_PROCESSOR_TRACE 0x14
  2724. /**
  2725. CPUID Intel Processor Trace Information Main Leaf
  2726. @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
  2727. @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)
  2728. @retval EAX Reports the maximum sub-leaf supported in leaf 14H.
  2729. @retval EBX Returns Intel processor trace information described by the
  2730. type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.
  2731. @retval ECX Returns Intel processor trace information described by the
  2732. type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.
  2733. @retval EDX Reserved.
  2734. <b>Example usage</b>
  2735. @code
  2736. UINT32 Eax;
  2737. CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;
  2738. CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
  2739. AsmCpuidEx (
  2740. CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
  2741. &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL
  2742. );
  2743. @endcode
  2744. **/
  2745. #define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00
  2746. /**
  2747. CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
  2748. sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
  2749. **/
  2750. typedef union {
  2751. ///
  2752. /// Individual bit fields
  2753. ///
  2754. struct {
  2755. ///
  2756. /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,
  2757. /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.
  2758. ///
  2759. UINT32 Cr3Filter:1;
  2760. ///
  2761. /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate
  2762. /// Mode.
  2763. ///
  2764. UINT32 ConfigurablePsb:1;
  2765. ///
  2766. /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,
  2767. /// and preservation of Intel PT MSRs across warm reset.
  2768. ///
  2769. UINT32 IpTraceStopFiltering:1;
  2770. ///
  2771. /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of
  2772. /// COFI-based packets.
  2773. ///
  2774. UINT32 Mtc:1;
  2775. ///
  2776. /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set
  2777. /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE
  2778. /// can generate packets.
  2779. ///
  2780. UINT32 PTWrite:1;
  2781. ///
  2782. /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set
  2783. /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet
  2784. /// generation.
  2785. ///
  2786. UINT32 PowerEventTrace:1;
  2787. UINT32 Reserved:26;
  2788. } Bits;
  2789. ///
  2790. /// All bit fields as a 32-bit value
  2791. ///
  2792. UINT32 Uint32;
  2793. } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX;
  2794. /**
  2795. CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
  2796. sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
  2797. **/
  2798. typedef union {
  2799. ///
  2800. /// Individual bit fields
  2801. ///
  2802. struct {
  2803. ///
  2804. /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence
  2805. /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and
  2806. /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
  2807. ///
  2808. UINT32 RTIT:1;
  2809. ///
  2810. /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to
  2811. /// the maximum allowed by the MaskOrTableOffset field of
  2812. /// IA32_RTIT_OUTPUT_MASK_PTRS.
  2813. ///
  2814. UINT32 ToPA:1;
  2815. ///
  2816. /// [Bit 2] If 1, indicates support of Single-Range Output scheme.
  2817. ///
  2818. UINT32 SingleRangeOutput:1;
  2819. ///
  2820. /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.
  2821. ///
  2822. UINT32 TraceTransportSubsystem:1;
  2823. UINT32 Reserved:27;
  2824. ///
  2825. /// [Bit 31] If 1, generated packets which contain IP payloads have LIP
  2826. /// values, which include the CS base component.
  2827. ///
  2828. UINT32 LIP:1;
  2829. } Bits;
  2830. ///
  2831. /// All bit fields as a 32-bit value
  2832. ///
  2833. UINT32 Uint32;
  2834. } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX;
  2835. /**
  2836. CPUID Intel Processor Trace Information Sub-leaf
  2837. @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
  2838. @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)
  2839. @retval EAX Returns Intel processor trace information described by the
  2840. type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.
  2841. @retval EBX Returns Intel processor trace information described by the
  2842. type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.
  2843. @retval ECX Reserved.
  2844. @retval EDX Reserved.
  2845. <b>Example usage</b>
  2846. @code
  2847. UINT32 MaximumSubLeaf;
  2848. UINT32 SubLeaf;
  2849. CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;
  2850. CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;
  2851. AsmCpuidEx (
  2852. CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
  2853. &MaximumSubLeaf, NULL, NULL, NULL
  2854. );
  2855. for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
  2856. AsmCpuidEx (
  2857. CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,
  2858. &Eax.Uint32, &Ebx.Uint32, NULL, NULL
  2859. );
  2860. }
  2861. @endcode
  2862. **/
  2863. #define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01
  2864. /**
  2865. CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
  2866. sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
  2867. **/
  2868. typedef union {
  2869. ///
  2870. /// Individual bit fields
  2871. ///
  2872. struct {
  2873. ///
  2874. /// [Bits 2:0] Number of configurable Address Ranges for filtering.
  2875. ///
  2876. UINT32 ConfigurableAddressRanges:3;
  2877. UINT32 Reserved:13;
  2878. ///
  2879. /// [Bits 31:16] Bitmap of supported MTC period encodings
  2880. ///
  2881. UINT32 MtcPeriodEncodings:16;
  2882. } Bits;
  2883. ///
  2884. /// All bit fields as a 32-bit value
  2885. ///
  2886. UINT32 Uint32;
  2887. } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX;
  2888. /**
  2889. CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
  2890. sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
  2891. **/
  2892. typedef union {
  2893. ///
  2894. /// Individual bit fields
  2895. ///
  2896. struct {
  2897. ///
  2898. /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.
  2899. ///
  2900. UINT32 CycleThresholdEncodings:16;
  2901. ///
  2902. /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.
  2903. ///
  2904. UINT32 PsbFrequencyEncodings:16;
  2905. } Bits;
  2906. ///
  2907. /// All bit fields as a 32-bit value
  2908. ///
  2909. UINT32 Uint32;
  2910. } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX;
  2911. /**
  2912. CPUID Time Stamp Counter and Nominal Core Crystal Clock Information
  2913. @note
  2914. If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.
  2915. EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core
  2916. crystal clock frequency.
  2917. If ECX is 0, the nominal core crystal clock frequency is not enumerated.
  2918. "TSC frequency" = "core crystal clock frequency" * EBX/EAX.
  2919. The core crystal clock may differ from the reference clock, bus clock, or core
  2920. clock frequencies.
  2921. @param EAX CPUID_TIME_STAMP_COUNTER (0x15)
  2922. @retval EAX An unsigned integer which is the denominator of the
  2923. TSC/"core crystal clock" ratio
  2924. @retval EBX An unsigned integer which is the numerator of the
  2925. TSC/"core crystal clock" ratio.
  2926. @retval ECX An unsigned integer which is the nominal frequency
  2927. of the core crystal clock in Hz.
  2928. @retval EDX Reserved.
  2929. <b>Example usage</b>
  2930. @code
  2931. UINT32 Eax;
  2932. UINT32 Ebx;
  2933. UINT32 Ecx;
  2934. AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);
  2935. @endcode
  2936. **/
  2937. #define CPUID_TIME_STAMP_COUNTER 0x15
  2938. /**
  2939. CPUID Processor Frequency Information
  2940. @note
  2941. Data is returned from this interface in accordance with the processor's
  2942. specification and does not reflect actual values. Suitable use of this data
  2943. includes the display of processor information in like manner to the processor
  2944. brand string and for determining the appropriate range to use when displaying
  2945. processor information e.g. frequency history graphs. The returned information
  2946. should not be used for any other purpose as the returned information does not
  2947. accurately correlate to information / counters returned by other processor
  2948. interfaces. While a processor may support the Processor Frequency Information
  2949. leaf, fields that return a value of zero are not supported.
  2950. @param EAX CPUID_TIME_STAMP_COUNTER (0x16)
  2951. @retval EAX Returns processor base frequency information described by the
  2952. type CPUID_PROCESSOR_FREQUENCY_EAX.
  2953. @retval EBX Returns maximum frequency information described by the type
  2954. CPUID_PROCESSOR_FREQUENCY_EBX.
  2955. @retval ECX Returns bus frequency information described by the type
  2956. CPUID_PROCESSOR_FREQUENCY_ECX.
  2957. @retval EDX Reserved.
  2958. <b>Example usage</b>
  2959. @code
  2960. CPUID_PROCESSOR_FREQUENCY_EAX Eax;
  2961. CPUID_PROCESSOR_FREQUENCY_EBX Ebx;
  2962. CPUID_PROCESSOR_FREQUENCY_ECX Ecx;
  2963. AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
  2964. @endcode
  2965. **/
  2966. #define CPUID_PROCESSOR_FREQUENCY 0x16
  2967. /**
  2968. CPUID Processor Frequency Information EAX for CPUID leaf
  2969. #CPUID_PROCESSOR_FREQUENCY.
  2970. **/
  2971. typedef union {
  2972. ///
  2973. /// Individual bit fields
  2974. ///
  2975. struct {
  2976. ///
  2977. /// [Bits 15:0] Processor Base Frequency (in MHz).
  2978. ///
  2979. UINT32 ProcessorBaseFrequency:16;
  2980. UINT32 Reserved:16;
  2981. } Bits;
  2982. ///
  2983. /// All bit fields as a 32-bit value
  2984. ///
  2985. UINT32 Uint32;
  2986. } CPUID_PROCESSOR_FREQUENCY_EAX;
  2987. /**
  2988. CPUID Processor Frequency Information EBX for CPUID leaf
  2989. #CPUID_PROCESSOR_FREQUENCY.
  2990. **/
  2991. typedef union {
  2992. ///
  2993. /// Individual bit fields
  2994. ///
  2995. struct {
  2996. ///
  2997. /// [Bits 15:0] Maximum Frequency (in MHz).
  2998. ///
  2999. UINT32 MaximumFrequency:16;
  3000. UINT32 Reserved:16;
  3001. } Bits;
  3002. ///
  3003. /// All bit fields as a 32-bit value
  3004. ///
  3005. UINT32 Uint32;
  3006. } CPUID_PROCESSOR_FREQUENCY_EBX;
  3007. /**
  3008. CPUID Processor Frequency Information ECX for CPUID leaf
  3009. #CPUID_PROCESSOR_FREQUENCY.
  3010. **/
  3011. typedef union {
  3012. ///
  3013. /// Individual bit fields
  3014. ///
  3015. struct {
  3016. ///
  3017. /// [Bits 15:0] Bus (Reference) Frequency (in MHz).
  3018. ///
  3019. UINT32 BusFrequency:16;
  3020. UINT32 Reserved:16;
  3021. } Bits;
  3022. ///
  3023. /// All bit fields as a 32-bit value
  3024. ///
  3025. UINT32 Uint32;
  3026. } CPUID_PROCESSOR_FREQUENCY_ECX;
  3027. /**
  3028. CPUID SoC Vendor Information
  3029. @param EAX CPUID_SOC_VENDOR (0x17)
  3030. @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
  3031. CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
  3032. CPUID_SOC_VENDOR_BRAND_STRING1 (0x02)
  3033. CPUID_SOC_VENDOR_BRAND_STRING1 (0x03)
  3034. @note
  3035. Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String
  3036. is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC
  3037. Vendor Brand String is constructed by concatenating in ascending order of
  3038. EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.
  3039. **/
  3040. #define CPUID_SOC_VENDOR 0x17
  3041. /**
  3042. CPUID SoC Vendor Information
  3043. @param EAX CPUID_SOC_VENDOR (0x17)
  3044. @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
  3045. @retval EAX MaxSOCID_Index. Reports the maximum input value of supported
  3046. sub-leaf in leaf 17H.
  3047. @retval EBX Returns SoC Vendor information described by the type
  3048. CPUID_SOC_VENDOR_MAIN_LEAF_EBX.
  3049. @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC
  3050. projects.
  3051. @retval EDX Stepping ID. A unique number within an SOC project that an SOC
  3052. vendor assigns.
  3053. <b>Example usage</b>
  3054. @code
  3055. UINT32 Eax;
  3056. CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;
  3057. UINT32 Ecx;
  3058. UINT32 Edx;
  3059. AsmCpuidEx (
  3060. CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,
  3061. &Eax, &Ebx.Uint32, &Ecx, &Edx
  3062. );
  3063. @endcode
  3064. **/
  3065. #define CPUID_SOC_VENDOR_MAIN_LEAF 0x00
  3066. /**
  3067. CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf
  3068. #CPUID_SOC_VENDOR_MAIN_LEAF.
  3069. **/
  3070. typedef union {
  3071. ///
  3072. /// Individual bit fields
  3073. ///
  3074. struct {
  3075. ///
  3076. /// [Bits 15:0] SOC Vendor ID.
  3077. ///
  3078. UINT32 SocVendorId:16;
  3079. ///
  3080. /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry
  3081. /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is
  3082. /// assigned by Intel.
  3083. ///
  3084. UINT32 IsVendorScheme:1;
  3085. UINT32 Reserved:15;
  3086. } Bits;
  3087. ///
  3088. /// All bit fields as a 32-bit value
  3089. ///
  3090. UINT32 Uint32;
  3091. } CPUID_SOC_VENDOR_MAIN_LEAF_EBX;
  3092. /**
  3093. CPUID SoC Vendor Information
  3094. @param EAX CPUID_SOC_VENDOR (0x17)
  3095. @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
  3096. @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
  3097. CPUID_SOC_VENDOR_BRAND_STRING_DATA.
  3098. @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
  3099. CPUID_SOC_VENDOR_BRAND_STRING_DATA.
  3100. @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
  3101. CPUID_SOC_VENDOR_BRAND_STRING_DATA.
  3102. @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
  3103. CPUID_SOC_VENDOR_BRAND_STRING_DATA.
  3104. <b>Example usage</b>
  3105. @code
  3106. CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
  3107. CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
  3108. CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
  3109. CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
  3110. AsmCpuidEx (
  3111. CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,
  3112. &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
  3113. );
  3114. @endcode
  3115. **/
  3116. #define CPUID_SOC_VENDOR_BRAND_STRING1 0x01
  3117. /**
  3118. CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,
  3119. #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3.
  3120. **/
  3121. typedef union {
  3122. ///
  3123. /// 4 UTF-8 characters of Soc Vendor Brand String
  3124. ///
  3125. CHAR8 BrandString[4];
  3126. ///
  3127. /// All fields as a 32-bit value
  3128. ///
  3129. UINT32 Uint32;
  3130. } CPUID_SOC_VENDOR_BRAND_STRING_DATA;
  3131. /**
  3132. CPUID SoC Vendor Information
  3133. @param EAX CPUID_SOC_VENDOR (0x17)
  3134. @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02)
  3135. @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
  3136. CPUID_SOC_VENDOR_BRAND_STRING_DATA.
  3137. @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
  3138. CPUID_SOC_VENDOR_BRAND_STRING_DATA.
  3139. @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
  3140. CPUID_SOC_VENDOR_BRAND_STRING_DATA.
  3141. @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
  3142. CPUID_SOC_VENDOR_BRAND_STRING_DATA.
  3143. <b>Example usage</b>
  3144. @code
  3145. CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
  3146. CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
  3147. CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
  3148. CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
  3149. AsmCpuidEx (
  3150. CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,
  3151. &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
  3152. );
  3153. @endcode
  3154. **/
  3155. #define CPUID_SOC_VENDOR_BRAND_STRING2 0x02
  3156. /**
  3157. CPUID SoC Vendor Information
  3158. @param EAX CPUID_SOC_VENDOR (0x17)
  3159. @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03)
  3160. @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
  3161. CPUID_SOC_VENDOR_BRAND_STRING_DATA.
  3162. @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
  3163. CPUID_SOC_VENDOR_BRAND_STRING_DATA.
  3164. @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
  3165. CPUID_SOC_VENDOR_BRAND_STRING_DATA.
  3166. @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
  3167. CPUID_SOC_VENDOR_BRAND_STRING_DATA.
  3168. <b>Example usage</b>
  3169. @code
  3170. CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
  3171. CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
  3172. CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
  3173. CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
  3174. AsmCpuidEx (
  3175. CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,
  3176. &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
  3177. );
  3178. @endcode
  3179. **/
  3180. #define CPUID_SOC_VENDOR_BRAND_STRING3 0x03
  3181. /**
  3182. CPUID Deterministic Address Translation Parameters
  3183. @note
  3184. Each sub-leaf enumerates a different address translation structure.
  3185. If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
  3186. index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX. A
  3187. sub-leaf index is also invalid if EDX[4:0] returns 0.
  3188. Valid sub-leaves do not need to be contiguous or in any particular order. A
  3189. valid sub-leaf may be in a higher input ECX value than an invalid sub-leaf or
  3190. than a valid sub-leaf of a higher or lower-level structure.
  3191. * Some unified TLBs will allow a single TLB entry to satisfy data read/write
  3192. and instruction fetches. Others will require separate entries (e.g., one
  3193. loaded on data read/write and another loaded on an instruction fetch).
  3194. Please see the Intel 64 and IA-32 Architectures Optimization Reference Manual
  3195. for details of a particular product.
  3196. ** Add one to the return value to get the result.
  3197. @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18)
  3198. @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00)
  3199. CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_SUB_LEAF (0x*)
  3200. **/
  3201. #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18
  3202. /**
  3203. CPUID Deterministic Address Translation Parameters
  3204. @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18)
  3205. @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00)
  3206. @retval EAX Reports the maximum input value of supported sub-leaf in leaf 18H.
  3207. @retval EBX Returns Deterministic Address Translation Parameters described by
  3208. the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX.
  3209. @retval ECX Number of Sets.
  3210. @retval EDX Returns Deterministic Address Translation Parameters described by
  3211. the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.
  3212. <b>Example usage</b>
  3213. @code
  3214. UINT32 Eax;
  3215. CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX Ebx;
  3216. UINT32 Ecx;
  3217. CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX Edx;
  3218. AsmCpuidEx (
  3219. CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS,
  3220. CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF,
  3221. &Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32
  3222. );
  3223. @endcode
  3224. **/
  3225. #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00
  3226. /**
  3227. CPUID Deterministic Address Translation Parameters EBX for CPUID leafs.
  3228. **/
  3229. typedef union {
  3230. ///
  3231. /// Individual bit fields
  3232. ///
  3233. struct {
  3234. ///
  3235. /// [Bits 0] 4K page size entries supported by this structure.
  3236. ///
  3237. UINT32 Page4K:1;
  3238. ///
  3239. /// [Bits 1] 2MB page size entries supported by this structure.
  3240. ///
  3241. UINT32 Page2M:1;
  3242. ///
  3243. /// [Bits 2] 4MB page size entries supported by this structure.
  3244. ///
  3245. UINT32 Page4M:1;
  3246. ///
  3247. /// [Bits 3] 1 GB page size entries supported by this structure.
  3248. ///
  3249. UINT32 Page1G:1;
  3250. ///
  3251. /// [Bits 7:4] Reserved.
  3252. ///
  3253. UINT32 Reserved1:4;
  3254. ///
  3255. /// [Bits 10:8] Partitioning (0: Soft partitioning between the logical
  3256. /// processors sharing this structure)
  3257. ///
  3258. UINT32 Partitioning:3;
  3259. ///
  3260. /// [Bits 15:11] Reserved.
  3261. ///
  3262. UINT32 Reserved2:5;
  3263. ///
  3264. /// [Bits 31:16] W = Ways of associativity.
  3265. ///
  3266. UINT32 Way:16;
  3267. } Bits;
  3268. ///
  3269. /// All bit fields as a 32-bit value
  3270. ///
  3271. UINT32 Uint32;
  3272. } CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX;
  3273. /**
  3274. CPUID Deterministic Address Translation Parameters EDX for CPUID leafs.
  3275. **/
  3276. typedef union {
  3277. ///
  3278. /// Individual bit fields
  3279. ///
  3280. struct {
  3281. ///
  3282. /// [Bits 4:0] Translation cache type field.
  3283. ///
  3284. UINT32 TranslationCacheType:5;
  3285. ///
  3286. /// [Bits 7:5] Translation cache level (starts at 1).
  3287. ///
  3288. UINT32 TranslationCacheLevel:3;
  3289. ///
  3290. /// [Bits 8] Fully associative structure.
  3291. ///
  3292. UINT32 FullyAssociative:1;
  3293. ///
  3294. /// [Bits 13:9] Reserved.
  3295. ///
  3296. UINT32 Reserved1:5;
  3297. ///
  3298. /// [Bits 25:14] Maximum number of addressable IDs for logical
  3299. /// processors sharing this translation cache.
  3300. ///
  3301. UINT32 MaximumNum:12;
  3302. ///
  3303. /// [Bits 31:26] Reserved.
  3304. ///
  3305. UINT32 Reserved2:6;
  3306. } Bits;
  3307. ///
  3308. /// All bit fields as a 32-bit value
  3309. ///
  3310. UINT32 Uint32;
  3311. } CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX;
  3312. ///
  3313. /// @{ Define value for CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.TranslationCacheType
  3314. ///
  3315. #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INVALID 0x00
  3316. #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_DATA_TLB 0x01
  3317. #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INSTRUCTION_TLB 0x02
  3318. #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_UNIFIED_TLB 0x03
  3319. ///
  3320. /// @}
  3321. ///
  3322. /**
  3323. CPUID V2 Extended Topology Enumeration Leaf
  3324. @note
  3325. CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking
  3326. for the existence of Leaf 1FH and using this if available.
  3327. Most of Leaf 1FH output depends on the initial value in ECX. The EDX output of leaf
  3328. 1FH is always valid and does not vary with input value in ECX. Output value in ECX[7:0]
  3329. always equals input value in ECX[7:0]. Sub-leaf index 0 enumerates SMT level. Each
  3330. subsequent higher sub-leaf index enumerates a higher-level topological entity in
  3331. hierarchical order. For sub-leaves that return an invalid level-type of 0 in ECX[15:8];
  3332. EAX and EBX will return 0. If an input value n in ECX returns the invalid level-type of
  3333. 0 in ECX[15:8], other input values with ECX > n also return 0 in ECX[15:8].
  3334. Software should use this field (EAX[4:0]) to enumerate processor topology of the system.
  3335. Software must not use EBX[15:0] to enumerate processor topology of the system. This value
  3336. in this field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual
  3337. number of logical processors available to BIOS/OS/Applications may be different from the
  3338. value of EBX[15:0], depending on software and platform hardware configurations.
  3339. @param EAX CPUID_V2_EXTENDED_TOPOLOGY (0x1F)
  3340. @param ECX Level number
  3341. **/
  3342. #define CPUID_V2_EXTENDED_TOPOLOGY 0x1F
  3343. ///
  3344. /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
  3345. /// The value of the "level type" field is not related to level numbers in
  3346. /// any way, higher "level type" values do not mean higher levels.
  3347. ///
  3348. #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03
  3349. #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04
  3350. #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05
  3351. ///
  3352. /// @}
  3353. ///
  3354. /**
  3355. CPUID Extended Function
  3356. @param EAX CPUID_EXTENDED_FUNCTION (0x80000000)
  3357. @retval EAX Maximum Input Value for Extended Function CPUID Information.
  3358. @retval EBX Reserved.
  3359. @retval ECX Reserved.
  3360. @retval EDX Reserved.
  3361. <b>Example usage</b>
  3362. @code
  3363. UINT32 Eax;
  3364. AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
  3365. @endcode
  3366. **/
  3367. #define CPUID_EXTENDED_FUNCTION 0x80000000
  3368. /**
  3369. CPUID Extended Processor Signature and Feature Bits
  3370. @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
  3371. @retval EAX CPUID_EXTENDED_CPU_SIG.
  3372. @retval EBX Reserved.
  3373. @retval ECX Extended Processor Signature and Feature Bits information
  3374. described by the type CPUID_EXTENDED_CPU_SIG_ECX.
  3375. @retval EDX Extended Processor Signature and Feature Bits information
  3376. described by the type CPUID_EXTENDED_CPU_SIG_EDX.
  3377. <b>Example usage</b>
  3378. @code
  3379. UINT32 Eax;
  3380. CPUID_EXTENDED_CPU_SIG_ECX Ecx;
  3381. CPUID_EXTENDED_CPU_SIG_EDX Edx;
  3382. AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);
  3383. @endcode
  3384. **/
  3385. #define CPUID_EXTENDED_CPU_SIG 0x80000001
  3386. /**
  3387. CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf
  3388. #CPUID_EXTENDED_CPU_SIG.
  3389. **/
  3390. typedef union {
  3391. ///
  3392. /// Individual bit fields
  3393. ///
  3394. struct {
  3395. ///
  3396. /// [Bit 0] LAHF/SAHF available in 64-bit mode.
  3397. ///
  3398. UINT32 LAHF_SAHF:1;
  3399. UINT32 Reserved1:4;
  3400. ///
  3401. /// [Bit 5] LZCNT.
  3402. ///
  3403. UINT32 LZCNT:1;
  3404. UINT32 Reserved2:2;
  3405. ///
  3406. /// [Bit 8] PREFETCHW.
  3407. ///
  3408. UINT32 PREFETCHW:1;
  3409. UINT32 Reserved3:23;
  3410. } Bits;
  3411. ///
  3412. /// All bit fields as a 32-bit value
  3413. ///
  3414. UINT32 Uint32;
  3415. } CPUID_EXTENDED_CPU_SIG_ECX;
  3416. /**
  3417. CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf
  3418. #CPUID_EXTENDED_CPU_SIG.
  3419. **/
  3420. typedef union {
  3421. ///
  3422. /// Individual bit fields
  3423. ///
  3424. struct {
  3425. UINT32 Reserved1:11;
  3426. ///
  3427. /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.
  3428. ///
  3429. UINT32 SYSCALL_SYSRET:1;
  3430. UINT32 Reserved2:8;
  3431. ///
  3432. /// [Bit 20] Execute Disable Bit available.
  3433. ///
  3434. UINT32 NX:1;
  3435. UINT32 Reserved3:5;
  3436. ///
  3437. /// [Bit 26] 1-GByte pages are available if 1.
  3438. ///
  3439. UINT32 Page1GB:1;
  3440. ///
  3441. /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.
  3442. ///
  3443. UINT32 RDTSCP:1;
  3444. UINT32 Reserved4:1;
  3445. ///
  3446. /// [Bit 29] Intel(R) 64 Architecture available if 1.
  3447. ///
  3448. UINT32 LM:1;
  3449. UINT32 Reserved5:2;
  3450. } Bits;
  3451. ///
  3452. /// All bit fields as a 32-bit value
  3453. ///
  3454. UINT32 Uint32;
  3455. } CPUID_EXTENDED_CPU_SIG_EDX;
  3456. /**
  3457. CPUID Processor Brand String
  3458. @param EAX CPUID_BRAND_STRING1 (0x80000002)
  3459. @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA.
  3460. @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
  3461. @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
  3462. @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
  3463. <b>Example usage</b>
  3464. @code
  3465. CPUID_BRAND_STRING_DATA Eax;
  3466. CPUID_BRAND_STRING_DATA Ebx;
  3467. CPUID_BRAND_STRING_DATA Ecx;
  3468. CPUID_BRAND_STRING_DATA Edx;
  3469. AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
  3470. @endcode
  3471. **/
  3472. #define CPUID_BRAND_STRING1 0x80000002
  3473. /**
  3474. CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,
  3475. #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3.
  3476. **/
  3477. typedef union {
  3478. ///
  3479. /// 4 ASCII characters of Processor Brand String
  3480. ///
  3481. CHAR8 BrandString[4];
  3482. ///
  3483. /// All fields as a 32-bit value
  3484. ///
  3485. UINT32 Uint32;
  3486. } CPUID_BRAND_STRING_DATA;
  3487. /**
  3488. CPUID Processor Brand String
  3489. @param EAX CPUID_BRAND_STRING2 (0x80000003)
  3490. @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
  3491. @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
  3492. @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
  3493. @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
  3494. <b>Example usage</b>
  3495. @code
  3496. CPUID_BRAND_STRING_DATA Eax;
  3497. CPUID_BRAND_STRING_DATA Ebx;
  3498. CPUID_BRAND_STRING_DATA Ecx;
  3499. CPUID_BRAND_STRING_DATA Edx;
  3500. AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
  3501. @endcode
  3502. **/
  3503. #define CPUID_BRAND_STRING2 0x80000003
  3504. /**
  3505. CPUID Processor Brand String
  3506. @param EAX CPUID_BRAND_STRING3 (0x80000004)
  3507. @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
  3508. @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
  3509. @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
  3510. @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
  3511. <b>Example usage</b>
  3512. @code
  3513. CPUID_BRAND_STRING_DATA Eax;
  3514. CPUID_BRAND_STRING_DATA Ebx;
  3515. CPUID_BRAND_STRING_DATA Ecx;
  3516. CPUID_BRAND_STRING_DATA Edx;
  3517. AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
  3518. @endcode
  3519. **/
  3520. #define CPUID_BRAND_STRING3 0x80000004
  3521. /**
  3522. CPUID Extended Cache information
  3523. @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006)
  3524. @retval EAX Reserved.
  3525. @retval EBX Reserved.
  3526. @retval ECX Extended cache information described by the type
  3527. CPUID_EXTENDED_CACHE_INFO_ECX.
  3528. @retval EDX Reserved.
  3529. <b>Example usage</b>
  3530. @code
  3531. CPUID_EXTENDED_CACHE_INFO_ECX Ecx;
  3532. AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);
  3533. @endcode
  3534. **/
  3535. #define CPUID_EXTENDED_CACHE_INFO 0x80000006
  3536. /**
  3537. CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.
  3538. **/
  3539. typedef union {
  3540. ///
  3541. /// Individual bit fields
  3542. ///
  3543. struct {
  3544. ///
  3545. /// [Bits 7:0] Cache line size in bytes.
  3546. ///
  3547. UINT32 CacheLineSize:8;
  3548. UINT32 Reserved:4;
  3549. ///
  3550. /// [Bits 15:12] L2 Associativity field. Supported values are in the range
  3551. /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to
  3552. /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL
  3553. ///
  3554. UINT32 L2Associativity:4;
  3555. ///
  3556. /// [Bits 31:16] Cache size in 1K units.
  3557. ///
  3558. UINT32 CacheSize:16;
  3559. } Bits;
  3560. ///
  3561. /// All bit fields as a 32-bit value
  3562. ///
  3563. UINT32 Uint32;
  3564. } CPUID_EXTENDED_CACHE_INFO_ECX;
  3565. ///
  3566. /// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity
  3567. ///
  3568. #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00
  3569. #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01
  3570. #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02
  3571. #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04
  3572. #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06
  3573. #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08
  3574. #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_32_WAY 0x0A
  3575. #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_48_WAY 0x0B
  3576. #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_64_WAY 0x0C
  3577. #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_96_WAY 0x0D
  3578. #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_128_WAY 0x0E
  3579. #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F
  3580. ///
  3581. /// @}
  3582. ///
  3583. /**
  3584. CPUID Extended Time Stamp Counter information
  3585. @param EAX CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007)
  3586. @retval EAX Reserved.
  3587. @retval EBX Reserved.
  3588. @retval ECX Reserved.
  3589. @retval EDX Extended time stamp counter (TSC) information described by the
  3590. type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX.
  3591. <b>Example usage</b>
  3592. @code
  3593. CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;
  3594. AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);
  3595. @endcode
  3596. **/
  3597. #define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007
  3598. /**
  3599. CPUID Extended Time Stamp Counter information EDX for CPUID leaf
  3600. #CPUID_EXTENDED_TIME_STAMP_COUNTER.
  3601. **/
  3602. typedef union {
  3603. ///
  3604. /// Individual bit fields
  3605. ///
  3606. struct {
  3607. UINT32 Reserved1:8;
  3608. ///
  3609. /// [Bit 8] Invariant TSC available if 1.
  3610. ///
  3611. UINT32 InvariantTsc:1;
  3612. UINT32 Reserved2:23;
  3613. } Bits;
  3614. ///
  3615. /// All bit fields as a 32-bit value
  3616. ///
  3617. UINT32 Uint32;
  3618. } CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX;
  3619. /**
  3620. CPUID Linear Physical Address Size
  3621. @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
  3622. @retval EAX Linear/Physical Address Size described by the type
  3623. CPUID_VIR_PHY_ADDRESS_SIZE_EAX.
  3624. @retval EBX Reserved.
  3625. @retval ECX Reserved.
  3626. @retval EDX Reserved.
  3627. <b>Example usage</b>
  3628. @code
  3629. CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;
  3630. AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);
  3631. @endcode
  3632. **/
  3633. #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
  3634. /**
  3635. CPUID Linear Physical Address Size EAX for CPUID leaf
  3636. #CPUID_VIR_PHY_ADDRESS_SIZE.
  3637. **/
  3638. typedef union {
  3639. ///
  3640. /// Individual bit fields
  3641. ///
  3642. struct {
  3643. ///
  3644. /// [Bits 7:0] Number of physical address bits.
  3645. ///
  3646. /// @note
  3647. /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address
  3648. /// number supported should come from this field.
  3649. ///
  3650. UINT32 PhysicalAddressBits:8;
  3651. ///
  3652. /// [Bits 15:8] Number of linear address bits.
  3653. ///
  3654. UINT32 LinearAddressBits:8;
  3655. UINT32 Reserved:16;
  3656. } Bits;
  3657. ///
  3658. /// All bit fields as a 32-bit value
  3659. ///
  3660. UINT32 Uint32;
  3661. } CPUID_VIR_PHY_ADDRESS_SIZE_EAX;
  3662. #endif