PrePi.c 7.0 KB

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  1. /** @file
  2. *
  3. * Copyright (c) 2011-2017, ARM Limited. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: BSD-2-Clause-Patent
  6. *
  7. **/
  8. #include <PiPei.h>
  9. #include <Library/DebugAgentLib.h>
  10. #include <Library/PrePiLib.h>
  11. #include <Library/PrintLib.h>
  12. #include <Library/PrePiHobListPointerLib.h>
  13. #include <Library/TimerLib.h>
  14. #include <Library/PerformanceLib.h>
  15. #include <Ppi/GuidedSectionExtraction.h>
  16. #include <Ppi/ArmMpCoreInfo.h>
  17. #include <Ppi/SecPerformance.h>
  18. #include "PrePi.h"
  19. #define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) || \
  20. ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) < FixedPcdGet64 (PcdSystemMemoryBase)))
  21. UINT64 mSystemMemoryEnd = FixedPcdGet64(PcdSystemMemoryBase) +
  22. FixedPcdGet64(PcdSystemMemorySize) - 1;
  23. EFI_STATUS
  24. GetPlatformPpi (
  25. IN EFI_GUID *PpiGuid,
  26. OUT VOID **Ppi
  27. )
  28. {
  29. UINTN PpiListSize;
  30. UINTN PpiListCount;
  31. EFI_PEI_PPI_DESCRIPTOR *PpiList;
  32. UINTN Index;
  33. PpiListSize = 0;
  34. ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
  35. PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);
  36. for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
  37. if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {
  38. *Ppi = PpiList->Ppi;
  39. return EFI_SUCCESS;
  40. }
  41. }
  42. return EFI_NOT_FOUND;
  43. }
  44. VOID
  45. PrePiMain (
  46. IN UINTN UefiMemoryBase,
  47. IN UINTN StacksBase,
  48. IN UINT64 StartTimeStamp
  49. )
  50. {
  51. EFI_HOB_HANDOFF_INFO_TABLE* HobList;
  52. ARM_MP_CORE_INFO_PPI* ArmMpCoreInfoPpi;
  53. UINTN ArmCoreCount;
  54. ARM_CORE_INFO* ArmCoreInfoTable;
  55. EFI_STATUS Status;
  56. CHAR8 Buffer[100];
  57. UINTN CharCount;
  58. UINTN StacksSize;
  59. FIRMWARE_SEC_PERFORMANCE Performance;
  60. // If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)
  61. ASSERT (IS_XIP() ||
  62. ((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&
  63. ((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd)));
  64. // Initialize the architecture specific bits
  65. ArchInitialize ();
  66. // Initialize the Serial Port
  67. SerialPortInitialize ();
  68. CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware (version %s built at %a on %a)\n\r",
  69. (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
  70. SerialPortWrite ((UINT8 *) Buffer, CharCount);
  71. // Initialize the Debug Agent for Source Level Debugging
  72. InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
  73. SaveAndSetDebugTimerInterrupt (TRUE);
  74. // Declare the PI/UEFI memory region
  75. HobList = HobConstructor (
  76. (VOID*)UefiMemoryBase,
  77. FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),
  78. (VOID*)UefiMemoryBase,
  79. (VOID*)StacksBase // The top of the UEFI Memory is reserved for the stacks
  80. );
  81. PrePeiSetHobList (HobList);
  82. // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)
  83. Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));
  84. ASSERT_EFI_ERROR (Status);
  85. // Create the Stacks HOB (reserve the memory for all stacks)
  86. if (ArmIsMpCore ()) {
  87. StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize) +
  88. ((FixedPcdGet32 (PcdCoreCount) - 1) * FixedPcdGet32 (PcdCPUCoreSecondaryStackSize));
  89. } else {
  90. StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);
  91. }
  92. BuildStackHob (StacksBase, StacksSize);
  93. //TODO: Call CpuPei as a library
  94. BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));
  95. if (ArmIsMpCore ()) {
  96. // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid
  97. Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);
  98. // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
  99. ASSERT_EFI_ERROR (Status);
  100. // Build the MP Core Info Table
  101. ArmCoreCount = 0;
  102. Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
  103. if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) {
  104. // Build MPCore Info HOB
  105. BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);
  106. }
  107. }
  108. // Store timer value logged at the beginning of firmware image execution
  109. Performance.ResetEnd = GetTimeInNanoSecond (StartTimeStamp);
  110. // Build SEC Performance Data Hob
  111. BuildGuidDataHob (&gEfiFirmwarePerformanceGuid, &Performance, sizeof (Performance));
  112. // Set the Boot Mode
  113. SetBootMode (ArmPlatformGetBootMode ());
  114. // Initialize Platform HOBs (CpuHob and FvHob)
  115. Status = PlatformPeim ();
  116. ASSERT_EFI_ERROR (Status);
  117. // Now, the HOB List has been initialized, we can register performance information
  118. PERF_START (NULL, "PEI", NULL, StartTimeStamp);
  119. // SEC phase needs to run library constructors by hand.
  120. ProcessLibraryConstructorList ();
  121. // Assume the FV that contains the SEC (our code) also contains a compressed FV.
  122. Status = DecompressFirstFv ();
  123. ASSERT_EFI_ERROR (Status);
  124. // Load the DXE Core and transfer control to it
  125. Status = LoadDxeCoreFromFv (NULL, 0);
  126. ASSERT_EFI_ERROR (Status);
  127. }
  128. VOID
  129. CEntryPoint (
  130. IN UINTN MpId,
  131. IN UINTN UefiMemoryBase,
  132. IN UINTN StacksBase
  133. )
  134. {
  135. UINT64 StartTimeStamp;
  136. // Initialize the platform specific controllers
  137. ArmPlatformInitialize (MpId);
  138. if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled ()) {
  139. // Initialize the Timer Library to setup the Timer HW controller
  140. TimerConstructor ();
  141. // We cannot call yet the PerformanceLib because the HOB List has not been initialized
  142. StartTimeStamp = GetPerformanceCounter ();
  143. } else {
  144. StartTimeStamp = 0;
  145. }
  146. // Data Cache enabled on Primary core when MMU is enabled.
  147. ArmDisableDataCache ();
  148. // Invalidate Data cache
  149. ArmInvalidateDataCache ();
  150. // Invalidate instruction cache
  151. ArmInvalidateInstructionCache ();
  152. // Enable Instruction Caches on all cores.
  153. ArmEnableInstructionCache ();
  154. // Define the Global Variable region when we are not running in XIP
  155. if (!IS_XIP()) {
  156. if (ArmPlatformIsPrimaryCore (MpId)) {
  157. if (ArmIsMpCore()) {
  158. // Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)
  159. ArmCallSEV ();
  160. }
  161. } else {
  162. // Wait the Primay core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)
  163. ArmCallWFE ();
  164. }
  165. }
  166. // If not primary Jump to Secondary Main
  167. if (ArmPlatformIsPrimaryCore (MpId)) {
  168. // Goto primary Main.
  169. PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);
  170. } else {
  171. SecondaryMain (MpId);
  172. }
  173. // DXE Core should always load and never return
  174. ASSERT (FALSE);
  175. }