PL111Lcd.h 6.9 KB

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  1. /** @file PL111Lcd.h
  2. Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #ifndef _PL111LCD_H__
  6. #define _PL111LCD_H__
  7. /**********************************************************************
  8. *
  9. * This header file contains all the bits of the PL111 that are
  10. * platform independent.
  11. *
  12. **********************************************************************/
  13. // Controller Register Offsets
  14. #define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000)
  15. #define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004)
  16. #define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008)
  17. #define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C)
  18. #define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010)
  19. #define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014)
  20. #define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018)
  21. #define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C)
  22. #define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020)
  23. #define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024)
  24. #define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028)
  25. #define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C)
  26. #define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030)
  27. #define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200)
  28. // Identification Register Offsets
  29. #define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0)
  30. #define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4)
  31. #define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8)
  32. #define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC)
  33. #define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0)
  34. #define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4)
  35. #define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8)
  36. #define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC)
  37. #define PL111_CLCD_PERIPH_ID_0 0x11
  38. #define PL111_CLCD_PERIPH_ID_1 0x11
  39. #define PL111_CLCD_PERIPH_ID_2 0x04
  40. #define PL111_CLCD_PERIPH_ID_3 0x00
  41. #define PL111_CLCD_P_CELL_ID_0 0x0D
  42. #define PL111_CLCD_P_CELL_ID_1 0xF0
  43. #define PL111_CLCD_P_CELL_ID_2 0x05
  44. #define PL111_CLCD_P_CELL_ID_3 0xB1
  45. /**********************************************************************/
  46. // Register components (register bits)
  47. // This should make life easier to program specific settings in the different registers
  48. // by simplifying the setting up of the individual bits of each register
  49. // and then assembling the final register value.
  50. /**********************************************************************/
  51. // Register: PL111_REG_LCD_TIMING_0
  52. #define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2))
  53. // Register: PL111_REG_LCD_TIMING_1
  54. #define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1))
  55. // Register: PL111_REG_LCD_TIMING_2
  56. #define PL111_BIT_SHIFT_PCD_HI 27
  57. #define PL111_BIT_SHIFT_BCD 26
  58. #define PL111_BIT_SHIFT_CPL 16
  59. #define PL111_BIT_SHIFT_IOE 14
  60. #define PL111_BIT_SHIFT_IPC 13
  61. #define PL111_BIT_SHIFT_IHS 12
  62. #define PL111_BIT_SHIFT_IVS 11
  63. #define PL111_BIT_SHIFT_ACB 6
  64. #define PL111_BIT_SHIFT_CLKSEL 5
  65. #define PL111_BIT_SHIFT_PCD_LO 0
  66. #define PL111_BCD (1 << 26)
  67. #define PL111_IPC (1 << 13)
  68. #define PL111_IHS (1 << 12)
  69. #define PL111_IVS (1 << 11)
  70. #define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16))
  71. // Register: PL111_REG_LCD_TIMING_3
  72. #define PL111_BIT_SHIFT_LEE 16
  73. #define PL111_BIT_SHIFT_LED 0
  74. #define PL111_CTRL_WATERMARK (1 << 16)
  75. #define PL111_CTRL_LCD_V_COMP (1 << 12)
  76. #define PL111_CTRL_LCD_PWR (1 << 11)
  77. #define PL111_CTRL_BEPO (1 << 10)
  78. #define PL111_CTRL_BEBO (1 << 9)
  79. #define PL111_CTRL_BGR (1 << 8)
  80. #define PL111_CTRL_LCD_DUAL (1 << 7)
  81. #define PL111_CTRL_LCD_MONO_8 (1 << 6)
  82. #define PL111_CTRL_LCD_TFT (1 << 5)
  83. #define PL111_CTRL_LCD_BW (1 << 4)
  84. #define PL111_CTRL_LCD_1BPP (0 << 1)
  85. #define PL111_CTRL_LCD_2BPP (1 << 1)
  86. #define PL111_CTRL_LCD_4BPP (2 << 1)
  87. #define PL111_CTRL_LCD_8BPP (3 << 1)
  88. #define PL111_CTRL_LCD_16BPP (4 << 1)
  89. #define PL111_CTRL_LCD_24BPP (5 << 1)
  90. #define PL111_CTRL_LCD_16BPP_565 (6 << 1)
  91. #define PL111_CTRL_LCD_12BPP_444 (7 << 1)
  92. #define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1)
  93. #define PL111_CTRL_LCD_EN 1
  94. /**********************************************************************/
  95. // Register: PL111_REG_LCD_TIMING_0
  96. #define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24)
  97. #define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16)
  98. #define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8)
  99. #define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)
  100. // Register: PL111_REG_LCD_TIMING_1
  101. #define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24)
  102. #define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16)
  103. #define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10)
  104. #define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC)
  105. // Register: PL111_REG_LCD_TIMING_2
  106. #define PL111_BIT_MASK_PCD_HI 0xF8000000
  107. #define PL111_BIT_MASK_BCD 0x04000000
  108. #define PL111_BIT_MASK_CPL 0x03FF0000
  109. #define PL111_BIT_MASK_IOE 0x00004000
  110. #define PL111_BIT_MASK_IPC 0x00002000
  111. #define PL111_BIT_MASK_IHS 0x00001000
  112. #define PL111_BIT_MASK_IVS 0x00000800
  113. #define PL111_BIT_MASK_ACB 0x000007C0
  114. #define PL111_BIT_MASK_CLKSEL 0x00000020
  115. #define PL111_BIT_MASK_PCD_LO 0x0000001F
  116. // Register: PL111_REG_LCD_TIMING_3
  117. #define PL111_BIT_MASK_LEE 0x00010000
  118. #define PL111_BIT_MASK_LED 0x0000007F
  119. #endif /* _PL111LCD_H__ */