PL011UartLib.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468
  1. /** @file
  2. Serial I/O Port library functions with no library constructor/destructor
  3. Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
  4. Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #include <Uefi.h>
  8. #include <Library/DebugLib.h>
  9. #include <Library/IoLib.h>
  10. #include <Library/PcdLib.h>
  11. #include <Protocol/SerialIo.h>
  12. #include "PL011Uart.h"
  13. #define FRACTION_PART_SIZE_IN_BITS 6
  14. #define FRACTION_PART_MASK ((1 << FRACTION_PART_SIZE_IN_BITS) - 1)
  15. //
  16. // EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE is the only
  17. // control bit that is not supported.
  18. //
  19. STATIC CONST UINT32 mInvalidControlBits = EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;
  20. /**
  21. Initialise the serial port to the specified settings.
  22. The serial port is re-configured only if the specified settings
  23. are different from the current settings.
  24. All unspecified settings will be set to the default values.
  25. @param UartBase The base address of the serial device.
  26. @param UartClkInHz The clock in Hz for the serial device.
  27. Ignored if the PCD PL011UartInteger is not 0
  28. @param BaudRate The baud rate of the serial device. If the
  29. baud rate is not supported, the speed will be
  30. reduced to the nearest supported one and the
  31. variable's value will be updated accordingly.
  32. @param ReceiveFifoDepth The number of characters the device will
  33. buffer on input. Value of 0 will use the
  34. device's default FIFO depth.
  35. @param Parity If applicable, this is the EFI_PARITY_TYPE
  36. that is computed or checked as each character
  37. is transmitted or received. If the device
  38. does not support parity, the value is the
  39. default parity value.
  40. @param DataBits The number of data bits in each character.
  41. @param StopBits If applicable, the EFI_STOP_BITS_TYPE number
  42. of stop bits per character.
  43. If the device does not support stop bits, the
  44. value is the default stop bit value.
  45. @retval RETURN_SUCCESS All attributes were set correctly on the
  46. serial device.
  47. @retval RETURN_INVALID_PARAMETER One or more of the attributes has an
  48. unsupported value.
  49. **/
  50. RETURN_STATUS
  51. EFIAPI
  52. PL011UartInitializePort (
  53. IN UINTN UartBase,
  54. IN UINT32 UartClkInHz,
  55. IN OUT UINT64 *BaudRate,
  56. IN OUT UINT32 *ReceiveFifoDepth,
  57. IN OUT EFI_PARITY_TYPE *Parity,
  58. IN OUT UINT8 *DataBits,
  59. IN OUT EFI_STOP_BITS_TYPE *StopBits
  60. )
  61. {
  62. UINT32 LineControl;
  63. UINT32 Divisor;
  64. UINT32 Integer;
  65. UINT32 Fractional;
  66. UINT32 HardwareFifoDepth;
  67. HardwareFifoDepth = (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) \
  68. > PL011_VER_R1P4) \
  69. ? 32 : 16 ;
  70. // The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept
  71. // 1 char buffer as the minimum FIFO size. Because everything can be rounded
  72. // down, there is no maximum FIFO size.
  73. if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= HardwareFifoDepth)) {
  74. // Enable FIFO
  75. LineControl = PL011_UARTLCR_H_FEN;
  76. *ReceiveFifoDepth = HardwareFifoDepth;
  77. } else {
  78. // Disable FIFO
  79. LineControl = 0;
  80. // Nothing else to do. 1 byte FIFO is default.
  81. *ReceiveFifoDepth = 1;
  82. }
  83. //
  84. // Parity
  85. //
  86. switch (*Parity) {
  87. case DefaultParity:
  88. *Parity = NoParity;
  89. case NoParity:
  90. // Nothing to do. Parity is disabled by default.
  91. break;
  92. case EvenParity:
  93. LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_EPS);
  94. break;
  95. case OddParity:
  96. LineControl |= PL011_UARTLCR_H_PEN;
  97. break;
  98. case MarkParity:
  99. LineControl |= ( PL011_UARTLCR_H_PEN \
  100. | PL011_UARTLCR_H_SPS \
  101. | PL011_UARTLCR_H_EPS);
  102. break;
  103. case SpaceParity:
  104. LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS);
  105. break;
  106. default:
  107. return RETURN_INVALID_PARAMETER;
  108. }
  109. //
  110. // Data Bits
  111. //
  112. switch (*DataBits) {
  113. case 0:
  114. *DataBits = 8;
  115. case 8:
  116. LineControl |= PL011_UARTLCR_H_WLEN_8;
  117. break;
  118. case 7:
  119. LineControl |= PL011_UARTLCR_H_WLEN_7;
  120. break;
  121. case 6:
  122. LineControl |= PL011_UARTLCR_H_WLEN_6;
  123. break;
  124. case 5:
  125. LineControl |= PL011_UARTLCR_H_WLEN_5;
  126. break;
  127. default:
  128. return RETURN_INVALID_PARAMETER;
  129. }
  130. //
  131. // Stop Bits
  132. //
  133. switch (*StopBits) {
  134. case DefaultStopBits:
  135. *StopBits = OneStopBit;
  136. case OneStopBit:
  137. // Nothing to do. One stop bit is enabled by default.
  138. break;
  139. case TwoStopBits:
  140. LineControl |= PL011_UARTLCR_H_STP2;
  141. break;
  142. case OneFiveStopBits:
  143. // Only 1 or 2 stop bits are supported
  144. default:
  145. return RETURN_INVALID_PARAMETER;
  146. }
  147. // Don't send the LineControl value to the PL011 yet,
  148. // wait until after the Baud Rate setting.
  149. // This ensures we do not mess up the UART settings halfway through
  150. // in the rare case when there is an error with the Baud Rate.
  151. //
  152. // Baud Rate
  153. //
  154. // If PL011 Integer value has been defined then always ignore the BAUD rate
  155. if (FixedPcdGet32 (PL011UartInteger) != 0) {
  156. Integer = FixedPcdGet32 (PL011UartInteger);
  157. Fractional = FixedPcdGet32 (PL011UartFractional);
  158. } else {
  159. // If BAUD rate is zero then replace it with the system default value
  160. if (*BaudRate == 0) {
  161. *BaudRate = FixedPcdGet32 (PcdSerialBaudRate);
  162. if (*BaudRate == 0) {
  163. return RETURN_INVALID_PARAMETER;
  164. }
  165. }
  166. if (0 == UartClkInHz) {
  167. return RETURN_INVALID_PARAMETER;
  168. }
  169. Divisor = (UartClkInHz * 4) / *BaudRate;
  170. Integer = Divisor >> FRACTION_PART_SIZE_IN_BITS;
  171. Fractional = Divisor & FRACTION_PART_MASK;
  172. }
  173. //
  174. // If PL011 is already initialized, check the current settings
  175. // and re-initialize only if the settings are different.
  176. //
  177. if (((MmioRead32 (UartBase + UARTCR) & PL011_UARTCR_UARTEN) != 0) &&
  178. (MmioRead32 (UartBase + UARTLCR_H) == LineControl) &&
  179. (MmioRead32 (UartBase + UARTIBRD) == Integer) &&
  180. (MmioRead32 (UartBase + UARTFBRD) == Fractional)) {
  181. // Nothing to do - already initialized with correct attributes
  182. return RETURN_SUCCESS;
  183. }
  184. // Wait for the end of transmission
  185. while ((MmioRead32 (UartBase + UARTFR) & PL011_UARTFR_TXFE) == 0);
  186. // Disable UART: "The UARTLCR_H, UARTIBRD, and UARTFBRD registers must not be changed
  187. // when the UART is enabled"
  188. MmioWrite32 (UartBase + UARTCR, 0);
  189. // Set Baud Rate Registers
  190. MmioWrite32 (UartBase + UARTIBRD, Integer);
  191. MmioWrite32 (UartBase + UARTFBRD, Fractional);
  192. // No parity, 1 stop, no fifo, 8 data bits
  193. MmioWrite32 (UartBase + UARTLCR_H, LineControl);
  194. // Clear any pending errors
  195. MmioWrite32 (UartBase + UARTECR, 0);
  196. // Enable Tx, Rx, and UART overall
  197. MmioWrite32 (UartBase + UARTCR,
  198. PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN);
  199. return RETURN_SUCCESS;
  200. }
  201. /**
  202. Assert or deassert the control signals on a serial port.
  203. The following control signals are set according their bit settings :
  204. . Request to Send
  205. . Data Terminal Ready
  206. @param[in] UartBase UART registers base address
  207. @param[in] Control The following bits are taken into account :
  208. . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
  209. "Request To Send" control signal if this bit is
  210. equal to one/zero.
  211. . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
  212. the "Data Terminal Ready" control signal if this
  213. bit is equal to one/zero.
  214. . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
  215. the hardware loopback if this bit is equal to
  216. one/zero.
  217. . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
  218. . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
  219. disable the hardware flow control based on CTS (Clear
  220. To Send) and RTS (Ready To Send) control signals.
  221. @retval RETURN_SUCCESS The new control bits were set on the device.
  222. @retval RETURN_UNSUPPORTED The device does not support this operation.
  223. **/
  224. RETURN_STATUS
  225. EFIAPI
  226. PL011UartSetControl (
  227. IN UINTN UartBase,
  228. IN UINT32 Control
  229. )
  230. {
  231. UINT32 Bits;
  232. if (Control & (mInvalidControlBits)) {
  233. return RETURN_UNSUPPORTED;
  234. }
  235. Bits = MmioRead32 (UartBase + UARTCR);
  236. if (Control & EFI_SERIAL_REQUEST_TO_SEND) {
  237. Bits |= PL011_UARTCR_RTS;
  238. } else {
  239. Bits &= ~PL011_UARTCR_RTS;
  240. }
  241. if (Control & EFI_SERIAL_DATA_TERMINAL_READY) {
  242. Bits |= PL011_UARTCR_DTR;
  243. } else {
  244. Bits &= ~PL011_UARTCR_DTR;
  245. }
  246. if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {
  247. Bits |= PL011_UARTCR_LBE;
  248. } else {
  249. Bits &= ~PL011_UARTCR_LBE;
  250. }
  251. if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {
  252. Bits |= (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN);
  253. } else {
  254. Bits &= ~(PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN);
  255. }
  256. MmioWrite32 (UartBase + UARTCR, Bits);
  257. return RETURN_SUCCESS;
  258. }
  259. /**
  260. Retrieve the status of the control bits on a serial device.
  261. @param[in] UartBase UART registers base address
  262. @param[out] Control Status of the control bits on a serial device :
  263. . EFI_SERIAL_DATA_CLEAR_TO_SEND,
  264. EFI_SERIAL_DATA_SET_READY,
  265. EFI_SERIAL_RING_INDICATE,
  266. EFI_SERIAL_CARRIER_DETECT,
  267. EFI_SERIAL_REQUEST_TO_SEND,
  268. EFI_SERIAL_DATA_TERMINAL_READY
  269. are all related to the DTE (Data Terminal Equipment)
  270. and DCE (Data Communication Equipment) modes of
  271. operation of the serial device.
  272. . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
  273. receive buffer is empty, 0 otherwise.
  274. . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
  275. transmit buffer is empty, 0 otherwise.
  276. . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
  277. the hardware loopback is enabled (the ouput feeds the
  278. receive buffer), 0 otherwise.
  279. . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if
  280. a loopback is accomplished by software, 0 otherwise.
  281. . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
  282. one if the hardware flow control based on CTS (Clear
  283. To Send) and RTS (Ready To Send) control signals is
  284. enabled, 0 otherwise.
  285. @retval RETURN_SUCCESS The control bits were read from the serial device.
  286. **/
  287. RETURN_STATUS
  288. EFIAPI
  289. PL011UartGetControl (
  290. IN UINTN UartBase,
  291. OUT UINT32 *Control
  292. )
  293. {
  294. UINT32 FlagRegister;
  295. UINT32 ControlRegister;
  296. FlagRegister = MmioRead32 (UartBase + UARTFR);
  297. ControlRegister = MmioRead32 (UartBase + UARTCR);
  298. *Control = 0;
  299. if ((FlagRegister & PL011_UARTFR_CTS) == PL011_UARTFR_CTS) {
  300. *Control |= EFI_SERIAL_CLEAR_TO_SEND;
  301. }
  302. if ((FlagRegister & PL011_UARTFR_DSR) == PL011_UARTFR_DSR) {
  303. *Control |= EFI_SERIAL_DATA_SET_READY;
  304. }
  305. if ((FlagRegister & PL011_UARTFR_RI) == PL011_UARTFR_RI) {
  306. *Control |= EFI_SERIAL_RING_INDICATE;
  307. }
  308. if ((FlagRegister & PL011_UARTFR_DCD) == PL011_UARTFR_DCD) {
  309. *Control |= EFI_SERIAL_CARRIER_DETECT;
  310. }
  311. if ((ControlRegister & PL011_UARTCR_RTS) == PL011_UARTCR_RTS) {
  312. *Control |= EFI_SERIAL_REQUEST_TO_SEND;
  313. }
  314. if ((ControlRegister & PL011_UARTCR_DTR) == PL011_UARTCR_DTR) {
  315. *Control |= EFI_SERIAL_DATA_TERMINAL_READY;
  316. }
  317. if ((FlagRegister & PL011_UARTFR_RXFE) == PL011_UARTFR_RXFE) {
  318. *Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;
  319. }
  320. if ((FlagRegister & PL011_UARTFR_TXFE) == PL011_UARTFR_TXFE) {
  321. *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
  322. }
  323. if ((ControlRegister & (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))
  324. == (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) {
  325. *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
  326. }
  327. if ((ControlRegister & PL011_UARTCR_LBE) == PL011_UARTCR_LBE) {
  328. *Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;
  329. }
  330. return RETURN_SUCCESS;
  331. }
  332. /**
  333. Write data to serial device.
  334. @param Buffer Point of data buffer which need to be written.
  335. @param NumberOfBytes Number of output bytes which are cached in Buffer.
  336. @retval 0 Write data failed.
  337. @retval !0 Actual number of bytes written to serial device.
  338. **/
  339. UINTN
  340. EFIAPI
  341. PL011UartWrite (
  342. IN UINTN UartBase,
  343. IN UINT8 *Buffer,
  344. IN UINTN NumberOfBytes
  345. )
  346. {
  347. UINT8* CONST Final = &Buffer[NumberOfBytes];
  348. while (Buffer < Final) {
  349. // Wait until UART able to accept another char
  350. while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK));
  351. MmioWrite8 (UartBase + UARTDR, *Buffer++);
  352. }
  353. return NumberOfBytes;
  354. }
  355. /**
  356. Read data from serial device and save the data in buffer.
  357. @param Buffer Point of data buffer which need to be written.
  358. @param NumberOfBytes Number of output bytes which are cached in Buffer.
  359. @retval 0 Read data failed.
  360. @retval !0 Actual number of bytes read from serial device.
  361. **/
  362. UINTN
  363. EFIAPI
  364. PL011UartRead (
  365. IN UINTN UartBase,
  366. OUT UINT8 *Buffer,
  367. IN UINTN NumberOfBytes
  368. )
  369. {
  370. UINTN Count;
  371. for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
  372. while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0);
  373. *Buffer = MmioRead8 (UartBase + UARTDR);
  374. }
  375. return NumberOfBytes;
  376. }
  377. /**
  378. Check to see if any data is available to be read from the debug device.
  379. @retval TRUE At least one byte of data is available to be read
  380. @retval FALSE No data is available to be read
  381. **/
  382. BOOLEAN
  383. EFIAPI
  384. PL011UartPoll (
  385. IN UINTN UartBase
  386. )
  387. {
  388. return ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) == 0);
  389. }