HdLcd.h 4.1 KB

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  1. /** @file
  2. Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #ifndef HDLCD_H_
  6. #define HDLCD_H_
  7. // HDLCD Controller Register Offsets
  8. #define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)
  9. #define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)
  10. #define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)
  11. #define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)
  12. #define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)
  13. #define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)
  14. #define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)
  15. #define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)
  16. #define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)
  17. #define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)
  18. #define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)
  19. #define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)
  20. #define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)
  21. #define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)
  22. #define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)
  23. #define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)
  24. #define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)
  25. #define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)
  26. #define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)
  27. #define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)
  28. #define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)
  29. #define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)
  30. #define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)
  31. #define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)
  32. // HDLCD Values of registers
  33. // HDLCD Interrupt mask, clear and status register
  34. #define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */
  35. #define HDLCD_BUS_ERROR BIT1 /* DMA bus error */
  36. #define HDLCD_SYNC BIT2 /* Vertical sync */
  37. #define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */
  38. // CLCD_CONTROL Control register
  39. #define HDLCD_DISABLE 0
  40. #define HDLCD_ENABLE BIT0
  41. // Bus Options
  42. #define HDLCD_BURST_1 BIT0
  43. #define HDLCD_BURST_2 BIT1
  44. #define HDLCD_BURST_4 BIT2
  45. #define HDLCD_BURST_8 BIT3
  46. #define HDLCD_BURST_16 BIT4
  47. // Polarities - HIGH
  48. #define HDLCD_VSYNC_HIGH BIT0
  49. #define HDLCD_HSYNC_HIGH BIT1
  50. #define HDLCD_DATEN_HIGH BIT2
  51. #define HDLCD_DATA_HIGH BIT3
  52. #define HDLCD_PXCLK_HIGH BIT4
  53. // Polarities - LOW (for completion and for ease of understanding the hardware settings)
  54. #define HDLCD_VSYNC_LOW 0
  55. #define HDLCD_HSYNC_LOW 0
  56. #define HDLCD_DATEN_LOW 0
  57. #define HDLCD_DATA_LOW 0
  58. #define HDLCD_PXCLK_LOW 0
  59. // Default polarities
  60. #define HDLCD_DEFAULT_POLARITIES (HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | \
  61. HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | \
  62. HDLCD_VSYNC_HIGH)
  63. // Pixel Format
  64. #define HDLCD_LITTLE_ENDIAN (0 << 31)
  65. #define HDLCD_BIG_ENDIAN (1 << 31)
  66. // Number of bytes per pixel
  67. #define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)
  68. #define HDLCD_PRODUCT_ID 0x1CDC
  69. #endif /* HDLCD_H_ */