ArmMaliDp.h 11 KB

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  1. /** @file
  2. This header file contains the platform independent parts of ARM Mali DP
  3. Copyright (c) 2017-2018, Arm Limited. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef ARMMALIDP_H_
  7. #define ARMMALIDP_H_
  8. #define DP_BASE (FixedPcdGet64 (PcdArmMaliDpBase))
  9. // MALI DP Ids
  10. #define MALIDP_NOT_PRESENT 0xFFF
  11. #define MALIDP_500 0x500
  12. #define MALIDP_550 0x550
  13. #define MALIDP_650 0x650
  14. // DP500 Peripheral Ids
  15. #define DP500_ID_PART_0 0x00
  16. #define DP500_ID_DES_0 0xB
  17. #define DP500_ID_PART_1 0x5
  18. #define DP500_ID_REVISION 0x1
  19. #define DP500_ID_JEDEC 0x1
  20. #define DP500_ID_DES_1 0x3
  21. #define DP500_PERIPHERAL_ID0_VAL (DP500_ID_PART_0)
  22. #define DP500_PERIPHERAL_ID1_VAL ((DP500_ID_DES_0 << 4) \
  23. | DP500_ID_PART_1)
  24. #define DP500_PERIPHERAL_ID2_VAL ((DP500_ID_REVISION << 4) \
  25. | (DP500_ID_JEDEC << 3) \
  26. | (DP500_ID_DES_1))
  27. // DP550 Peripheral Ids
  28. #define DP550_ID_PART_0 0x50
  29. #define DP550_ID_DES_0 0xB
  30. #define DP550_ID_PART_1 0x5
  31. #define DP550_ID_REVISION 0x0
  32. #define DP550_ID_JEDEC 0x1
  33. #define DP550_ID_DES_1 0x3
  34. #define DP550_PERIPHERAL_ID0_VAL (DP550_ID_PART_0)
  35. #define DP550_PERIPHERAL_ID1_VAL ((DP550_ID_DES_0 << 4) \
  36. | DP550_ID_PART_1)
  37. #define DP550_PERIPHERAL_ID2_VAL ((DP550_ID_REVISION << 4) \
  38. | (DP550_ID_JEDEC << 3) \
  39. | (DP550_ID_DES_1))
  40. // DP650 Peripheral Ids
  41. #define DP650_ID_PART_0 0x50
  42. #define DP650_ID_DES_0 0xB
  43. #define DP650_ID_PART_1 0x6
  44. #define DP650_ID_REVISION 0x0
  45. #define DP650_ID_JEDEC 0x1
  46. #define DP650_ID_DES_1 0x3
  47. #define DP650_PERIPHERAL_ID0_VAL (DP650_ID_PART_0)
  48. #define DP650_PERIPHERAL_ID1_VAL ((DP650_ID_DES_0 << 4) \
  49. | DP650_ID_PART_1)
  50. #define DP650_PERIPHERAL_ID2_VAL ((DP650_ID_REVISION << 4) \
  51. | (DP650_ID_JEDEC << 3) \
  52. | (DP650_ID_DES_1))
  53. // Display Engine (DE) control register offsets for DP550/DP650
  54. #define DP_DE_STATUS 0x00000
  55. #define DP_DE_IRQ_SET 0x00004
  56. #define DP_DE_IRQ_MASK 0x00008
  57. #define DP_DE_IRQ_CLEAR 0x0000C
  58. #define DP_DE_CONTROL 0x00010
  59. #define DP_DE_PROG_LINE 0x00014
  60. #define DP_DE_AXI_CONTROL 0x00018
  61. #define DP_DE_AXI_QOS 0x0001C
  62. #define DP_DE_DISPLAY_FUNCTION 0x00020
  63. #define DP_DE_H_INTERVALS 0x00030
  64. #define DP_DE_V_INTERVALS 0x00034
  65. #define DP_DE_SYNC_CONTROL 0x00038
  66. #define DP_DE_HV_ACTIVESIZE 0x0003C
  67. #define DP_DE_DISPLAY_SIDEBAND 0x00040
  68. #define DP_DE_BACKGROUND_COLOR 0x00044
  69. #define DP_DE_DISPLAY_SPLIT 0x00048
  70. #define DP_DE_OUTPUT_DEPTH 0x0004C
  71. // Display Engine (DE) control register offsets for DP500
  72. #define DP_DE_DP500_CORE_ID 0x00018
  73. #define DP_DE_DP500_CONTROL 0x0000C
  74. #define DP_DE_DP500_PROG_LINE 0x00010
  75. #define DP_DE_DP500_H_INTERVALS 0x00028
  76. #define DP_DE_DP500_V_INTERVALS 0x0002C
  77. #define DP_DE_DP500_SYNC_CONTROL 0x00030
  78. #define DP_DE_DP500_HV_ACTIVESIZE 0x00034
  79. #define DP_DE_DP500_BG_COLOR_RG 0x0003C
  80. #define DP_DE_DP500_BG_COLOR_B 0x00040
  81. /* Display Engine (DE) graphics layer (LG) register offsets
  82. * NOTE: For DP500 it will be LG2.
  83. */
  84. #define DE_LG_OFFSET 0x00300
  85. #define DP_DE_LG_FORMAT (DE_LG_OFFSET)
  86. #define DP_DE_LG_CONTROL (DE_LG_OFFSET + 0x04)
  87. #define DP_DE_LG_COMPOSE (DE_LG_OFFSET + 0x08)
  88. #define DP_DE_LG_IN_SIZE (DE_LG_OFFSET + 0x0C)
  89. #define DP_DE_LG_CMP_SIZE (DE_LG_OFFSET + 0x10)
  90. #define DP_DE_LG_OFFSET (DE_LG_OFFSET + 0x14)
  91. #define DP_DE_LG_H_STRIDE (DE_LG_OFFSET + 0x18)
  92. #define DP_DE_LG_PTR_LOW (DE_LG_OFFSET + 0x1C)
  93. #define DP_DE_LG_PTR_HIGH (DE_LG_OFFSET + 0x20)
  94. #define DP_DE_LG_CHROMA_KEY (DE_LG_OFFSET + 0x2C)
  95. #define DP_DE_LG_AD_CONTROL (DE_LG_OFFSET + 0x30)
  96. #define DP_DE_LG_MMU_CONTROL (DE_LG_OFFSET + 0x48)
  97. // Display core (DC) control register offsets.
  98. #define DP_DC_OFFSET 0x0C000
  99. #define DP_DC_STATUS (DP_DC_OFFSET + 0x00)
  100. #define DP_DC_IRQ_SET (DP_DC_OFFSET + 0x04)
  101. #define DP_DC_IRQ_MASK (DP_DC_OFFSET + 0x08)
  102. #define DP_DC_IRQ_CLEAR (DP_DC_OFFSET + 0x0C)
  103. #define DP_DC_CONTROL (DP_DC_OFFSET + 0x10)
  104. #define DP_DC_CONFIG_VALID (DP_DC_OFFSET + 0x14)
  105. #define DP_DC_CORE_ID (DP_DC_OFFSET + 0x18)
  106. // DP500 has a global configuration register.
  107. #define DP_DP500_CONFIG_VALID (0xF00)
  108. // Display core ID register offsets.
  109. #define DP_DC_ID_OFFSET 0x0FF00
  110. #define DP_DC_ID_PERIPHERAL_ID4 (DP_DC_ID_OFFSET + 0xD0)
  111. #define DP_DC_CONFIGURATION_ID (DP_DC_ID_OFFSET + 0xD4)
  112. #define DP_DC_PERIPHERAL_ID0 (DP_DC_ID_OFFSET + 0xE0)
  113. #define DP_DC_PERIPHERAL_ID1 (DP_DC_ID_OFFSET + 0xE4)
  114. #define DP_DC_PERIPHERAL_ID2 (DP_DC_ID_OFFSET + 0xE8)
  115. #define DP_DC_COMPONENT_ID0 (DP_DC_ID_OFFSET + 0xF0)
  116. #define DP_DC_COMPONENT_ID1 (DP_DC_ID_OFFSET + 0xF4)
  117. #define DP_DC_COMPONENT_ID2 (DP_DC_ID_OFFSET + 0xF8)
  118. #define DP_DC_COMPONENT_ID3 (DP_DC_ID_OFFSET + 0xFC)
  119. #define DP_DP500_ID_OFFSET 0x0F00
  120. #define DP_DP500_ID_PERIPHERAL_ID4 (DP_DP500_ID_OFFSET + 0xD0)
  121. #define DP_DP500_CONFIGURATION_ID (DP_DP500_ID_OFFSET + 0xD4)
  122. #define DP_DP500_PERIPHERAL_ID0 (DP_DP500_ID_OFFSET + 0xE0)
  123. #define DP_DP500_PERIPHERAL_ID1 (DP_DP500_ID_OFFSET + 0xE4)
  124. #define DP_DP500_PERIPHERAL_ID2 (DP_DP500_ID_OFFSET + 0xE8)
  125. #define DP_DP500_COMPONENT_ID0 (DP_DP500_ID_OFFSET + 0xF0)
  126. #define DP_DP500_COMPONENT_ID1 (DP_DP500_ID_OFFSET + 0xF4)
  127. #define DP_DP500_COMPONENT_ID2 (DP_DP500_ID_OFFSET + 0xF8)
  128. #define DP_DP500_COMPONENT_ID3 (DP_DP500_ID_OFFSET + 0xFC)
  129. // Display status configuration mode activation flag
  130. #define DP_DC_STATUS_CM_ACTIVE_FLAG (0x1U << 16)
  131. // Display core control configuration mode
  132. #define DP_DC_CONTROL_SRST_ACTIVE (0x1U << 18)
  133. #define DP_DC_CONTROL_CRST_ACTIVE (0x1U << 17)
  134. #define DP_DC_CONTROL_CM_ACTIVE (0x1U << 16)
  135. #define DP_DE_DP500_CONTROL_SOFTRESET_REQ (0x1U << 16)
  136. #define DP_DE_DP500_CONTROL_CONFIG_REQ (0x1U << 17)
  137. // Display core configuration valid register
  138. #define DP_DC_CONFIG_VALID_CVAL (0x1U)
  139. // DC_CORE_ID
  140. // Display core version register PRODUCT_ID
  141. #define DP_DC_CORE_ID_SHIFT 16
  142. #define DP_DE_DP500_CORE_ID_SHIFT DP_DC_CORE_ID_SHIFT
  143. // Timing settings
  144. #define DP_DE_HBACKPORCH_SHIFT 16
  145. #define DP_DE_VBACKPORCH_SHIFT 16
  146. #define DP_DE_VSP_SHIFT 28
  147. #define DP_DE_VSYNCWIDTH_SHIFT 16
  148. #define DP_DE_HSP_SHIFT 13
  149. #define DP_DE_V_ACTIVE_SHIFT 16
  150. // BACKGROUND_COLOR
  151. #define DP_DE_BG_R_PIXEL_SHIFT 16
  152. #define DP_DE_BG_G_PIXEL_SHIFT 8
  153. //Graphics layer LG_FORMAT Pixel Format
  154. #define DP_PIXEL_FORMAT_ARGB_8888 0x8
  155. #define DP_PIXEL_FORMAT_ABGR_8888 0x9
  156. #define DP_PIXEL_FORMAT_RGBA_8888 0xA
  157. #define DP_PIXEL_FORMAT_BGRA_8888 0xB
  158. #define DP_PIXEL_FORMAT_XRGB_8888 0x10
  159. #define DP_PIXEL_FORMAT_XBGR_8888 0x11
  160. #define DP_PIXEL_FORMAT_RGBX_8888 0x12
  161. #define DP_PIXEL_FORMAT_BGRX_8888 0x13
  162. #define DP_PIXEL_FORMAT_RGB_888 0x18
  163. #define DP_PIXEL_FORMAT_BGR_888 0x19
  164. // DP500 format code are different than DP550/DP650
  165. #define DP_PIXEL_FORMAT_DP500_ARGB_8888 0x2
  166. #define DP_PIXEL_FORMAT_DP500_ABGR_8888 0x3
  167. #define DP_PIXEL_FORMAT_DP500_XRGB_8888 0x4
  168. #define DP_PIXEL_FORMAT_DP500_XBGR_8888 0x5
  169. // Graphics layer LG_PTR_LOW and LG_PTR_HIGH
  170. #define DP_DE_LG_PTR_LOW_MASK 0xFFFFFFFFU
  171. #define DP_DE_LG_PTR_HIGH_SHIFT 32
  172. // Graphics layer LG_CONTROL register characteristics
  173. #define DP_DE_LG_L_ALPHA_SHIFT 16
  174. #define DP_DE_LG_CHK_SHIFT 15
  175. #define DP_DE_LG_PMUL_SHIFT 14
  176. #define DP_DE_LG_COM_SHIFT 12
  177. #define DP_DE_LG_VFP_SHIFT 11
  178. #define DP_DE_LG_HFP_SHIFT 10
  179. #define DP_DE_LG_ROTATION_SHIFT 8
  180. #define DP_DE_LG_LAYER_BLEND_NO_BG 0x0U
  181. #define DP_DE_LG_PIXEL_BLEND_NO_BG 0x1U
  182. #define DP_DE_LG_LAYER_BLEND_BG 0x2U
  183. #define DP_DE_LG_PIXEL_BLEND_BG 0x3U
  184. #define DP_DE_LG_ENABLE 0x1U
  185. // Graphics layer LG_IN_SIZE register characteristics
  186. #define DP_DE_LG_V_IN_SIZE_SHIFT 16
  187. // Graphics layer LG_CMP_SIZE register characteristics
  188. #define DP_DE_LG_V_CMP_SIZE_SHIFT 16
  189. #define DP_DE_LG_V_OFFSET_SHIFT 16
  190. // Helper display timing macro functions.
  191. #define H_INTERVALS(Hfp, Hbp) ((Hbp << DP_DE_HBACKPORCH_SHIFT) | Hfp)
  192. #define V_INTERVALS(Vfp, Vbp) ((Vbp << DP_DE_VBACKPORCH_SHIFT) | Vfp)
  193. #define SYNC_WIDTH(Hsw, Vsw) ((Vsw << DP_DE_VSYNCWIDTH_SHIFT) | Hsw)
  194. #define HV_ACTIVE(Hor, Ver) ((Ver << DP_DE_V_ACTIVE_SHIFT) | Hor)
  195. // Helper layer graphics macros.
  196. #define FRAME_IN_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_IN_SIZE_SHIFT) | Hor)
  197. #define FRAME_CMP_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_CMP_SIZE_SHIFT) | Hor)
  198. #endif /* ARMMALIDP_H_ */