PL180Mci.h 6.8 KB

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  1. /** @file
  2. Header for the MMC Host Protocol implementation for the ARM PrimeCell PL180.
  3. Copyright (c) 2011-2012, ARM Limited. All rights reserved.
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef __PL180_MCI_H
  7. #define __PL180_MCI_H
  8. #include <Uefi.h>
  9. #include <Protocol/MmcHost.h>
  10. #include <Library/UefiLib.h>
  11. #include <Library/DebugLib.h>
  12. #include <Library/UefiBootServicesTableLib.h>
  13. #include <Library/IoLib.h>
  14. #include <Library/TimerLib.h>
  15. #include <Library/PcdLib.h>
  16. #define PL180_MCI_DXE_VERSION 0x10
  17. #define MCI_SYSCTL FixedPcdGet32 (PcdPL180MciBaseAddress)
  18. #define MCI_POWER_CONTROL_REG (MCI_SYSCTL + 0x000)
  19. #define MCI_CLOCK_CONTROL_REG (MCI_SYSCTL + 0x004)
  20. #define MCI_ARGUMENT_REG (MCI_SYSCTL + 0x008)
  21. #define MCI_COMMAND_REG (MCI_SYSCTL + 0x00C)
  22. #define MCI_RESPCMD_REG (MCI_SYSCTL + 0x010)
  23. #define MCI_RESPONSE3_REG (MCI_SYSCTL + 0x014)
  24. #define MCI_RESPONSE2_REG (MCI_SYSCTL + 0x018)
  25. #define MCI_RESPONSE1_REG (MCI_SYSCTL + 0x01C)
  26. #define MCI_RESPONSE0_REG (MCI_SYSCTL + 0x020)
  27. #define MCI_DATA_TIMER_REG (MCI_SYSCTL + 0x024)
  28. #define MCI_DATA_LENGTH_REG (MCI_SYSCTL + 0x028)
  29. #define MCI_DATA_CTL_REG (MCI_SYSCTL + 0x02C)
  30. #define MCI_DATA_COUNTER (MCI_SYSCTL + 0x030)
  31. #define MCI_STATUS_REG (MCI_SYSCTL + 0x034)
  32. #define MCI_CLEAR_STATUS_REG (MCI_SYSCTL + 0x038)
  33. #define MCI_INT0_MASK_REG (MCI_SYSCTL + 0x03C)
  34. #define MCI_INT1_MASK_REG (MCI_SYSCTL + 0x040)
  35. #define MCI_SELECT_REG (MCI_SYSCTL + 0x044)
  36. #define MCI_FIFOCOUNT_REG (MCI_SYSCTL + 0x048)
  37. #define MCI_FIFO_REG (MCI_SYSCTL + 0x080)
  38. #define MCI_PERIPH_ID_REG0 (MCI_SYSCTL + 0xFE0)
  39. #define MCI_PERIPH_ID_REG1 (MCI_SYSCTL + 0xFE4)
  40. #define MCI_PERIPH_ID_REG2 (MCI_SYSCTL + 0xFE8)
  41. #define MCI_PERIPH_ID_REG3 (MCI_SYSCTL + 0xFEC)
  42. #define MCI_PCELL_ID_REG0 (MCI_SYSCTL + 0xFF0)
  43. #define MCI_PCELL_ID_REG1 (MCI_SYSCTL + 0xFF4)
  44. #define MCI_PCELL_ID_REG2 (MCI_SYSCTL + 0xFF8)
  45. #define MCI_PCELL_ID_REG3 (MCI_SYSCTL + 0xFFC)
  46. #define MCI_PERIPH_ID0 0x80
  47. #define MCI_PERIPH_ID1 0x11
  48. #define MCI_PERIPH_ID2 0x04
  49. #define MCI_PERIPH_ID3 0x00
  50. #define MCI_PCELL_ID0 0x0D
  51. #define MCI_PCELL_ID1 0xF0
  52. #define MCI_PCELL_ID2 0x05
  53. #define MCI_PCELL_ID3 0xB1
  54. #define MCI_POWER_OFF 0
  55. #define MCI_POWER_UP BIT1
  56. #define MCI_POWER_ON (BIT1 | BIT0)
  57. #define MCI_POWER_OPENDRAIN BIT6
  58. #define MCI_POWER_ROD BIT7
  59. #define MCI_CLOCK_ENABLE BIT8
  60. #define MCI_CLOCK_POWERSAVE BIT9
  61. #define MCI_CLOCK_BYPASS BIT10
  62. #define MCI_CLOCK_WIDEBUS BIT11
  63. #define MCI_STATUS_CMD_CMDCRCFAIL BIT0
  64. #define MCI_STATUS_CMD_DATACRCFAIL BIT1
  65. #define MCI_STATUS_CMD_CMDTIMEOUT BIT2
  66. #define MCI_STATUS_CMD_DATATIMEOUT BIT3
  67. #define MCI_STATUS_CMD_TX_UNDERRUN BIT4
  68. #define MCI_STATUS_CMD_RXOVERRUN BIT5
  69. #define MCI_STATUS_CMD_RESPEND BIT6
  70. #define MCI_STATUS_CMD_SENT BIT7
  71. #define MCI_STATUS_CMD_DATAEND BIT8
  72. #define MCI_STATUS_CMD_START_BIT_ERROR BIT9
  73. #define MCI_STATUS_CMD_DATABLOCKEND BIT10
  74. #define MCI_STATUS_CMD_ACTIVE BIT11
  75. #define MCI_STATUS_CMD_TXACTIVE BIT12
  76. #define MCI_STATUS_CMD_RXACTIVE BIT13
  77. #define MCI_STATUS_CMD_TXFIFOHALFEMPTY BIT14
  78. #define MCI_STATUS_CMD_RXFIFOHALFFULL BIT15
  79. #define MCI_STATUS_CMD_TXFIFOFULL BIT16
  80. #define MCI_STATUS_CMD_RXFIFOFULL BIT17
  81. #define MCI_STATUS_CMD_TXFIFOEMPTY BIT18
  82. #define MCI_STATUS_CMD_RXFIFOEMPTY BIT19
  83. #define MCI_STATUS_CMD_TXDATAAVAILBL BIT20
  84. #define MCI_STATUS_CMD_RXDATAAVAILBL BIT21
  85. #define MCI_STATUS_TXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)
  86. #define MCI_STATUS_RXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)
  87. #define MCI_STATUS_READ_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \
  88. | MCI_STATUS_CMD_DATATIMEOUT \
  89. | MCI_STATUS_CMD_RXOVERRUN \
  90. | MCI_STATUS_CMD_START_BIT_ERROR )
  91. #define MCI_STATUS_WRITE_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \
  92. | MCI_STATUS_CMD_DATATIMEOUT \
  93. | MCI_STATUS_CMD_TX_UNDERRUN )
  94. #define MCI_STATUS_CMD_ERROR ( MCI_STATUS_CMD_CMDCRCFAIL \
  95. | MCI_STATUS_CMD_CMDTIMEOUT \
  96. | MCI_STATUS_CMD_START_BIT_ERROR )
  97. #define MCI_CLR_CMD_STATUS ( MCI_STATUS_CMD_RESPEND \
  98. | MCI_STATUS_CMD_SENT \
  99. | MCI_STATUS_CMD_ERROR )
  100. #define MCI_CLR_READ_STATUS ( MCI_STATUS_RXDONE \
  101. | MCI_STATUS_READ_ERROR )
  102. #define MCI_CLR_WRITE_STATUS ( MCI_STATUS_TXDONE \
  103. | MCI_STATUS_WRITE_ERROR )
  104. #define MCI_CLR_ALL_STATUS (BIT11 - 1)
  105. #define MCI_DATACTL_DISABLE_MASK 0xFE
  106. #define MCI_DATACTL_ENABLE BIT0
  107. #define MCI_DATACTL_CONT_TO_CARD 0
  108. #define MCI_DATACTL_CARD_TO_CONT BIT1
  109. #define MCI_DATACTL_BLOCK_TRANS 0
  110. #define MCI_DATACTL_STREAM_TRANS BIT2
  111. #define MCI_DATACTL_DMA_DISABLED 0
  112. #define MCI_DATACTL_DMA_ENABLE BIT3
  113. #define INDX_MASK 0x3F
  114. #define MCI_CPSM_WAIT_RESPONSE BIT6
  115. #define MCI_CPSM_LONG_RESPONSE BIT7
  116. #define MCI_CPSM_LONG_INTERRUPT BIT8
  117. #define MCI_CPSM_LONG_PENDING BIT9
  118. #define MCI_CPSM_ENABLE BIT10
  119. #define MCI_TRACE(txt) DEBUG ((EFI_D_BLKIO, "ARM_MCI: " txt "\n"))
  120. EFI_STATUS
  121. EFIAPI
  122. MciGetDriverName (
  123. IN EFI_COMPONENT_NAME_PROTOCOL *This,
  124. IN CHAR8 *Language,
  125. OUT CHAR16 **DriverName
  126. );
  127. EFI_STATUS
  128. EFIAPI
  129. MciGetControllerName (
  130. IN EFI_COMPONENT_NAME_PROTOCOL *This,
  131. IN EFI_HANDLE ControllerHandle,
  132. IN EFI_HANDLE ChildHandle OPTIONAL,
  133. IN CHAR8 *Language,
  134. OUT CHAR16 **ControllerName
  135. );
  136. #endif