BaseSerialPortLib16550.c 32 KB

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  1. /** @file
  2. 16550 UART Serial Port library functions
  3. (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
  4. Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #include <Base.h>
  8. #include <IndustryStandard/Pci.h>
  9. #include <Library/SerialPortLib.h>
  10. #include <Library/PcdLib.h>
  11. #include <Library/IoLib.h>
  12. #include <Library/PciLib.h>
  13. #include <Library/PlatformHookLib.h>
  14. #include <Library/BaseLib.h>
  15. //
  16. // PCI Definitions.
  17. //
  18. #define PCI_BRIDGE_32_BIT_IO_SPACE 0x01
  19. //
  20. // 16550 UART register offsets and bitfields
  21. //
  22. #define R_UART_RXBUF 0
  23. #define R_UART_TXBUF 0
  24. #define R_UART_BAUD_LOW 0
  25. #define R_UART_BAUD_HIGH 1
  26. #define R_UART_FCR 2
  27. #define B_UART_FCR_FIFOE BIT0
  28. #define B_UART_FCR_FIFO64 BIT5
  29. #define R_UART_LCR 3
  30. #define B_UART_LCR_DLAB BIT7
  31. #define R_UART_MCR 4
  32. #define B_UART_MCR_DTRC BIT0
  33. #define B_UART_MCR_RTS BIT1
  34. #define R_UART_LSR 5
  35. #define B_UART_LSR_RXRDY BIT0
  36. #define B_UART_LSR_TXRDY BIT5
  37. #define B_UART_LSR_TEMT BIT6
  38. #define R_UART_MSR 6
  39. #define B_UART_MSR_CTS BIT4
  40. #define B_UART_MSR_DSR BIT5
  41. #define B_UART_MSR_RI BIT6
  42. #define B_UART_MSR_DCD BIT7
  43. //
  44. // 4-byte structure for each PCI node in PcdSerialPciDeviceInfo
  45. //
  46. typedef struct {
  47. UINT8 Device;
  48. UINT8 Function;
  49. UINT16 PowerManagementStatusAndControlRegister;
  50. } PCI_UART_DEVICE_INFO;
  51. /**
  52. Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is read from
  53. MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O space. The
  54. parameter Offset is added to the base address of the 16550 registers that is specified
  55. by PcdSerialRegisterBase.
  56. @param Base The base address register of UART device.
  57. @param Offset The offset of the 16550 register to read.
  58. @return The value read from the 16550 register.
  59. **/
  60. UINT8
  61. SerialPortReadRegister (
  62. UINTN Base,
  63. UINTN Offset
  64. )
  65. {
  66. if (PcdGetBool (PcdSerialUseMmio)) {
  67. return MmioRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
  68. } else {
  69. return IoRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
  70. }
  71. }
  72. /**
  73. Write an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is written to
  74. MMIO space. If PcdSerialUseMmio is FALSE, then the value is written to I/O space. The
  75. parameter Offset is added to the base address of the 16550 registers that is specified
  76. by PcdSerialRegisterBase.
  77. @param Base The base address register of UART device.
  78. @param Offset The offset of the 16550 register to write.
  79. @param Value The value to write to the 16550 register specified by Offset.
  80. @return The value written to the 16550 register.
  81. **/
  82. UINT8
  83. SerialPortWriteRegister (
  84. UINTN Base,
  85. UINTN Offset,
  86. UINT8 Value
  87. )
  88. {
  89. if (PcdGetBool (PcdSerialUseMmio)) {
  90. return MmioWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), Value);
  91. } else {
  92. return IoWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), Value);
  93. }
  94. }
  95. /**
  96. Update the value of an 16-bit PCI configuration register in a PCI device. If the
  97. PCI Configuration register specified by PciAddress is already programmed with a
  98. non-zero value, then return the current value. Otherwise update the PCI configuration
  99. register specified by PciAddress with the value specified by Value and return the
  100. value programmed into the PCI configuration register. All values must be masked
  101. using the bitmask specified by Mask.
  102. @param PciAddress PCI Library address of the PCI Configuration register to update.
  103. @param Value The value to program into the PCI Configuration Register.
  104. @param Mask Bitmask of the bits to check and update in the PCI configuration register.
  105. **/
  106. UINT16
  107. SerialPortLibUpdatePciRegister16 (
  108. UINTN PciAddress,
  109. UINT16 Value,
  110. UINT16 Mask
  111. )
  112. {
  113. UINT16 CurrentValue;
  114. CurrentValue = PciRead16 (PciAddress) & Mask;
  115. if (CurrentValue != 0) {
  116. return CurrentValue;
  117. }
  118. return PciWrite16 (PciAddress, Value & Mask);
  119. }
  120. /**
  121. Update the value of an 32-bit PCI configuration register in a PCI device. If the
  122. PCI Configuration register specified by PciAddress is already programmed with a
  123. non-zero value, then return the current value. Otherwise update the PCI configuration
  124. register specified by PciAddress with the value specified by Value and return the
  125. value programmed into the PCI configuration register. All values must be masked
  126. using the bitmask specified by Mask.
  127. @param PciAddress PCI Library address of the PCI Configuration register to update.
  128. @param Value The value to program into the PCI Configuration Register.
  129. @param Mask Bitmask of the bits to check and update in the PCI configuration register.
  130. @return The Secondary bus number that is actually programed into the PCI to PCI Bridge device.
  131. **/
  132. UINT32
  133. SerialPortLibUpdatePciRegister32 (
  134. UINTN PciAddress,
  135. UINT32 Value,
  136. UINT32 Mask
  137. )
  138. {
  139. UINT32 CurrentValue;
  140. CurrentValue = PciRead32 (PciAddress) & Mask;
  141. if (CurrentValue != 0) {
  142. return CurrentValue;
  143. }
  144. return PciWrite32 (PciAddress, Value & Mask);
  145. }
  146. /**
  147. Retrieve the I/O or MMIO base address register for the PCI UART device.
  148. This function assumes Root Bus Numer is Zero, and enables I/O and MMIO in PCI UART
  149. Device if they are not already enabled.
  150. @return The base address register of the UART device.
  151. **/
  152. UINTN
  153. GetSerialRegisterBase (
  154. VOID
  155. )
  156. {
  157. UINTN PciLibAddress;
  158. UINTN BusNumber;
  159. UINTN SubordinateBusNumber;
  160. UINT32 ParentIoBase;
  161. UINT32 ParentIoLimit;
  162. UINT16 ParentMemoryBase;
  163. UINT16 ParentMemoryLimit;
  164. UINT32 IoBase;
  165. UINT32 IoLimit;
  166. UINT16 MemoryBase;
  167. UINT16 MemoryLimit;
  168. UINTN SerialRegisterBase;
  169. UINTN BarIndex;
  170. UINT32 RegisterBaseMask;
  171. PCI_UART_DEVICE_INFO *DeviceInfo;
  172. //
  173. // Get PCI Device Info
  174. //
  175. DeviceInfo = (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInfo);
  176. //
  177. // If PCI Device Info is empty, then assume fixed address UART and return PcdSerialRegisterBase
  178. //
  179. if (DeviceInfo->Device == 0xff) {
  180. return (UINTN)PcdGet64 (PcdSerialRegisterBase);
  181. }
  182. //
  183. // Assume PCI Bus 0 I/O window is 0-64KB and MMIO windows is 0-4GB
  184. //
  185. ParentMemoryBase = 0 >> 16;
  186. ParentMemoryLimit = 0xfff00000 >> 16;
  187. ParentIoBase = 0 >> 12;
  188. ParentIoLimit = 0xf000 >> 12;
  189. //
  190. // Enable I/O and MMIO in PCI Bridge
  191. // Assume Root Bus Numer is Zero.
  192. //
  193. for (BusNumber = 0; (DeviceInfo + 1)->Device != 0xff; DeviceInfo++) {
  194. //
  195. // Compute PCI Lib Address to PCI to PCI Bridge
  196. //
  197. PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);
  198. //
  199. // Retrieve and verify the bus numbers in the PCI to PCI Bridge
  200. //
  201. BusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
  202. SubordinateBusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
  203. if (BusNumber == 0 || BusNumber > SubordinateBusNumber) {
  204. return 0;
  205. }
  206. //
  207. // Retrieve and verify the I/O or MMIO decode window in the PCI to PCI Bridge
  208. //
  209. if (PcdGetBool (PcdSerialUseMmio)) {
  210. MemoryLimit = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit)) & 0xfff0;
  211. MemoryBase = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase)) & 0xfff0;
  212. //
  213. // If PCI Bridge MMIO window is disabled, then return 0
  214. //
  215. if (MemoryLimit < MemoryBase) {
  216. return 0;
  217. }
  218. //
  219. // If PCI Bridge MMIO window is not in the address range decoded by the parent PCI Bridge, then return 0
  220. //
  221. if (MemoryBase < ParentMemoryBase || MemoryBase > ParentMemoryLimit || MemoryLimit > ParentMemoryLimit) {
  222. return 0;
  223. }
  224. ParentMemoryBase = MemoryBase;
  225. ParentMemoryLimit = MemoryLimit;
  226. } else {
  227. IoLimit = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimit));
  228. if ((IoLimit & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
  229. IoLimit = IoLimit >> 4;
  230. } else {
  231. IoLimit = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimitUpper16)) << 4) | (IoLimit >> 4);
  232. }
  233. IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase));
  234. if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
  235. IoBase = IoBase >> 4;
  236. } else {
  237. IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16)) << 4) | (IoBase >> 4);
  238. }
  239. //
  240. // If PCI Bridge I/O window is disabled, then return 0
  241. //
  242. if (IoLimit < IoBase) {
  243. return 0;
  244. }
  245. //
  246. // If PCI Bridge I/O window is not in the address range decoded by the parent PCI Bridge, then return 0
  247. //
  248. if (IoBase < ParentIoBase || IoBase > ParentIoLimit || IoLimit > ParentIoLimit) {
  249. return 0;
  250. }
  251. ParentIoBase = IoBase;
  252. ParentIoLimit = IoLimit;
  253. }
  254. }
  255. //
  256. // Compute PCI Lib Address to PCI UART
  257. //
  258. PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);
  259. //
  260. // Find the first IO or MMIO BAR
  261. //
  262. RegisterBaseMask = 0xFFFFFFF0;
  263. for (BarIndex = 0; BarIndex < PCI_MAX_BAR; BarIndex ++) {
  264. SerialRegisterBase = PciRead32 (PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarIndex * 4);
  265. if (PcdGetBool (PcdSerialUseMmio) && ((SerialRegisterBase & BIT0) == 0)) {
  266. //
  267. // MMIO BAR is found
  268. //
  269. RegisterBaseMask = 0xFFFFFFF0;
  270. break;
  271. }
  272. if ((!PcdGetBool (PcdSerialUseMmio)) && ((SerialRegisterBase & BIT0) != 0)) {
  273. //
  274. // IO BAR is found
  275. //
  276. RegisterBaseMask = 0xFFFFFFF8;
  277. break;
  278. }
  279. }
  280. //
  281. // MMIO or IO BAR is not found.
  282. //
  283. if (BarIndex == PCI_MAX_BAR) {
  284. return 0;
  285. }
  286. //
  287. // Program UART BAR
  288. //
  289. SerialRegisterBase = SerialPortLibUpdatePciRegister32 (
  290. PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarIndex * 4,
  291. (UINT32)PcdGet64 (PcdSerialRegisterBase),
  292. RegisterBaseMask
  293. );
  294. //
  295. // Verify that the UART BAR is in the address range decoded by the parent PCI Bridge
  296. //
  297. if (PcdGetBool (PcdSerialUseMmio)) {
  298. if (((SerialRegisterBase >> 16) & 0xfff0) < ParentMemoryBase || ((SerialRegisterBase >> 16) & 0xfff0) > ParentMemoryLimit) {
  299. return 0;
  300. }
  301. } else {
  302. if ((SerialRegisterBase >> 12) < ParentIoBase || (SerialRegisterBase >> 12) > ParentIoLimit) {
  303. return 0;
  304. }
  305. }
  306. //
  307. // Enable I/O and MMIO in PCI UART Device if they are not already enabled
  308. //
  309. PciOr16 (
  310. PciLibAddress + PCI_COMMAND_OFFSET,
  311. PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_PCI_COMMAND_IO_SPACE
  312. );
  313. //
  314. // Force D0 state if a Power Management and Status Register is specified
  315. //
  316. if (DeviceInfo->PowerManagementStatusAndControlRegister != 0x00) {
  317. if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister) & (BIT0 | BIT1)) != 0x00) {
  318. PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister, (UINT16)~(BIT0 | BIT1));
  319. //
  320. // If PCI UART was not in D0, then make sure FIFOs are enabled, but do not reset FIFOs
  321. //
  322. SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
  323. }
  324. }
  325. //
  326. // Get PCI Device Info
  327. //
  328. DeviceInfo = (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInfo);
  329. //
  330. // Enable I/O or MMIO in PCI Bridge
  331. // Assume Root Bus Numer is Zero.
  332. //
  333. for (BusNumber = 0; (DeviceInfo + 1)->Device != 0xff; DeviceInfo++) {
  334. //
  335. // Compute PCI Lib Address to PCI to PCI Bridge
  336. //
  337. PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);
  338. //
  339. // Enable the I/O or MMIO decode windows in the PCI to PCI Bridge
  340. //
  341. PciOr16 (
  342. PciLibAddress + PCI_COMMAND_OFFSET,
  343. PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_PCI_COMMAND_IO_SPACE
  344. );
  345. //
  346. // Force D0 state if a Power Management and Status Register is specified
  347. //
  348. if (DeviceInfo->PowerManagementStatusAndControlRegister != 0x00) {
  349. if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister) & (BIT0 | BIT1)) != 0x00) {
  350. PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister, (UINT16)~(BIT0 | BIT1));
  351. }
  352. }
  353. BusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
  354. }
  355. return SerialRegisterBase;
  356. }
  357. /**
  358. Return whether the hardware flow control signal allows writing.
  359. @param SerialRegisterBase The base address register of UART device.
  360. @retval TRUE The serial port is writable.
  361. @retval FALSE The serial port is not writable.
  362. **/
  363. BOOLEAN
  364. SerialPortWritable (
  365. UINTN SerialRegisterBase
  366. )
  367. {
  368. if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
  369. if (PcdGetBool (PcdSerialDetectCable)) {
  370. //
  371. // Wait for both DSR and CTS to be set
  372. // DSR is set if a cable is connected.
  373. // CTS is set if it is ok to transmit data
  374. //
  375. // DSR CTS Description Action
  376. // === === ======================================== ========
  377. // 0 0 No cable connected. Wait
  378. // 0 1 No cable connected. Wait
  379. // 1 0 Cable connected, but not clear to send. Wait
  380. // 1 1 Cable connected, and clear to send. Transmit
  381. //
  382. return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) == (B_UART_MSR_DSR | B_UART_MSR_CTS));
  383. } else {
  384. //
  385. // Wait for both DSR and CTS to be set OR for DSR to be clear.
  386. // DSR is set if a cable is connected.
  387. // CTS is set if it is ok to transmit data
  388. //
  389. // DSR CTS Description Action
  390. // === === ======================================== ========
  391. // 0 0 No cable connected. Transmit
  392. // 0 1 No cable connected. Transmit
  393. // 1 0 Cable connected, but not clear to send. Wait
  394. // 1 1 Cable connected, and clear to send. Transmit
  395. //
  396. return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) != (B_UART_MSR_DSR));
  397. }
  398. }
  399. return TRUE;
  400. }
  401. /**
  402. Initialize the serial device hardware.
  403. If no initialization is required, then return RETURN_SUCCESS.
  404. If the serial device was successfully initialized, then return RETURN_SUCCESS.
  405. If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
  406. @retval RETURN_SUCCESS The serial device was initialized.
  407. @retval RETURN_DEVICE_ERROR The serial device could not be initialized.
  408. **/
  409. RETURN_STATUS
  410. EFIAPI
  411. SerialPortInitialize (
  412. VOID
  413. )
  414. {
  415. RETURN_STATUS Status;
  416. UINTN SerialRegisterBase;
  417. UINT32 Divisor;
  418. UINT32 CurrentDivisor;
  419. BOOLEAN Initialized;
  420. //
  421. // Perform platform specific initialization required to enable use of the 16550 device
  422. // at the location specified by PcdSerialUseMmio and PcdSerialRegisterBase.
  423. //
  424. Status = PlatformHookSerialPortInitialize ();
  425. if (RETURN_ERROR (Status)) {
  426. return Status;
  427. }
  428. //
  429. // Calculate divisor for baud generator
  430. // Ref_Clk_Rate / Baud_Rate / 16
  431. //
  432. Divisor = PcdGet32 (PcdSerialClockRate) / (PcdGet32 (PcdSerialBaudRate) * 16);
  433. if ((PcdGet32 (PcdSerialClockRate) % (PcdGet32 (PcdSerialBaudRate) * 16)) >= PcdGet32 (PcdSerialBaudRate) * 8) {
  434. Divisor++;
  435. }
  436. //
  437. // Get the base address of the serial port in either I/O or MMIO space
  438. //
  439. SerialRegisterBase = GetSerialRegisterBase ();
  440. if (SerialRegisterBase ==0) {
  441. return RETURN_DEVICE_ERROR;
  442. }
  443. //
  444. // See if the serial port is already initialized
  445. //
  446. Initialized = TRUE;
  447. if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & 0x3F) != (PcdGet8 (PcdSerialLineControl) & 0x3F)) {
  448. Initialized = FALSE;
  449. }
  450. SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) | B_UART_LCR_DLAB));
  451. CurrentDivisor = SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_HIGH) << 8;
  452. CurrentDivisor |= (UINT32) SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_LOW);
  453. SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & ~B_UART_LCR_DLAB));
  454. if (CurrentDivisor != Divisor) {
  455. Initialized = FALSE;
  456. }
  457. if (Initialized) {
  458. return RETURN_SUCCESS;
  459. }
  460. //
  461. // Wait for the serial port to be ready.
  462. // Verify that both the transmit FIFO and the shift register are empty.
  463. //
  464. while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
  465. //
  466. // Configure baud rate
  467. //
  468. SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);
  469. SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));
  470. SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));
  471. //
  472. // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
  473. // Strip reserved bits from PcdSerialLineControl
  474. //
  475. SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(PcdGet8 (PcdSerialLineControl) & 0x3F));
  476. //
  477. // Enable and reset FIFOs
  478. // Strip reserved bits from PcdSerialFifoControl
  479. //
  480. SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00);
  481. SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
  482. //
  483. // Set RTS and DTR in Modem Control Register(MCR)
  484. //
  485. SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR,
  486. EFI_SERIAL_REQUEST_TO_SEND | EFI_SERIAL_DATA_TERMINAL_READY);
  487. return RETURN_SUCCESS;
  488. }
  489. /**
  490. Write data from buffer to serial device.
  491. Writes NumberOfBytes data bytes from Buffer to the serial device.
  492. The number of bytes actually written to the serial device is returned.
  493. If the return value is less than NumberOfBytes, then the write operation failed.
  494. If Buffer is NULL, then ASSERT().
  495. If NumberOfBytes is zero, then return 0.
  496. @param Buffer Pointer to the data buffer to be written.
  497. @param NumberOfBytes Number of bytes to written to the serial device.
  498. @retval 0 NumberOfBytes is 0.
  499. @retval >0 The number of bytes written to the serial device.
  500. If this value is less than NumberOfBytes, then the write operation failed.
  501. **/
  502. UINTN
  503. EFIAPI
  504. SerialPortWrite (
  505. IN UINT8 *Buffer,
  506. IN UINTN NumberOfBytes
  507. )
  508. {
  509. UINTN SerialRegisterBase;
  510. UINTN Result;
  511. UINTN Index;
  512. UINTN FifoSize;
  513. if (Buffer == NULL) {
  514. return 0;
  515. }
  516. SerialRegisterBase = GetSerialRegisterBase ();
  517. if (SerialRegisterBase ==0) {
  518. return 0;
  519. }
  520. if (NumberOfBytes == 0) {
  521. //
  522. // Flush the hardware
  523. //
  524. //
  525. // Wait for both the transmit FIFO and shift register empty.
  526. //
  527. while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
  528. //
  529. // Wait for the hardware flow control signal
  530. //
  531. while (!SerialPortWritable (SerialRegisterBase));
  532. return 0;
  533. }
  534. //
  535. // Compute the maximum size of the Tx FIFO
  536. //
  537. FifoSize = 1;
  538. if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFOE) != 0) {
  539. if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFO64) == 0) {
  540. FifoSize = 16;
  541. } else {
  542. FifoSize = PcdGet32 (PcdSerialExtendedTxFifoSize);
  543. }
  544. }
  545. Result = NumberOfBytes;
  546. while (NumberOfBytes != 0) {
  547. //
  548. // Wait for the serial port to be ready, to make sure both the transmit FIFO
  549. // and shift register empty.
  550. //
  551. while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_TEMT) == 0);
  552. //
  553. // Fill then entire Tx FIFO
  554. //
  555. for (Index = 0; Index < FifoSize && NumberOfBytes != 0; Index++, NumberOfBytes--, Buffer++) {
  556. //
  557. // Wait for the hardware flow control signal
  558. //
  559. while (!SerialPortWritable (SerialRegisterBase));
  560. //
  561. // Write byte to the transmit buffer.
  562. //
  563. SerialPortWriteRegister (SerialRegisterBase, R_UART_TXBUF, *Buffer);
  564. }
  565. }
  566. return Result;
  567. }
  568. /**
  569. Reads data from a serial device into a buffer.
  570. @param Buffer Pointer to the data buffer to store the data read from the serial device.
  571. @param NumberOfBytes Number of bytes to read from the serial device.
  572. @retval 0 NumberOfBytes is 0.
  573. @retval >0 The number of bytes read from the serial device.
  574. If this value is less than NumberOfBytes, then the read operation failed.
  575. **/
  576. UINTN
  577. EFIAPI
  578. SerialPortRead (
  579. OUT UINT8 *Buffer,
  580. IN UINTN NumberOfBytes
  581. )
  582. {
  583. UINTN SerialRegisterBase;
  584. UINTN Result;
  585. UINT8 Mcr;
  586. if (NULL == Buffer) {
  587. return 0;
  588. }
  589. SerialRegisterBase = GetSerialRegisterBase ();
  590. if (SerialRegisterBase ==0) {
  591. return 0;
  592. }
  593. Mcr = (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS);
  594. for (Result = 0; NumberOfBytes-- != 0; Result++, Buffer++) {
  595. //
  596. // Wait for the serial port to have some data.
  597. //
  598. while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) == 0) {
  599. if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
  600. //
  601. // Set RTS to let the peer send some data
  602. //
  603. SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(Mcr | B_UART_MCR_RTS));
  604. }
  605. }
  606. if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
  607. //
  608. // Clear RTS to prevent peer from sending data
  609. //
  610. SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
  611. }
  612. //
  613. // Read byte from the receive buffer.
  614. //
  615. *Buffer = SerialPortReadRegister (SerialRegisterBase, R_UART_RXBUF);
  616. }
  617. return Result;
  618. }
  619. /**
  620. Polls a serial device to see if there is any data waiting to be read.
  621. Polls a serial device to see if there is any data waiting to be read.
  622. If there is data waiting to be read from the serial device, then TRUE is returned.
  623. If there is no data waiting to be read from the serial device, then FALSE is returned.
  624. @retval TRUE Data is waiting to be read from the serial device.
  625. @retval FALSE There is no data waiting to be read from the serial device.
  626. **/
  627. BOOLEAN
  628. EFIAPI
  629. SerialPortPoll (
  630. VOID
  631. )
  632. {
  633. UINTN SerialRegisterBase;
  634. SerialRegisterBase = GetSerialRegisterBase ();
  635. if (SerialRegisterBase ==0) {
  636. return FALSE;
  637. }
  638. //
  639. // Read the serial port status
  640. //
  641. if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) != 0) {
  642. if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
  643. //
  644. // Clear RTS to prevent peer from sending data
  645. //
  646. SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS));
  647. }
  648. return TRUE;
  649. }
  650. if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
  651. //
  652. // Set RTS to let the peer send some data
  653. //
  654. SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) | B_UART_MCR_RTS));
  655. }
  656. return FALSE;
  657. }
  658. /**
  659. Sets the control bits on a serial device.
  660. @param Control Sets the bits of Control that are settable.
  661. @retval RETURN_SUCCESS The new control bits were set on the serial device.
  662. @retval RETURN_UNSUPPORTED The serial device does not support this operation.
  663. @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
  664. **/
  665. RETURN_STATUS
  666. EFIAPI
  667. SerialPortSetControl (
  668. IN UINT32 Control
  669. )
  670. {
  671. UINTN SerialRegisterBase;
  672. UINT8 Mcr;
  673. //
  674. // First determine the parameter is invalid.
  675. //
  676. if ((Control & (~(EFI_SERIAL_REQUEST_TO_SEND | EFI_SERIAL_DATA_TERMINAL_READY |
  677. EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE))) != 0) {
  678. return RETURN_UNSUPPORTED;
  679. }
  680. SerialRegisterBase = GetSerialRegisterBase ();
  681. if (SerialRegisterBase ==0) {
  682. return RETURN_UNSUPPORTED;
  683. }
  684. //
  685. // Read the Modem Control Register.
  686. //
  687. Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR);
  688. Mcr &= (~(B_UART_MCR_DTRC | B_UART_MCR_RTS));
  689. if ((Control & EFI_SERIAL_DATA_TERMINAL_READY) == EFI_SERIAL_DATA_TERMINAL_READY) {
  690. Mcr |= B_UART_MCR_DTRC;
  691. }
  692. if ((Control & EFI_SERIAL_REQUEST_TO_SEND) == EFI_SERIAL_REQUEST_TO_SEND) {
  693. Mcr |= B_UART_MCR_RTS;
  694. }
  695. //
  696. // Write the Modem Control Register.
  697. //
  698. SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
  699. return RETURN_SUCCESS;
  700. }
  701. /**
  702. Retrieve the status of the control bits on a serial device.
  703. @param Control A pointer to return the current control signals from the serial device.
  704. @retval RETURN_SUCCESS The control bits were read from the serial device.
  705. @retval RETURN_UNSUPPORTED The serial device does not support this operation.
  706. @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
  707. **/
  708. RETURN_STATUS
  709. EFIAPI
  710. SerialPortGetControl (
  711. OUT UINT32 *Control
  712. )
  713. {
  714. UINTN SerialRegisterBase;
  715. UINT8 Msr;
  716. UINT8 Mcr;
  717. UINT8 Lsr;
  718. SerialRegisterBase = GetSerialRegisterBase ();
  719. if (SerialRegisterBase ==0) {
  720. return RETURN_UNSUPPORTED;
  721. }
  722. *Control = 0;
  723. //
  724. // Read the Modem Status Register.
  725. //
  726. Msr = SerialPortReadRegister (SerialRegisterBase, R_UART_MSR);
  727. if ((Msr & B_UART_MSR_CTS) == B_UART_MSR_CTS) {
  728. *Control |= EFI_SERIAL_CLEAR_TO_SEND;
  729. }
  730. if ((Msr & B_UART_MSR_DSR) == B_UART_MSR_DSR) {
  731. *Control |= EFI_SERIAL_DATA_SET_READY;
  732. }
  733. if ((Msr & B_UART_MSR_RI) == B_UART_MSR_RI) {
  734. *Control |= EFI_SERIAL_RING_INDICATE;
  735. }
  736. if ((Msr & B_UART_MSR_DCD) == B_UART_MSR_DCD) {
  737. *Control |= EFI_SERIAL_CARRIER_DETECT;
  738. }
  739. //
  740. // Read the Modem Control Register.
  741. //
  742. Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR);
  743. if ((Mcr & B_UART_MCR_DTRC) == B_UART_MCR_DTRC) {
  744. *Control |= EFI_SERIAL_DATA_TERMINAL_READY;
  745. }
  746. if ((Mcr & B_UART_MCR_RTS) == B_UART_MCR_RTS) {
  747. *Control |= EFI_SERIAL_REQUEST_TO_SEND;
  748. }
  749. if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
  750. *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
  751. }
  752. //
  753. // Read the Line Status Register.
  754. //
  755. Lsr = SerialPortReadRegister (SerialRegisterBase, R_UART_LSR);
  756. if ((Lsr & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) == (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) {
  757. *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
  758. }
  759. if ((Lsr & B_UART_LSR_RXRDY) == 0) {
  760. *Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;
  761. }
  762. return RETURN_SUCCESS;
  763. }
  764. /**
  765. Sets the baud rate, receive FIFO depth, transmit/receive time out, parity,
  766. data bits, and stop bits on a serial device.
  767. @param BaudRate The requested baud rate. A BaudRate value of 0 will use the
  768. device's default interface speed.
  769. On output, the value actually set.
  770. @param ReceiveFifoDepth The requested depth of the FIFO on the receive side of the
  771. serial interface. A ReceiveFifoDepth value of 0 will use
  772. the device's default FIFO depth.
  773. On output, the value actually set.
  774. @param Timeout The requested time out for a single character in microseconds.
  775. This timeout applies to both the transmit and receive side of the
  776. interface. A Timeout value of 0 will use the device's default time
  777. out value.
  778. On output, the value actually set.
  779. @param Parity The type of parity to use on this serial device. A Parity value of
  780. DefaultParity will use the device's default parity value.
  781. On output, the value actually set.
  782. @param DataBits The number of data bits to use on the serial device. A DataBits
  783. value of 0 will use the device's default data bit setting.
  784. On output, the value actually set.
  785. @param StopBits The number of stop bits to use on this serial device. A StopBits
  786. value of DefaultStopBits will use the device's default number of
  787. stop bits.
  788. On output, the value actually set.
  789. @retval RETURN_SUCCESS The new attributes were set on the serial device.
  790. @retval RETURN_UNSUPPORTED The serial device does not support this operation.
  791. @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value.
  792. @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
  793. **/
  794. RETURN_STATUS
  795. EFIAPI
  796. SerialPortSetAttributes (
  797. IN OUT UINT64 *BaudRate,
  798. IN OUT UINT32 *ReceiveFifoDepth,
  799. IN OUT UINT32 *Timeout,
  800. IN OUT EFI_PARITY_TYPE *Parity,
  801. IN OUT UINT8 *DataBits,
  802. IN OUT EFI_STOP_BITS_TYPE *StopBits
  803. )
  804. {
  805. UINTN SerialRegisterBase;
  806. UINT32 SerialBaudRate;
  807. UINTN Divisor;
  808. UINT8 Lcr;
  809. UINT8 LcrData;
  810. UINT8 LcrParity;
  811. UINT8 LcrStop;
  812. SerialRegisterBase = GetSerialRegisterBase ();
  813. if (SerialRegisterBase ==0) {
  814. return RETURN_UNSUPPORTED;
  815. }
  816. //
  817. // Check for default settings and fill in actual values.
  818. //
  819. if (*BaudRate == 0) {
  820. *BaudRate = PcdGet32 (PcdSerialBaudRate);
  821. }
  822. SerialBaudRate = (UINT32) *BaudRate;
  823. if (*DataBits == 0) {
  824. LcrData = (UINT8) (PcdGet8 (PcdSerialLineControl) & 0x3);
  825. *DataBits = LcrData + 5;
  826. } else {
  827. if ((*DataBits < 5) || (*DataBits > 8)) {
  828. return RETURN_INVALID_PARAMETER;
  829. }
  830. //
  831. // Map 5..8 to 0..3
  832. //
  833. LcrData = (UINT8) (*DataBits - (UINT8) 5);
  834. }
  835. if (*Parity == DefaultParity) {
  836. LcrParity = (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 3) & 0x7);
  837. switch (LcrParity) {
  838. case 0:
  839. *Parity = NoParity;
  840. break;
  841. case 3:
  842. *Parity = EvenParity;
  843. break;
  844. case 1:
  845. *Parity = OddParity;
  846. break;
  847. case 7:
  848. *Parity = SpaceParity;
  849. break;
  850. case 5:
  851. *Parity = MarkParity;
  852. break;
  853. default:
  854. break;
  855. }
  856. } else {
  857. switch (*Parity) {
  858. case NoParity:
  859. LcrParity = 0;
  860. break;
  861. case EvenParity:
  862. LcrParity = 3;
  863. break;
  864. case OddParity:
  865. LcrParity = 1;
  866. break;
  867. case SpaceParity:
  868. LcrParity = 7;
  869. break;
  870. case MarkParity:
  871. LcrParity = 5;
  872. break;
  873. default:
  874. return RETURN_INVALID_PARAMETER;
  875. }
  876. }
  877. if (*StopBits == DefaultStopBits) {
  878. LcrStop = (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 2) & 0x1);
  879. switch (LcrStop) {
  880. case 0:
  881. *StopBits = OneStopBit;
  882. break;
  883. case 1:
  884. if (*DataBits == 5) {
  885. *StopBits = OneFiveStopBits;
  886. } else {
  887. *StopBits = TwoStopBits;
  888. }
  889. break;
  890. default:
  891. break;
  892. }
  893. } else {
  894. switch (*StopBits) {
  895. case OneStopBit:
  896. LcrStop = 0;
  897. break;
  898. case OneFiveStopBits:
  899. case TwoStopBits:
  900. LcrStop = 1;
  901. break;
  902. default:
  903. return RETURN_INVALID_PARAMETER;
  904. }
  905. }
  906. //
  907. // Calculate divisor for baud generator
  908. // Ref_Clk_Rate / Baud_Rate / 16
  909. //
  910. Divisor = PcdGet32 (PcdSerialClockRate) / (SerialBaudRate * 16);
  911. if ((PcdGet32 (PcdSerialClockRate) % (SerialBaudRate * 16)) >= SerialBaudRate * 8) {
  912. Divisor++;
  913. }
  914. //
  915. // Configure baud rate
  916. //
  917. SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);
  918. SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));
  919. SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));
  920. //
  921. // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
  922. // Strip reserved bits from line control value
  923. //
  924. Lcr = (UINT8) ((LcrParity << 3) | (LcrStop << 2) | LcrData);
  925. SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8) (Lcr & 0x3F));
  926. return RETURN_SUCCESS;
  927. }