ArmPlatformHelper.S 4.2 KB

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  1. //
  2. // Copyright (c) 2022, Google LLC. All rights reserved.
  3. //
  4. // SPDX-License-Identifier: BSD-2-Clause-Patent
  5. //
  6. //
  7. #include <AsmMacroIoLibV8.h>
  8. .macro mov_i, reg:req, imm:req
  9. movz \reg, :abs_g1:\imm
  10. movk \reg, :abs_g0_nc:\imm
  11. .endm
  12. .set MAIR_DEV_nGnRnE, 0x00
  13. .set MAIR_MEM_NC, 0x44
  14. .set MAIR_MEM_WT, 0xbb
  15. .set MAIR_MEM_WBWA, 0xff
  16. .set mairval, MAIR_DEV_nGnRnE | (MAIR_MEM_NC << 8) | (MAIR_MEM_WT << 16) | (MAIR_MEM_WBWA << 24)
  17. .set TCR_TG0_4KB, 0x0 << 14
  18. .set TCR_TG1_4KB, 0x2 << 30
  19. .set TCR_IPS_SHIFT, 32
  20. .set TCR_EPD1, 0x1 << 23
  21. .set TCR_SH_INNER, 0x3 << 12
  22. .set TCR_RGN_OWB, 0x1 << 10
  23. .set TCR_RGN_IWB, 0x1 << 8
  24. .set tcrval, TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1 | TCR_RGN_OWB
  25. .set tcrval, tcrval | TCR_RGN_IWB | TCR_SH_INNER
  26. .set SCTLR_ELx_I, 0x1 << 12
  27. .set SCTLR_ELx_SA, 0x1 << 3
  28. .set SCTLR_ELx_C, 0x1 << 2
  29. .set SCTLR_ELx_M, 0x1 << 0
  30. .set SCTLR_EL1_SPAN, 0x1 << 23
  31. .set SCTLR_EL1_WXN, 0x1 << 19
  32. .set SCTLR_EL1_SED, 0x1 << 8
  33. .set SCTLR_EL1_ITD, 0x1 << 7
  34. .set SCTLR_EL1_RES1, (0x1 << 11) | (0x1 << 20) | (0x1 << 22) | (0x1 << 28) | (0x1 << 29)
  35. .set sctlrval, SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_EL1_ITD | SCTLR_EL1_SED
  36. .set sctlrval, sctlrval | SCTLR_ELx_I | SCTLR_EL1_SPAN | SCTLR_EL1_RES1
  37. ASM_FUNC(ArmPlatformPeiBootAction)
  38. #ifdef CAVIUM_ERRATUM_27456
  39. /*
  40. * On Cavium ThunderX, using non-global mappings that are executable at EL1
  41. * results in I-cache corruption. So just avoid the early ID mapping there.
  42. *
  43. * MIDR implementor 0x43
  44. * MIDR part numbers 0xA1 0xA2 (but not 0xAF)
  45. */
  46. mrs x0, midr_el1 // read the MIDR into X0
  47. ubfx x1, x0, #24, #8 // grab implementor id
  48. ubfx x0, x0, #7, #9 // grab part number bits [11:3]
  49. cmp x1, #0x43 // compare implementor id
  50. ccmp x0, #0xA0 >> 3, #0, eq // compare part# bits [11:3]
  51. b.eq 0f
  52. #endif
  53. mrs x0, CurrentEL // check current exception level
  54. tbnz x0, #3, 0f // omit early ID map if above EL1
  55. mov_i x0, mairval
  56. mov_i x1, tcrval
  57. adrp x2, idmap
  58. orr x2, x2, #0xff << 48 // set non-zero ASID
  59. mov_i x3, sctlrval
  60. mrs x6, id_aa64mmfr0_el1 // get the supported PA range
  61. and x6, x6, #0xf // isolate PArange bits
  62. cmp x6, #6 // 0b0110 == 52 bits
  63. sub x6, x6, #1 // subtract 1
  64. cinc x6, x6, ne // add back 1 unless PArange == 52 bits
  65. bfi x1, x6, #32, #3 // copy updated PArange into TCR_EL1.IPS
  66. cmp x6, #3 // 0b0011 == 42 bits
  67. sub x6, x6, #1 // subtract 1
  68. cinc x6, x6, lt // add back 1 unless VA range >= 42
  69. mov x7, #32
  70. sub x6, x7, x6, lsl #2 // T0SZ for PArange != 42
  71. mov x7, #64 - 42 // T0SZ for PArange == 42
  72. csel x6, x6, x7, ne
  73. orr x1, x1, x6 // set T0SZ field in TCR
  74. cmp x6, #64 - 40 // VA size < 40 bits?
  75. add x4, x2, #0x1000 // advance to level 1 descriptor
  76. csel x2, x4, x2, gt
  77. msr mair_el1, x0 // set up the 1:1 mapping
  78. msr tcr_el1, x1
  79. msr ttbr0_el1, x2
  80. isb
  81. tlbi vmalle1 // invalidate any cached translations
  82. ic iallu // invalidate the I-cache
  83. dsb nsh
  84. isb
  85. msr sctlr_el1, x3 // enable MMU and caches
  86. isb
  87. 0:b ArmEnableVFP // enable SIMD before entering C code
  88. //UINTN
  89. //ArmPlatformGetCorePosition (
  90. // IN UINTN MpId
  91. // );
  92. // With this function: CorePos = (ClusterId * 4) + CoreId
  93. ASM_FUNC(ArmPlatformGetCorePosition)
  94. mov x0, xzr
  95. ret
  96. //UINTN
  97. //ArmPlatformGetPrimaryCoreMpId (
  98. // VOID
  99. // );
  100. ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
  101. MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
  102. ret
  103. //UINTN
  104. //ArmPlatformIsPrimaryCore (
  105. // IN UINTN MpId
  106. // );
  107. ASM_FUNC(ArmPlatformIsPrimaryCore)
  108. mov x0, #1
  109. ret