XhciReg.h 19 KB

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  1. /** @file
  2. This file contains the register definition of XHCI host controller.
  3. Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef _EFI_XHCI_REG_H_
  7. #define _EFI_XHCI_REG_H_
  8. #define PCI_IF_XHCI 0x30
  9. //
  10. // PCI Configuration Registers
  11. //
  12. #define XHC_BAR_INDEX 0x00
  13. #define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset
  14. #define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask
  15. #define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset
  16. #define USB_HUB_CLASS_CODE 0x09
  17. #define USB_HUB_SUBCLASS_CODE 0x00
  18. #define XHC_CAP_USB_LEGACY 0x01
  19. #define XHC_CAP_USB_DEBUG 0x0A
  20. #define XHC_CAP_USB_SUPPORTED_PROTOCOL 0x02
  21. // ============================================//
  22. // XHCI register offset //
  23. // ============================================//
  24. //
  25. // Capability registers offset
  26. //
  27. #define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
  28. #define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
  29. #define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
  30. #define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
  31. #define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
  32. #define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
  33. #define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
  34. #define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
  35. //
  36. // Operational registers offset
  37. //
  38. #define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
  39. #define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
  40. #define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
  41. #define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
  42. #define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
  43. #define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
  44. #define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
  45. #define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
  46. //
  47. // Runtime registers offset
  48. //
  49. #define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
  50. #define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
  51. #define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
  52. #define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
  53. #define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
  54. #define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
  55. //
  56. // Debug registers offset
  57. //
  58. #define XHC_DC_DCCTRL 0x20
  59. #define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
  60. #define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
  61. //
  62. // xHCI Supported Protocol Capability
  63. //
  64. #define XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB2 0x02
  65. #define XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB3 0x03
  66. #define XHC_SUPPORTED_PROTOCOL_NAME_STRING_OFFSET 0x04
  67. #define XHC_SUPPORTED_PROTOCOL_NAME_STRING_VALUE 0x20425355
  68. #define XHC_SUPPORTED_PROTOCOL_DW2_OFFSET 0x08
  69. #define XHC_SUPPORTED_PROTOCOL_PSI_OFFSET 0x10
  70. #define XHC_SUPPORTED_PROTOCOL_USB2_HIGH_SPEED_PSIM 480
  71. #define XHC_SUPPORTED_PROTOCOL_USB2_LOW_SPEED_PSIM 1500
  72. #pragma pack (1)
  73. typedef struct {
  74. UINT8 MaxSlots; // Number of Device Slots
  75. UINT16 MaxIntrs : 11; // Number of Interrupters
  76. UINT16 Rsvd : 5;
  77. UINT8 MaxPorts; // Number of Ports
  78. } HCSPARAMS1;
  79. //
  80. // Structural Parameters 1 Register Bitmap Definition
  81. //
  82. typedef union {
  83. UINT32 Dword;
  84. HCSPARAMS1 Data;
  85. } XHC_HCSPARAMS1;
  86. typedef struct {
  87. UINT32 Ist : 4; // Isochronous Scheduling Threshold
  88. UINT32 Erst : 4; // Event Ring Segment Table Max
  89. UINT32 Rsvd : 13;
  90. UINT32 ScratchBufHi : 5; // Max Scratchpad Buffers Hi
  91. UINT32 Spr : 1; // Scratchpad Restore
  92. UINT32 ScratchBufLo : 5; // Max Scratchpad Buffers Lo
  93. } HCSPARAMS2;
  94. //
  95. // Structural Parameters 2 Register Bitmap Definition
  96. //
  97. typedef union {
  98. UINT32 Dword;
  99. HCSPARAMS2 Data;
  100. } XHC_HCSPARAMS2;
  101. typedef struct {
  102. UINT16 Ac64 : 1; // 64-bit Addressing Capability
  103. UINT16 Bnc : 1; // BW Negotiation Capability
  104. UINT16 Csz : 1; // Context Size
  105. UINT16 Ppc : 1; // Port Power Control
  106. UINT16 Pind : 1; // Port Indicators
  107. UINT16 Lhrc : 1; // Light HC Reset Capability
  108. UINT16 Ltc : 1; // Latency Tolerance Messaging Capability
  109. UINT16 Nss : 1; // No Secondary SID Support
  110. UINT16 Pae : 1; // Parse All Event Data
  111. UINT16 Rsvd : 3;
  112. UINT16 MaxPsaSize : 4; // Maximum Primary Stream Array Size
  113. UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer
  114. } HCCPARAMS;
  115. //
  116. // Capability Parameters Register Bitmap Definition
  117. //
  118. typedef union {
  119. UINT32 Dword;
  120. HCCPARAMS Data;
  121. } XHC_HCCPARAMS;
  122. //
  123. // xHCI Supported Protocol Cabability
  124. //
  125. typedef struct {
  126. UINT8 CapId;
  127. UINT8 NextExtCapReg;
  128. UINT8 RevMinor;
  129. UINT8 RevMajor;
  130. } SUPPORTED_PROTOCOL_DW0;
  131. typedef union {
  132. UINT32 Dword;
  133. SUPPORTED_PROTOCOL_DW0 Data;
  134. } XHC_SUPPORTED_PROTOCOL_DW0;
  135. typedef struct {
  136. UINT32 NameString;
  137. } XHC_SUPPORTED_PROTOCOL_DW1;
  138. typedef struct {
  139. UINT8 CompPortOffset;
  140. UINT8 CompPortCount;
  141. UINT16 ProtocolDef : 12;
  142. UINT16 Psic : 4;
  143. } SUPPORTED_PROTOCOL_DW2;
  144. typedef union {
  145. UINT32 Dword;
  146. SUPPORTED_PROTOCOL_DW2 Data;
  147. } XHC_SUPPORTED_PROTOCOL_DW2;
  148. typedef struct {
  149. UINT16 Psiv : 4;
  150. UINT16 Psie : 2;
  151. UINT16 Plt : 2;
  152. UINT16 Pfd : 1;
  153. UINT16 RsvdP : 5;
  154. UINT16 Lp : 2;
  155. UINT16 Psim;
  156. } SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID;
  157. typedef union {
  158. UINT32 Dword;
  159. SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID Data;
  160. } XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID;
  161. #pragma pack ()
  162. //
  163. // Register Bit Definition
  164. //
  165. #define XHC_USBCMD_RUN BIT0 // Run/Stop
  166. #define XHC_USBCMD_RESET BIT1 // Host Controller Reset
  167. #define XHC_USBCMD_INTE BIT2 // Interrupter Enable
  168. #define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
  169. #define XHC_USBSTS_HALT BIT0 // Host Controller Halted
  170. #define XHC_USBSTS_HSE BIT2 // Host System Error
  171. #define XHC_USBSTS_EINT BIT3 // Event Interrupt
  172. #define XHC_USBSTS_PCD BIT4 // Port Change Detect
  173. #define XHC_USBSTS_SSS BIT8 // Save State Status
  174. #define XHC_USBSTS_RSS BIT9 // Restore State Status
  175. #define XHC_USBSTS_SRE BIT10 // Save/Restore Error
  176. #define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
  177. #define XHC_USBSTS_HCE BIT12 // Host Controller Error
  178. #define XHC_PAGESIZE_MASK 0xFFFF // Page Size
  179. #define XHC_CRCR_RCS BIT0 // Ring Cycle State
  180. #define XHC_CRCR_CS BIT1 // Command Stop
  181. #define XHC_CRCR_CA BIT2 // Command Abort
  182. #define XHC_CRCR_CRR BIT3 // Command Ring Running
  183. #define XHC_CONFIG_MASK 0xFF // Command Ring Running
  184. #define XHC_PORTSC_CCS BIT0 // Current Connect Status
  185. #define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
  186. #define XHC_PORTSC_OCA BIT3 // Over-current Active
  187. #define XHC_PORTSC_RESET BIT4 // Port Reset
  188. #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
  189. #define XHC_PORTSC_PP BIT9 // Port Power
  190. #define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
  191. #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
  192. #define XHC_PORTSC_CSC BIT17 // Connect Status Change
  193. #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
  194. #define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
  195. #define XHC_PORTSC_OCC BIT20 // Over-Current Change
  196. #define XHC_PORTSC_PRC BIT21 // Port Reset Change
  197. #define XHC_PORTSC_PLC BIT22 // Port Link State Change
  198. #define XHC_PORTSC_CEC BIT23 // Port Config Error Change
  199. #define XHC_PORTSC_CAS BIT24 // Cold Attach Status
  200. #define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
  201. #define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
  202. #define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
  203. #define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
  204. #define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
  205. #define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
  206. #define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
  207. #define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
  208. #define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
  209. #define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
  210. #define XHC_IMAN_IP BIT0 // Interrupt Pending
  211. #define XHC_IMAN_IE BIT1 // Interrupt Enable
  212. #define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
  213. #define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
  214. //
  215. // Hub Class Feature Selector for Clear Port Feature Request
  216. // It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.
  217. // For more details, Please refer to USB 3.0 Spec Table 10-7.
  218. //
  219. typedef enum {
  220. Usb3PortBHPortReset = 28,
  221. Usb3PortBHPortResetChange = 29
  222. } XHC_PORT_FEATURE;
  223. //
  224. // Structure to map the hardware port states to the
  225. // UEFI's port states.
  226. //
  227. typedef struct {
  228. UINT32 HwState;
  229. UINT16 UefiState;
  230. } USB_PORT_STATE_MAP;
  231. //
  232. // Structure to map the hardware port states to feature selector for clear port feature request.
  233. //
  234. typedef struct {
  235. UINT32 HwState;
  236. UINT16 Selector;
  237. } USB_CLEAR_PORT_MAP;
  238. /**
  239. Read 1-byte width XHCI capability register.
  240. @param Xhc The XHCI Instance.
  241. @param Offset The offset of the 1-byte width capability register.
  242. @return The register content read.
  243. @retval If err, return 0xFFFF.
  244. **/
  245. UINT8
  246. XhcReadCapReg8 (
  247. IN USB_XHCI_INSTANCE *Xhc,
  248. IN UINT32 Offset
  249. );
  250. /**
  251. Read 4-bytes width XHCI capability register.
  252. @param Xhc The XHCI Instance.
  253. @param Offset The offset of the 4-bytes width capability register.
  254. @return The register content read.
  255. @retval If err, return 0xFFFFFFFF.
  256. **/
  257. UINT32
  258. XhcReadCapReg (
  259. IN USB_XHCI_INSTANCE *Xhc,
  260. IN UINT32 Offset
  261. );
  262. /**
  263. Read 4-bytes width XHCI Operational register.
  264. @param Xhc The XHCI Instance.
  265. @param Offset The offset of the 4-bytes width operational register.
  266. @return The register content read.
  267. @retval If err, return 0xFFFFFFFF.
  268. **/
  269. UINT32
  270. XhcReadOpReg (
  271. IN USB_XHCI_INSTANCE *Xhc,
  272. IN UINT32 Offset
  273. );
  274. /**
  275. Write the data to the 4-bytes width XHCI operational register.
  276. @param Xhc The XHCI Instance.
  277. @param Offset The offset of the 4-bytes width operational register.
  278. @param Data The data to write.
  279. **/
  280. VOID
  281. XhcWriteOpReg (
  282. IN USB_XHCI_INSTANCE *Xhc,
  283. IN UINT32 Offset,
  284. IN UINT32 Data
  285. );
  286. /**
  287. Read XHCI runtime register.
  288. @param Xhc The XHCI Instance.
  289. @param Offset The offset of the runtime register.
  290. @return The register content read
  291. **/
  292. UINT32
  293. XhcReadRuntimeReg (
  294. IN USB_XHCI_INSTANCE *Xhc,
  295. IN UINT32 Offset
  296. );
  297. /**
  298. Write the data to the XHCI runtime register.
  299. @param Xhc The XHCI Instance.
  300. @param Offset The offset of the runtime register.
  301. @param Data The data to write.
  302. **/
  303. VOID
  304. XhcWriteRuntimeReg (
  305. IN USB_XHCI_INSTANCE *Xhc,
  306. IN UINT32 Offset,
  307. IN UINT32 Data
  308. );
  309. /**
  310. Write the data to the XHCI door bell register.
  311. @param Xhc The XHCI Instance.
  312. @param Offset The offset of the door bell register.
  313. @param Data The data to write.
  314. **/
  315. VOID
  316. XhcWriteDoorBellReg (
  317. IN USB_XHCI_INSTANCE *Xhc,
  318. IN UINT32 Offset,
  319. IN UINT32 Data
  320. );
  321. /**
  322. Set one bit of the operational register while keeping other bits.
  323. @param Xhc The XHCI Instance.
  324. @param Offset The offset of the operational register.
  325. @param Bit The bit mask of the register to set.
  326. **/
  327. VOID
  328. XhcSetOpRegBit (
  329. IN USB_XHCI_INSTANCE *Xhc,
  330. IN UINT32 Offset,
  331. IN UINT32 Bit
  332. );
  333. /**
  334. Clear one bit of the operational register while keeping other bits.
  335. @param Xhc The XHCI Instance.
  336. @param Offset The offset of the operational register.
  337. @param Bit The bit mask of the register to clear.
  338. **/
  339. VOID
  340. XhcClearOpRegBit (
  341. IN USB_XHCI_INSTANCE *Xhc,
  342. IN UINT32 Offset,
  343. IN UINT32 Bit
  344. );
  345. /**
  346. Wait the operation register's bit as specified by Bit
  347. to be set (or clear).
  348. @param Xhc The XHCI Instance.
  349. @param Offset The offset of the operational register.
  350. @param Bit The bit of the register to wait for.
  351. @param WaitToSet Wait the bit to set or clear.
  352. @param Timeout The time to wait before abort (in millisecond, ms).
  353. @retval EFI_SUCCESS The bit successfully changed by host controller.
  354. @retval EFI_TIMEOUT The time out occurred.
  355. **/
  356. EFI_STATUS
  357. XhcWaitOpRegBit (
  358. IN USB_XHCI_INSTANCE *Xhc,
  359. IN UINT32 Offset,
  360. IN UINT32 Bit,
  361. IN BOOLEAN WaitToSet,
  362. IN UINT32 Timeout
  363. );
  364. /**
  365. Read XHCI runtime register.
  366. @param Xhc The XHCI Instance.
  367. @param Offset The offset of the runtime register.
  368. @return The register content read
  369. **/
  370. UINT32
  371. XhcReadRuntimeReg (
  372. IN USB_XHCI_INSTANCE *Xhc,
  373. IN UINT32 Offset
  374. );
  375. /**
  376. Write the data to the XHCI runtime register.
  377. @param Xhc The XHCI Instance.
  378. @param Offset The offset of the runtime register.
  379. @param Data The data to write.
  380. **/
  381. VOID
  382. XhcWriteRuntimeReg (
  383. IN USB_XHCI_INSTANCE *Xhc,
  384. IN UINT32 Offset,
  385. IN UINT32 Data
  386. );
  387. /**
  388. Set one bit of the runtime register while keeping other bits.
  389. @param Xhc The XHCI Instance.
  390. @param Offset The offset of the runtime register.
  391. @param Bit The bit mask of the register to set.
  392. **/
  393. VOID
  394. XhcSetRuntimeRegBit (
  395. IN USB_XHCI_INSTANCE *Xhc,
  396. IN UINT32 Offset,
  397. IN UINT32 Bit
  398. );
  399. /**
  400. Clear one bit of the runtime register while keeping other bits.
  401. @param Xhc The XHCI Instance.
  402. @param Offset The offset of the runtime register.
  403. @param Bit The bit mask of the register to set.
  404. **/
  405. VOID
  406. XhcClearRuntimeRegBit (
  407. IN USB_XHCI_INSTANCE *Xhc,
  408. IN UINT32 Offset,
  409. IN UINT32 Bit
  410. );
  411. /**
  412. Read XHCI extended capability register.
  413. @param Xhc The XHCI Instance.
  414. @param Offset The offset of the extended capability register.
  415. @return The register content read
  416. **/
  417. UINT32
  418. XhcReadExtCapReg (
  419. IN USB_XHCI_INSTANCE *Xhc,
  420. IN UINT32 Offset
  421. );
  422. /**
  423. Whether the XHCI host controller is halted.
  424. @param Xhc The XHCI Instance.
  425. @retval TRUE The controller is halted.
  426. @retval FALSE It isn't halted.
  427. **/
  428. BOOLEAN
  429. XhcIsHalt (
  430. IN USB_XHCI_INSTANCE *Xhc
  431. );
  432. /**
  433. Whether system error occurred.
  434. @param Xhc The XHCI Instance.
  435. @retval TRUE System error happened.
  436. @retval FALSE No system error.
  437. **/
  438. BOOLEAN
  439. XhcIsSysError (
  440. IN USB_XHCI_INSTANCE *Xhc
  441. );
  442. /**
  443. Reset the XHCI host controller.
  444. @param Xhc The XHCI Instance.
  445. @param Timeout Time to wait before abort (in millisecond, ms).
  446. @retval EFI_SUCCESS The XHCI host controller is reset.
  447. @return Others Failed to reset the XHCI before Timeout.
  448. **/
  449. EFI_STATUS
  450. XhcResetHC (
  451. IN USB_XHCI_INSTANCE *Xhc,
  452. IN UINT32 Timeout
  453. );
  454. /**
  455. Halt the XHCI host controller.
  456. @param Xhc The XHCI Instance.
  457. @param Timeout Time to wait before abort (in millisecond, ms).
  458. @return EFI_SUCCESS The XHCI host controller is halt.
  459. @return EFI_TIMEOUT Failed to halt the XHCI before Timeout.
  460. **/
  461. EFI_STATUS
  462. XhcHaltHC (
  463. IN USB_XHCI_INSTANCE *Xhc,
  464. IN UINT32 Timeout
  465. );
  466. /**
  467. Set the XHCI host controller to run.
  468. @param Xhc The XHCI Instance.
  469. @param Timeout Time to wait before abort (in millisecond, ms).
  470. @return EFI_SUCCESS The XHCI host controller is running.
  471. @return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.
  472. **/
  473. EFI_STATUS
  474. XhcRunHC (
  475. IN USB_XHCI_INSTANCE *Xhc,
  476. IN UINT32 Timeout
  477. );
  478. /**
  479. Calculate the offset of the XHCI capability.
  480. @param Xhc The XHCI Instance.
  481. @param CapId The XHCI Capability ID.
  482. @return The offset of XHCI legacy support capability register.
  483. **/
  484. UINT32
  485. XhcGetCapabilityAddr (
  486. IN USB_XHCI_INSTANCE *Xhc,
  487. IN UINT8 CapId
  488. );
  489. /**
  490. Calculate the offset of the xHCI Supported Protocol Capability.
  491. @param Xhc The XHCI Instance.
  492. @param MajorVersion The USB Major Version in xHCI Support Protocol Capability Field
  493. @return The offset of xHCI Supported Protocol capability register.
  494. **/
  495. UINT32
  496. XhcGetSupportedProtocolCapabilityAddr (
  497. IN USB_XHCI_INSTANCE *Xhc,
  498. IN UINT8 MajorVersion
  499. );
  500. /**
  501. Find PortSpeed value match case in XHCI Supported Protocol Capability
  502. @param Xhc The XHCI Instance.
  503. @param PortSpeed The Port Speed Field in USB PortSc register
  504. @param PortNumber The Port Number (0-indexed)
  505. @return The USB Port Speed.
  506. **/
  507. UINT16
  508. XhcCheckUsbPortSpeedUsedPsic (
  509. IN USB_XHCI_INSTANCE *Xhc,
  510. IN UINT8 PortSpeed,
  511. IN UINT8 PortNumber
  512. );
  513. #endif