IoApicLib.c 5.2 KB

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  1. /** @file
  2. I/O APIC library.
  3. I/O APIC library assumes I/O APIC is enabled. It does not
  4. handles cases where I/O APIC is disabled.
  5. Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
  6. SPDX-License-Identifier: BSD-2-Clause-Patent
  7. **/
  8. #include <Base.h>
  9. #include <Library/IoApicLib.h>
  10. #include <Library/DebugLib.h>
  11. #include <Library/PcdLib.h>
  12. #include <Library/IoLib.h>
  13. #include <Library/LocalApicLib.h>
  14. #include <Register/IoApic.h>
  15. /**
  16. Read a 32-bit I/O APIC register.
  17. If Index is >= 0x100, then ASSERT().
  18. @param Index Specifies the I/O APIC register to read.
  19. @return The 32-bit value read from the I/O APIC register specified by Index.
  20. **/
  21. UINT32
  22. EFIAPI
  23. IoApicRead (
  24. IN UINTN Index
  25. )
  26. {
  27. ASSERT (Index < 0x100);
  28. MmioWrite8 (PcdGet32 (PcdIoApicBaseAddress) + IOAPIC_INDEX_OFFSET, (UINT8)Index);
  29. return MmioRead32 (PcdGet32 (PcdIoApicBaseAddress) + IOAPIC_DATA_OFFSET);
  30. }
  31. /**
  32. Write a 32-bit I/O APIC register.
  33. If Index is >= 0x100, then ASSERT().
  34. @param Index Specifies the I/O APIC register to write.
  35. @param Value Specifies the value to write to the I/O APIC register specified by Index.
  36. @return The 32-bit value written to I/O APIC register specified by Index.
  37. **/
  38. UINT32
  39. EFIAPI
  40. IoApicWrite (
  41. IN UINTN Index,
  42. IN UINT32 Value
  43. )
  44. {
  45. ASSERT (Index < 0x100);
  46. MmioWrite8 (PcdGet32 (PcdIoApicBaseAddress) + IOAPIC_INDEX_OFFSET, (UINT8)Index);
  47. return MmioWrite32 (PcdGet32 (PcdIoApicBaseAddress) + IOAPIC_DATA_OFFSET, Value);
  48. }
  49. /**
  50. Set the interrupt mask of an I/O APIC interrupt.
  51. If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
  52. @param Irq Specifies the I/O APIC interrupt to enable or disable.
  53. @param Enable If TRUE, then enable the I/O APIC interrupt specified by Irq.
  54. If FALSE, then disable the I/O APIC interrupt specified by Irq.
  55. **/
  56. VOID
  57. EFIAPI
  58. IoApicEnableInterrupt (
  59. IN UINTN Irq,
  60. IN BOOLEAN Enable
  61. )
  62. {
  63. IO_APIC_VERSION_REGISTER Version;
  64. IO_APIC_REDIRECTION_TABLE_ENTRY Entry;
  65. Version.Uint32 = IoApicRead (IO_APIC_VERSION_REGISTER_INDEX);
  66. ASSERT (Version.Bits.MaximumRedirectionEntry < 0xF0);
  67. ASSERT (Irq <= Version.Bits.MaximumRedirectionEntry);
  68. Entry.Uint32.Low = IoApicRead (IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX + Irq * 2);
  69. Entry.Bits.Mask = Enable ? 0 : 1;
  70. IoApicWrite (IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX + Irq * 2, Entry.Uint32.Low);
  71. }
  72. /**
  73. Configures an I/O APIC interrupt.
  74. Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical
  75. mode to the Local APIC of the currntly executing CPU. The default state of the
  76. entry is for the interrupt to be disabled (masked). IoApicEnableInterrupts() must
  77. be used to enable(unmask) the I/O APIC Interrupt.
  78. If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
  79. If Vector >= 0x100, then ASSERT().
  80. If DeliveryMode is not supported, then ASSERT().
  81. @param Irq Specifies the I/O APIC interrupt to initialize.
  82. @param Vector The 8-bit interrupt vector associated with the I/O APIC
  83. Interrupt. Must be in the range 0x10..0xFE.
  84. @param DeliveryMode A 3-bit value that specifies how the recept of the I/O APIC
  85. interrupt is handled. The only supported values are:
  86. 0: IO_APIC_DELIVERY_MODE_FIXED
  87. 1: IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY
  88. 2: IO_APIC_DELIVERY_MODE_SMI
  89. 4: IO_APIC_DELIVERY_MODE_NMI
  90. 5: IO_APIC_DELIVERY_MODE_INIT
  91. 7: IO_APIC_DELIVERY_MODE_EXTINT
  92. @param LevelTriggered TRUE specifies a level triggered interrupt.
  93. FALSE specifies an edge triggered interrupt.
  94. @param AssertionLevel TRUE specified an active high interrupt.
  95. FALSE specifies an active low interrupt.
  96. **/
  97. VOID
  98. EFIAPI
  99. IoApicConfigureInterrupt (
  100. IN UINTN Irq,
  101. IN UINTN Vector,
  102. IN UINTN DeliveryMode,
  103. IN BOOLEAN LevelTriggered,
  104. IN BOOLEAN AssertionLevel
  105. )
  106. {
  107. IO_APIC_VERSION_REGISTER Version;
  108. IO_APIC_REDIRECTION_TABLE_ENTRY Entry;
  109. Version.Uint32 = IoApicRead (IO_APIC_VERSION_REGISTER_INDEX);
  110. ASSERT (Version.Bits.MaximumRedirectionEntry < 0xF0);
  111. ASSERT (Irq <= Version.Bits.MaximumRedirectionEntry);
  112. ASSERT (Vector <= 0xFF);
  113. ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
  114. Entry.Uint32.Low = IoApicRead (IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX + Irq * 2);
  115. Entry.Bits.Vector = (UINT8)Vector;
  116. Entry.Bits.DeliveryMode = (UINT32)DeliveryMode;
  117. Entry.Bits.DestinationMode = 0;
  118. Entry.Bits.Polarity = AssertionLevel ? 0 : 1;
  119. Entry.Bits.TriggerMode = LevelTriggered ? 1 : 0;
  120. Entry.Bits.Mask = 1;
  121. IoApicWrite (IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX + Irq * 2, Entry.Uint32.Low);
  122. Entry.Uint32.High = IoApicRead (IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX + Irq * 2 + 1);
  123. Entry.Bits.DestinationID = GetApicId ();
  124. IoApicWrite (IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX + Irq * 2 + 1, Entry.Uint32.High);
  125. }