IoApicLib.h 3.2 KB

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  1. /** @file
  2. Public include file for I/O APIC library.
  3. I/O APIC library assumes I/O APIC is enabled. It does not
  4. handles cases where I/O APIC is disabled.
  5. Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
  6. SPDX-License-Identifier: BSD-2-Clause-Patent
  7. **/
  8. #ifndef __IO_APIC_LIB_H__
  9. #define __IO_APIC_LIB_H__
  10. /**
  11. Read a 32-bit I/O APIC register.
  12. If Index is >= 0x100, then ASSERT().
  13. @param Index Specifies the I/O APIC register to read.
  14. @return The 32-bit value read from the I/O APIC register specified by Index.
  15. **/
  16. UINT32
  17. EFIAPI
  18. IoApicRead (
  19. IN UINTN Index
  20. );
  21. /**
  22. Write a 32-bit I/O APIC register.
  23. If Index is >= 0x100, then ASSERT().
  24. @param Index Specifies the I/O APIC register to write.
  25. @param Value Specifies the value to write to the I/O APIC register specified by Index.
  26. @return The 32-bit value written to I/O APIC register specified by Index.
  27. **/
  28. UINT32
  29. EFIAPI
  30. IoApicWrite (
  31. IN UINTN Index,
  32. IN UINT32 Value
  33. );
  34. /**
  35. Set the interrupt mask of an I/O APIC interrupt.
  36. If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
  37. @param Irq Specifies the I/O APIC interrupt to enable or disable.
  38. @param Enable If TRUE, then enable the I/O APIC interrupt specified by Irq.
  39. If FALSE, then disable the I/O APIC interrupt specified by Irq.
  40. **/
  41. VOID
  42. EFIAPI
  43. IoApicEnableInterrupt (
  44. IN UINTN Irq,
  45. IN BOOLEAN Enable
  46. );
  47. /**
  48. Configures an I/O APIC interrupt.
  49. Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical
  50. mode to the Local APIC of the currntly executing CPU. The default state of the
  51. entry is for the interrupt to be disabled (masked). IoApicEnableInterrupts() must
  52. be used to enable(unmask) the I/O APIC Interrupt.
  53. If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
  54. If Vector >= 0x100, then ASSERT().
  55. If DeliveryMode is not supported, then ASSERT().
  56. @param Irq Specifies the I/O APIC interrupt to initialize.
  57. @param Vector The 8-bit interrupt vector associated with the I/O APIC
  58. Interrupt. Must be in the range 0x10..0xFE.
  59. @param DeliveryMode A 3-bit value that specifies how the recept of the I/O APIC
  60. interrupt is handled. The only supported values are:
  61. 0: IO_APIC_DELIVERY_MODE_FIXED
  62. 1: IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY
  63. 2: IO_APIC_DELIVERY_MODE_SMI
  64. 4: IO_APIC_DELIVERY_MODE_NMI
  65. 5: IO_APIC_DELIVERY_MODE_INIT
  66. 7: IO_APIC_DELIVERY_MODE_EXTINT
  67. @param LevelTriggered TRUE specifies a level triggered interrupt.
  68. FALSE specifies an edge triggered interrupt.
  69. @param AssertionLevel TRUE specified an active high interrupt.
  70. FALSE specifies an active low interrupt.
  71. **/
  72. VOID
  73. EFIAPI
  74. IoApicConfigureInterrupt (
  75. IN UINTN Irq,
  76. IN UINTN Vector,
  77. IN UINTN DeliveryMode,
  78. IN BOOLEAN LevelTriggered,
  79. IN BOOLEAN AssertionLevel
  80. );
  81. #endif