FspGlobalData.h 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104
  1. /** @file
  2. Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #ifndef _FSP_GLOBAL_DATA_H_
  6. #define _FSP_GLOBAL_DATA_H_
  7. #include <FspEas.h>
  8. #define FSP_IN_API_MODE 0
  9. #define FSP_IN_DISPATCH_MODE 1
  10. #define FSP_GLOBAL_DATA_VERSION 0x3
  11. #pragma pack(1)
  12. typedef enum {
  13. TempRamInitApiIndex,
  14. FspInitApiIndex,
  15. NotifyPhaseApiIndex,
  16. FspMemoryInitApiIndex,
  17. TempRamExitApiIndex,
  18. FspSiliconInitApiIndex,
  19. FspMultiPhaseSiInitApiIndex,
  20. FspSmmInitApiIndex,
  21. FspMultiPhaseMemInitApiIndex,
  22. FspApiIndexMax
  23. } FSP_API_INDEX;
  24. typedef struct {
  25. VOID *DataPtr;
  26. UINTN MicrocodeRegionBase;
  27. UINTN MicrocodeRegionSize;
  28. UINTN CodeRegionBase;
  29. UINTN CodeRegionSize;
  30. UINTN Reserved;
  31. } FSP_PLAT_DATA;
  32. #define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')
  33. #define FSP_PERFORMANCE_DATA_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', 'F')
  34. #define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF
  35. typedef struct {
  36. UINT32 Signature;
  37. UINT8 Version;
  38. UINT8 Reserved1[3];
  39. ///
  40. /// Offset 0x08
  41. ///
  42. UINTN CoreStack;
  43. VOID *SmmInitUpdPtr;
  44. ///
  45. /// IA32: Offset 0x10; X64: Offset 0x18
  46. ///
  47. UINT32 StatusCode;
  48. UINT8 ApiIdx;
  49. ///
  50. /// 0: FSP in API mode; 1: FSP in DISPATCH mode
  51. ///
  52. UINT8 FspMode;
  53. UINT8 OnSeparateStack;
  54. UINT8 Reserved2;
  55. UINT32 NumberOfPhases;
  56. UINT32 PhasesExecuted;
  57. UINT32 Reserved3[8];
  58. ///
  59. /// IA32: Offset 0x40; X64: Offset 0x48
  60. /// Start of UINTN and pointer section
  61. /// All UINTN and pointer members are put in this section
  62. /// for maintaining natural alignment for both IA32 and X64 builds.
  63. ///
  64. FSP_PLAT_DATA PlatformData;
  65. VOID *TempRamInitUpdPtr;
  66. VOID *MemoryInitUpdPtr;
  67. VOID *SiliconInitUpdPtr;
  68. ///
  69. /// IA32: Offset 0x64; X64: Offset 0x90
  70. /// To store function parameters pointer
  71. /// so it can be retrieved after stack switched.
  72. ///
  73. VOID *FunctionParameterPtr;
  74. FSP_INFO_HEADER *FspInfoHeader;
  75. VOID *UpdDataPtr;
  76. VOID *FspHobListPtr;
  77. VOID *VariableRequestParameterPtr;
  78. ///
  79. /// End of UINTN and pointer section
  80. /// At this point, next field offset must be either *0h or *8h to
  81. /// meet natural alignment requirement.
  82. ///
  83. UINT8 Reserved4[16];
  84. UINT32 PerfSig;
  85. UINT16 PerfLen;
  86. UINT16 Reserved5;
  87. UINT32 PerfIdx;
  88. UINT32 Reserved6;
  89. UINT64 PerfData[32];
  90. } FSP_GLOBAL_DATA;
  91. #pragma pack()
  92. #endif