SmramSaveState.c 31 KB

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  1. /** @file
  2. Provides services to access SMRAM Save State Map
  3. Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <PiSmm.h>
  7. #include <Library/SmmCpuFeaturesLib.h>
  8. #include <Library/BaseLib.h>
  9. #include <Library/BaseMemoryLib.h>
  10. #include <Library/SmmServicesTableLib.h>
  11. #include <Library/DebugLib.h>
  12. #include "PiSmmCpuDxeSmm.h"
  13. typedef struct {
  14. UINT64 Signature; // Offset 0x00
  15. UINT16 Reserved1; // Offset 0x08
  16. UINT16 Reserved2; // Offset 0x0A
  17. UINT16 Reserved3; // Offset 0x0C
  18. UINT16 SmmCs; // Offset 0x0E
  19. UINT16 SmmDs; // Offset 0x10
  20. UINT16 SmmSs; // Offset 0x12
  21. UINT16 SmmOtherSegment; // Offset 0x14
  22. UINT16 Reserved4; // Offset 0x16
  23. UINT64 Reserved5; // Offset 0x18
  24. UINT64 Reserved6; // Offset 0x20
  25. UINT64 Reserved7; // Offset 0x28
  26. UINT64 SmmGdtPtr; // Offset 0x30
  27. UINT32 SmmGdtSize; // Offset 0x38
  28. UINT32 Reserved8; // Offset 0x3C
  29. UINT64 Reserved9; // Offset 0x40
  30. UINT64 Reserved10; // Offset 0x48
  31. UINT16 Reserved11; // Offset 0x50
  32. UINT16 Reserved12; // Offset 0x52
  33. UINT32 Reserved13; // Offset 0x54
  34. UINT64 Reserved14; // Offset 0x58
  35. } PROCESSOR_SMM_DESCRIPTOR;
  36. extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;
  37. //
  38. // EFER register LMA bit
  39. //
  40. #define LMA BIT10
  41. ///
  42. /// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
  43. ///
  44. #define SMM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)
  45. ///
  46. /// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE
  47. ///
  48. #define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }
  49. ///
  50. /// Structure used to describe a range of registers
  51. ///
  52. typedef struct {
  53. EFI_SMM_SAVE_STATE_REGISTER Start;
  54. EFI_SMM_SAVE_STATE_REGISTER End;
  55. UINTN Length;
  56. } CPU_SMM_SAVE_STATE_REGISTER_RANGE;
  57. ///
  58. /// Structure used to build a lookup table to retrieve the widths and offsets
  59. /// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
  60. ///
  61. #define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1
  62. #define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX 2
  63. #define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX 3
  64. #define SMM_SAVE_STATE_REGISTER_MAX_INDEX 4
  65. typedef struct {
  66. UINT8 Width32;
  67. UINT8 Width64;
  68. UINT16 Offset32;
  69. UINT16 Offset64Lo;
  70. UINT16 Offset64Hi;
  71. BOOLEAN Writeable;
  72. } CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
  73. ///
  74. /// Structure used to build a lookup table for the IOMisc width information
  75. ///
  76. typedef struct {
  77. UINT8 Width;
  78. EFI_SMM_SAVE_STATE_IO_WIDTH IoWidth;
  79. } CPU_SMM_SAVE_STATE_IO_WIDTH;
  80. ///
  81. /// Variables from SMI Handler
  82. ///
  83. X86_ASSEMBLY_PATCH_LABEL gPatchSmbase;
  84. X86_ASSEMBLY_PATCH_LABEL gPatchSmiStack;
  85. X86_ASSEMBLY_PATCH_LABEL gPatchSmiCr3;
  86. extern volatile UINT8 gcSmiHandlerTemplate[];
  87. extern CONST UINT16 gcSmiHandlerSize;
  88. //
  89. // Variables used by SMI Handler
  90. //
  91. IA32_DESCRIPTOR gSmiHandlerIdtr;
  92. ///
  93. /// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
  94. /// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
  95. ///
  96. CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {
  97. SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO),
  98. SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP),
  99. SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4),
  100. { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0}
  101. };
  102. ///
  103. /// Lookup table used to retrieve the widths and offsets associated with each
  104. /// supported EFI_SMM_SAVE_STATE_REGISTER value
  105. ///
  106. CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
  107. { 0, 0, 0, 0, 0, FALSE }, // Reserved
  108. //
  109. // Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol.
  110. //
  111. { 4, 4, SMM_CPU_OFFSET (x86.SMMRevId), SMM_CPU_OFFSET (x64.SMMRevId), 0, FALSE }, // SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX = 1
  112. { 4, 4, SMM_CPU_OFFSET (x86.IOMisc), SMM_CPU_OFFSET (x64.IOMisc), 0, FALSE }, // SMM_SAVE_STATE_REGISTER_IOMISC_INDEX = 2
  113. { 4, 8, SMM_CPU_OFFSET (x86.IOMemAddr), SMM_CPU_OFFSET (x64.IOMemAddr), SMM_CPU_OFFSET (x64.IOMemAddr) + 4, FALSE }, // SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX = 3
  114. //
  115. // CPU Save State registers defined in PI SMM CPU Protocol.
  116. //
  117. { 0, 8, 0, SMM_CPU_OFFSET (x64.GdtBaseLoDword), SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
  118. { 0, 8, 0, SMM_CPU_OFFSET (x64.IdtBaseLoDword), SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
  119. { 0, 8, 0, SMM_CPU_OFFSET (x64.LdtBaseLoDword), SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
  120. { 0, 0, 0, 0, 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
  121. { 0, 0, 0, 0, 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
  122. { 0, 0, 0, 0, 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
  123. { 0, 0, 0, 0, 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
  124. { 4, 4, SMM_CPU_OFFSET (x86._ES), SMM_CPU_OFFSET (x64._ES), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
  125. { 4, 4, SMM_CPU_OFFSET (x86._CS), SMM_CPU_OFFSET (x64._CS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
  126. { 4, 4, SMM_CPU_OFFSET (x86._SS), SMM_CPU_OFFSET (x64._SS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
  127. { 4, 4, SMM_CPU_OFFSET (x86._DS), SMM_CPU_OFFSET (x64._DS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
  128. { 4, 4, SMM_CPU_OFFSET (x86._FS), SMM_CPU_OFFSET (x64._FS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
  129. { 4, 4, SMM_CPU_OFFSET (x86._GS), SMM_CPU_OFFSET (x64._GS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
  130. { 0, 4, 0, SMM_CPU_OFFSET (x64._LDTR), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
  131. { 4, 4, SMM_CPU_OFFSET (x86._TR), SMM_CPU_OFFSET (x64._TR), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
  132. { 4, 8, SMM_CPU_OFFSET (x86._DR7), SMM_CPU_OFFSET (x64._DR7), SMM_CPU_OFFSET (x64._DR7) + 4, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
  133. { 4, 8, SMM_CPU_OFFSET (x86._DR6), SMM_CPU_OFFSET (x64._DR6), SMM_CPU_OFFSET (x64._DR6) + 4, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
  134. { 0, 8, 0, SMM_CPU_OFFSET (x64._R8), SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
  135. { 0, 8, 0, SMM_CPU_OFFSET (x64._R9), SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
  136. { 0, 8, 0, SMM_CPU_OFFSET (x64._R10), SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
  137. { 0, 8, 0, SMM_CPU_OFFSET (x64._R11), SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
  138. { 0, 8, 0, SMM_CPU_OFFSET (x64._R12), SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
  139. { 0, 8, 0, SMM_CPU_OFFSET (x64._R13), SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
  140. { 0, 8, 0, SMM_CPU_OFFSET (x64._R14), SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
  141. { 0, 8, 0, SMM_CPU_OFFSET (x64._R15), SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
  142. { 4, 8, SMM_CPU_OFFSET (x86._EAX), SMM_CPU_OFFSET (x64._RAX), SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
  143. { 4, 8, SMM_CPU_OFFSET (x86._EBX), SMM_CPU_OFFSET (x64._RBX), SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
  144. { 4, 8, SMM_CPU_OFFSET (x86._ECX), SMM_CPU_OFFSET (x64._RCX), SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40
  145. { 4, 8, SMM_CPU_OFFSET (x86._EDX), SMM_CPU_OFFSET (x64._RDX), SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
  146. { 4, 8, SMM_CPU_OFFSET (x86._ESP), SMM_CPU_OFFSET (x64._RSP), SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
  147. { 4, 8, SMM_CPU_OFFSET (x86._EBP), SMM_CPU_OFFSET (x64._RBP), SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
  148. { 4, 8, SMM_CPU_OFFSET (x86._ESI), SMM_CPU_OFFSET (x64._RSI), SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
  149. { 4, 8, SMM_CPU_OFFSET (x86._EDI), SMM_CPU_OFFSET (x64._RDI), SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
  150. { 4, 8, SMM_CPU_OFFSET (x86._EIP), SMM_CPU_OFFSET (x64._RIP), SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
  151. { 4, 8, SMM_CPU_OFFSET (x86._EFLAGS), SMM_CPU_OFFSET (x64._RFLAGS), SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
  152. { 4, 8, SMM_CPU_OFFSET (x86._CR0), SMM_CPU_OFFSET (x64._CR0), SMM_CPU_OFFSET (x64._CR0) + 4, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
  153. { 4, 8, SMM_CPU_OFFSET (x86._CR3), SMM_CPU_OFFSET (x64._CR3), SMM_CPU_OFFSET (x64._CR3) + 4, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
  154. { 0, 4, 0, SMM_CPU_OFFSET (x64._CR4), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
  155. };
  156. ///
  157. /// Lookup table for the IOMisc width information
  158. ///
  159. CONST CPU_SMM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] = {
  160. { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 0
  161. { 1, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // SMM_IO_LENGTH_BYTE = 1
  162. { 2, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 }, // SMM_IO_LENGTH_WORD = 2
  163. { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 3
  164. { 4, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 }, // SMM_IO_LENGTH_DWORD = 4
  165. { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 5
  166. { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 6
  167. { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 } // Undefined = 7
  168. };
  169. ///
  170. /// Lookup table for the IOMisc type information
  171. ///
  172. CONST EFI_SMM_SAVE_STATE_IO_TYPE mSmmCpuIoType[] = {
  173. EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_DX = 0
  174. EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_IN_DX = 1
  175. EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_OUTS = 2
  176. EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_INS = 3
  177. (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 4
  178. (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 5
  179. EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_OUTS = 6
  180. EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_INS = 7
  181. EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_IMMEDIATE = 8
  182. EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_OUT_IMMEDIATE = 9
  183. (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 10
  184. (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 11
  185. (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 12
  186. (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 13
  187. (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 14
  188. (EFI_SMM_SAVE_STATE_IO_TYPE)0 // Undefined = 15
  189. };
  190. ///
  191. /// The mode of the CPU at the time an SMI occurs
  192. ///
  193. UINT8 mSmmSaveStateRegisterLma;
  194. /**
  195. Read information from the CPU save state.
  196. @param Register Specifies the CPU register to read form the save state.
  197. @retval 0 Register is not valid
  198. @retval >0 Index into mSmmCpuWidthOffset[] associated with Register
  199. **/
  200. UINTN
  201. GetRegisterIndex (
  202. IN EFI_SMM_SAVE_STATE_REGISTER Register
  203. )
  204. {
  205. UINTN Index;
  206. UINTN Offset;
  207. for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_MAX_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) {
  208. if ((Register >= mSmmCpuRegisterRanges[Index].Start) && (Register <= mSmmCpuRegisterRanges[Index].End)) {
  209. return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
  210. }
  211. Offset += mSmmCpuRegisterRanges[Index].Length;
  212. }
  213. return 0;
  214. }
  215. /**
  216. Read a CPU Save State register on the target processor.
  217. This function abstracts the differences that whether the CPU Save State register is in the
  218. IA32 CPU Save State Map or X64 CPU Save State Map.
  219. This function supports reading a CPU Save State register in SMBase relocation handler.
  220. @param[in] CpuIndex Specifies the zero-based index of the CPU save state.
  221. @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
  222. @param[in] Width The number of bytes to read from the CPU save state.
  223. @param[out] Buffer Upon return, this holds the CPU register value read from the save state.
  224. @retval EFI_SUCCESS The register was read from Save State.
  225. @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
  226. @retval EFI_INVALID_PARAMETER This or Buffer is NULL.
  227. **/
  228. EFI_STATUS
  229. ReadSaveStateRegisterByIndex (
  230. IN UINTN CpuIndex,
  231. IN UINTN RegisterIndex,
  232. IN UINTN Width,
  233. OUT VOID *Buffer
  234. )
  235. {
  236. SMRAM_SAVE_STATE_MAP *CpuSaveState;
  237. if (RegisterIndex == 0) {
  238. return EFI_NOT_FOUND;
  239. }
  240. CpuSaveState = gSmst->CpuSaveState[CpuIndex];
  241. if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
  242. //
  243. // If 32-bit mode width is zero, then the specified register can not be accessed
  244. //
  245. if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
  246. return EFI_NOT_FOUND;
  247. }
  248. //
  249. // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
  250. //
  251. if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
  252. return EFI_INVALID_PARAMETER;
  253. }
  254. //
  255. // Write return buffer
  256. //
  257. ASSERT (CpuSaveState != NULL);
  258. CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);
  259. } else {
  260. //
  261. // If 64-bit mode width is zero, then the specified register can not be accessed
  262. //
  263. if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
  264. return EFI_NOT_FOUND;
  265. }
  266. //
  267. // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
  268. //
  269. if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
  270. return EFI_INVALID_PARAMETER;
  271. }
  272. //
  273. // Write at most 4 of the lower bytes of the return buffer
  274. //
  275. CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN (4, Width));
  276. if (Width > 4) {
  277. //
  278. // Write at most 4 of the upper bytes of the return buffer
  279. //
  280. CopyMem ((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);
  281. }
  282. }
  283. return EFI_SUCCESS;
  284. }
  285. /**
  286. Read a CPU Save State register on the target processor.
  287. This function abstracts the differences that whether the CPU Save State register is in the
  288. IA32 CPU Save State Map or X64 CPU Save State Map.
  289. This function supports reading a CPU Save State register in SMBase relocation handler.
  290. @param[in] CpuIndex Specifies the zero-based index of the CPU save state.
  291. @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
  292. @param[in] Width The number of bytes to read from the CPU save state.
  293. @param[out] Buffer Upon return, this holds the CPU register value read from the save state.
  294. @retval EFI_SUCCESS The register was read from Save State.
  295. @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
  296. @retval EFI_INVALID_PARAMETER Buffer is NULL, or Width does not meet requirement per Register type.
  297. **/
  298. EFI_STATUS
  299. EFIAPI
  300. ReadSaveStateRegister (
  301. IN UINTN CpuIndex,
  302. IN EFI_SMM_SAVE_STATE_REGISTER Register,
  303. IN UINTN Width,
  304. OUT VOID *Buffer
  305. )
  306. {
  307. UINT32 SmmRevId;
  308. SMRAM_SAVE_STATE_IOMISC IoMisc;
  309. EFI_SMM_SAVE_STATE_IO_INFO *IoInfo;
  310. //
  311. // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
  312. //
  313. if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
  314. //
  315. // Only byte access is supported for this register
  316. //
  317. if (Width != 1) {
  318. return EFI_INVALID_PARAMETER;
  319. }
  320. *(UINT8 *)Buffer = mSmmSaveStateRegisterLma;
  321. return EFI_SUCCESS;
  322. }
  323. //
  324. // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO
  325. //
  326. if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
  327. //
  328. // Get SMM Revision ID
  329. //
  330. ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof (SmmRevId), &SmmRevId);
  331. //
  332. // See if the CPU supports the IOMisc register in the save state
  333. //
  334. if (SmmRevId < SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC) {
  335. return EFI_NOT_FOUND;
  336. }
  337. //
  338. // Get the IOMisc register value
  339. //
  340. ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_IOMISC_INDEX, sizeof (IoMisc.Uint32), &IoMisc.Uint32);
  341. //
  342. // Check for the SMI_FLAG in IOMisc
  343. //
  344. if (IoMisc.Bits.SmiFlag == 0) {
  345. return EFI_NOT_FOUND;
  346. }
  347. //
  348. // Only support IN/OUT, but not INS/OUTS/REP INS/REP OUTS.
  349. //
  350. if ((mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_INPUT) &&
  351. (mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT))
  352. {
  353. return EFI_NOT_FOUND;
  354. }
  355. //
  356. // Compute index for the I/O Length and I/O Type lookup tables
  357. //
  358. if ((mSmmCpuIoWidth[IoMisc.Bits.Length].Width == 0) || (mSmmCpuIoType[IoMisc.Bits.Type] == 0)) {
  359. return EFI_NOT_FOUND;
  360. }
  361. //
  362. // Make sure the incoming buffer is large enough to hold IoInfo before accessing
  363. //
  364. if (Width < sizeof (EFI_SMM_SAVE_STATE_IO_INFO)) {
  365. return EFI_INVALID_PARAMETER;
  366. }
  367. //
  368. // Zero the IoInfo structure that will be returned in Buffer
  369. //
  370. IoInfo = (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer;
  371. ZeroMem (IoInfo, sizeof (EFI_SMM_SAVE_STATE_IO_INFO));
  372. //
  373. // Use lookup tables to help fill in all the fields of the IoInfo structure
  374. //
  375. IoInfo->IoPort = (UINT16)IoMisc.Bits.Port;
  376. IoInfo->IoWidth = mSmmCpuIoWidth[IoMisc.Bits.Length].IoWidth;
  377. IoInfo->IoType = mSmmCpuIoType[IoMisc.Bits.Type];
  378. ReadSaveStateRegister (CpuIndex, EFI_SMM_SAVE_STATE_REGISTER_RAX, mSmmCpuIoWidth[IoMisc.Bits.Length].Width, &IoInfo->IoData);
  379. return EFI_SUCCESS;
  380. }
  381. //
  382. // Convert Register to a register lookup table index
  383. //
  384. return ReadSaveStateRegisterByIndex (CpuIndex, GetRegisterIndex (Register), Width, Buffer);
  385. }
  386. /**
  387. Write value to a CPU Save State register on the target processor.
  388. This function abstracts the differences that whether the CPU Save State register is in the
  389. IA32 CPU Save State Map or X64 CPU Save State Map.
  390. This function supports writing a CPU Save State register in SMBase relocation handler.
  391. @param[in] CpuIndex Specifies the zero-based index of the CPU save state.
  392. @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
  393. @param[in] Width The number of bytes to read from the CPU save state.
  394. @param[in] Buffer Upon entry, this holds the new CPU register value.
  395. @retval EFI_SUCCESS The register was written to Save State.
  396. @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
  397. @retval EFI_INVALID_PARAMETER ProcessorIndex or Width is not correct.
  398. **/
  399. EFI_STATUS
  400. EFIAPI
  401. WriteSaveStateRegister (
  402. IN UINTN CpuIndex,
  403. IN EFI_SMM_SAVE_STATE_REGISTER Register,
  404. IN UINTN Width,
  405. IN CONST VOID *Buffer
  406. )
  407. {
  408. UINTN RegisterIndex;
  409. SMRAM_SAVE_STATE_MAP *CpuSaveState;
  410. //
  411. // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
  412. //
  413. if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
  414. return EFI_SUCCESS;
  415. }
  416. //
  417. // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported
  418. //
  419. if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
  420. return EFI_NOT_FOUND;
  421. }
  422. //
  423. // Convert Register to a register lookup table index
  424. //
  425. RegisterIndex = GetRegisterIndex (Register);
  426. if (RegisterIndex == 0) {
  427. return EFI_NOT_FOUND;
  428. }
  429. CpuSaveState = gSmst->CpuSaveState[CpuIndex];
  430. //
  431. // Do not write non-writable SaveState, because it will cause exception.
  432. //
  433. if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {
  434. return EFI_UNSUPPORTED;
  435. }
  436. //
  437. // Check CPU mode
  438. //
  439. if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
  440. //
  441. // If 32-bit mode width is zero, then the specified register can not be accessed
  442. //
  443. if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
  444. return EFI_NOT_FOUND;
  445. }
  446. //
  447. // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
  448. //
  449. if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
  450. return EFI_INVALID_PARAMETER;
  451. }
  452. //
  453. // Write SMM State register
  454. //
  455. ASSERT (CpuSaveState != NULL);
  456. CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
  457. } else {
  458. //
  459. // If 64-bit mode width is zero, then the specified register can not be accessed
  460. //
  461. if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
  462. return EFI_NOT_FOUND;
  463. }
  464. //
  465. // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
  466. //
  467. if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
  468. return EFI_INVALID_PARAMETER;
  469. }
  470. //
  471. // Write at most 4 of the lower bytes of SMM State register
  472. //
  473. CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
  474. if (Width > 4) {
  475. //
  476. // Write at most 4 of the upper bytes of SMM State register
  477. //
  478. CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
  479. }
  480. }
  481. return EFI_SUCCESS;
  482. }
  483. /**
  484. Hook the code executed immediately after an RSM instruction on the currently
  485. executing CPU. The mode of code executed immediately after RSM must be
  486. detected, and the appropriate hook must be selected. Always clear the auto
  487. HALT restart flag if it is set.
  488. @param[in] CpuIndex The processor index for the currently
  489. executing CPU.
  490. @param[in] CpuState Pointer to SMRAM Save State Map for the
  491. currently executing CPU.
  492. @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
  493. 32-bit mode from 64-bit SMM.
  494. @param[in] NewInstructionPointer Instruction pointer to use if resuming to
  495. same mode as SMM.
  496. @retval The value of the original instruction pointer before it was hooked.
  497. **/
  498. UINT64
  499. EFIAPI
  500. HookReturnFromSmm (
  501. IN UINTN CpuIndex,
  502. SMRAM_SAVE_STATE_MAP *CpuState,
  503. UINT64 NewInstructionPointer32,
  504. UINT64 NewInstructionPointer
  505. )
  506. {
  507. UINT64 OriginalInstructionPointer;
  508. OriginalInstructionPointer = SmmCpuFeaturesHookReturnFromSmm (
  509. CpuIndex,
  510. CpuState,
  511. NewInstructionPointer32,
  512. NewInstructionPointer
  513. );
  514. if (OriginalInstructionPointer != 0) {
  515. return OriginalInstructionPointer;
  516. }
  517. if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
  518. OriginalInstructionPointer = (UINT64)CpuState->x86._EIP;
  519. CpuState->x86._EIP = (UINT32)NewInstructionPointer;
  520. //
  521. // Clear the auto HALT restart flag so the RSM instruction returns
  522. // program control to the instruction following the HLT instruction.
  523. //
  524. if ((CpuState->x86.AutoHALTRestart & BIT0) != 0) {
  525. CpuState->x86.AutoHALTRestart &= ~BIT0;
  526. }
  527. } else {
  528. OriginalInstructionPointer = CpuState->x64._RIP;
  529. if ((CpuState->x64.IA32_EFER & LMA) == 0) {
  530. CpuState->x64._RIP = (UINT32)NewInstructionPointer32;
  531. } else {
  532. CpuState->x64._RIP = (UINT32)NewInstructionPointer;
  533. }
  534. //
  535. // Clear the auto HALT restart flag so the RSM instruction returns
  536. // program control to the instruction following the HLT instruction.
  537. //
  538. if ((CpuState->x64.AutoHALTRestart & BIT0) != 0) {
  539. CpuState->x64.AutoHALTRestart &= ~BIT0;
  540. }
  541. }
  542. return OriginalInstructionPointer;
  543. }
  544. /**
  545. Get the size of the SMI Handler in bytes.
  546. @retval The size, in bytes, of the SMI Handler.
  547. **/
  548. UINTN
  549. EFIAPI
  550. GetSmiHandlerSize (
  551. VOID
  552. )
  553. {
  554. UINTN Size;
  555. Size = SmmCpuFeaturesGetSmiHandlerSize ();
  556. if (Size != 0) {
  557. return Size;
  558. }
  559. return gcSmiHandlerSize;
  560. }
  561. /**
  562. Install the SMI handler for the CPU specified by CpuIndex. This function
  563. is called by the CPU that was elected as monarch during System Management
  564. Mode initialization.
  565. @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
  566. The value must be between 0 and the NumberOfCpus field
  567. in the System Management System Table (SMST).
  568. @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
  569. @param[in] SmiStack The stack to use when an SMI is processed by the
  570. the CPU specified by CpuIndex.
  571. @param[in] StackSize The size, in bytes, if the stack used when an SMI is
  572. processed by the CPU specified by CpuIndex.
  573. @param[in] GdtBase The base address of the GDT to use when an SMI is
  574. processed by the CPU specified by CpuIndex.
  575. @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
  576. processed by the CPU specified by CpuIndex.
  577. @param[in] IdtBase The base address of the IDT to use when an SMI is
  578. processed by the CPU specified by CpuIndex.
  579. @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
  580. processed by the CPU specified by CpuIndex.
  581. @param[in] Cr3 The base address of the page tables to use when an SMI
  582. is processed by the CPU specified by CpuIndex.
  583. **/
  584. VOID
  585. EFIAPI
  586. InstallSmiHandler (
  587. IN UINTN CpuIndex,
  588. IN UINT32 SmBase,
  589. IN VOID *SmiStack,
  590. IN UINTN StackSize,
  591. IN UINTN GdtBase,
  592. IN UINTN GdtSize,
  593. IN UINTN IdtBase,
  594. IN UINTN IdtSize,
  595. IN UINT32 Cr3
  596. )
  597. {
  598. PROCESSOR_SMM_DESCRIPTOR *Psd;
  599. UINT32 CpuSmiStack;
  600. //
  601. // Initialize PROCESSOR_SMM_DESCRIPTOR
  602. //
  603. Psd = (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + SMM_PSD_OFFSET);
  604. CopyMem (Psd, &gcPsd, sizeof (gcPsd));
  605. Psd->SmmGdtPtr = (UINT64)GdtBase;
  606. Psd->SmmGdtSize = (UINT32)GdtSize;
  607. if (SmmCpuFeaturesGetSmiHandlerSize () != 0) {
  608. //
  609. // Install SMI handler provided by library
  610. //
  611. SmmCpuFeaturesInstallSmiHandler (
  612. CpuIndex,
  613. SmBase,
  614. SmiStack,
  615. StackSize,
  616. GdtBase,
  617. GdtSize,
  618. IdtBase,
  619. IdtSize,
  620. Cr3
  621. );
  622. return;
  623. }
  624. InitShadowStack (CpuIndex, (VOID *)((UINTN)SmiStack + StackSize));
  625. //
  626. // Initialize values in template before copy
  627. //
  628. CpuSmiStack = (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN));
  629. PatchInstructionX86 (gPatchSmiStack, CpuSmiStack, 4);
  630. PatchInstructionX86 (gPatchSmiCr3, Cr3, 4);
  631. PatchInstructionX86 (gPatchSmbase, SmBase, 4);
  632. gSmiHandlerIdtr.Base = IdtBase;
  633. gSmiHandlerIdtr.Limit = (UINT16)(IdtSize - 1);
  634. //
  635. // Set the value at the top of the CPU stack to the CPU Index
  636. //
  637. *(UINTN *)(UINTN)CpuSmiStack = CpuIndex;
  638. //
  639. // Copy template to CPU specific SMI handler location
  640. //
  641. CopyMem (
  642. (VOID *)((UINTN)SmBase + SMM_HANDLER_OFFSET),
  643. (VOID *)gcSmiHandlerTemplate,
  644. gcSmiHandlerSize
  645. );
  646. }