CpuPaging.c 18 KB

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  1. /** @file
  2. Basic paging support for the CPU to enable Stack Guard.
  3. Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <Register/Intel/Cpuid.h>
  7. #include <Register/Intel/Msr.h>
  8. #include <Library/MemoryAllocationLib.h>
  9. #include <Library/CpuLib.h>
  10. #include <Library/BaseLib.h>
  11. #include <Guid/MigratedFvInfo.h>
  12. #include "CpuMpPei.h"
  13. #define IA32_PG_P BIT0
  14. #define IA32_PG_RW BIT1
  15. #define IA32_PG_U BIT2
  16. #define IA32_PG_A BIT5
  17. #define IA32_PG_D BIT6
  18. #define IA32_PG_PS BIT7
  19. #define IA32_PG_NX BIT63
  20. #define PAGE_ATTRIBUTE_BITS (IA32_PG_RW | IA32_PG_P)
  21. #define PAGE_PROGATE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_NX | IA32_PG_U | \
  22. PAGE_ATTRIBUTE_BITS)
  23. #define PAGING_PAE_INDEX_MASK 0x1FF
  24. #define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
  25. #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
  26. #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
  27. #define PAGING_512G_ADDRESS_MASK_64 0x000FFF8000000000ull
  28. typedef enum {
  29. PageNone = 0,
  30. PageMin = 1,
  31. Page4K = PageMin,
  32. Page2M = 2,
  33. Page1G = 3,
  34. Page512G = 4,
  35. PageMax = Page512G
  36. } PAGE_ATTRIBUTE;
  37. typedef struct {
  38. PAGE_ATTRIBUTE Attribute;
  39. UINT64 Length;
  40. UINT64 AddressMask;
  41. UINTN AddressBitOffset;
  42. UINTN AddressBitLength;
  43. } PAGE_ATTRIBUTE_TABLE;
  44. PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
  45. { PageNone, 0, 0, 0, 0 },
  46. { Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64, 12, 9 },
  47. { Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64, 21, 9 },
  48. { Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64, 30, 9 },
  49. { Page512G, SIZE_512GB, PAGING_512G_ADDRESS_MASK_64, 39, 9 },
  50. };
  51. EFI_PEI_NOTIFY_DESCRIPTOR mPostMemNotifyList[] = {
  52. {
  53. (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
  54. &gEfiPeiMemoryDiscoveredPpiGuid,
  55. MemoryDiscoveredPpiNotifyCallback
  56. }
  57. };
  58. /**
  59. The function will check if IA32 PAE is supported.
  60. @retval TRUE IA32 PAE is supported.
  61. @retval FALSE IA32 PAE is not supported.
  62. **/
  63. BOOLEAN
  64. IsIa32PaeSupported (
  65. VOID
  66. )
  67. {
  68. UINT32 RegEax;
  69. CPUID_VERSION_INFO_EDX RegEdx;
  70. AsmCpuid (CPUID_SIGNATURE, &RegEax, NULL, NULL, NULL);
  71. if (RegEax >= CPUID_VERSION_INFO) {
  72. AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx.Uint32);
  73. if (RegEdx.Bits.PAE != 0) {
  74. return TRUE;
  75. }
  76. }
  77. return FALSE;
  78. }
  79. /**
  80. This API provides a way to allocate memory for page table.
  81. @param Pages The number of 4 KB pages to allocate.
  82. @return A pointer to the allocated buffer or NULL if allocation fails.
  83. **/
  84. VOID *
  85. AllocatePageTableMemory (
  86. IN UINTN Pages
  87. )
  88. {
  89. VOID *Address;
  90. Address = AllocatePages (Pages);
  91. if (Address != NULL) {
  92. ZeroMem (Address, EFI_PAGES_TO_SIZE (Pages));
  93. }
  94. return Address;
  95. }
  96. /**
  97. Get the address width supported by current processor.
  98. @retval 32 If processor is in 32-bit mode.
  99. @retval 36-48 If processor is in 64-bit mode.
  100. **/
  101. UINTN
  102. GetPhysicalAddressWidth (
  103. VOID
  104. )
  105. {
  106. UINT32 RegEax;
  107. if (sizeof (UINTN) == 4) {
  108. return 32;
  109. }
  110. AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
  111. if (RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) {
  112. AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &RegEax, NULL, NULL, NULL);
  113. RegEax &= 0xFF;
  114. if (RegEax > 48) {
  115. return 48;
  116. }
  117. return (UINTN)RegEax;
  118. }
  119. return 36;
  120. }
  121. /**
  122. Get the type of top level page table.
  123. @retval Page512G PML4 paging.
  124. @retval Page1G PAE paging.
  125. **/
  126. PAGE_ATTRIBUTE
  127. GetPageTableTopLevelType (
  128. VOID
  129. )
  130. {
  131. MSR_IA32_EFER_REGISTER MsrEfer;
  132. MsrEfer.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);
  133. return (MsrEfer.Bits.LMA == 1) ? Page512G : Page1G;
  134. }
  135. /**
  136. Return page table entry matching the address.
  137. @param[in] Address The address to be checked.
  138. @param[out] PageAttributes The page attribute of the page entry.
  139. @return The page entry.
  140. **/
  141. VOID *
  142. GetPageTableEntry (
  143. IN PHYSICAL_ADDRESS Address,
  144. OUT PAGE_ATTRIBUTE *PageAttribute
  145. )
  146. {
  147. INTN Level;
  148. UINTN Index;
  149. UINT64 *PageTable;
  150. UINT64 AddressEncMask;
  151. AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask);
  152. PageTable = (UINT64 *)(UINTN)(AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);
  153. for (Level = (INTN)GetPageTableTopLevelType (); Level > 0; --Level) {
  154. Index = (UINTN)RShiftU64 (Address, mPageAttributeTable[Level].AddressBitOffset);
  155. Index &= PAGING_PAE_INDEX_MASK;
  156. //
  157. // No mapping?
  158. //
  159. if (PageTable[Index] == 0) {
  160. *PageAttribute = PageNone;
  161. return NULL;
  162. }
  163. //
  164. // Page memory?
  165. //
  166. if (((PageTable[Index] & IA32_PG_PS) != 0) || (Level == PageMin)) {
  167. *PageAttribute = (PAGE_ATTRIBUTE)Level;
  168. return &PageTable[Index];
  169. }
  170. //
  171. // Page directory or table
  172. //
  173. PageTable = (UINT64 *)(UINTN)(PageTable[Index] &
  174. ~AddressEncMask &
  175. PAGING_4K_ADDRESS_MASK_64);
  176. }
  177. *PageAttribute = PageNone;
  178. return NULL;
  179. }
  180. /**
  181. This function splits one page entry to smaller page entries.
  182. @param[in] PageEntry The page entry to be splitted.
  183. @param[in] PageAttribute The page attribute of the page entry.
  184. @param[in] SplitAttribute How to split the page entry.
  185. @param[in] Recursively Do the split recursively or not.
  186. @retval RETURN_SUCCESS The page entry is splitted.
  187. @retval RETURN_INVALID_PARAMETER If target page attribute is invalid
  188. @retval RETURN_OUT_OF_RESOURCES No resource to split page entry.
  189. **/
  190. RETURN_STATUS
  191. SplitPage (
  192. IN UINT64 *PageEntry,
  193. IN PAGE_ATTRIBUTE PageAttribute,
  194. IN PAGE_ATTRIBUTE SplitAttribute,
  195. IN BOOLEAN Recursively
  196. )
  197. {
  198. UINT64 BaseAddress;
  199. UINT64 *NewPageEntry;
  200. UINTN Index;
  201. UINT64 AddressEncMask;
  202. PAGE_ATTRIBUTE SplitTo;
  203. if ((SplitAttribute == PageNone) || (SplitAttribute >= PageAttribute)) {
  204. ASSERT (SplitAttribute != PageNone);
  205. ASSERT (SplitAttribute < PageAttribute);
  206. return RETURN_INVALID_PARAMETER;
  207. }
  208. NewPageEntry = AllocatePageTableMemory (1);
  209. if (NewPageEntry == NULL) {
  210. ASSERT (NewPageEntry != NULL);
  211. return RETURN_OUT_OF_RESOURCES;
  212. }
  213. //
  214. // One level down each step to achieve more compact page table.
  215. //
  216. SplitTo = PageAttribute - 1;
  217. AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &
  218. mPageAttributeTable[SplitTo].AddressMask;
  219. BaseAddress = *PageEntry &
  220. ~PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &
  221. mPageAttributeTable[PageAttribute].AddressMask;
  222. for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {
  223. NewPageEntry[Index] = BaseAddress | AddressEncMask |
  224. ((*PageEntry) & PAGE_PROGATE_BITS);
  225. if (SplitTo != PageMin) {
  226. NewPageEntry[Index] |= IA32_PG_PS;
  227. }
  228. if (Recursively && (SplitTo > SplitAttribute)) {
  229. SplitPage (&NewPageEntry[Index], SplitTo, SplitAttribute, Recursively);
  230. }
  231. BaseAddress += mPageAttributeTable[SplitTo].Length;
  232. }
  233. (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | PAGE_ATTRIBUTE_BITS;
  234. return RETURN_SUCCESS;
  235. }
  236. /**
  237. This function modifies the page attributes for the memory region specified
  238. by BaseAddress and Length from their current attributes to the attributes
  239. specified by Attributes.
  240. Caller should make sure BaseAddress and Length is at page boundary.
  241. @param[in] BaseAddress Start address of a memory region.
  242. @param[in] Length Size in bytes of the memory region.
  243. @param[in] Attributes Bit mask of attributes to modify.
  244. @retval RETURN_SUCCESS The attributes were modified for the memory
  245. region.
  246. @retval RETURN_INVALID_PARAMETER Length is zero; or,
  247. Attributes specified an illegal combination
  248. of attributes that cannot be set together; or
  249. Addressis not 4KB aligned.
  250. @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to modify
  251. the attributes.
  252. @retval RETURN_UNSUPPORTED Cannot modify the attributes of given memory.
  253. **/
  254. RETURN_STATUS
  255. EFIAPI
  256. ConvertMemoryPageAttributes (
  257. IN PHYSICAL_ADDRESS BaseAddress,
  258. IN UINT64 Length,
  259. IN UINT64 Attributes
  260. )
  261. {
  262. UINT64 *PageEntry;
  263. PAGE_ATTRIBUTE PageAttribute;
  264. RETURN_STATUS Status;
  265. EFI_PHYSICAL_ADDRESS MaximumAddress;
  266. if ((Length == 0) ||
  267. ((BaseAddress & (SIZE_4KB - 1)) != 0) ||
  268. ((Length & (SIZE_4KB - 1)) != 0))
  269. {
  270. ASSERT (Length > 0);
  271. ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
  272. ASSERT ((Length & (SIZE_4KB - 1)) == 0);
  273. return RETURN_INVALID_PARAMETER;
  274. }
  275. MaximumAddress = (EFI_PHYSICAL_ADDRESS)MAX_UINT32;
  276. if ((BaseAddress > MaximumAddress) ||
  277. (Length > MaximumAddress) ||
  278. (BaseAddress > MaximumAddress - (Length - 1)))
  279. {
  280. return RETURN_UNSUPPORTED;
  281. }
  282. //
  283. // Below logic is to check 2M/4K page to make sure we do not waste memory.
  284. //
  285. while (Length != 0) {
  286. PageEntry = GetPageTableEntry (BaseAddress, &PageAttribute);
  287. if (PageEntry == NULL) {
  288. return RETURN_UNSUPPORTED;
  289. }
  290. if (PageAttribute != Page4K) {
  291. Status = SplitPage (PageEntry, PageAttribute, Page4K, FALSE);
  292. if (RETURN_ERROR (Status)) {
  293. return Status;
  294. }
  295. //
  296. // Do it again until the page is 4K.
  297. //
  298. continue;
  299. }
  300. //
  301. // Just take care of 'present' bit for Stack Guard.
  302. //
  303. if ((Attributes & IA32_PG_P) != 0) {
  304. *PageEntry |= (UINT64)IA32_PG_P;
  305. } else {
  306. *PageEntry &= ~((UINT64)IA32_PG_P);
  307. }
  308. //
  309. // Convert success, move to next
  310. //
  311. BaseAddress += SIZE_4KB;
  312. Length -= SIZE_4KB;
  313. }
  314. return RETURN_SUCCESS;
  315. }
  316. /**
  317. Get maximum size of page memory supported by current processor.
  318. @param[in] TopLevelType The type of top level page entry.
  319. @retval Page1G If processor supports 1G page and PML4.
  320. @retval Page2M For all other situations.
  321. **/
  322. PAGE_ATTRIBUTE
  323. GetMaxMemoryPage (
  324. IN PAGE_ATTRIBUTE TopLevelType
  325. )
  326. {
  327. UINT32 RegEax;
  328. UINT32 RegEdx;
  329. if (TopLevelType == Page512G) {
  330. AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
  331. if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
  332. AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
  333. if ((RegEdx & BIT26) != 0) {
  334. return Page1G;
  335. }
  336. }
  337. }
  338. return Page2M;
  339. }
  340. /**
  341. Create PML4 or PAE page table.
  342. @return The address of page table.
  343. **/
  344. UINTN
  345. CreatePageTable (
  346. VOID
  347. )
  348. {
  349. RETURN_STATUS Status;
  350. UINTN PhysicalAddressBits;
  351. UINTN NumberOfEntries;
  352. PAGE_ATTRIBUTE TopLevelPageAttr;
  353. UINTN PageTable;
  354. PAGE_ATTRIBUTE MaxMemoryPage;
  355. UINTN Index;
  356. UINT64 AddressEncMask;
  357. UINT64 *PageEntry;
  358. EFI_PHYSICAL_ADDRESS PhysicalAddress;
  359. TopLevelPageAttr = (PAGE_ATTRIBUTE)GetPageTableTopLevelType ();
  360. PhysicalAddressBits = GetPhysicalAddressWidth ();
  361. NumberOfEntries = (UINTN)1 << (PhysicalAddressBits -
  362. mPageAttributeTable[TopLevelPageAttr].AddressBitOffset);
  363. PageTable = (UINTN)AllocatePageTableMemory (1);
  364. if (PageTable == 0) {
  365. return 0;
  366. }
  367. AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask);
  368. AddressEncMask &= mPageAttributeTable[TopLevelPageAttr].AddressMask;
  369. MaxMemoryPage = GetMaxMemoryPage (TopLevelPageAttr);
  370. PageEntry = (UINT64 *)PageTable;
  371. PhysicalAddress = 0;
  372. for (Index = 0; Index < NumberOfEntries; ++Index) {
  373. *PageEntry = PhysicalAddress | AddressEncMask | PAGE_ATTRIBUTE_BITS;
  374. //
  375. // Split the top page table down to the maximum page size supported
  376. //
  377. if (MaxMemoryPage < TopLevelPageAttr) {
  378. Status = SplitPage (PageEntry, TopLevelPageAttr, MaxMemoryPage, TRUE);
  379. ASSERT_EFI_ERROR (Status);
  380. }
  381. if (TopLevelPageAttr == Page1G) {
  382. //
  383. // PDPTE[2:1] (PAE Paging) must be 0. SplitPage() might change them to 1.
  384. //
  385. *PageEntry &= ~(UINT64)(IA32_PG_RW | IA32_PG_U);
  386. }
  387. PageEntry += 1;
  388. PhysicalAddress += mPageAttributeTable[TopLevelPageAttr].Length;
  389. }
  390. return PageTable;
  391. }
  392. /**
  393. Setup page tables and make them work.
  394. **/
  395. VOID
  396. EnablePaging (
  397. VOID
  398. )
  399. {
  400. UINTN PageTable;
  401. PageTable = CreatePageTable ();
  402. ASSERT (PageTable != 0);
  403. if (PageTable != 0) {
  404. AsmWriteCr3 (PageTable);
  405. AsmWriteCr4 (AsmReadCr4 () | BIT5); // CR4.PAE
  406. AsmWriteCr0 (AsmReadCr0 () | BIT31); // CR0.PG
  407. }
  408. }
  409. /**
  410. Get the base address of current AP's stack.
  411. This function is called in AP's context and assumes that whole calling stacks
  412. (till this function) consumed by AP's wakeup procedure will not exceed 4KB.
  413. PcdCpuApStackSize must be configured with value taking the Guard page into
  414. account.
  415. @param[in,out] Buffer The pointer to private data buffer.
  416. **/
  417. VOID
  418. EFIAPI
  419. GetStackBase (
  420. IN OUT VOID *Buffer
  421. )
  422. {
  423. EFI_PHYSICAL_ADDRESS StackBase;
  424. StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)&StackBase;
  425. StackBase += BASE_4KB;
  426. StackBase &= ~((EFI_PHYSICAL_ADDRESS)BASE_4KB - 1);
  427. StackBase -= PcdGet32 (PcdCpuApStackSize);
  428. *(EFI_PHYSICAL_ADDRESS *)Buffer = StackBase;
  429. }
  430. /**
  431. Setup stack Guard page at the stack base of each processor. BSP and APs have
  432. different way to get stack base address.
  433. **/
  434. VOID
  435. SetupStackGuardPage (
  436. VOID
  437. )
  438. {
  439. EFI_PEI_HOB_POINTERS Hob;
  440. EFI_PHYSICAL_ADDRESS StackBase;
  441. UINTN NumberOfProcessors;
  442. UINTN Bsp;
  443. UINTN Index;
  444. //
  445. // One extra page at the bottom of the stack is needed for Guard page.
  446. //
  447. if (PcdGet32 (PcdCpuApStackSize) <= EFI_PAGE_SIZE) {
  448. DEBUG ((DEBUG_ERROR, "PcdCpuApStackSize is not big enough for Stack Guard!\n"));
  449. ASSERT (FALSE);
  450. }
  451. MpInitLibGetNumberOfProcessors (&NumberOfProcessors, NULL);
  452. MpInitLibWhoAmI (&Bsp);
  453. for (Index = 0; Index < NumberOfProcessors; ++Index) {
  454. StackBase = 0;
  455. if (Index == Bsp) {
  456. Hob.Raw = GetHobList ();
  457. while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, Hob.Raw)) != NULL) {
  458. if (CompareGuid (
  459. &gEfiHobMemoryAllocStackGuid,
  460. &(Hob.MemoryAllocationStack->AllocDescriptor.Name)
  461. ))
  462. {
  463. StackBase = Hob.MemoryAllocationStack->AllocDescriptor.MemoryBaseAddress;
  464. break;
  465. }
  466. Hob.Raw = GET_NEXT_HOB (Hob);
  467. }
  468. } else {
  469. //
  470. // Ask AP to return is stack base address.
  471. //
  472. MpInitLibStartupThisAP (GetStackBase, Index, NULL, 0, (VOID *)&StackBase, NULL);
  473. }
  474. ASSERT (StackBase != 0);
  475. //
  476. // Set Guard page at stack base address.
  477. //
  478. ConvertMemoryPageAttributes (StackBase, EFI_PAGE_SIZE, 0);
  479. DEBUG ((
  480. DEBUG_INFO,
  481. "Stack Guard set at %lx [cpu%lu]!\n",
  482. (UINT64)StackBase,
  483. (UINT64)Index
  484. ));
  485. }
  486. //
  487. // Publish the changes of page table.
  488. //
  489. CpuFlushTlb ();
  490. }
  491. /**
  492. Enable/setup stack guard for each processor if PcdCpuStackGuard is set to TRUE.
  493. Doing this in the memory-discovered callback is to make sure the Stack Guard
  494. feature to cover as most PEI code as possible.
  495. @param[in] PeiServices General purpose services available to every PEIM.
  496. @param[in] NotifyDescriptor The notification structure this PEIM registered on install.
  497. @param[in] Ppi The memory discovered PPI. Not used.
  498. @retval EFI_SUCCESS The function completed successfully.
  499. @retval others There's error in MP initialization.
  500. **/
  501. EFI_STATUS
  502. EFIAPI
  503. MemoryDiscoveredPpiNotifyCallback (
  504. IN EFI_PEI_SERVICES **PeiServices,
  505. IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
  506. IN VOID *Ppi
  507. )
  508. {
  509. EFI_STATUS Status;
  510. BOOLEAN InitStackGuard;
  511. EDKII_MIGRATED_FV_INFO *MigratedFvInfo;
  512. EFI_PEI_HOB_POINTERS Hob;
  513. //
  514. // Paging must be setup first. Otherwise the exception TSS setup during MP
  515. // initialization later will not contain paging information and then fail
  516. // the task switch (for the sake of stack switch).
  517. //
  518. InitStackGuard = FALSE;
  519. Hob.Raw = NULL;
  520. if (IsIa32PaeSupported ()) {
  521. Hob.Raw = GetFirstGuidHob (&gEdkiiMigratedFvInfoGuid);
  522. InitStackGuard = PcdGetBool (PcdCpuStackGuard);
  523. }
  524. if (InitStackGuard || (Hob.Raw != NULL)) {
  525. EnablePaging ();
  526. }
  527. Status = InitializeCpuMpWorker ((CONST EFI_PEI_SERVICES **)PeiServices);
  528. ASSERT_EFI_ERROR (Status);
  529. if (InitStackGuard) {
  530. SetupStackGuardPage ();
  531. }
  532. while (Hob.Raw != NULL) {
  533. MigratedFvInfo = GET_GUID_HOB_DATA (Hob);
  534. //
  535. // Enable #PF exception, so if the code access SPI after disable NEM, it will generate
  536. // the exception to avoid potential vulnerability.
  537. //
  538. ConvertMemoryPageAttributes (MigratedFvInfo->FvOrgBase, MigratedFvInfo->FvLength, 0);
  539. Hob.Raw = GET_NEXT_HOB (Hob);
  540. Hob.Raw = GetNextGuidHob (&gEdkiiMigratedFvInfoGuid, Hob.Raw);
  541. }
  542. CpuFlushTlb ();
  543. return Status;
  544. }